U.S. patent application number 12/168786 was filed with the patent office on 2008-10-30 for channel discharging after erasing flash memory devices.
This patent application is currently assigned to Atmel Corporation. Invention is credited to Stephen T. Trinh.
Application Number | 20080266982 12/168786 |
Document ID | / |
Family ID | 37694109 |
Filed Date | 2008-10-30 |
United States Patent
Application |
20080266982 |
Kind Code |
A1 |
Trinh; Stephen T. |
October 30, 2008 |
CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES
Abstract
A post-erase channel clearing procedure for double well,
floating gate, non-volatile memory cells. The channel is cleared of
charged particles coming from the floating gate after an erase
operation in two steps. In the first step the charged particles are
pushed into an upper substrate well below the floating gate but not
allowed into a deeper well of opposite conductivity type relative
to the upper well. After a brief time, T, the charged particles are
pushed by a bias voltage into the deeper well from the upper well.
This two step clearing procedure avoids device latchup that might
occur otherwise.
Inventors: |
Trinh; Stephen T.; (San
Jose, CA) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG & WOESSNER / ATMEL
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Atmel Corporation
San Jose
CA
|
Family ID: |
37694109 |
Appl. No.: |
12/168786 |
Filed: |
July 7, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11190722 |
Jul 27, 2005 |
7397699 |
|
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12168786 |
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Current U.S.
Class: |
365/185.29 ;
257/E29.304; 365/185.18 |
Current CPC
Class: |
G11C 16/14 20130101;
H01L 29/7883 20130101 |
Class at
Publication: |
365/185.29 ;
365/185.18 |
International
Class: |
G11C 16/06 20060101
G11C016/06 |
Claims
1. A channel clearing method, comprising: discharging a floating
gate into a double well vertical p and n type subsurface structure
by applying an erase voltage at a first time causing charged
particle flow from the floating gate to a first well in the
substrate; at a second time, discharging the first well into a
second well in the substrate by applying a channel-clearing voltage
causing charged particle flow from the first well into the second
well; and at a third time, discharging the second well.
2. The method of claim 1, wherein applying the erase voltage
includes applying a greater potential than the channel-clearing
voltage.
3. The method of claim 1 wherein discharging the second well at a
time, T, after the discharging of the first well, and wherein the
time, T, is less than the time for a next sequential program and
erase operation.
4. The method of claim 1, wherein discharging the floating gate
into a double well involves maintaining a less than 0.1 volt
differential between the first well and second well.
5. The method of claim 1, wherein applying channel-clearing voltage
includes switching the voltage from high voltage to a power supply
voltage on the second well.
6. The method of claim 1, wherein applying channel-clearing voltage
includes switching the voltage from high voltage to a voltage used
for auxiliary devices.
7. The method of claim 1, wherein applying an erase voltage at a
first time includes driving the first and second deep wells with
high voltage transistor switches.
8. The method of claim 1, wherein discharging the second time
includes optimizing the rate of discharge to prevent snap back.
9. The method of claim 1, wherein discharging the first well and
discharging the second well include discharging by a same
switch.
10. A method of channel clearing in a double well floating gate
non-volatile memory device subject to sequential program and erase
operations comprising: discharging the floating gate at a first
time by controlling voltages on a control gate above the floating
gate and in a subsurface region below the floating gate; and
starting a channel clearing operation at a second time after
initiation of the discharging step at a first voltage level but
changing to a second voltage level at a third time before the next
memory operation that provides a discharge path through the double
well.
11. The method of claim 10, wherein voltages in the subsurface
region below the floating gate is applied through double wells, one
double well atop the other double well.
12. The method of claim 10, wherein the first voltage level
establishes a greater potential difference relative to the voltage
in the control gate above the floating gate than the second voltage
level.
13. The method of claim 10, wherein said double well forms a
parasitic p-n diode junction wherein said first and second voltage
levels provide a reverse bias across the p-n junction.
14. The method of claim 10, wherein discharging the floating gate a
first time includes maintaining a less than 0.1 volt differential
between the first well and the second well.
15. The method of claim 10, wherein applying discharging the
floating gate a first time includes driving the double well with
high voltage transistor switches.
16. The method of claim 10, wherein starting a channel clearing
operation at a second time includes optimizing a rate of discharge
to prevent snap back.
17. A method of channel clearing in a double well floating gate
memory transistor, comprising: discharging a floating gate at a
first time by a high voltage having a first polarity on the control
gate and a second polarity on both a first well and a second well
of a double well; clearing the channel at a second time later than
the first time by grounding the control gate and grounding the
first well while allowing the second well to remain at the voltage
of the second polarity thereby reverse biasing the parasitic p-n
junction of first and second wells; after a third time, lowering
the voltage of the second well to an intermediate voltage while the
first well remains at ground.
18. The method of claim 17, wherein the voltage of the first
polarity for discharging the floating gate is approximately equal
in voltage to the voltage of second polarity.
19. The method of claim 17, wherein discharging the floating gate a
first time includes maintaining a less than 0.1 volt differential
between the first well and the second well.
20. The method of claim 17, wherein the second polarity is coupled
to a power supply voltage.
21. The method of claim 17, wherein the second polarity is coupled
to an auxiliary device voltage.
22. The method of claim 17, wherein applying floating gate at a
first time by a high voltage includes setting the second polarity
to voltage driven by high voltage switches.
23. The method of claim 17, wherein the clearing the channel at a
second time includes optimizing the rate of clearing to prevent
snap back.
24. A system for reducing snap-back in a non-volatile memory array,
comprising: an array of non-volatile memory cells comprising a
first well and a second well; a high-voltage charge pump; a switch
transistor circuit with two discreet outputs coupled to the first
well and the second well that switches between high-voltage from
the high-voltage charge pump and power supply voltage; a clock
circuit to controls the switch transistor circuit.
25. The system of claim 24, wherein the first well is a n-type well
and the second well is a p-type well.
26. The system of claim 24 wherein the first well is a p-type
well.
27. The system of claim 24, wherein the clock circuit is optimized
to reduce snap-back caused by erasing and programming operations.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 11/190,722, filed Jul. 27, 2005, the specification of which is
herein incorporated by reference.
TECHNICAL FIELD
[0002] The invention relates to non-volatile memory transistors
and, in particular, to a post-erase channel clearing procedure for
double well non-volatile memory transistors in a flash array memory
architecture.
BACKGROUND ART
[0003] Well voltage control after an erase operation in
non-volatile memory transistors is important for preventing
latchup, a condition that prevents useful operation. Generally,
latchup occurs due to the presence of parasitic PN junctions,
particularly when the junctions form parasitic NPN and PNP bipolar
transistors. Typically a parasitic transistor is a vertical
transistor formed in subsurface wells. When two parasitic
transistors interact, the second one often a lateral transistor,
latchup occurs. An anti-latchup invention is described in U.S. Pat.
No. 6,549,465 to Y. Hirano et al. In the patent, a well voltage
setting circuit has a P-MOS transistor for applying an erase pulse,
a first N-MOS transistor for applying a reference voltage Vss to a
P-well in a shutdown sequence after erase pulse application, and a
second N-MOS transistor for forcing the P-well to a reference
voltage during write and read. The first N-MOS transistor has a
driving capacity set to about 1/50 of that of the second N-MOS
transistor, so that a time for forcing the P-well to the reference
voltage is long enough to prevent occurrence of local latchup
during erase.
[0004] In flash memory arrays, the channel clearing operation after
a flash erase has been known to employ a special discharge circuit.
Such a discharge circuit is described in published U.S. Patent
Application US2004/0184321 and U.S. Pat. No. 6,714,458, both to S.
Gualandri et al. These documents describe an erase discharge
circuit in a flash that is coupled to an array source and a P-well
bias signal and receives first and second discharge signals. The
erase discharge circuit operates during a discharge cycle in a
first mode in response to the first discharge signal to couple the
first node to the second node and to discharge voltages on the
first and second nodes at a first rate. The erase discharge circuit
operates in a second mode in response to the second discharge
signal to couple the first node to the second node to discharge the
voltages on the first and second nodes at a second rate.
[0005] In memory devices having a P-well within a deep N-well, the
channel clearing operation after an erase can present a special
challenge. For example, see U.S. Pat. No. 6,667,910 to Abedifard et
al. This patent describes a flash memory device in which an erase
voltage is applied to a well containing flash memory transistors.
The well is then discharged toward ground, first by one discharge
circuit which discharges the well until the voltage on the well is
lower than a snap-back characteristic of a transistor employed in
another well discharge circuit. After the well voltage is below the
snap-back characteristic of the transistor, the well is discharged
by the other discharge circuit.
[0006] The existence of a subsurface parasitic p-n junction in
double well devices gives rise to special concerns. Forward bias on
a vertical parasitic junction can cause device latchup. On the
other hand, channel clearing voltages creating forward bias
conditions are needed after erase pulses. An object of the
invention is to devise a channel clearing bias scheme after an
erase pulse which avoids forward bias conditions in parasitic p-n
junctions formed by vertical subsurface wells.
SUMMARY
[0007] The above object has been achieved by following an erase
operation with a two-stage channel clearing operation in a vertical
double well device, i.e., having for example a P-well in a deep
N-well. In the first stage the same or approximately the same
(within 0.1 volts) high voltage on the deep well used for erase is
maintained for channel clearing. This strongly attracts charged
particles out of the channel. The shallow well within the deep well
is at the same potential so that the deep well and shallow well are
essentially reverse biased to prevent current flow due to the
parasitic diode formed by the two wells. After an instant, the high
voltage on the deep well is switched to Vcc, or an intermediate
voltage, and the shallow well is grounded, to allow charged
particles to continue to move toward the deep well and to a high
capacity shorting supply, while relaxing any demand on the high
voltage supply. The channel clearing method of the present
invention is implemented with high voltage supplies of positive and
negative (first and second) polarities regularly found in memory
cells.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a sectional plan view of a double well
non-volatile memory transistor with program bias in accordance with
the present invention.
[0009] FIG. 2 is a sectional plan view of the device of FIG. 1 with
erase and discharge bias available in accordance with the present
invention.
[0010] FIG. 3 is a schematic view of a portion of a memory array
with memory transistors having bias lines to apply bias as shown in
FIG. 2.
[0011] FIG. 4 is a top view of an integrated circuit package
containing a memory array, as in FIG. 3, having pins for bias
voltages as shown in FIGS. 1 and 2.
[0012] FIG. 5 is a time versus voltage chart for operating the
apparatus of FIGS. 1 and 2.
DETAILED DESCRIPTION
[0013] With reference to FIG. 1, a non-volatile memory cell 11,
typically an EEPROM (electrically erasable programmable read only
memory) transistor, is constructed within a silicon wafer or
substrate 17, shown as a p-type substrate. Within this substrate
the memory cell 11, an EEPROM device, is built within an active
region defined by a field oxide FO.sub.x boundary 13. The substrate
has a surface 15, with portions of the device above the surface and
portions below.
[0014] Below surface 15, a deep N-well 21 is established in
substrate 17, overlapping with the field oxide boundaries FO.sub.x
13 across the entire subsurface regions of the device, by
implantation or diffusion of n-type ionic impurities in a known
manner. After N-well 21 is established a less deep P-well 23 is
established within the upper half, more or less, of the deep N-well
21. The P-well 23 extends from surface 15 downwardly to about
one-half of the depth of the N-well 21 and from one field oxide
boundary to the other. Building of a P-well within an N-well,
within a p-substrate, is well known in EEPROM manufacturing. Within
the P-well 23, a first and a second n+ ion implant 25 and 27 will
serve as source and drain electrodes, with both the source and
drain electrodes below surface 15, but with one electrode having an
available bias lead 37, know as V.sub.DS.
[0015] Above surface 15 the conductive floating gate 31, typically
made from a layer of polysilicon, is situated roughly aligned with
the interior edges of source and drain 25 and 27, or sometimes
overlapping somewhat with the source and drain. Above the floating
gate is control gate 33, also made from a layer of polysilicon and
having the same dimensions as the control gate. The control gate is
insulatively spaced over the floating gate, just as the floating
gate is insulatively spaced over the surface 15 of the P-well 23,
with insulation usually supplied by a silicon dioxide layer. While
the floating gate 31 has no electrical contacts, the control gate
is connected to a first bias supply 41 that is electrically
grounded on the negative side to ground 35 and connected to a
switch 43, typically a transistor, on the positive side, typically
at positive ten volts in the programming mode, leading to a bias
line or gate lead 45, known as Vgate. The charging and discharging
of the floating gate are by known mechanisms, such as
Fowler-Nordheim tunneling, or hot electron tunneling. In the
programming mode, electrons are drawn from one subsurface electrode
25 or 27, onto the floating gate by tunneling action. The floating
gate remains charged as an indication of the programmed state of
the device until erased.
[0016] A second bias supply 47 has a negative side connected to
ground lead 51 and a positive side, at about positive 1.8 (VDD)
volts, connected to switch 49 and hence to the deep N-well lead 53.
A third bias supply 55 has a positive side connected to switch 57
that is, in turn, connected to P-well lead 59, at about 0 volts and
a negative side connected to ground lead 61. By maintaining these
two regions at reverse electrical potential during a program
operation there is no forward bias across the p-n junction that
would cause a subsurface current to flow. Such subsurface currents
lead to latchup, a condition that prevents proper memory cell
conduction when the device is read.
[0017] The device of FIG. 2 is essentially the same device as in
FIG. 1, except that bias configurations have been changed for erase
and discharge operations. Voltage polarities are different and
different voltage levels are available at each connection though
double pole switches. The V.sub.gate lead 45 has the double pole
switch 43, a transistor switch in actuality, connected to bias
supply 41 which is now supplying negative 10 volts relative to the
ground lead 35 during erase operations. Of particular importance,
the P-well 23 has positive bias at +10 volts from bias supply 83
acting through the double pole switch 87 relative to ground 85 at
the same time as negative bias is applied to control gate 33 from
supply 41. The double pole switch 87 is a transistor switch. The
positive bias on the P-well pulls electrons from the floating gate
31 and partially clears the channel immediately below the floating
gate. At the same time, the deep N-well 21 is biased by a 10 volt
10V supply 79 having its negative terminal coupled to a ground 81
and acting through the double pole switch 75 to place a positive
bias at +10 volts on the deep N-well. The drain and source are
allowed to float, being pulled up to the P-well voltage of +10
volts. The +10 volt voltages on both the deep N-well 21 and the
P-well 23 are an effective reverse bias on the parasitic P-N
junction between these two regions, preventing conduction, as well
as being an effective reverse bias relative to ground 20 for the
parasitic P-N junction between the deep N-well 21 and the P
substrate 17. Subsurface currents in these parasitic P-N junctions
might occur without such reverse bias and such currents could cause
device latchup by preventing proper transistor action.
[0018] To complete the erase operation it is necessary to clear the
channel of electrons. To accomplish this, the control gate is
grounded at ground 71 through switch 41 and just before the P-well
23 is grounded at ground 30. The deep N-well 21 is still biased at
+10 volts, but after a time, T, the deep N-well is discharged to
VDD using supply 73, acting through switch 75 and having its
negative terminal coupled to a ground 77. The time T is a time
shorter than the time before another possible program operation by
at least one-half of a cycle. The shift or lowering of the voltage
in the deep N-well allows current flow in the parasitic diode
formed between the P-well and the deep N-well but in a controlled
manner, preventing excess electrons from being trapped in the
P-well 23. Vcc is the usual bias voltage used in sense amplifiers
and other auxiliary memory transistors.
[0019] With reference to FIG. 3, a portion of a flash memory array
101 is shown having rows and columns of memory cells. For example,
EEPROM transistors 103 and 105 are shown in a first column and
EEPROM transistors 107 and 109 are shown in a second column. Each
of the memory transistors has P-well and deep N-well bias lines.
For example, the P-well bias line 117 is provides simultaneous bias
to all memory cells in the array and the deep N-well bias line 119,
parallel to line 117, also provides simultaneous bias to all memory
cells in the array. The parallel bit line BL0 111, associated with
V.sub.DS line 37 and the parallel bit line BL1 121, associated with
a similar V.sub.DS line, together with the parallel word lines WL1
113 and WL2 115, and the chip select C/S line 123, serve to provide
transistor selection voltages so that each individual transistor
can be addressed for programming and reading, but all transistors
are simultaneously erased and discharged.
[0020] FIG. 4 shows a packaged flash memory array chip 131 with
various external bias voltages applied to the chip including Vcc,
+10 volts, -10 volts and ground. These are the fundamental voltages
supplied to the chip. All other voltages can be obtained from
these. Word line WL and bit line BL voltages can be from a separate
supply or may be derived from other voltages. Similarly the P-well
and the deep N-well voltages can be from a separate supply or may
be derived from other voltages already present.
[0021] With reference to FIG. 5, a three-stage erase operation is
shown. Programming occurs at a time, T0, where a first voltage is
applied to the device of FIG. 1, labeled PROGRAM, showing +10 volts
on control gate 33, approximately 0 volts on P-well 23 and VTD on
N-well 21. VDD is close to 0 volts within a volt or two. An erase
cycle is commenced at a time T1 where a voltage labeled DISCHARGE
FLOATING GATE shows application of -10 bolts on control gate 33 and
+10 volts on both N-well 21 and P-well 23. Down arrow 2 or 3 is
illustrative of this voltage. At a later time, T2, a switch applies
new voltages to the device and the control gate, formerly at +10
volts is switched to ground 31 but the deep N-well is till biased
at +10 volts, indicated by arrow 207. This is a channel clearing
operation after the switch, indicated by line 205 as shown. After a
time T, the deep N-well is discharged at time T3 to voltage VDD,
indicated by arrow 209. The time T is shorter than the time for the
next memory operation, a programming operation which occurs at a
time T4 since memory operations are sequential program and erase
operations.
* * * * *