U.S. patent application number 12/020598 was filed with the patent office on 2008-10-23 for semiconductor structure of a display device and method for fabricating the same.
This patent application is currently assigned to AU OPTRONICS CORP.. Invention is credited to Yu-Cheng Chen.
Application Number | 20080258196 12/020598 |
Document ID | / |
Family ID | 39871327 |
Filed Date | 2008-10-23 |
United States Patent
Application |
20080258196 |
Kind Code |
A1 |
Chen; Yu-Cheng |
October 23, 2008 |
SEMICONDUCTOR STRUCTURE OF A DISPLAY DEVICE AND METHOD FOR
FABRICATING THE SAME
Abstract
A semiconductor structure of a display device and the method for
fabricating the same are provided. The semiconductor structure is
formed on a substrate having a TFT region and a pixel capacitor
region thereon. A TFT, including a gate electrode, a source
electrode, a drain electrode, a channel layer, and a gate
insulating layer, is formed on the TFT region of the substrate. A
pixel capacitor is formed on the pixel capacitor region, wherein
the pixel capacitor comprises a bottom electrode formed on a bottom
dielectric layer, an interlayer dielectric layer formed on the
bottom electrode, a top electrode formed on the interlayer
dielectric layer, a contact plug passing through the interlayer
dielectric layer and electrically connected to the top and bottom
electrodes, a capacitor dielectric layer formed on the top
electrode, a transparent electrode formed on the capacitor
dielectric layer and electrically connected to the drain
electrode.
Inventors: |
Chen; Yu-Cheng; (Hsinchu,
TW) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
600 GALLERIA PARKWAY, S.E., STE 1500
ATLANTA
GA
30339-5994
US
|
Assignee: |
AU OPTRONICS CORP.
Hsinchu
TW
|
Family ID: |
39871327 |
Appl. No.: |
12/020598 |
Filed: |
January 28, 2008 |
Current U.S.
Class: |
257/296 ;
257/535; 257/E21.008; 257/E21.411; 257/E27.111; 257/E27.113;
257/E29.273; 257/E29.343; 438/155 |
Current CPC
Class: |
G02F 1/136213 20130101;
H01L 27/1255 20130101; H01L 27/1248 20130101 |
Class at
Publication: |
257/296 ;
438/155; 257/535; 257/E29.273; 257/E29.343; 257/E21.411;
257/E21.008 |
International
Class: |
H01L 29/786 20060101
H01L029/786; H01L 21/336 20060101 H01L021/336; H01L 29/92 20060101
H01L029/92 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 20, 2007 |
TW |
96114024 |
Claims
1. A method for fabricating a semiconductor structure of a display
device, comprising: providing a substrate with a thin film
transistor region and a pixel capacitor region; forming a first
semiconductor layer on the thin film transistor region of the
substrate; forming a gate dielectric layer on the substrate;
forming a gate electrode on the gate dielectric layer within the
thin film transistor region and a bottom electrode on the gate
dielectric layer within the pixel capacitor region; performing a
heavily doped ion implantation on the first semiconductor layer to
form a source electrode and a drain electrode, wherein the undoped
first semiconductor layer defines as a channel region; forming an
interlayer dielectric layer on the substrate; forming first and
second contact holes respectively exposing the source electrode and
the drain electrode and a third contact hole exposing the bottom
electrode; forming a source electrode plug and a drain electrode
plug passing through the first and second contact holes to
electrically contact to the source electrode and the drain
electrode, respectively; forming a top electrode electrically
contacted to the bottom electrode via the third contact hole;
sequentially forming a capacitor dielectric layer and a
planarization layer on the substrate; patterning the capacitor
dielectric layer and the planarization layer to form a fourth
contact hole passing through the capacitor dielectric layer and the
planarization layer exposing the drain electrode plug and an
opening passing through the planarization layer exposing the
capacitor dielectric layer directly over the top electrode; and
forming a pixel electrode filled in the fourth contact hole and the
opening and electrically connected to t he drain electrode.
2. The method as claimed in claim 1, wherein the top electrode and
bottom electrode comprises a first capacitor electrode.
3. The method as claimed in claim 1, wherein the steps for forming
the first semiconductor layer on the thin film transistor region of
the substrate further comprises: simultaneously forming a second
semiconductor layer on the pixel capacitor region of the
substrate.
4. The method as claimed in claim 3, wherein the second
semiconductor layer and the pixel electrode comprises a second
capacitor electrode.
5. The method as claimed in claim 3. after forming a second
semiconductor layer further comprising: performing a heavily doped
ion implantation on the second semiconductor layer.
6. The method as claimed in claim 3, wherein the first
semiconductor layer electrically connects to the second
semiconductor layer.
7. The method as claimed in claim 3, wherein the first and second
semiconductor layers are of the same material and formed by the
same process.
8. The method as claimed in claim 3, wherein the first and second
semiconductor layers are simultaneously subjected to heavily doped
ion implantation.
9. The method as claimed in claim 1, further comprising: performing
a lightly doped ion implantation on the first semiconductor layer
to form a lightly doped region.
10. The method as claimed in claim 9, wherein the first
semiconductor layer is subjected to the heavily doped ion
implantation and the lightly doped ion implantation with the gate
electrode serving as a mask.
11. The method as claimed in claim 1, wherein the fourth contact
hole and the opening are formed simultaneously by one
photolithography step.
12. The method as claimed in claim 1, wherein the photolithography
step for forming the fourth contact hole and the opening employs a
halftone mask or Gray-tone mask.
13. The method as claimed in claim 1, wherein the gate electrode
and the bottom electrode are of the same material and formed by the
same process.
14. The method as claimed in claim 1, wherein the source electrode
plug, drain electrode plug, and the top electrode are of the same
material and formed by the same process.
15. A semiconductor structure of display device, comprising: a
substrate with a thin film transistor region and a pixel capacitor
region; a thin film transistor, a source electrode plug and a drain
electrode plug formed on the thin film transistor region of the
substrate, wherein the thin film transistor comprises a gate
electrode, a source electrode, a drain electrode, a channel, and a
gate dielectric layer, and the source electrode plug and the drain
electrode plug electrically connected to the source electrode and
the drain electrode, respectively; a pixel capacitor is formed on
the pixel capacitor region of the substrate, wherein the pixel
capacitor comprises: a bottom electrode formed on a bottom
dielectric layer; an interlayer dielectric layer formed on the
substrate and the bottom electrode; a top electrode formed on the
interlayer dielectric layer, wherein the top electrode electrically
connected to the bottom electrode; a capacitor dielectric layer is
formed on the substrate and the top electrode; and a transparent
electrode formed on the capacitor dielectric layer over the top
electrode and electrically connected to the drain electrode
plug.
16. The semiconductor structure of display device as claimed in
claim 15, further comprising a semiconductor layer on the
substrate, directly under the bottom electrode.
17. The semiconductor structure of display device as claimed in
claim 16, wherein the semiconductor layer is electrically connected
to the drain electrode.
18. The semiconductor structure of display device as claimed in
claim 16, wherein the semiconductor layer comprises a heavily doped
semiconductor layer.
19. The semiconductor structure of display device as claimed in
claim 15, wherein the dielectric layer comprises oxide-containing
silicon, nitride-containing silicon, and a combination thereof.
20. The semiconductor structure of display device as claimed in
claim 15, wherein the transparent electrode comprises ITO, IZO,
AZO, ZnO, GaN, GaInN, CdS, ZnS, CdSe, or ZnSe.
21. The semiconductor structure of display device as claimed in
claim 15, wherein the top electrode and the bottom electrode
comprises Mo, W, Al, Ti, Cr, and combinations thereof.
22. The semiconductor structure of display device as claimed in
claim 15, wherein the gate electrode and the bottom electrode are
of the same material and formed by the same process.
23. The semiconductor structure of display device as claimed in
claim 15, wherein the source electrode plug, the drain electrode
plug and the top electrode are of the same material and formed by
the same process.
24. A pixel structure, comprising: a semiconductor layer formed on
a substrate; a bottom dielectric layer formed on the semiconductor
layer; a bottom electrode formed on the bottom dielectric layer; an
interlayer dielectric layer formed on the bottom electrode; a top
electrode formed on the dielectric layer and electrically connected
to the bottom electrode via a first plug, wherein the first plug
passes through the interlayer dielectric layer; a capacitor
dielectric layer formed on the top electrode; a planarization layer
formed on the capacitor dielectric layer and an opening exposing
the capacitor dielectric layer directly over the top electrode; and
a transparent electrode formed on the capacitor dielectric layer
directly over the top electrode, wherein the transparent electrode
electrically connects to the semiconductor layer via a second
plug.
25. The pixel capacitor structure as claimed in claim 24, wherein
the semiconductor layer comprises a heavily doped semiconductor
layer.
26. The pixel structure as claimed in claim 24, wherein the
dielectric layer comprises oxide-containing silicon,
nitride-containing silicon, and a combination thereof.
27. The pixel structure as claimed in claim 24, wherein the
capacitor dielectric layer comprises oxide-containing silicon,
nitride-containing silicon, and a combination thereof.
28. The pixel structure as claimed in claim 24, wherein the
transparent electrode comprises ITO, IZO, AZO, ZnO, GaN, GaInN,
CdS, ZnS, CdSe, or ZnSe.
29. The pixel structure as claimed in claim 24, wherein the top
electrode and the bottom electrode comprises Mo, W, Al, Ti, Cr, and
combinations thereof.
30. The pixel structure as claimed in claim 24, wherein the bottom
electrode and top electrode comprises a first capacitor
electrode.
31. The pixel structure as claimed in claim 24, wherein the
semiconductor layer and the transparent electrode comprises a
second capacitor electrode.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a display device and method for
fabricating the same and more particularly to a pixel capacitor
structure of a display device and method for fabricating the
same.
[0003] 2. Description of the Related Art
[0004] With increasing resolution of LCDs, it has become important
to increase the aperture ratio of each pixel for improved
performance. To increase the aperture ratio, the plane area of the
storage capacitor must be reduced, and the occupied area of pixel
electrodes must be enlarged as much as possible. Nevertheless, for
TFT-LCD displays, as resolution increases, requirements for
reducing the pixel size and plane area of the storage capacitor
result in problems such as flickering, low color contrast and
cross-talk.
[0005] Accordingly, a new structure capable of increasing storage
capacitance without sacrificing the aperture ratio of a pixel, or
maintaining the storage capacitance while increasing the aperture
ratio of a pixel is desirable.
BRIEF SUMMARY OF THE INVENTION
[0006] An exemplary embodiment a semiconductor structure of a
display device comprises: a substrate with a thin film transistor
region and a pixel capacitor region; a thin film transistor, a
source electrode plug and a drain electrode plug formed on the thin
film transistor region of the substrate, wherein the thin film
transistor comprises a gate electrode, a source electrode, a drain
electrode, a channel, and a gate dielectric layer, and the source
electrode plug and the drain electrode plug electrically connected
to the source electrode and the drain electrode, respectively; and
a pixel capacitor formed on the pixel capacitor region of the
substrate, wherein the pixel capacitor comprises a bottom electrode
formed on a bottom dielectric layer, an interlayer dielectric layer
formed on the substrate and the bottom electrode, a top electrode
formed on the interlayer, dielectric layer, wherein the top
electrode electrically connects to the bottom electrode, a
capacitor dielectric layer formed on the substrate and the top
electrode, and a transparent electrode formed on the capacitor
dielectric layer over the top electrode and electrically connected
to the drain electrode plug.
[0007] According to another embodiment of the invention, a pixel
capacitor structure comprises: a semiconductor layer formed on a
substrate; a bottom dielectric layer formed on the semiconductor
layer; a bottom electrode formed on the bottom dielectric layer; an
interlayer dielectric layer formed on the bottom electrode; a top
electrode formed on the dielectric layer and electrically connected
to the bottom electrode via a first plug, wherein the first plug
passes through the interlayer dielectric layer; a capacitor
dielectric layer formed on the top electrode; a planarization layer
formed on the capacitor dielectric layer and an opening exposing
the capacitor dielectric layer directly over the top electrode; and
a transparent electrode formed on the capacitor dielectric layer
directly over the top electrode, wherein the transparent electrode
electrically connects to the semiconductor layer via a second
plug.
[0008] Methods for fabricating a semiconductor structure of a
display device are provided. An exemplary embodiment of a method
for fabricating the semiconductor structure of the display device
comprises: providing a substrate with a thin film transistor region
and a pixel capacitor region; forming a first semiconductor layer
on the thin film transistor region of the substrate; forming a gate
dielectric layer on the substrate; forming a gate electrode on the
gate dielectric layer within the thin film transistor region and a
bottom electrode on the gate dielectric layer within the pixel
capacitor region; performing a heavily doped ion implantation on
the first semiconductor layer to form a source electrode and a
drain electrode, and performing a light doped ion implantation on
the first semiconductor layer to form a light doped region, wherein
the undoped first semiconductor layer is defined as a channel
region; forming an interlayer dielectric layer on the substrate,
forming; first and second contact holes respectively exposing the
source electrode and the drain electrode and a third contact hole
exposing the bottom electrode; forming a source electrode plug and
a drain electrode plug passing through the first and second contact
holes to electrically contact the source electrode and the drain
electrode, respectively; forming a top electrode electrically
contacted to the bottom electrode via the third contact hole;
sequentially forming a capacitor dielectric layer and a
planarization layer on the substrate; patterning the capacitor
dielectric layer and the planarization layer to form a fourth
contact hole passing through the capacitor dielectric layer and the
planarization layer exposing the drain electrode plug and an
opening passing through the planarization layer exposing the
capacitor dielectric layer directly over the top electrode; and
forming a pixel electrode filled the fourth contact hole and the
opening and electrically connected to the drain electrode.
[0009] A detailed description is given in the following embodiments
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The invention can be more fully understood by reading the
subsequent detailed description and examples with references made
to the accompanying drawings, wherein:
[0011] FIGS. 1a-1i are sectional diagrams of the method for
fabricating a semiconductor structure of display device according
to an embodiment of the invention.
[0012] FIG. 2 is a sectional diagram of a semiconductor structure
of a display device according to another embodiment of the
invention.
[0013] FIG. 3 is a sectional diagram of a semiconductor structure
of a display device according to yet another embodiment of the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] The following description is of the best-contemplated mode
of carrying out the invention. This description is made for the
purpose of illustrating the general principles of the invention and
should not be taken in a limiting sense. The scope of the invention
is best determined by reference to the appended claims.
[0015] FIGS. 1a to 1i show the steps of a method for fabricating a
semiconductor structure of a display device according to an
embodiment of the invention.
[0016] First, referring to FIG. 1a, a substrate 10 with thin film
transistor region 12 and a pixel capacitor region 14 is provided.
The substrate 10 can be transparent substrate, such as glass
substrate or plastic substrate. The substrate 10 has a first
semiconductor layer 16 on the thin film transistor region 12 and a
second semiconductor layer 18 on the pixel capacitor region 14. The
first semiconductor layer 16 and the second semiconductor layer 18
can be of the same material and formed by the same process.
Suitable materials of the first and second semiconductor layers can
be polycrystalline silicon or amorphous silicon.
[0017] Next, referring to FIG. 1b, a heavily doped ion implantation
is performed to the first semiconductor layer 16 to form a source
electrode (heavily doped region) 21, a drain electrode (heavily
doped region) 22. Next, a gate dielectric layer 27 (bottom
dielectric layer) is blanketly formed on the substrate 10, and a
gate electrode 28 is formed on the gate dielectric layer 27 over a
channel region. It should be noted that the plane area of the gate
electrode 28 is smaller than that of the channel region 20. A
conductive layer is formed on the gate dielectric layer 27 of the
pixel capacitor region 14, serving as a bottom electrode 29. Next,
a lightly doped ion implantation is performed to the first
semiconductor layer 16 to form lightly doped regions 23. Further,
when performing the heavily doped ion implantation on the first
semiconductor layer 16, the second semiconductor layer 18 is
simultaneously subjected to the heavily doped ion implantation to
form a heavily doped semiconductor layer 25. In an embodiment of
the invention, the source electrode 21, the drain electrode 22, and
the heavily doped semiconductor layer 25 are formed by heavily
doped ion implantation with one photo-mask. The lightly doped
regions 23 are formed by lightly doped ion implantation with the
gate electrode 28 serving as a mask.
[0018] Further, in another embodiment of the invention, the source
electrode 21 and drain electrode 22 can be formed by heavily doped
ion implantation with the gate electrode 28 as mask. After
performing the heavily doped ion implantation, the gate electrode
28 is etched to be reduced and the first semiconductor layer is
subjected to a lightly doped ion implantation with the reduced gate
electrode 28 serving as a mask. The gate electrode 28 and the
bottom electrode 29 are of the same material and formed by the same
process. Suitable materials of the gate electrode 28 and the bottom
electrode 29 can be Mo, W, Al, Ti, Cr, and combinations thereof.
The gate dielectric layer 27 comprises a dielectric layer, with a
material such as silicon oxide, with a thickness between 50
nm.about.200 nm, for example 100 mn.
[0019] Next, referring to FIG. 1c, an interlayer dielectric layer
30 is blanketly formed on the substrate 10. The interlayer
dielectric layer 30 can comprise a first dielectric layer 31 and a
second dielectric layer 32, wherein the first dielectric layer 31
can be silicon oxide or silicon nitride with a thickness between 50
nm to 300 nm, and the second dielectric layer 32 can silicon oxide
or silicon nitride with a thickness between 50 nm to 300 nm.
[0020] Next, referring to FIG. 1d, the interlayer dielectric layer
30 and the gate dielectric layer 27 are patterned to form a first
contact hole 41 and a second contact hole 42 passing through the
interlayer dielectric layer 30 and the gate dielectric layer 27
respectively exposing the source electrode 21 and the drain
electrode 22, and a third contact hole 43 passing through the
dielectric layer 30 exposing the surface of the bottom electrode
29.
[0021] Next, referring to FIG. 1e, a conductive layer (not shown)
is formed on the substrate 10 and fills the first contact hole 41,
the second contact hole 42, and the third contact hole 43. Next,
the conductive layer is patterned to form a source line (not
shown), a source electrode plug 44 and a drain electrode plug 45,
respectively, electrically connected to the source electrode 21 and
drain electrode 22 via the first and second contact hole 41 and 42.
A top electrode 46 is simultaneously formed and, electrically
connects through the third contact hole 43 to the bottom electrode
29 via the plug 47. The bottom electrode 29 and the top electrode
46 comprises a first capacitor electrode with a first electric
potential. The top electrode 46 and the bottom electrode 29 can be
the same or different material and comprises Mo (molybdenum), W
(tungsten), Al (aluminum), Ti (titanium), Cr (chromium), alloy, or
multi-layer structure thereof.
[0022] Next, referring to FIG. 1f, a capacitor dielectric layer 50
and a planarization layer 55 are formed on the substrate 10. The
capacitor dielectric layer 50 can be dielectric material, such as
oxide-containing silicon, nitride-containing silicon, or
multi-layer structure with a thickness between 50 nm to 200 nm, for
example 100 nm. The planarization layer 55 can be organic material,
such as polymer material, with a thickness of 2000 nm.about.4000 nm
and formed by spin-coating, printing or screen printing.
[0023] Next, referring to FIG. 1g, the planarization layer 55 is
patterned by a photo-mask to form a fourth contact hole 61 over the
drain electrode plug 45 and a first opening 62 over the top
electrode 46. It should be noted that the patterned planarization
layer 55 has different thicknesses. The planarization layer 55 over
the drain electrode plug 45 is completely removed to form a contact
hole 61 exposing the capacitor dielectric layer 50 over the drain
electrode plug 45. The unpatterned planarization layer 55 has a
first thickness t1. The planarization layer 55 on the top electrode
46 is partially removed to remain a planarization layer 56 with a
second thickness t2. Herein, the first thickness t1 can be between
2000 nm.about.4000 nm, and the second thickness t2 can be 200
nm.about.500 nm. The photo-mask for forming the fourth contact hole
61 and the first opening 62 can be a halftone mask or Gray-tone
mask.
[0024] Next, referring to FIG. 1h, the capacitor dielectric layer
50 and the planarization layer 55 are etched by anisotropic etching
with the patterned planarization layer 55 serving as a mask,
forming a fifth contact hole 71 passing through the capacitor
dielectric layer 50 and the planarization layer 55 exposing the
drain electrode plug 45, and a second opening 72 passing through
the planarization layer 55 exposing the surface 73 of the capacitor
dielectric layer 50 formed on the top electrode 46. The
planarization layer 56 with the second thickness t2 can be removed
during the anisotropic etching procedure, and the planarization
layer 55 with the first thickness can be etched so that the
planarization layer 55' on the capacitor dielectric layer 50
outside the fifth contact hole 71 and the second opening 72
remains.
[0025] Finally, referring to FIG. 1i, a transparent conductive
layer is formed on the capacitor dielectric layer 50 and filled
into the fifth contact hole 71 and the second opening 72, serving
as pixel electrode 80, thus fabrication of a semiconductor
structure of a display device with high capacity storage is
completed, requiring at least six photolithography steps according
to the embodiment. Specifically, the pixel electrode 80 is
electrically connected to the drain electrode 22 via the drain
electrode plug 45. It should be noted that the pixel electrode 80
formed in the second opening 72 and the heavily doped second
semiconductor layer 25 comprises a second capacitor electrode with
a second electrical potential. The transparent electrode can
comprise ITO (indium tin oxide), IZO (indium zinc oxide), AZO
(aluminum zinc oxide), ZnO (zinc oxide), GaN (gallium nitride),
GaInN (gallium indium nitride), CdS (cadmium sulfide), ZnS (zinc
sulfide), CdSe (cadmium selenide), or ZnSe (zinc selenide).
[0026] Still referring to FIG. 1i, the pixel capacitor of the
invention can comprise: a second semiconductor layer 25 formed on
the substrate 10; a bottom dielectric layer (gate dielectric layer)
27 formed on the second semiconductor layer 27; a bottom electrode
29 formed on the bottom dielectric layer 27; an interlayer
dielectric layer 30 formed on the bottom electrode 29; a plug 47
passing through the dielectric layer 30 and contact to bottom
electrode 29; a top electrode 46 formed on the dielectric layer 30
and electrically connected to the bottom electrode 29 via the plug
47; the capacitor dielectric layer 50 formed on the top electrode
46; the planarization layer 55 formed on the capacitor dielectric
layer 50 with a second opening 72 exposing the capacitor dielectric
layer 50 directly over the top electrode 46; and the transparent
electrode 80 formed on the capacitor dielectric layer 50 over the
top electrode 46, wherein the transparent electrode 80 electrically
connects to the drain electrode 22 and the second semiconductor
layer 25 via the drain electrode plug 45.
[0027] It should be noted that the pixel capacitor comprises a
pixel electrode, thereby increasing the capacity storage without
reducing the area of the display area (pixel electrode area).
Further, the first capacitor electrode and the second capacitor
electrode comprise two capacitors in different locations.
Therefore, the capacity storage can be increased and the aperture
rate of the pixel electrode can be kept. Moreover, a heavily doped
semiconductor layer can be simultaneously formed to increase
capacity storage of the capacitor when forming the source electrode
and drain electrode by heavily doped ion implantation.
[0028] According to another embodiment of the invention, referring
to FIG. 2, the second semiconductor layer can also be an undoped
semiconductor layer 33, and the thickness and material of the
capacitor dielectric layer 50 can be modified to increase capacity
storage. Further, according to yet another embodiment of the
invention, referring to FIG. 3, the pixel capacitor can also only
consist of the top electrode 46 and the pixel electrode 80, and the
thickness and material of the capacitor dielectric layer 50 can be
modified to increase capacity storage.
[0029] While the invention has been described by way of example and
in terms of preferred embodiment, it is to be understood that the
invention is not limited thereto. To the contrary, it is intended
to cover various modifications and similar arrangements (as would
be apparent to those skilled in the art). Therefore, the scope of
the appended claims should be accorded the broadest interpretation
so as to encompass all such modifications and similar
arrangements.
* * * * *