U.S. patent application number 12/007243 was filed with the patent office on 2008-10-23 for method of manufacturing printed circuit board for semiconductor package.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Dong Gi An, Mi Jung Han, Kyung Jin Heo, Going Sik Kim, Yang Je Lee, Young Kyu Lim.
Application Number | 20080257742 12/007243 |
Document ID | / |
Family ID | 39649389 |
Filed Date | 2008-10-23 |
United States Patent
Application |
20080257742 |
Kind Code |
A1 |
Lee; Yang Je ; et
al. |
October 23, 2008 |
Method of manufacturing printed circuit board for semiconductor
package
Abstract
Disclosed is a method of manufacturing a printed circuit board
for a semiconductor package, which minimizes or completely obviates
masking work upon the plating of each pad for the surface treatment
of a printed circuit board for a semiconductor package, thereby
simplifying the overall process and increasing the mounting
reliability.
Inventors: |
Lee; Yang Je;
(Chungcheongbuk-do, KR) ; Kim; Going Sik; (Busan
I, KR) ; An; Dong Gi; (Gyeongsangnam-do, KR) ;
Han; Mi Jung; (Gyunggi-do, KR) ; Heo; Kyung Jin;
(Busan, KR) ; Lim; Young Kyu; (Busan, KR) |
Correspondence
Address: |
STAAS & HALSEY LLP
SUITE 700, 1201 NEW YORK AVENUE, N.W.
WASHINGTON
DC
20005
US
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
39649389 |
Appl. No.: |
12/007243 |
Filed: |
January 8, 2008 |
Current U.S.
Class: |
205/126 |
Current CPC
Class: |
H01L 21/4846 20130101;
H05K 3/243 20130101; H05K 2203/0723 20130101; H01L 2924/00
20130101; H05K 3/244 20130101; H01L 2924/0002 20130101; H01L
2924/0002 20130101; H05K 2201/0391 20130101; H05K 2203/072
20130101 |
Class at
Publication: |
205/126 |
International
Class: |
C25D 5/02 20060101
C25D005/02 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 18, 2007 |
KR |
10-2007-0037892 |
Claims
1. A method of manufacturing a printed circuit board for a
semiconductor package, comprising: (a) providing a printed circuit
board for a package, including wire bonding pads and surface mount
device mounting pads and having a predetermined circuit pattern;
(b) forming a solder resist layer on a portion of the printed
circuit board, other than the wire bonding pads and the surface
mount device mounting pads; (c) forming an electroless nickel
immersion gold layer, composed of an electroless nickel plating
layer and an electroless gold plating layer, on each of the wire
bonding pads and surface mount device mounting pads, through
electroless nickel plating and electroless gold plating; and (d)
forming a gold electroplating layer on the electroless nickel
immersion gold layer of the surface mount device mounting pad to
which a plating lead wire is connected, among the surface mount
device mounting pads, and the electroless nickel immersion gold
layer of each of the wire bonding pads, through gold
electroplating.
2. The method as set forth in claim 1, wherein the electroless gold
plating layer of the electroless nickel immersion gold layer has a
thickness ranging from 0.01 .mu.m to 0.1 .mu.m.
3. The method as set forth in claim 1, wherein the electroless
nickel plating layer of the electroless nickel immersion gold layer
has a thickness ranging from 0.3 .mu.m to 15 .mu.m.
4. The method as set forth in claim 1, wherein the gold
electroplating layer has a thickness ranging from 0.1 .mu.m to 1.0
.mu.m.
5. A method of manufacturing a printed circuit board for a
semiconductor package, comprising: (a) providing a printed circuit
board for a package, including wire bonding pads, surface mount
device mounting pads and ZIF connector pads and having a
predetermined circuit pattern; (b) forming a solder resist layer on
a portion of the printed circuit board, other than the wire bonding
pads, the surface mount device mounting pads, and the ZIF connector
pad; (c) applying a plating resist on a portion of the printed
circuit board, other than the wire bonding pads and the surface
mount device mounting pads; (d) forming an electroless nickel
immersion gold layer, composed of an electroless nickel plating
layer and an electroless gold plating layer, on each of the wire
bonding pads and surface mount device mounting pads, through
electroless nickel plating and electroless gold plating; (e)
removing the plating resist; and (f) forming a gold electroplating
layer on the electroless nickel immersion gold layer of the surface
mount device mounting pad to which a plating lead wire is
connected, among the surface mount device mounting pads, the
electroless nickel immersion gold layer of each of the wire bonding
pads, and the ZIF connector pad, through gold electroplating.
6. The method as set forth in claim 5, wherein the electroless gold
plating layer of the electroless nickel immersion gold layer has a
thickness ranging from 0.01 .mu.m to 0.1 .mu.m.
7. The method as set forth in claim 5, wherein the electroless
nickel plating layer of the electroless nickel immersion gold layer
has a thickness ranging from 0.3 .mu.m to 15 .mu.m.
8. The method as set forth in claim 5, wherein the gold
electroplating layer has a thickness ranging from 0.1 .mu.m to 1.0
.mu.m.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of Korean Patent
Application No. 10-2007-0037892, filed Apr. 18, 2007, entitled
"Method for manufacturing printed circuit board for semi-conductor
package", which is hereby incorporated by reference in its entirety
into this application.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates, in general, to a method of
manufacturing a printed circuit board (PCB) for a semiconductor
package. More particularly, the present invention relates to a
method of manufacturing a PCB for a semiconductor package, which
minimizes masking work upon the plating of each pad for the surface
treatment of a PCB for a semiconductor package.
[0004] 2. Description of the Related Art
[0005] Generally, semiconductor packaging is a technique having a
great influence on the proliferation of electronic hardware systems
composed of active devices (e.g., semiconductor chips) and passive
devices (e.g., resistors, condensers, etc.), and the packaging
technique is responsible for power supply, signal connection, heat
emission, and protection from the outside.
[0006] Because the packaging technique is developed to satisfy
various purposes, including power supply, signal connection, and
heat emission, while the package is operated in a state of being
exposed to the surrounding environment, the price of products is
increased, undesirably making it difficult to realize the
commercialization thereof.
[0007] The international demand for semiconductor packages is
increasing according to the advancement of electronic products, and
in particular, the popularity of packages, such as CSP, used for
notebook PCs, mobile phones, mobile data facsimile devices, disk
drivers, etc., is growing.
[0008] In the PCB for a semiconductor package, when a single
substrate is provided with a wire bonding pad and a pad for
mounting an SMD (Surface Mount Device), such as BGA, soft gold
electroplating for wire bonding is applied to the wire bonding pad,
and furthermore, in the case of the BGA mounting pad, electroless
OSP or electroless plating (ENIG: Electroless Nickel Immersion
Gold) is applied if it is difficult to withdraw a lead wire for
electroplating.
[0009] Depending on the increase in the density of the substrate
for a semiconductor package, in the case where two or more
purposes, including wire bonding and SMD mounting, for example,
wire bonding and surface mounting techniques (when it is impossible
to withdraw a lead wire for soft gold electroplating), or a surface
mounting technique and a ZIF connector specification, are required,
surface treatment is performed through different types of plating,
including electroplating and electroless plating.
[0010] In order to conduct the above-mentioned different types of
plating, masking work using a dry film or peelable ink is carried
out. In this case, however, many problems related to the masking
work are caused, including design limitations upon the masking of a
plating resist.
[0011] Below, with reference to FIGS. 3A to 3G, the method of
manufacturing a PCB for a semiconductor package according to a
conventional technique is described.
[0012] According to a widely known method in the art, a PCB 400,
including a resin substrate 401, and wire bonding pads 402, 405 and
SMD mounting pads 403, 404 formed thereon and having a
predetermined circuit pattern, is prepared, and a solder resist
layer 406 is formed on the portion of the PCB 400 other than the
wire bonding pads 402, 405 and the SMD mounting pads 403, 404 (FIG.
3A).
[0013] Subsequently, a first plating resist 407, such as a dry
film, is applied on the portion of the PCB other than the SMD
mounting pads 403, 404, to thus mask it (FIG. 3B), after which
electroless plating and electroplating are typically conducted,
thus forming electroless nickel/gold (ENIG) layers 408, 409 on the
SMD mounting pads 403, 404 (FIG. 3C). As in the ENIG layer 408, an
example of which is shown in FIG. 3C, the ENIG layer is provided in
the form of a double layer including an electroless nickel plating
layer 408a and an electroless gold plating layer 408b.
[0014] The first plating resist 407 is removed (FIG. 3D), and a
second plating resist 410 is applied on the portion of the PCB
other than the wire bonding pads 402, 405, to thus mask it (FIG.
3E). Through typical soft gold electroplating, nickel/gold
electroplating layers 411, 412 are formed on the wire bonding pads
402, 405 (FIG. 3F). As such, as in the nickel/gold electroplating
layer 412 illustrated in this drawing, the nickel/gold
electroplating layer is composed of a double layer including a
nickel electroplating layer 412a and a gold electroplating layer
412b. Finally, the second plating resist 410 is removed, thus
completing surface treatment (FIG. 3G).
[0015] With reference to FIGS. 4A to 4J, the method of
manufacturing a PCB for a semiconductor package according to
another conventional technique is described.
[0016] According to a widely known method in the art, a PCB 500,
including wire bonding pads 503, 506, SMD mounting pads 504, 505,
and ZIF connector pads 507 and having a predetermined circuit
pattern, is prepared. The wire bonding pads 503, 506 and the SMD
mounting pads 504, 505 are formed on a rigid resin substrate 501,
and the ZIF connector pads 507 are formed below the resin substrate
501 with a polyimide coverlay 502 disposed therebetween, in which a
coverlay adhesive 508 is loaded into spaces between the ZIF
connector pads 507. A solder resist layer 509 is formed on the
portion of the PCB 500 other than the wire bonding pads 503, 506,
the SMD mounting pads 504, 505, and the ZIF connector pads 507
(FIG. 4A).
[0017] Subsequently, a first plating resist 510 is applied on the
portion of the PCB other than the SMD mounting pads 504, 505, to
thus mask it (FIG. 4B), after which electroless plating and
electroplating are typically conducted, thus forming ENIG layers
511, 512 on the SMD mounting pads 504, 505 (FIG. 4C). As in the
ENIG layer 511, an example of which is shown in FIG. 4C, the ENIG
layer is provided in the form of a double layer including an
electroless nickel plating layer 511a and an electroless gold
plating layer 511b.
[0018] The first plating resist 510 is removed (FIG. 4D), and a
second plating resist 513 is applied on the portion of the PCB
other than the wire bonding pads 503, 506, to thus mask it (FIG.
4E), after which typical soft gold electroplating is conducted,
thus forming nickel/gold electroplating layers 514, 515 on the wire
bonding pads 503, 506 (FIG. 4F). As such, as in the nickel/gold
electroplating layer 515, illustrated in this drawing, the
nickel/gold electroplating layer is composed of a double layer
including a nickel electroplating layer 515a and a gold
electroplating layer 515b.
[0019] The second plating resist 513 is removed (FIG. 4G), and a
third plating resist 516 is applied on the portion of the PCB other
than the ZIF connector pad 507, to thus mask it (FIG. 4H), after
which typical direct gold electroplating is carried out, thus
forming a gold electroplating layer 517 on the ZIF connector pad
507 (FIG. 4I). The third plating resist 516 is removed, thereby
completing surface treatment (FIG. 4J).
[0020] As mentioned above, the method of manufacturing the PCB for
a semiconductor package according to the conventional techniques
suffers because the masking work should be conducted at least two
or three times when conducting two or three types of plating,
undesirably making it easy for gold plating to be poor in places
due to the penetration of the masking solution, and generating
defects due to the residual plating resist.
[0021] Further, in the case where the plating layer is formed on
the wire bonding pad through electroless soft gold plating, lead
wire problems may be solved, but the wire bonding properties may be
relatively deteriorated. Moreover, the electroless soft gold
plating typically results in poor SMD mounting reliability, and is
also problematic in that the running cost is at least doubled.
SUMMARY OF THE INVENTION
[0022] Leading to the present invention, intensive and extensive
research into avoiding the problems encountered in the related art
resulted in the finding that the surface treatment of a PCB for a
semiconductor package may be conducted in a manner such that ENIG
plating is conducted on both a wire bonding pad and an SMD mounting
pad, after which gold electroplating is performed to thus form a
gold electroplating layer on the wire bonding pad and/or ZIF
connector pad, and only the SMD mounting pad to which a plating
lead wire is connected, thereby minimizing the masking work and
satisfying the properties required for respective pads.
[0023] Accordingly, an aspect of the present invention is to
provide a method of manufacturing a PCB for a semiconductor
package, which is capable of minimizing or completely obviating
masking work in the surface treatment of the PCB for a
semiconductor package.
[0024] Another aspect of the present invention is to provide a
method of manufacturing a PCB for a semiconductor package, which is
capable of economically and efficiently satisfying the respective
properties required for the outermost pads of the PCB for a
semiconductor package.
[0025] According to a preferred embodiment of the present
invention, a method of manufacturing a PCB for a semiconductor
package may include (a) providing a PCB for a package, including
wire bonding pads and SMD mounting pads and having a predetermined
circuit pattern; (b) forming a solder resist layer on the portion
of the PCB, other than the wire bonding pads and the SMD mounting
pads; (c) forming an ENIG layer, composed of an electroless nickel
plating layer and an electroless gold plating layer, on each of the
wire bonding pads and SMD mounting pads, through electroless nickel
plating and electroless gold plating; and (d) forming a gold
electroplating layer on the ENIG layer of the SMD mounting pad to
which a plating lead wire is connected, among the SMD mounting
pads, and the ENIG layer of each of the wire bonding pads, through
gold electroplating.
[0026] In the above method, of the ENIG layer, the electroless gold
plating layer may have a thickness ranging from 0.01 .mu.m to 0.1
.mu.m, and the electroless nickel plating layer may have a
thickness ranging from 0.3 .mu.m to 15 .mu.m.
[0027] The gold electroplating layer may have a thickness ranging
from 0.1 .mu.m to 1.0 .mu.m.
[0028] According to another embodiment of the present invention, a
method of manufacturing a PCB for a semiconductor package may
include (a) providing a PCB for a package, including wire bonding
pads, SMD mounting pads and ZIF connector pads and having a
predetermined circuit pattern; (b) forming a solder resist layer on
the portion of the PCB, other than the wire bonding pads, the SMD
mounting pads, and the ZIF connector pad; (c) applying a plating
resist on the portion of the PCB, other than the wire bonding pads
and the SMD mounting pads; (d) forming an ENIG layer, composed of
an electroless nickel plating layer and an electroless gold plating
layer, on each of the wire bonding pads and SMD mounting pads,
through electroless nickel plating and electroless gold plating;
(d) removing the plating resist; and (e) forming a gold
electroplating layer on the ENIG layer of the SMD mounting pad to
which a plating lead wire is connected, among the SMD mounting
pads, the ENIG layer of each of the wire bonding pads, and the ZIF
connector pad, through gold electroplating.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] FIGS. 1A to 1C are sectional views sequentially illustrating
the process of manufacturing a PCB for a semiconductor package,
according to a first embodiment of the present invention;
[0030] FIGS. 2A to 2E are sectional views sequentially illustrating
the process of manufacturing a PCB for a semiconductor package,
according to a second embodiment of the present invention;
[0031] FIGS. 3A to 3G are sectional views sequentially illustrating
the process of manufacturing a PCB for a semiconductor package,
according to a conventional technique; and
[0032] FIGS. 4A to 4J are sectional views sequentially illustrating
the process of manufacturing a PCB for a semiconductor package,
according to another conventional technique.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0033] Hereinafter, a detailed description will be given of the
present invention, with reference to the appended drawings.
[0034] In FIGS. 1A to 1C, the method of manufacturing a PCB for a
semiconductor package, according to a first embodiment of the
present invention, is schematically illustrated and is described
below.
[0035] According to a widely known method in the art, a PCB 100,
including a resin substrate 101, and wire bonding pads 102, 105 and
SMD mounting pads 103, 104 formed thereon and having a
predetermined circuit pattern, is prepared. In these drawings, the
inner layer structure of the substrate is omitted to simplify the
description, and only a single side thereof is illustratively
shown, but any substrate may be used, without limitation, including
double-sided, single-sided or multilayered BGA or MLB substrates.
As the resin substrate 101, any substrate may be used, without
limitation, including an epoxy resin substrate, a fluorinated resin
substrate, etc., as long as it is known in the art. The material
for the circuit pattern is not particularly limited, as long as it
is conductive metal typically used in the art. Particularly useful
is copper.
[0036] On the portion of the PCB 100 thus prepared, other than wire
bonding pads 102, 105 and the SMD mounting pads 103, 104, a solder
resist is typically applied, cured, and opened, thus forming a
solder resist layer 106 (FIG. 1A). The solder resist is typically
formed of photosensitive material.
[0037] Then, electroless nickel plating and electroless gold
plating are performed, thus forming electroless nickel immersion
gold (ENIG) layers 107, 108, 109, 110 on respective wire bonding
pads 102, 105 and respective SMD mounting pads 103, 104 (FIG. 1B).
As in the ENIG layer 109, enlarged for illustration in FIG. 1B, the
ENIG layer is provided in the form of a double layer including an
electroless nickel plating layer 109a and an electroless gold
plating layer 109b. The thickness of the electroless gold plating
layer of the ENIG layer may range from about 0.01 .mu.m to about
0.1 .mu.m depending on the requirements of efficacy versus economy.
The thickness of the electroless nickel plating layer of the ENIG
layer may range from about 0.3 .mu.m to abut 15 .mu.m, depending on
the requirements of efficacy versus economy.
[0038] Subsequently, gold electroplating is carried out, so that
gold electroplating layers 111, 113, 112 are formed respectively on
the ENIG layers 107, 110 of the wire bonding pads 102, 105 and the
ENIG layer 109 of the SMD mounting pad 104 to which a plating lead
wire is connected (FIG. 1C). That is, both the wire bonding pads
102, 105 are connected with the plating lead wires for
electroplating, and, among the SMD mounting pads, only the SMD
mounting pad 104 is connected with a plating lead wire for
electroplating as needed, thereby enabling gold electroplating to
be conducted via such plating lead wires. Such gold electroplating
may be performed through a plating process called soft gold
electroplating, but nickel plating is omitted because there is no
dissolution behavior of Cu. The gold electroplating layers 111,
112, 113 may have a thickness ranging from about 0.1 .mu.m to about
1.0 .mu.m, depending on the requirements of efficacy versus
economy.
[0039] In this way, the ENIG layers 107, 110 and the gold
electroplating layers 111, 113 are sequentially formed on the wire
bonding pads 102, 105, and the ENIG layer 108 may be formed alone
on the SMD mounting pad 103, or the ENIG layer 109 and the gold
electroplating layer 112 may be formed together on only the SMD
mounting pad 104 having the plating lead wire connected thereto.
Thereby, the plating lead wires may be limitedly designed, and
therefore the degree of freedom of CAD may be increased. Further,
the masking work, which is conventionally conducted two times, is
omitted, thus decreasing the process time, increasing the degree of
freedom of design, and averting various causes of defects occurring
when conducting the masking work. Furthermore, the use of the wire
bonding pad alone advantageously enables the formation of an
alignment mark.
[0040] Turning to FIGS. 2A to 2E, the method of manufacturing a PCB
for a semiconductor package according to a second embodiment of the
present invention is schematically illustrated, and is mentioned
below.
[0041] According to a widely known method in the art, a PCB 300
including wire bonding pads 303, 306, SMD mounting pads 304, 305,
and ZIF connector pads 307 and having a predetermined circuit
pattern, is prepared. The wire bonding pads 303, 306, and SMD
mounting pads 304, 305 are formed on a rigid resin substrate 301,
and the ZIF connector pads 307 are formed below the rigid resin
substrate 301 with a polyimide flexible substrate or a polyimide
coverlay 302 disposed therebetween, in which a coverlay adhesive
308 is loaded into spaces between the ZIF connector pads 307, but
the present invention is not limited thereto.
[0042] In these drawings, the inner layer structure of the
substrate is omitted for simplicity of description, and only a
single side thereof is illustrated, but any substrate may be used,
without limitation, including double-sided, single-sided or
multilayered BGA or MLB substrates. As the resin substrate 301, any
substrate may be used, without limitation, including an epoxy resin
substrate, a fluorinated resin substrate, etc., as long as it is
known in the art. The material for the circuit pattern is not
particularly limited as long as it is conductive metal typically
used in the art. Particularly useful is copper.
[0043] On the portion of the PCB 300 thus prepared, other than the
wire bonding pads 303, 306, the SMD mounting pads 304, 305, and the
ZIF connector pads 307, a solder resist is typically applied, cured
and opened, thus forming a solder resist layer 309 (FIG. 2A). The
solder resist is typically formed of photosensitive material.
[0044] Subsequently, a plating resist 310 is applied on the portion
of the PCB 300 other than the wire bonding pads 303, 306 and the
SMD mounting pads 304, 305, to thus mask it (FIG. 2B). Examples of
the plating resist 310 include, but are not limited to, a dry film,
and peelable ink.
[0045] Subsequently, electroless nickel plating and electroless
gold plating are performed, thus forming ENIG layers 311, 312, 313,
314 on the wire bonding pads 303, 306 and the SMD mounting pads
304, 305 exposed by the plating resist 310 (FIG. 2C). As in the
ENIG layer 312 enlarged for illustration in FIG. 2C, the ENIG layer
is provided in the form of a double layer including an electroless
nickel plating layer 312a and an electroless gold plating layer
312b. The thickness of the electroless gold plating layer of the
ENIG layer may range from about 0.01 .mu.m to about 0.1 .mu.m,
depending on the requirements of efficacy versus economy. The
thickness of the electroless nickel plating layer of the ENIG layer
may range from about 0.3 .mu.m to about 15 .mu.m, depending on the
requirements of efficacy versus economy.
[0046] Subsequently, the plating resist 310 is removed (FIG. 2D),
and direct gold electroplating is performed, thus forming gold
electroplating layers 315, 317, 318, 316 respectively on the ENIG
layers 311, 314 of the wire bonding pads 303, 306, the ZIF
connector pad 307, and the ENIG layer 313 of the SMD mounting pad
305, to which a plating lead wire is connected (FIG. 2E). That is,
all the wire bonding pads 303, 306 and the ZIF connector pad 307
are connected with the plating lead wires for electroplating, and,
among the SMD mounting pads, only the SMD mounting pad 305 is
connected with a plating lead wire for electroplating as needed,
thereby enabling the gold electroplating to be conducted via such
plating lead wires. The gold electroplating may be carried out
through a plating process called direct gold electroplating. The
gold electroplating layers 315, 316, 317, 318 thus formed may have
a thickness ranging from about 0.1 .mu.m to about 1.0 .mu.m,
depending on the requirements of efficacy versus economy.
[0047] In this way, the masking work is conducted once, whereby the
ENIG layers 311, 314 and the gold electroplating layers 315, 317
are formed on the wire bonding pads 303, 306, and the ENIG layer
312 may be formed on the SMD mounting pad 304 alone, or the ENIG
layer 313 and the gold electroplating layer 316 may be formed
together on only the SMD mounting pad 305 having the plating lead
wire connected thereto. Further, only the gold electroplating layer
308 is formed on the ZIF connector pad 307. Thereby, the plating
lead wires may be limitedly designed, thus increasing the degree of
freedom of a CAD. In addition, the masking work, which is
conventionally conducted three times, may be conducted once,
consequently decreasing the process time, increasing the degree of
freedom of design, and averting various causes of defects that
occur when conducting the masking work. Furthermore, the use of the
wire bonding pad alone advantageously enables the formation of an
alignment mark.
[0048] The method of manufacturing the PCB for a semiconductor
package according to the present invention may be applied to image
sensor packages for camera modules, for example, BGA substrates,
including COB (Chip On Board) and SIP (System In Package)
substrates, but the present invention is not limited thereto.
[0049] Although the preferred embodiments of the present invention,
with regard to the method of manufacturing the PCB for a
semiconductor package, have been disclosed for illustrative
purposes, those skilled in the art will appreciate that various
modifications, additions and substitutions are possible within the
technical spirit of the invention.
[0050] As described hereinbefore, the present invention provides a
method of manufacturing a PCB for a semiconductor package.
According to the method of the present invention, high defect
rates, attributable to several rounds of masking work, may be
minimized, and the process time may be decreased.
[0051] The masking work, which is conventionally performed two or
three times in the course of surface treatment, may be completely
omitted or performed once, thereby simplifying the overall process
and improving the mounting reliability.
[0052] Further, the respective properties required for the
outermost pads of the PCB for a semiconductor package may be
economically and efficiently satisfied.
[0053] Simple modifications, additions and substitutions fall
within the scope of the present invention as defined in the
accompanying claims.
* * * * *