U.S. patent application number 11/866830 was filed with the patent office on 2008-10-09 for high capacity low cost multi-state magnetic memory.
This patent application is currently assigned to YADAV TECHNOLOGY. Invention is credited to Parviz Keshtbod, Roger Klas Malmhall, Rajiv Yadav Ranjan.
Application Number | 20080246104 11/866830 |
Document ID | / |
Family ID | 39690750 |
Filed Date | 2008-10-09 |
United States Patent
Application |
20080246104 |
Kind Code |
A1 |
Ranjan; Rajiv Yadav ; et
al. |
October 9, 2008 |
High Capacity Low Cost Multi-State Magnetic Memory
Abstract
One embodiment of the present invention includes multi-state
current-switching magnetic memory element including a stack of two
or more magnetic tunneling junctions (MTJs), each MTJ having a free
layer and being separated from other MTJs in the stack by a seeding
layer formed upon an isolation layer, the stack for storing more
than one bit of information, wherein different levels of current
applied to the memory element causes switching to different
states.
Inventors: |
Ranjan; Rajiv Yadav; (San
Jose, CA) ; Keshtbod; Parviz; (Los Altos Hills,
CA) ; Malmhall; Roger Klas; (San Jose, CA) |
Correspondence
Address: |
LAW OFFICES OF IMAM
111 N. MARKET STREET, SUITE 1010
SAN JOSE
CA
95113
US
|
Assignee: |
YADAV TECHNOLOGY
Fremont
CA
|
Family ID: |
39690750 |
Appl. No.: |
11/866830 |
Filed: |
October 3, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11678515 |
Feb 23, 2007 |
|
|
|
11866830 |
|
|
|
|
11674124 |
Feb 12, 2007 |
|
|
|
11678515 |
|
|
|
|
11860467 |
Sep 24, 2007 |
|
|
|
11674124 |
|
|
|
|
11678515 |
Feb 23, 2007 |
|
|
|
11860467 |
|
|
|
|
Current U.S.
Class: |
257/421 ;
257/E29.323 |
Current CPC
Class: |
G11C 11/161 20130101;
G11C 11/1675 20130101; G11C 11/5607 20130101; G11C 11/1673
20130101; H01L 27/222 20130101; H01L 43/08 20130101; H01L 43/02
20130101; H01L 43/10 20130101 |
Class at
Publication: |
257/421 ;
257/E29.323 |
International
Class: |
H01L 29/82 20060101
H01L029/82 |
Claims
1. A multi-state current-switching magnetic memory element
comprising: a stack of two or more magnetic tunneling junctions
(MTJs), each MTJ having a free layer and being separated from other
MTJs in the stack by a seeding layer formed upon an isolation
layer, the stack for storing more than one bit of information,
wherein different levels of current applied to the memory element
causes switching to different states.
2. A multi-state current-switching magnetic memory element, as
recited in claim 1, wherein the free layers of the MTJs each have a
unique composition, thereby causing each MTJ to switch states at a
unique switching current.
3. A multi-state current-switching magnetic memory element, as
recited in claim 1, wherein the free layers of the MTJs each have a
unique thickness, thereby causing each MTJ to switch states at a
unique switching current.
4. A multi-state current-switching magnetic memory element, as
recited in claim 1, wherein the barrier layers of the MTJs each
have a unique thickness, thereby causing each MTJ to switch states
at a unique switching current.
5. A multi-state current-switching magnetic memory element, as
recited in claim 4, wherein the barrier layer of each of the MTJs
is made substantially of magnesium oxide (MgO) and may include one
or more of the following compounds--aluminum oxide
(Al.sub.2O.sub.3), titanium oxide (TiO2), magnesium oxide (MgOx),
ruthenium oxide (RuO), strontium oxide (SrO), Zinc oxide (ZnO).
6. A multi-state current-switching magnetic memory element, as
recited in claim 5, wherein each of the MTJs includes a fixed
layer, and a barrier layer, the barrier layer separating the fixed
layer and the free layer.
7. A multi-state current-switching magnetic memory element, as
recited in claim 6, wherein the fixed layer of each of the MTJs is
made substantially of magnetic material.
8. A multi-state current-switching magnetic memory element, as
recited in claim 7, further including a pinning layer formed
adjacent to the fixed layer of each of the MTJs.
9. A multi-state current-switching magnetic memory element, as
recited in claim 8, further including a bottom electrode on top of
which is formed the pinning layer of one of the MTJs.
10. A multi-state current-switching magnetic memory element, as
recited in claim 9, further including a top electrode formed on top
of the free layer of one of the MTJs.
11. A multi-state current-switching magnetic memory element
comprising: A first magnetic tunneling junction (MTJ) formed on top
of a bottom electrode; A second MTJ, formed on top of the first
MTJ, and the second MTJ separated from the first MTJ by and a
seeding layer formed on top of an insulation layer; and A top
electrode formed on top of the second MTJ; Wherein different levels
of current applied to the memory element causes switching to
different states.
12. A multi-state current-switching magnetic memory element, as
recited in claim 11, further including a first pinning layer formed
between the bottom electrode and the first MTJ.
13. A multi-state current-switching magnetic memory element, as
recited in claim 12, further including a second pinning layer
formed between the seeding layer formed on top of the insulation
layer, and the second MTJ.
14. A multi-state current-switching magnetic memory element, as
recited in claim 13, wherein each MTJ includes a fixed layer, and a
barrier layer, the barrier layer separating the free layer from the
fixed layer.
15. A multi-state current-switching magnetic memory element, as
recited in claim 14, wherein the barrier layer of each MTJ is made
substantially of magnesium oxide (MgO) and may include one or more
of the following compounds--aluminum oxide (Al2O3), titanium oxide
(TiO2), magnesium oxide (MgOx), ruthenium oxide (RuO), strontium
oxide (SrO), Zinc oxide (ZnO).
16. A multi-state current-switching magnetic memory element, as
recited in claim 15, wherein the barrier layer of each MTJ has a
unique thickness, thereby causing each MTJ to have a unique
resistance.
17. A multi-state current-switching magnetic memory element, as
recited in claim 16, wherein the fixed layer of each of the MTJs is
made substantially of magnetic material.
18. A multi-state current-switching magnetic memory element, as
recited in claim 17, wherein the free layer of each of the MTJs is
unique in composition, causing each MTJ to have a unique switching
current.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 11/678,515, entitled "A High Capacity Low Cost
Multi-State Magnetic Memory," filed Feb. 23, 2007, which was a
continuation-in-part of U.S. patent application Ser. No.
11/674,124, entitled "Non-Uniform Switching Based on Non-Volatile
Magnetic Base Memory," filed Feb. 12, 2007, and is a
continuation-in-part of U.S. patent application Ser. No.
11/860,467, entitled, "A Low Cost Multi-State Magnetic Memory",
filed Sep. 24, 2007, which is a continuation-in-part of U.S. patent
application Ser. No. 11/678,515, entitled "A High Capacity Low Cost
Multi-State Magnetic Memory," filed Feb. 23, 2007, the disclosures
of which are incorporated herein by reference, as though set forth
in full.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to non-volatile
magnetic memory and particular to multi-state magnetic memory.
[0004] 2. Description of the Prior Art
[0005] Computers conventionally use rotating magnetic media, such
as hard disk drives (HDDs), for data storage. Though widely used
and commonly accepted, such media suffer from a variety of
deficiencies, such as access latency, higher power dissipation,
large physical size and inability to withstand any physical shock.
Thus, there is a need for a new type of storage device devoid of
such drawbacks.
[0006] Other dominant storage devices are dynamic random access
memory (DRAM) and static RAM (SRAM), which are volatile and very
costly but have fast random read/write access time. Solid state
storage, such as solid-state-nonvolatile-memory (SSNVM) devices
having memory structures made of NOR/NAND-based Flash memory,
providing fast access time, increased input/output (IOP) speed,
decreased power dissipation and physical size and increased
reliability but at a higher cost which tends to be generally
multiple times higher than hard disk drives (HDDs).
[0007] Although NAND-based Flash memory is more costly than HDD's,
it has replaced magnetic hard drives in many applications such as
digital cameras, MP3-players, cell phones, and hand held multimedia
devices due, at least in part, to its characteristic of being able
to retain data even when power is disconnected. However, as memory
dimension requirements are dictating decreased sizes, scalability
is becoming an issue because the designs of NAND-based Flash memory
and DRAM memory are becoming difficult to scale with smaller
dimensions. For example, NAND-based Flash memory has issues related
to capacitive coupling, few electrons/bit, poor error-rate
performance and reduced reliability due to decreased read-write
endurance. Read-write endurance refers to the number of reading,
writing and erase cycles before the memory starts to degrade in
performance due primarily to the high voltages required in the
program, erase cycles.
[0008] It is believed that NAND Flash, especially multi-bit designs
thereof, would be extremely difficult to scale below 45 nanometers.
Likewise, DRAM has issues related to scaling of the trench
capacitors leading to very complex designs that are becoming
increasingly difficult to manufacture, leading to higher cost.
[0009] Currently, applications commonly employ combinations of
EEPROM/NOR, NAND, HDD, and DRAM as a part of the memory in a system
design. Design of different memory technology in a product adds to
design complexity, time to market and increased costs. For example,
in hand-held multi-media applications incorporating various memory
technologies, such as NAND Flash, DRAM and EEPROM/NOR Flash memory,
complexity of design is increased as are manufacturing costs and
time to market. Another disadvantage is the increase in size of a
device that incorporates all of these types of memories
therein.
[0010] There has been an extensive effort in development of
alternative technologies such as Ovanic RAM (or phase-change
memory), Ferromagnetic RAM (FeRAM), Magnetic RAM (MRAM),
probe-based storage such as Millipede from International Business
Machines, Inc. of San Jose, Calif., or Nanochip, and others to
replace memories used in current designs such as DRAM, SRAM,
EEPROM/NOR Flash, NAND Flash and HDD in one form or another.
Although these various memory/storage technologies have created
many challenges, there have been advances made in this field in
recent years. MRAM seems to lead the way in terms of its progress
in the past few years to replace all types of memories in the
system as a universal memory solution.
[0011] One of the problems with prior art memory structures is that
the current and power requirements are too high to make a
functional memory device or cell. This also poses a key concern
regarding the reliability of such devices due to likely dielectric
breakdown of the tunneling barrier layer and thereby making it
non-functional.
[0012] The challenge with other prior art techniques has been that
the switching current is too high to allow the making of a
functional device for memory applications due to the memory's high
power consumption. Several recent publications, such as those cited
below as references 5 and 6.sup.(5,6) have shown that the switching
current can be reduced by having the memory element pinned by two
anti-ferromagnetic (AF)-couple layers resulting in spin
oscillations or "pumping" and thereby reducing the switching
current.
[0013] An additionally known problem is using magnetic memory to
store more than two states therein. To this end, multi-level or
multi-state magnetic memory cells or elements for storing more than
one bit of information do not exist.
[0014] What is needed is magnetic memory for storing more than one
bit of digital information.
SUMMARY OF THE INVENTION
[0015] To overcome the limitations in the prior art described
above, and to overcome other limitations that will become apparent
upon reading and understanding the present specification, the
present invention discloses a method and a corresponding structure
for a magnetic storage memory device that is based on
current-induced-magnetization-switching having reduced switching
current in the magnetic memory.
[0016] Briefly, an embodiment of the present invention includes
multi-state current-switching magnetic memory element including a
stack of two or more magnetic tunneling junctions (MTJs), each MTJ
having a free layer and being separated from other MTJs in the
stack by a seeding layer formed upon an isolation layer, the stack
for storing more than one bit of information, wherein different
levels of current applied to the memory element causes switching to
different states.
[0017] These and other objects and advantages of the present
invention will no doubt become apparent to those skilled in the art
after having read the following detailed description of the
preferred embodiments illustrated in the several figures of the
drawing.
IN THE DRAWINGS
[0018] FIG. 1 shows relevant layers of a multi-state
current-switching magnetic memory element 100 are shown, in
accordance with an embodiment of the present invention.
[0019] FIG. 2 shows various states of the memory element 100.
[0020] FIG. 3 shows a graph of the level of resistance (R) of each
of the layers 118, 114, 110 and 106 (shown in the y-axis) vs. the
state of the memory element 100.
[0021] FIG. 4 shows a graph 250 of the tunneling magneto resistance
(TMR), shown in the y-axis, vs. the resistance area (RA). FIG. 5
shows.
[0022] FIG. 5 shows relevant layers of a multi-state
current-switching magnetic memory element 600 are shown, in
accordance with another embodiment of the present invention.
[0023] FIG. 6 shows relevant layers of a multi-state
current-switching magnetic memory element 700, in accordance with
yet another embodiment of the present invention.
[0024] FIG. 7 shows relevant layers of a multi-state
current-switching magnetic memory element 800, in accordance with
still another embodiment of the present invention.
[0025] FIG. 8 shows a program/erase circuit for programming and/or
erasing the memory elements of the various embodiments of the
present invention.
[0026] FIG. 9 shows a read circuit for reading the memory elements
of the various embodiments of the present invention.
[0027] FIG. 10 shows the relevant layers of a multi-state
current-switching magnetic memory element 1100, in accordance with
an embodiment of the present invention.
[0028] FIGS. 11(a) and (b) show the problems inherent to the
manufacturing of earlier memory elements having mirrored MTJs.
[0029] FIGS. 12(a) and (b) show the manufacturing efficiency
benefits of the method of manufacturing of an embodiment of the
present invention.
[0030] Table 1 shows certain exemplary characteristics of the
embodiments of FIGS. 1, 5 and 6.
[0031] Table 2 shows certain exemplary characteristics of the
embodiment of FIG. 7.
[0032] Table 3 shows the possible magnetic states of two MTJs, in
an embodiment of the present invention.
[0033] Table 4 shows three potential configurations, or scenarios,
of MTJ resistance values, as a function of the magnesium oxide
(MgO) tunnel sizes, of magnetic memory element 1100.
[0034] Table 5 shows a comparison of total resistance values,
depending on the state of the memory element 1100 in Table 4, and
the different MgO tunnel barrier thickness scenarios of Table
3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0035] In the following description of the embodiments, reference
is made to the accompanying drawings that form a part hereof, and
in which is shown by way of illustration of the specific
embodiments in which the invention may be practiced. It is to be
understood that other embodiments may be utilized, because
structural changes may be made without departing from the scope of
the present invention.
[0036] In an embodiment of the present invention, a multi-state
magnetic memory cell is disclosed. A stack of magnetic tunnel
junctions (MTJs) are formed, with each MTJ of the stack formed of a
fixed layer, a barrier layer, and a free layer. The fixed layer's
magnetic polarity is static, or "fixed," by an adjacent "pinning
layer;" while the free layer's magnetic polarity can be switched
between two states by passing an electrical current through the
MTJ. Depending on the magnetic polarity, or state, of the free
layer relative to the fixed layer, the MTJ is either in a `0` or a
`1` state.
[0037] The individual MTJs are stacked upon each other, and are
separated from MTJs that are above or below by an isolation layer.
At the top of the top-most MTJ, and at the bottom of the
bottom-most MTJ, are electrodes, which serve to pass the electrical
current through the stack for programming, erasing, and reading
operations. Each collective of MTJs is oriented in a vertical
manner, and are known as a stack, or memory element. All
neighboring stacks are created by the same steps of the same
process (i.e. the stepwise addition of layers), and only become
individual stacks after an etching step in the manufacturing
process, whereby fractions of each layer are physically removed at
precise spacing intervals, creating the stack structures.
[0038] The memory element disclosed herein reduces the number of
manufacturing steps, manufacturing time, and consequently
manufacturing costs, while increasing the consistency and
reliability relative to MTJs within a stack.
[0039] In prior embodiments of multi-state magnetic memory
elements, the mirrored layer order of the bottom stacks and top
stacks required that each MTJ undergo a unique series of otherwise
identical layering steps (i.e. step 1, step 2, step 3 to form MTJ
1; but step 3, step 2, step 1 to form MTJ 2); or to manufacture MTJ
1 and MTJ 2 side-by-side, and then institute a mid-manufacturing
etching step, thus requiring two unique passes of the etching
equipment (see U.S. patent application Ser. No. 11/678,515,
entitled "A High Capacity Low Cost Multi-State Magnetic Memory,"
filed on Feb. 23, 2007, by Ranjan et al. for more detail in this
respect). This problem is better illustrated in FIGS. 11(a) and
(b).
[0040] Referring now to FIG. 1, relevant layers of a multi-state
current-switching magnetic memory element 100 are shown, in
accordance with an embodiment of the present invention. The memory
element 100 is shown to include a bottom electrode 122 on top of
which is shown formed a pinning layer 120 on top of which is shown
formed a fixed layer 118, on top of which is shown formed a barrier
layer 116, on top of which is formed a free layer 114, on top of
which is shown formed a non-magnetic layer 112, on top of which is
shown formed a free layer 110, on top of which is shown formed a
barrier layer 108, on top of which is shown formed a fixed layer
106, on top of which is shown formed a pinning layer 104, on top of
which is shown formed a top electrode 102. The top electrode 102
and the bottom electrode 122 are each made of Tantalum (Ta) in an
exemplary embodiment although other suitable materials are
contemplated. The layers 114, 116 and 118 are shown to form a MTJ
126 separated by the layer 112 from an MTJ 124, which is formed
from the layers 106, 108 and 110. The MTJ 124 and 126 form the
relevant parts of a stack of memory elements. In fact, while two
MTJs are shown to form the stack of FIG. 1, other number of MTJs
may be stacked for storing additional bits of information.
[0041] In FIG. 1, the MTJ 126 is for storing a bit of information
or two states, `1` and `0`, while the MTJ 124 is for storing
another bit of information and since each bit represents two binary
states, i.e. `1` and `0`, two bits represent four binary states,
generally represented as `00`, `01`, `10`, `11`, or 0, 1, 2 and 3
in decimal notation, respectively. The memory element 100
advantageously stores two bits of information thereby decreasing
the real estate dedicated for memory and further increases system
performance. This is particularly attractive for embedded memory
applications. Additionally, manufacturing is made easier and less
costly and scalability is realized.
[0042] In FIG. 1, the barrier layers of each of the MTJs, such as
the layer 116 acts as a filter for electrons with different spins
giving rise to different amounts of tunneling current for electrons
with different spins thereby causing two unique resistance values
associated with each MTJ for two different orientations of the free
layer. In the case where additional MTJs are employed, each MTJ
similarly has associated therewith, a unique resistance value.
[0043] In one embodiment of the present invention, the thickness of
the layers 108 and 116 to cause the MTJs 124 and 126 to have
different resistances and therefore capable of storing more than
one bit.
[0044] Examples of materials used to form each of the layers of the
memory element 100 will now be presented. It should be noted that
these materials are merely examples and other types of materials
may be employed. The layers 104 and 122, are each typically formed
substantially of IrMn or PtMn or NiMn or any other material
including Manganese (Mn). The layers 106 and 120 are typically
formed substantially of a magnetic material. Examples of such
magnetic material include CoFeB or CoFe/Ru/CoFeB. The layers 108
and 116 are each made substantially of a non-magnetic material, an
example of which is magnesium oxide (MgO). The layer 112 is a
non-magnetic layer made substantially of, for example, NiNb, NiP,
NiV or CuZr. The layer 112 serves to insulate the two MTJs 124 and
126 from one another. In an embodiment employing more than two
MTJs, another layer, such as the layer 112 would be formed on top
of the layer 104 or on the bottom of the layer 120. The layers 110
and 114 are each made of CoFeB containing oxides intermixed. The
layers 110 and 114 are substantially amorphous in an at-deposited
state. The top electrode 102 and the bottom electrode 122 are each
made of tantalum (Ta), in one embodiment of the present invention,
however, other types of conductive material may be employed.
[0045] The layers 120 and 104 are anti-ferromagnetic (AF) coupling
layers. More specifically, for example, the magnetic moment of the
layer 104 helps to pin the magnetic moment of the layer 106.
Similarly, the magnetic moment of the layer 120 serves to pin the
magnetic moment of the layer 118. The magnetic moment of each of
the layers 120 and 104 are permanently fixed.
[0046] Other choices of material for the layers 108 and 166 are
aluminum oxide (Al2O3) and titanium oxide (TiO2). A thin-layer of
one of the constituent elements may be deposited prior to the
deposition of the barrier oxide layer. For example, a 2-5 A thick
Mg layer may be deposited prior to the deposition of the layers 108
and 116. This limits any damage of the magnetic-free layer from
intermixing of the elements during deposition. The layer 112 is a
non-magnetic layer which is substantially amorphous made of, for
example, Nickel niobium (NiNb), Nickel phosphorous (NiP), Nickel
vanadium (NiV), Nickel borom (NiB) or copper-zirconium (CuZr). It
should be noted that the composition of these alloys is chosen in
such a way that the resulting alloy becomes substantially
amorphous, for example, for nickel niobium (NiNb), the typical Nb
content is maintained between 30 to 70 atomic percent and for
nickel phosphorous (NiP) the phosphorous (P) content is maintained
between 12 and 30 atomic percent. The layer 112 serves to isolate
the two MTJs 124 and 126 from one another. In an embodiment of the
present invention, which employs more than two MTJs, another layer,
such as the layer 112 would be formed on top of the layer 104 or on
the bottom of the layer 120. The layers 110 and 114 are each made
of CoFeB containing oxides intermixed. The layers 110 and 114 are
substantially amorphous in an as-deposited state. The top and the
bottom electrodes are typically made of tantalum (Ta).
[0047] The layers 120 and 104 are anti-ferromagnetic (AF) coupling
layers. More specifically, for example, the magnetic moment of the
layer 104 helps to pin the magnetic moment of the layer 106.
Similarly, the magnetic moment of the layer 120 serves to pin the
magnetic moment of the layer 118. The magnetic moment of each of
the layers 120 and 104 are permanently fixed. This is typically
done by a magnetic annealing process following the deposition of
all the layers and involves heating the whole wafer under the
application of a substantially uni-axial magnetic field of Over 5
kilo-oersted and a temperature of over 350 degree centigrade for
typically 2 hours. This annealing process also serves to
re-crystallize the layers 108 and 116 and their respective adjacent
free layers 110 and 114. This process is essential for making high
performing magnetic tunnel junction.
[0048] Typical thicknesses for each of the layers of the memory
element 100 are now presented. However, these sizes are merely
examples, as other thicknesses are anticipated. A typical thickness
of each of the top electrode 102 and the bottom electrode 122 is 30
to 200 nm. While a preferred thickness is typically 50 nm, the
actual thickness choice may depend on the requirements from the
metallization process. The layers 104 and 120 are typically 20 to
100 nm in thickness with a preferred thickness of 25-50 nm. The
layers 108 and 118 are typically made of three layers of
Cobalt-Iron (CoFe)--Ruthenium (Ru)/Cobalt-Iron-Boron (CoFeB) with
CoFe layer being placed adjacent to the layers 104 and 120. The
typical thickness of the CoFe layer is 3 to 10 nm, Ru layer is 0.6
to 1.0 nm to create anti-ferromagnetic coupling between the two
adjacent magnetic layers of CoFe and CoFeB. The CoFeB layer is
typically 2 to 10 nm thick with a preferred range of 2.5 to 5 nm.
The free layers 110 and 114 are typically 2 to 7 nm thick with a
preferred range of 2-5 nm and may contain a 1-2 nm thick layer of
Co--Fe-oxide inter-dispersed in that layer in order to get low
switching current during current induced switching. The barrier
layers 108 and 116 are typically 0.8 to 3 nm. It is very likely
that the two barrier layers may have slightly different thickness,
for example layer 116 can be 1.5 to 2.5 nm thick while the second
barrier layer 108 may be 0.8 to 1.2 nm thick, and vice-versa.
Additionally, the thickness and the amounts of oxide in the
free-layers 110 and 114 may be different by a factor of 1.5 or
higher. The amorphous isolation layer 112 is typically 2 to 50 nm
thick with a preferred range being 2 to 10 nm. It should be pointed
out that while the most preferred choice of the non-magnetic
isolation layer is amorphous non-magnetic alloys, a crystalline
non-magnetic alloy may also work.
[0049] During manufacturing, the layers of the memory element 100
are formed in the manner described hereinabove. Additionally, an
annealing process, which is well known, is performed heating the
memory element 100 in the presence of a magnetic field after which
channels are formed in each of the layers 108 and 116. Following
the annealing process, the fix layers are oriented in a particular
orientation and the layers 108 and 116 as well as the layers 110
and 114 take on a crystalline characteristic.
[0050] During operation, current is applied, in a perpendicular
direction relative to the plane of the paper of FIG. 1, either from
a direction indicated by the arrow 128 or a direction indicated by
the arrow 130. When current is applied, depending on the level of
current, the magnetic moment of the layers 110 and 114 are each
caused to be switched to an opposite direction, or not. Since the
MTJs 124 and 126 are made with different aspect ratios (or
anisotropy), the switching current is different for these two MTJs.
For example, in one embodiment of the present invention, the aspect
ratio for MTJ 124 is approximately 1:1.3 to 1:1.5 while the aspect
ratio for the MTJ 126 is approximately 1:2 to 1:2.5. Therefore, the
switching current for the MTJ 126 is 3-5 times higher than that of
the MTJ 124, in the foregoing embodiment. At high current levels
both MTJs switch magnetic orientation, while at low current levels
only the MTJ 124 having the smaller aspect ratio switches.
[0051] The state of the magnetic moment of each of the layers of
the MTJ defines the state of the memory element 100. As the layers
104 and 120 each act as AF coupling layers, they pin or switch the
magnetic moments of the their neighboring fixed layer, which, then,
by the application of current, causes neighboring free layers to
switch or not. More specifically, the layer 118 defines one state,
the layer 114 defines another state, the layer 110 defines yet
another state and the layer 106 defines still another state. For
the sake of understanding, the states of each of the layers 118,
114, 110 and 106 are referred to as states 1, 2, 3 and 4,
respectively.
[0052] FIG. 2 shows various states of the memory element 100. Due
to the use of two MTJs, four different states or two bits may be
stored, therefore, the states 1-4 are shown. At each state, the
directions of the arrows indicate the direction of the magnetic
moments of free layers and pinning layers. The direction of the
arrow 200 shows the direction of high current applied to the memory
element 100 and in this case, the state of the memory element 100
is at an all `1`s or all `0`s state. The direction of the arrow 202
shows the direction of low current applied to the memory element
100 when at state 1. The direction of the arrow 204 shows the
direction of high current applied to the memory element 100 when
the latter is at state 2 and the direction of the arrow 206 shows
the direction of low current applied to the memory element 100 when
at state 3.
[0053] FIG. 3 shows a graph of the level of resistance (R) of each
of the layers 118, 114, 110 and 106 (shown in the y-axis) vs. the
state of the memory element 100. Thus, at, for example, at 208, the
memory element 100 has taken on the state 1 (corresponding to 200
on FIG. 2), at 210, the memory element 100 has taken on the state 2
(corresponding to 202 on FIG. 2), at 212, the memory element 100
has taken on the state 3 (corresponding to 206 on FIG. 2), and at
214, the memory element 100 has taken on the state 4 (corresponding
to 204 on FIG. 2). The level of resistance for each of these states
is indicated in Table 1, at a column labeled "Total R". For
example, at state 1, the R, in FIG. 3 is indicated as being 3 kilo
ohms (K Ohms) by Table 1. At state 2, the R, in FIG. 3, is
indicated as being 4 K Ohms and so on. The values used for
resistance serve as examples only such that other values may be
employed without departing from the scope and spirit of the present
invention.
[0054] It should be noted that different aspect ratio or anisotropy
associated with the different MTJs 124 and 126 causes the different
switching of the MTJs, which results in two bits being stored in
the memory element 100. In other embodiments, some of which will be
shortly presented and discussed, the size of the barrier layers of
the MTJs are changed to effectuate different resistances. In yet
other embodiments, the size of the MTJs are changed to the
same.
[0055] FIG. 4 shows a graph 250 of the tunneling magneto resistance
(TMR), shown in the y-axis, vs. the resistance area (RA). The TMR
is defined as:
TMR=(Rh-Rl)/Rl Eq. (1)
[0056] Wherein Rh is resistance at a high state and Rl is
resistance at a low state.
[0057] The graph 250 of FIG. 4 serves merely as an example to
convey the difference in TMR or percentage increase as the RA
increases. For instance, at an RA of 2 ohm-micro-meters squared,
the TMR is 100% while at a RA of 10, the TMR is 150% where the
thickness of the barrier layer of the MTJ is between 14-24
Angstroms.
[0058] FIG. 5 shows relevant layers of a multi-state
current-switching magnetic memory element 600 are shown, in
accordance with another embodiment of the present invention. The
memory element 600 is shown to include a bottom electrode 122 on
top of which is shown formed a pinning layer 120 on top of which is
shown formed a fixed layer 118, on top of which is shown formed a
barrier layer 116, on top of which is formed a free layer 114, on
top of which is shown formed a non-magnetic layer 112, as that
shown in FIG. 1. As previously indicated, relative to FIG. 1, the
MTJ 126 comprises the layers 114, 116 and 118. However, in the
embodiment of FIG. 5, the MTJ 612, which is made of a free layer
602, a barrier layer 604 and a fixed layer 606, is smaller, in its
planar dimension, than the MTJ 126 of FIG. 1, which causes the MTJ
612 to have a different resistance than that of the MTJ 126.
[0059] In FIG. 5, the free layer 602 is shown to be formed on top
of the layer 112 and on top of the layer 602 is shown formed the
layer 604, on top of which is shown formed the layer 606, on top of
which is shown formed a pining layer 608, a top electrode 610. The
MTJs 126 and 612 are shown separated by the layer 112. The MTJs 126
and 612 form the relevant parts of a stack of memory elements. In
fact, while two MTJs are shown to form the stack of FIG. 5, other
number of MTJs may be stacked for storing additional bits of
information.
[0060] The difference in the planar dimension of the MTJs 612 to
that of the MTJ 126 is approximately 1 to 10 and typically 1 to 3,
in one embodiment of the present invention. The material for each
of the layers of the memory element 600 may be the same as that of
counterpart layers of the memory element 100. For example, the
layer 602 is made of the same material as that of the layer 110 and
the layer 604 is made of the same material as that of the layer 108
and the layer 606 is made of the same material as the layer 106 and
the layer 608 is made of the same material as the layer 104. The
top electrodes 610 and 102 are made of the same material. In
another embodiment, the MTJ 612 may be larger, in size, in the same
planar dimension, that the MTJ 126.
[0061] The operation of the embodiment of the embodiment of FIG. 5
is the same as that of FIG. 1.
[0062] FIG. 6 shows relevant layers of a multi-state
current-switching magnetic memory element 700, in accordance with
yet another embodiment of the present invention. The memory element
700 to include a bottom electrode 122 on top of which is shown
formed a pinning layer 120 on top of which is shown formed a fixed
layer 118, on top of which is shown formed a barrier layer 116, on
top of which is formed a free layer 114, on top of which is shown
formed a non-magnetic layer 112, as that shown in FIGS. 1 and 6. As
previously indicated, relative to FIGS. 1 and 6, the MTJ 126
comprises the layers 114, 116 and 118. However, in the embodiment
of FIG. 6, the MTJ 714, which is shown to comprise a free layer
706, a barrier layer 708 and a fixed layer 710, is shown to be
smaller in its planar dimension than the MTJ 126 causing the MTJ
710 to have a different resistance than that of the MTJ 126.
[0063] The MTJs 126 and 714 are shown separated by the layers 702
and 704. Although the layer 704 serves to pin the layer 706 while
the layer 702 serves to isolate the MTJ 126 and is an amorphous
only to the layer 114. The layer 702, in one embodiment of the
present invention, is made of two non-magnetic layers, such as Ta
and/or an amorphous alloy, the same as Nickel-niobium (NiNb) or
nickel-phosphorus (NiP). The MTJs 126 and 612 form the relevant
parts of a stack of memory elements. In fact, while two MTJs are
shown to form the stack of FIG. 5, other number of MTJs may be
stacked for storing additional bits of information.
[0064] The difference in the planar dimension of the MTJs 714 to
that of the MTJ 126 is 1 to 10, and typically 1 to 3 in one
embodiment of the present invention. The material for each of the
layers of the memory element 700 may be the same as the counterpart
layers of the memory element 100 or that of the memory element 600.
For example, the layer 710 is made of the same material as that of
the layer 110 and the layer 708 is made of the same material as
that of the layer 108 and the layer 706 is made of the same
material as the layer 106 and the layer 704 is made of the same
material as the layer 104. The top electrodes 712 and 102 are made
of the same material. In another embodiment, the MTJ 714 may be
larger, in size, in the same planar dimension, that the MTJ
126.
[0065] FIG. 7 shows relevant layers of a multi-state
current-switching magnetic memory element 800, in accordance with
still another embodiment of the present invention. In FIG. 7, the
memory element 800 is shown to include a bottom electrode 802 on
top of which is shown formed a pinning layer 804 on top of which is
shown formed two fixed layers on either side thereof. That is, a
fixed layer 806 is shown formed on one side of the layer 804 and a
fixed layer 808 is shown formed on an opposite side of the layer
804.
[0066] In FIG. 7, two MTJs are shown formed on either side or top
of the layer 804. Namely, an MTJ 820 is shown formed on one side of
the layer 804 and another MTJ 822 is shown formed on an opposite
side of the layer 804. The MTJ 820 includes the fixed layer 806,
which is formed on top of the layer 804 and the barrier layer 810
shown formed on top of the layer 806 and the free layer 812 shown
formed on top of the layer 810. The MTJ 822 is shown to include the
fixed layer 808, which is formed on top of the layer 704 and the
barrier layer 814, which is shown formed on top of the layer 808
and the free layer 816, which is shown formed on top of the layer
814. A top electrode 818 is shown formed on top of the MTJs 820 and
822 or more specifically on top of the layers 812 and 816. The top
electrode 818 is typically made of two layers, such as Ta and a
conductive, non-magnetic material.
[0067] In forming the memory element 800, the layer 804 is formed
on top of the bottom electrode and the layers of the MTJs 820 and
822 are formed on top of the layer 804 and on top of the MTJs 820
and 822 is formed the top electrode 818. The layers of the MTJs 820
and 822 are formed uniformly and continuously on top of the layer
804 and a trench 824, which is basically an empty space or hole is
formed, prior to depositing the top electrode 818, by etching
through the layers of the MTJs 820 and 822. In this manner, the
fixed layers of the MTJs 820 and 822 are the same layer prior to
etching and the barrier layers of the MTJs 820 and 822 are the same
layer prior to etching and the free layers of the MTJs 820 and 822
are the same layer prior to etching.
[0068] In one embodiment of the present invention, the trench 824
is filled with a dielectric material, such as silicon dioxide
(SiO2) or silicon nitride (SiNx) to enhance stability.
[0069] After etching, the top electrode 818 is deposited or formed
on top of the MTJs 820 and 822. The embodiment of FIG. 7, as the
embodiments of FIGS. 6, 5 and 1 store two bits of information, on
bit in each MTJ. Thus, the MTJ 820 is for storing one bit and the
MTJ 822 is for storing another bit of information. However, more
bits may be stored by adding MTJs. In FIG. 7, additional MTJs may
be added on top of the layer 804 or the MTJs 820 and 822. With the
addition of MTJs, beyond that which is shown in FIG. 7, additional
notches or spaces are formed between the MTJs, such as the space or
notch 824.
[0070] Table 2 shows certain exemplary characteristics of the
embodiment of FIG. 7. It should be noted that similarly, Table 1
shows certain exemplary characteristics of the embodiments of FIGS.
1, 5 and 6.
[0071] For example, in Table 2, under the "Total R" column, there
is shown the resistance at each state of the memory element 800,
such as the state 1, the state 2, the state 3 and the state 4. As
previously noted, each state represents a binary value such that
four states, and represented by two bits are stored. The
programming current, in micro amps, i.e. the current needed to
program the memory element 800 to a given state, is indicated in
the last column of Table 2, under the label "Prog I".
[0072] In an alternative embodiment of the present invention, a
non-uniform switching based non-volatile magnetic memory element,
such as the non-uniform switching based non-volatile magnetic
memory element 100 disclosed in U.S. patent application Ser. No.
11/674,124 entitled "Non-Uniform Switching Based Non-Volatile
Magnetic Base Memory", filed on Feb. 12, 2007, may be employed to
replace the MTJs of the various embodiments shown and discussed
herein. For example, the MTJ 124 or the MTJ 126 may be replaced
with a non-uniform switching based non-volatile magnetic memory
element. Other MTJs discussed herein may also be replaced with
non-uniform switching based non-volatile magnetic memory element.
This advantageously further reduces the requisite switching current
to enhance system performance.
[0073] FIG. 8 shows a program/erase circuit for programming and/or
erasing the memory elements of the various embodiments of the
present invention. In FIG. 8, a current source 902 is shown coupled
to a current mirror circuit 904, which is shown coupled to the
switch 906, which is, in turn, shown coupled to the switch 908,
which is shown coupled to the multi-state current-switching
magnetic memory cell 914, which is shown coupled to the switch 916.
Further shown in FIG. 8, a current source 918 is shown coupled to a
current mirror circuit 920 and further shown coupled to Vcc on an
opposite end thereto. The circuit 920 is further shown coupled to
the switch 910.
[0074] The circuit 904 is shown to include a P-type transistor 922,
a P-type transistor 924 and a P-type transistor 926. The source of
each of the transistors 922, 924 and 926 are shown coupled to Vcc.
Vcc is at a predetermined voltage level that is higher than ground.
The gate of the transistor 922 is shown coupled to the current
source 902 and the opposite side of the current source 902 is shown
coupled to ground. The drain of the transistor 922 is shown coupled
to its gate as well as to the gate of the transistor 924 and the
gate of the transistor 926. The drains of the transistors 924 and
926 are shown coupled to the switch 906. The memory cell 914 is
shown to include an MTJ 910, an MTJ 912 and an access transistor
940. The MTJ 912 is shown coupled in series to the MTJ 912, which
is shown coupled to the drain of the transistor 940. The gate of
the transistor 940 is shown coupled to the word line 942. The word
line 942 selects a memory cell. The source of the transistor 940 is
shown coupled to the switch 916.
[0075] The circuit 920 is shown to include an N-type transistor
928, an N-type transistor 930 and an N-type transistor 932. The
drains of the transistors 928, 930 and 932 are shown coupled to
ground. The gate of the transistor 932 is coupled to the current
source 918 and is further coupled to the drain of the transistor
932 and is further coupled to the gate of the transistor 930 as
well as to the gate of the transistor 928. The drain of the
transistors 930 and 928 are shown coupled to the switch 910.
[0076] Each of the switches 908 and 916 are shown operative to
switch between two states, a program state and an erase state. The
switches 906 and 910 are shown operative to switch between two
states.
[0077] The MTJs 910 and 912 are similar to the MTJs of previous
figures, such as those depicted in FIGS. 1 and 6. In an alternative
embodiment, the MTJs 910 and 912, coupled in parallel, would be
similar to the MTJs shown in FIG. 7. Each MTJ 910 and 912 possesses
a resistance of a different or unique value. The difference in
their resistance results from the difference in the aspect ratio or
size or anisotropy of the MTJs.
[0078] The size of the transistor 926 is greater than the size of
the transistors 922 and 924. Similarly, the size of the transistor
928 is greater than the size of the transistors 930 and 932. In one
embodiment of the present invention, the size difference of the
foregoing transistors is 4 to 1. To explain the operation of
programming, an example is provided with fixed values but it should
be noted that these values may be altered without departing from
the scope and spirit of the present invention.
[0079] In operation, to program the memory cell 914 to a state 1, a
current of level of 50 micro Amps is applied by the current source
902 to the circuit 904, which is amplified to 4.times. the current
level or 200 microAmps, as shown in Table 1 because the transistor
926 is able to drive this level of current. This causes the switch
906 to switch to the state indicated at 944. The switch 908 is set
to `program` state, as is the switch 916, which causes the 200
micro amp current to flow through the MTJs 910 and 912 and the
transistor 940 is selected by raising the voltage on the word line
942. This results in programming of state 1. The magnetic moment of
the free layers of the MTJs 910 and 912 will be caused to be
aligned with the magnetic moment of that of their respective fixed
layers. This results in the lowest resistance of the memory cell
914, as indicated in Table 1.
[0080] In programming the memory cell 914 to a state 2, a current
of level of 50 micro Amps is applied by the current source 918 to
the circuit 920, which is the same current level as that generated
by the circuit 920. The current level for state 2 is indicated in
Table 1. The switch 910 is caused to be switched to the state
indicated at 948. The switches 908 and 916 are both set to `erase`
state, which causes the 50 micro amp current to flow through the
MTJs 910 and 912 and the transistor 940 is selected by raising the
voltage on the word line 942. This results in programming of state
2. The magnetic moment of the free layer of the MTJ 910 is caused
to be switched to an anti-parallel state or a state that is in
opposite to being aligned with its respective fixed layer. The MTJ
912 remains in the state it was in at state 1. The reason for this
is, that in one embodiment of the present invention, with the
aspect ratio of the MTJ 912 being higher than that of MTJ 910, it
is prevented from switching. This results in the resistance of the
memory cell 914 indicated in Table 1.
[0081] In programming the memory cell 914 to a state 3, a current
of level of 50 micro Amps is applied by the current source 918 to
the circuit 920, which causes the current level, generated by the
transistor 928 to be 4 times that of the level of the current
source, or 200 micro amps. The current level for state 3 is
indicated in Table 1. The switch 910 is caused to be switched to
the state indicated at 950. The switches 908 and 916 are both set
to `erase` state, which causes the 200 micro amp current to flow
through the MTJs 910 and 912 and the transistor 940 is selected by
raising the voltage on the word line 942. This results in
programming of state 3. The magnetic moment of the free layers of
the MTJs 910 and 912 are caused to be switched to an anti-parallel
state relative to their respective fixed layers. This results in
the resistance of the memory cell 914 to be that indicated in Table
1.
[0082] To program the memory cell 914 to a state 4, a current of
level of 50 micro Amps is applied by the current source 902 to the
circuit 904, which is the current level of the circuit 904 and that
which is indicated in Table 1 for state 4. This causes the switch
906 to switch to the state indicated at 946. The switch 908 is set
to `program` state, as is the switch 916, which causes the 50 micro
amp current to flow through the MTJs 910 and 912 and the transistor
940 is selected by raising the voltage on the word line 942. This
results in programming of state 4. The magnetic moment of the free
layer of the MTJ 910 will be caused to be aligned with the magnetic
moment of that of its respective fixed layer. The MTJ 912 remains
in its anti-parallel state, the reason for this is due the
difference in the aspect ratios of the two MTJs as discussed
hereinabove. This results in a resistance of the memory cell 914
indicated in Table 1.
[0083] FIG. 9 shows a read circuit for reading the memory elements
of the various embodiments of the present invention. FIG. 9 is
shown to include a memory cell 1002 coupled to a sense amplifier
circuit 1004, which is shown coupled to a reference circuit 1006.
The memory cell 1002 is shown to include an access transistor 1008,
an MTJ 1010 and an MTJ 1012. The transistor 1008 is shown to have a
drain, a source and a gate. The gate of the transistor 1008 is
shown coupled to a word line 1014, the drain of the transistor is
shown coupled to ground and the source of the transistor is shown
coupled to the MTJ 1010.
[0084] It should be noted that wherever values are indicated
herein, they are to merely serve as examples with the understanding
that other suitable values are anticipated. It is further noted
that while reference is made to an N-type or P-type transistor,
either type or other suitable types of transistors may be employed,
as the type of transistor indicated in the foregoing embodiments,
merely serve as examples.
[0085] The circuit 1006 is shown to include a number of state
reference circuits, indicated as state reference circuit 1020, 1022
and 1024. Each of the circuits 1020-1024 includes an access
transistor and a reference resistor. For example, the circuit 1020
is shown to include a reference resistor 1026 coupled on one side
to the circuit 1004 and Vcc and on the other side to the drain of
an access transistor 1028. The gate of the transistor 1028 is shown
coupled to a select signal, namely select 1 signal 1040.
[0086] Similarly, the circuit 1022 is shown to include a reference
resistor 1030 coupled on one side to the circuit 1004 and Vcc and
on the other side to the drain of an access transistor 1032. The
gate of the transistor 1032 is shown coupled to a select signal,
namely the select 2 signal 1042. The circuit 1024 is shown to
include a reference resistor 1034 coupled on one side to the
circuit 1004 and Vcc and on the other side to the drain of an
access transistor 1036. The gate of the transistor 1044 is shown
coupled to a select signal, namely the select 3 signal 1044.
[0087] The MTJs 1010 and 1012, as stated relative to FIG. 8, are
similar to the MTJs of the embodiments of the present invention
except that in the case of FIG. 7, the MTJs of the read circuit
would be coupled in parallel rather than in series, shown in FIG.
9.
[0088] During a read operation, the memory cell 1002 is selected by
raising the voltage of the word line 1014. The circuit 1004
compares the total resistance of the MTJs 1010 and 1012 with the
resistances of the reference resistors of the state reference
circuits. For example, the resistance of the MTJs 1010 and 1012
(collectively or added together) is compared to the resistance of
the resistor 1026 and if it is determined to be less, the state of
the memory cell 1002 is declared as binary value `00` or perhaps,
state 1. However, if the resistance of the MTJs 1010 and 1012,
collectively, is determined to be higher than that of the resistor
1026, the former is then compared to the resistance of the resistor
1030 and there again, if the resistance of the MTJs 1010 and 1012
is less than the resistor 1030, the state 2 or binary value `01`.
If the resistance of the MTJs 1010 and 1012 is determined to be
greater than the resistor 1030, the resistance of the MTJs 1010 and
1012 is compared to the resistance of the resistor 1034 and if the
resistance of the former is determined to be lower, the state 3 or
binary value `10' is declared (or read), otherwise, the state 4 or
binary value `11` is declared.
[0089] The select signal of each of the circuits 1020-1024 are used
to select the corresponding circuit. For example, to compare the
resistance of the MTJs to the resistance of the resistor 1026, the
signal 1040 is activated thereby turning on the transistor 1028. In
the meanwhile, the remaining transistors of the circuit 1006 are
off. Similarly, to compare the resistance of the MTJs to the
resistance of the resistor 1030, the signal 1042 is activated
thereby turning on the transistor 1032. In the meanwhile, the
remaining transistors of the circuit 1006 are off. To compare the
resistance of the MTJs to the resistance of the resistor 1034, the
signal 1044 is activated thereby turning on the transistor 1036. In
the meanwhile, the remaining transistors of the circuit 1006 are
off.
[0090] Examples of resistance values of the reference resistors are
averages of the resistances of the MTJs 1010 and 1012. For example,
the resistance of the resistor 1026 is the average of the
resistances of the MTJs 1010 and 1012 at the states 1 and 4, as
indicated in Table 1. The resistance of the resistor 1030 is the
average of the resistances of the MTJs 1010 and 1012 at the states
2 and 4, as indicated in Table 1. The resistance of the resistor
1034 is the average of the resistances of the MTJs 1010 and 1012 at
the states 2 and 3, as indicated in Table 1. For example, in one
embodiment of the present invention, the resistor 1026 has a
resistance of 3.5 kilo-ohm, which is the average of 3 and 4
kilo-ohms. The resistance of the resistor 1030 is 4.5 kilo-ohms,
which is the average of 5 and 4 kilo-ohms and the resistance of the
resistor 1034 is 5.5 kilo-ohms, which is the average of 5 and 6
kilo-ohms.
[0091] In alternative embodiments of the present invention, the
MTJs (or memory elements) disclosed in U.S. patent application Ser.
No. 11/674,124 entitled "Non-Uniform Switching Based Non-Volatile
Magnetic Base Memory", filed on Feb. 12, 2007, may be employed in
the embodiments of FIGS. 8 and 9 herein.
[0092] It should be noted that the objects of the drawings or
figures discussed and presented herein are not necessarily drawn to
scale.
[0093] Referring now to FIG. 11(a), a flowchart illustrates the
manufacturing steps of prior multi-state magnetic memory element
wafers. The process begins with the movement of wafer #1 to station
seed layer with step 1182, and a seed layer is then formed on wafer
#1. From there, wafer #1 proceeds to station AFM layer with step
1183, and an anti-ferromagnetic (AFM) layer is formed on wafer #1.
At step 1184, wafer #1 is transported to station fixed layer so
that a fixed layer can be formed thereon. Subsequent to the
formation of a fixed layer, step 1185 transports wafer #1 to
station barrier layer for the formation of a barrier layer; step
1186 transports wafer #1 to station free layer for the formation of
a free layer; and step 1187 transports wafer #1 to station
isolation layer for the formation of an isolation layer. At this
point, wafer #1 then flows backwards through the prior steps,
beginning by going from station isolation layer to station free
layer in step 1188, and so on. After the deposition of a fixed
layer on wafer #1 at station fixed layer, wafer #1 travels to
station anti-ferromagnetic layer at step 1191 and an
anti-ferromagnetic layer is formed; and then on to receive a cap
layer in step 1192. As better shown in FIG. 11(b), wafer #1 must
pass backwards through the manufacturing hardware (notice step 1188
after step 1187), the manufacturing of wafer #2 is delayed until
wafer #1 has cleared step 1192 in the wafer transport module.
Ultimately, this results in a single wafer tying up an entire wafer
transport module until the manufacturing off the wafer is
completed.
[0094] Conversely, in an embodiment of the present invention, it is
possible for multiple wafers to be undergoing manufacturing steps
within the wafer transport module at all times, and the rate of
manufacturing is thereby dramatically increased.
[0095] Referring now to FIG. 12(a), a flow chart shows the
manufacturing process of an embodiment of the present invention.
After a seed layer is formed on wafer #1, and wafer #1 is moved to
station AFM layer at step 1183, wafer #2 can immediately be placed
into station seed layer, step 1205, for the formation of a seed
layer thereon. Subsequently, wafer #2 moves to station AFM layer at
step 1210 at the same time wafer #1 is moved from station AFM layer
to station fixed layer in step 1184, and wafer #3 is moved to
station seed layer in step 1206. This process continues on in such
a manner so that at step 1186, when wafer #1 is at station free
layer, there are five wafers in the wafer transport module being
manufactured in parallel, wafer #5 being at station seed layer. At
this point, shown as step 1200 in FIG. 12(a), the wafer transport
module determines whether a second MTJ has yet been deposited on
the wafer within. If not, the wafer, wafer #1, now moves to station
seed layer in step 1201, and proceeds, for a second time, through
the stations of the wafer transport module. Upon wafer #1's return
to step 1200, a second MTJ is present, and wafer #1 proceeds to
station cap layer, step 1202, and a cap layer is formed
thereon.
[0096] Subsequent to wafer #1 having formed a second seeding layer,
wafer #2 will as well, and so on to wafer #5. Because each station
will contain wafers #1-5 during this time, no new wafers will be
entering the wafer transport module until wafer #5 is at station
AFM layer for formation of the second AFM layer and wafer #1 has
been removed from the wafer transport module.
[0097] In other embodiments of the present invention, `n` number of
MTJs (more than two) may be desired on each wafer, and consequently
the cycle will therefore proceed n times through each of the
stations prior to step 1200.
[0098] This manner of manufacturing results in faster process
qualification and optimization, and, because of the frequency at
which wafer transport modules are shut down for maintenance and
repair, consequently results in increased manufacturing uptime.
This in turn results in higher throughput during manufacturing
(i.e. larger number of wafers/hr) and hence lower cost per wafer
and thereby lower cost for the finished memory products. In
addition, more than one process step can be combined into one
process chamber, e.g. if the process chamber has more than one
sputtering cathode.
[0099] Referring now to FIG. 10, the relevant layers of multi-state
current-switching magnetic memory element 1100 are shown, in
accordance with an embodiment of the present invention. Memory
element 1100 is shown to include bottom electrode 1101, on top of
which is formed seeding layer 1103, on top of which is formed
pinning layer 1105, on top of which is formed fixed layer 1107, on
top of which is formed barrier layer 1109, on top of which is
formed free layer 1111, on top of which is formed isolation layer
1113, on top off which is formed seeding layer 1115, on top of
which is formed pinning layer 1117, on top of which is formed fixed
layer 1119, on top of which is formed barrier layer 1121, on top of
which is formed free layer 1123, on top of which is formed a cap
layer 1124, on top of which is formed top electrode 1125.
[0100] Together, free layer 1111, barrier layer 1109, and fixed
layer 1107 form MTJ 1, or MTJ 1140, of stack 1100 Similarly free
layer 1123, barrier layer 1121, and fixed layer 1119 form MTJ 2, or
MTJ 1150, of stack 1100.
[0101] Top electrode 1125 and bottom electrode 1101 are made of
tantalum (Ta) in one embodiment of the present invention; however,
other conductive materials, which are capable of passing current to
MTJs 1140 and 1150, may be used. Materials such as TiW, Ti, CrTa,
NiTi, NiZr, AlCu may function as ideal electrode materials in
alternative embodiments of the present invention. Bottom electrode
1101 is built on a metal line, aluminum or copper, for example,
which is connected to a select transistor. In an alternative
embodiment of the present invention, bottom electrode 1101 may also
serve the purpose of seeding layer 1103, completely negating the
need to have seeding layer 1103, and guide the formation of pinning
layer 1105. In such an embodiment, pinning layer 1105 would be
formed directly on top of bottom electrode 1101.
[0102] Seeding layers 1103 and 1115 assist pinning layers 1105 and
1117, respectively, in obtaining the desired crystalline structure
at the atomic level. Seeding layers 1103 and 1115 are made of a
material, for example, tantalum, which has molecular structure that
induces the subsequently applied pinning layer to conform to a
specific atomic pattern. This pattern, or crystalline structure, is
required for pinning layers 1105 and 1117 to function as intended.
Additionally, other face-centered-cubic (fcc) non-magnetic-alloys,
such as that of NiFe--Cr, NiFe--Si, NiFeZr or NiFeTa, can be
inserted underneath the antiferromagnetic layer of the pinning
layer 1105 as well as 1117. This again results in a better
conformal growth at the atomic-level and thereby resulting in a
higher pinning field.
[0103] Pinning layers 1105 and 1117 are also known as synthetic
anti-ferromagnetic layers with the adjacent ferromagnetic layers
namely, 1107 and 1119, and function to keep the magnetic
orientation of fixed layer 1107 and fixed layer 1119, respectively,
static. In an embodiment of the current invention, pinning layers
1105 and 1117 are each further formed of three components or
sub-layers--ruthenium (Ru) layer 1130, cobalt iron (CoFe) layer
1132, and iron manganese (IrMn) layer 1134. IrMn layer 1134 is
formed on top of either seeding layer 1115, which will be discussed
in more detail shortly, or bottom electrode 1101. CoFe layer 1132
is formed on top of IrMn layer 1134, and Ru layer 1130 is formed on
top of the CoFe layer 1132. Similarly, the pinning layer 1105 is
made of multiple or sub-layers, in one embodiment of the present
invention. In this case, the IrMn is formed on top of the seeding
layer 1103, the CoFe layer is formed on top of the IrMn layer, and
the Ru layer is formed on top of the IrMn layer.
[0104] The typical thickness of CoFe layer 1132 is 2-10 nm thick,
the Ru layer 1130 is 0.6-1.0 nm thick, and IrMn layer 1134 is 5-25
nm thick. These thickness values provide the right combination to
ensure pinning of the fixed layer as well as ensuring lower
demagnetization field for making a high reliability as well as high
performance storage memory.
[0105] The magnetic polarity of pinning layers 1105 and 1117 are
permanently fixed by an annealing process that follows the complete
deposition of all layers of stack 1100. The process involves
heating of the entire wafer under conditions of a large single
direction magnetic field, for an extended period of time. In one
embodiment the annealing temperature is 375 degC and the external
uniaxial field is 6 kOe for over 2 hours.
[0106] The switching currents of free layers 1123 and 1111 are
dependent upon the composition, structure, size and geometry of
each respective layer. The switching current of free layers 1123
and 1111, of MTJs 1140 and 1150 respectively, is defined as the
amount of current that, when applied to memory element 1100, causes
the reversal of a free layer's magnetic moment. Each free layer in
an embodiment of the present invention has a unique switching
current. In an embodiment of the present invention the unique
switching currents are a consequence of the composition of free
layers 1123 and 1111; and the composition of free layers 1123 and
1111 is manipulated by changing the amount of reactive gas used to
form each free layer. In a yet another embodiment, a target
(sputtering process) containing oxide such as SiO2, TiO2 with the
magnetic alloy is deposited on top of the free-layers 1123, 1111
while the other layer is deposited using a target containing
substantially no (or small amount) of oxides. Thus, for example, if
free layer 1123 is composed of 30-60% oxide, and free layer 1111 is
composed of less than 10% oxide, and layers 1123 and 1111 are in a
stacked configuration, sharing the same size footprint
(100.times.200 nanometers (nm) in this case), free layer 1123's
switching current will be approximately 600 micro-amps (.mu.A),
while the switching current of the free layer 1111 will only be
approximately 1/3 of that, 200 .mu.A.
[0107] The unique switching currents of the free layers is a
consequence of the oxides imparting unique a microstructure to each
of the free layers, the microstructure being a direct function of
the amount of oxides present when the free layer was formed. After
deposition of both free layers 1123 and 1111 an annealing process
is performed in one embodiment of the present invention. The
annealing process, for example, involves heating of memory element
1100 to temperatures of 350.degree. C. for over 2 hours. The
annealing process results in the formation of non-conductive and
non-magnetic micro-channels within the free layers, which are
explained in detail in respect to free layer 104, of FIGS. 6(b) and
(c) of U.S. patent application Ser. No. 11/674,124, entitled
"Non-Uniform Switching Based Non-Volatile Magnetic Based Memory,"
by Ranjan, et al., filed Feb. 12, 2007, the contents of which is
incorporated herewith as if set out in full. In other embodiments
of the present invention, the micro-channels of free layers 1123
and 1111 can be formed by depositing one of the free-layers in
presence of reactive gases as described in patent application Ser.
No. 11/674,124, entitled "Non-Uniform Switching Based Non-Volatile
Magnetic Based Memory," by Ranjan, et al., filed Feb. 12, 2007. In
a yet another embodiment, one of the free-layers 1123 or 1111 is
made of CoFeB-X where X is chosen from one or more of: chromium
(Cr), tantalum (Ta), molybedenum (Mo), nickel (Ni), copper (Cu),
and the thickness is less than 80% of the other free-layer, and
thereby resulting in switching current ratios of over 2 between the
two individual magnetic tunnel junctions (MTJs). In a yet another
embodiment, one of the free-layers 1123 or 1111, typically the
topmost free layer has the effective average saturation
magnetization of less than 75% of the bottom free layer. In any
case, the free layers are designed in such a way that their
switching currents are different by at least a factor of two.
[0108] Table 3 further shows how stack 1100 has four possible
states, depending upon the amount and direction of current that is
applied to stack 1100. In the case of State I, or `00`, the
magnetic moments of the free layers 1111 and 1123 are in a
direction parallel to that of their respective fixed layers, 1107
and 1119, upon the application of approximately 600 .mu.A of
current to stack 1100. The application of approximately -600 .mu.A
of current results in the magnetic moment of both free layers 1111
and 1123 being switched to a state anti-parallel with their
respective fixed layers, 1107 and 1119, resulting state `11`.
[0109] In one embodiment of the present invention, current 1181 is
generally applied to the stack 1100 at the bottom electrode 1101
and through the intermediate layers to the top electrode 1125. In
another embodiment of the present invention, current 1180 is
applied to the top electrode 1125, through the intermediate layers,
to the bottom electrode 1101. The application of current with a
positive value (i.e., 600 .mu.A) is current that is applied in the
direction of current 1180; starting at top electrode 1125, passing
through the intermediate layers of memory element 1100, and exiting
at bottom electrode 1101. The application of current with a
negative value (i.e., -600 .mu.A) is current that is applied in the
direction of current 1181; starting at bottom electrode 1101,
passing through the intermediate layers of memory element 1100, and
exiting at top electrode 1125.
[0110] Alternatively, when only approximately 200 .mu.A and -200
.mu.A of current is applied to stack 1100, the magnetic moment of a
free layer of one MTJ is caused to be parallel with the magnetic
moment of the fixed layer, and the other is caused to be
anti-parallel. To further clarify, for example, approximately 200
.mu.A results in parallel magnetic moments in MTJ 1150, and
anti-parallel magnetic moments in MTJ 1140; whereas -200 .mu.A
results in anti-parallel magnetic moments in MTJ 1150 and parallel
magnetic moments in MTJ 1140--the states `01` and `10`
respectively.
[0111] The switching current applied to stack 1100 controls the
state of the magnetic moments of the free layers of MTJs 1140 and
1150, and thus the binary value represented within stack 1100. The
application of this switching current therefore results in what are
program and erase operations, and these operations are controlled
by a program and erase circuit. For further details regarding the
function of the program and erase circuit, see circuit 900 and
related discussion, in FIG. 8 of U.S. patent application Ser. No.
11/678,515, entitled "A High Capacity Low Cost Multi-State Magnetic
Memory," filed Feb. 23, 2007, by Ranjan et al, the contents of
which are incorporated herewith as though set forth in full.
[0112] Barrier layers 1109 and 1121 act as filters for electrons
with different spins, which gives rise to different amounts of
tunneling currents, thereby causing there to be two unique
resistance values for each MTJ, depending on the orientation of the
magnetic moment of the free layer in relation to that of its
respective fixed layer. In an embodiment of the present invention,
barrier layers 1109 and 1121 are composed of substantially
crystalline, having a (100) crystalline structure with (100)
indicating crystal planes substantially parallel to the film plane)
magnesium oxide (MgO). The MgO barrier layers 1109 and 1121 are
initially formed as crystalline layers of MgO whereas the adjacent
layers 1111 and 1107 for 1109 layer, and layers 1123 and 1119 to
the barrier layer 1121, are substantially amorphous of CoFeB alloy.
The annealing process previously discussed herein brings about a
change in the transformation in the amorphous layers into
crystalline layer of substantially cubic CoFeB alloy, such as one
having a (100) structure. This results in the formation of coherent
channels for tunneling of magnetic spins leading to high TMR
(tunneling magneto-resistance) ratio.
[0113] In one embodiment of the present invention, the barrier
layer of each MTJ has a different thickness, i.e., the thickness of
barrier layer 1109 is different from that of barrier layer 1121.
This difference in thickness causes MTJs 1140 and 1150 to have not
only two unique resistance values per MTJ, but entirely unique
resistance values from each other--thus causing stack 1100 to have
four different resistance values--two for each MTJ. A stack, for
example, with three MTJs would have a third barrier layer of a
third thickness, different from the other two, causing the
associated stack to then have six different resistance values--the
resistance value at any time being dependent upon the states of the
MTJs within.
[0114] Referring now to Table 4, resistance values of MTJs,
depending upon the MTJ state and barrier layer thickness, are
estimated. For example, in Scenario 1 the ratio of the thickness of
the barrier layer of one of the MTJs of a stack, to the thickness
of the barrier layer of another MTJ of the same stack is 1:1.2--or
a thickness of approximately 1 nm for layer 1109 and a thickness of
approximately 1.2 nm for barrier layer 1121. As a consequence of
the different barrier layer thicknesses, the resistance of MTJ1
(MTJ 1140) is approximately 400 ohms (.OMEGA.) when it is in state
0, and about 800% when it is in state 1. Accordingly, the
resistance for MTJ2 (MTJ 1150) will be about 600% when it is in
state 0, and about 1320% when it is in state 1. Scenarios 2 and 3
of Table 4 estimate other relative resistance values, depending
upon the thickness of the barrier layers.
[0115] The resistance of MTJs 1140 and 1150 is used to determine
the state of stack 1100 (i.e. 00, 01, 10 or 11) whenever a read
operation takes place. The total resistance of stack 1100, a
combination of the resistance of MJT 1140 and MJT 1150, is read by
a read circuit, which then compares the resistance of stack 1100 to
a series of reference circuits. The resistance of each MTJ in stack
1100 is dependent upon the MTJs state; that is, whether the free
layer and fixed layer are parallel or anti-parallel at that time. A
detailed description of the reading process of stack 1100 is
discussed in further detail in regards to read circuit 1000 within
U.S. patent application Ser. No. 11/678,515, entitled "A High
Capacity Low Cost Multi-State Magnetic Memory, filed on Feb. 23,
2007, by Ranjan et al.
[0116] Table 5 shows how the total resistance of stack 1100 changes
depending upon the state of MTJs 1140 and 1150 within. In scenario
1 of Tables 4 and 5, a 1:1.2 barrier layer thickness ratio, as
described prior, is used, and the total resistance of stack 1100 is
estimated to be 1000.OMEGA. with both MTJ 1140 and MTJ 1150 having
free layers with magnetic moments in a parallel direction relative
to their respective fixed layers, state 00. The total resistance of
stack 1100 is increased by about 400%, to 1400%, when switched to
state 01. Total resistance of stack 1100 can be further increased
by switching stack 1100 to states 01, or 11, for resistances off
about 1720.OMEGA. and 2120.OMEGA. respectively.
[0117] Each sequential increase in resistance of stack 1100 under
scenario 1 is approximately 300-400% greater than that of the prior
state. This roughly equal stepwise increase of each subsequent
resistance value is an ideal configuration, as it lends itself to a
more simpler and reliable reading circuit design.
[0118] Referring now to scenarios 2 and 3 of Table 5, it becomes
apparent that as the ratio of the barrier thickness increases, so
will the total resistance of stack 1100 while in any of its four
possible states. In scenario 3, where barrier layer 1121 of MTJ
1151 is twice as thick as barrier layer 1109 of MTJ 1140, i.e. 2 nm
and 1 nm thick, the total resistance of the circuit with both MTJs'
magnetic moments being in parallel (state 00) is
2400.OMEGA.--significantly more than the maximum resistance of
stack 1100 with a barrier layer ratio of 1:1.2; even when the free
layers of MTJs 1140 and 1150 have magnetic moments in anti-parallel
states relative to their respective fixed layers. The remaining
total resistances values of stack 1100 under the scenario of a 2:1
barrier layer thickness ratio is 2800 in state 01, then 6400% in
state 10, and 6800% in state 11. The relatively consistent stepwise
increase in resistance, as experienced in scenario 1, is lost in
scenario 3, and instead the total resistance increases in an
irregular manner although monotonic--from 400-3600% between
subsequent states. Such radical differences may make the circuit
more complicated.
[0119] In an embodiment of the present invention, barrier layers
1109 and 1121 are composed substantially of a non-magnetic
material, for example, magnesium oxide (MgO). In alternative
embodiments of the present invention, barrier layers 1109 and 1121
are composed of one or more of the following compounds--aluminum
oxide (Al2O3), titanium oxide (TiO2), magnesium oxide (MgOx),
ruthenium oxide (RuO), strontium oxide (SrO), Zinc oxide (ZnO).
Isolation layer 1113 is typically 2-200 nm thick, with a preferred
thickness range of 2-50 nm. Isolation layer 1113 is formed on top
of free layer 1111 of MTJ 1140, and isolates MTJs 1140 and 1150
from each other. The isolation of MTJ 1140 from 1150 serves three
purposes: (1) magnetic isolation by reducing magnetostatic
interaction, (2) microstructure isolation by separating the seeding
effect, and (3) separation of layer states.
[0120] If additional MTJs were to be formed on stack 1100, an
additional isolation layer would be formed below the seeding layer
of each of the additional MTJs, and on top of the free layer of the
MTJs below each addition MTJ. It should be noted that the most
preferred choice of materials for isolation layer 1113 is an
amorphous non-magnetic alloy, for example, nickel niobium (NiNb),
nickel phosphorous (NiP), nickel vanadium (NiV), nickel boron
(NiB), or copper zirconium (CuZr); a crystalline non-magnetic alloy
may also work.
[0121] While the embodiments described here so far have their
magnetic moments in-plane, i.e., substantially parallel to the
surface planes, this invention also applies to magnetic memory
cells having substantially perpendicular magnetic orientation where
the magnetic momemnts of the free- and fixed layers 1107, 1111,
1119 and 1123 are substantially perpendicular to the film plane. Of
course, the choice of the alloys for these layers as well as
adjacent layers will be different in order to induce and support
the perpendicular magnetic orientation in these layers.
[0122] Although the present invention has been described in terms
of specific embodiment, it is anticipated that alterations and
modifications thereof will no doubt become apparent to those more
skilled in the art. It is therefore intended that the following
claims be interpreted as covering all such alterations and
modification as fall within the true spirit and scope of the
invention.
TABLE-US-00001 TABLE 1 MLC cell with two or more stacked MTJ with
different anisotrophy. I density 100 n = 2 Parallel Anti-parallel
Anisotrophy 2 R(K .OMEGA.) large 1 2 ratio Large Small R(K .OMEGA.)
small 2 4 Fixed layers Free layer 1 Free layer 2 State Total R Prog
I (uA) .fwdarw. .fwdarw. .fwdarw. 1 3 200 .fwdarw. .fwdarw. .rarw.
2 5 -50 .fwdarw. .rarw. .rarw. 3 6 -200 .fwdarw. .rarw. .fwdarw. 4
4 50
TABLE-US-00002 TABLE 2 MLC cell with two or more MTJs side by side
with different anisotrophy. I density 50 n = 2 Parallel
Anti-parallel Anisotrophy 1.3 R(K .OMEGA.) large 3 6 ratio Small
Large R(K .OMEGA.) small 3.9 7.8 Fixed laye Free layer Free layer
State Total R Prog I (uA) .fwdarw. .fwdarw. .fwdarw. 1 1.70 -134.5
.fwdarw. .fwdarw. .rarw. 2 2.36 50 .fwdarw. .rarw. .rarw. 3 3.39
134.5 .fwdarw. .rarw. .fwdarw. 4 2.17 -50 From one state to another
1 to 2 2 to 3 3 to 4 R differences 0.67 1.03 1.22 0.47 between
different states indicates data missing or illegible when filed
TABLE-US-00003 TABLE 3 III IV I II I = -600 I = -200 I = 600 .mu.A
I = 200 .mu.A .mu.A .mu.A MTJ1 Free .fwdarw. .rarw. .rarw. .fwdarw.
Fixed .fwdarw. .fwdarw. .fwdarw. .fwdarw. MTJ2 Free .fwdarw.
.fwdarw. .rarw. .rarw. Fixed .fwdarw. .fwdarw. .fwdarw. .fwdarw.
State 0 0 0 1 1 1 1 0
TABLE-US-00004 TABLE 4 MgO MTJ1 MTJ2 Tunnel R1 (.OMEGA.) R2
(.OMEGA.) R3 (.OMEGA.) R4 (.OMEGA.) Scenario 1 1.0:1.2 400 800 600
1320 Scenario 2 1.2:1.5 600 1320 800 2000 Scenario 3 1.0:2.0 400
800 2000 6000 State 0 1 0 1
TABLE-US-00005 TABLE 5 Total Stack Resistance by State (in .OMEGA.)
00 01 10 11 Scenario 1 1000 1400 1720 2120 Scenario 2 1400 2120
2600 3320 Scenario 3 2400 2800 6400 6800
* * * * *