U.S. patent application number 12/076084 was filed with the patent office on 2008-09-18 for column sample-and-hold cell for cmos aps sensor.
Invention is credited to Giuseppe Rossi.
Application Number | 20080225149 12/076084 |
Document ID | / |
Family ID | 33158554 |
Filed Date | 2008-09-18 |
United States Patent
Application |
20080225149 |
Kind Code |
A1 |
Rossi; Giuseppe |
September 18, 2008 |
Column sample-and-hold cell for CMOS APS sensor
Abstract
A sample and hold readout circuit, and method of operation which
minimizes fixed pattern noise during a read out operation. The
circuit improves the consistency of the pixel to pixel output of
the pixel array and increases the dynamic range of the pixel
output. This is accomplished by eliminating the crowbar between the
storage elements in the sample and hold circuit. Switches are added
to isolate the sample and hold circuit from the column line coupled
to the pixel array and to short the front plates of the capacitors
together. Activating these switches allows the signals stored in
the sample and hold circuit to be transferred downstream without
the use of a crowbar switch.
Inventors: |
Rossi; Giuseppe; (Pasadena,
CA) |
Correspondence
Address: |
DICKSTEIN SHAPIRO LLP
1825 EYE STREET, NW
WASHINGTON
DC
20006
US
|
Family ID: |
33158554 |
Appl. No.: |
12/076084 |
Filed: |
March 13, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10413365 |
Apr 15, 2003 |
7365784 |
|
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12076084 |
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Current U.S.
Class: |
348/308 ;
348/294; 348/E3.021; 348/E5.091 |
Current CPC
Class: |
H04N 5/3658 20130101;
H04N 5/3575 20130101; H04N 5/3745 20130101 |
Class at
Publication: |
348/308 ;
348/294; 348/E05.091 |
International
Class: |
H04N 5/335 20060101
H04N005/335; H04N 3/14 20060101 H04N003/14 |
Claims
1. A sample and hold circuit for an imager, comprising: a selection
circuit for selectively coupling a common node to a pixel output
column line and for sequentially coupling a first and second
storage element to said common node to sample and store respective
pixel output signals, said selection circuit for selectively
uncoupling said common node from said pixel output column line and
for selectively coupling said first and second storage elements
through said common node to transfer said stored respective pixel
output signals to an output stage.
2. The sample and hold circuit of claim 1, wherein said selection
circuit further comprises: a first switch, disposed between said
common node and said column line.
3. The sample and hold circuit of claim 2, wherein said selection
circuit further comprises: a second switch, disposed between said
common node and said first storage element; and a third switch,
disposed between said common node and said second storage
element.
4. The sample and hold circuit of claim 3, wherein said selection
circuit selectively couples said common node to a first
voltage.
5. The sample and hold circuit of claim 4, wherein said first
voltage is a load voltage.
6. (canceled)
7. (canceled)
8. A sample and hold circuit for an imager, comprising: a first
switch for selectively coupling a common node to an imager array
column line; a first storage circuit for sampling and holding a
first signal from said imager array column line, said first storage
circuit having an input side and an output side; a second switch
for selectively coupling the input side of said first storage
circuit to said common node; a second storage circuit for sampling
and holding a second signal from said imager array column line,
said second storage circuit having an input side and an output
side; and a third switch for selectively coupling the input side of
said second storage circuit to said common node.
9. The sample and hold circuit of claim 8, further comprising: a
fourth switch for selectively coupling the output side of said
first storage circuit to an output stage; and a fifth switch for
selectively coupling the output side of said second storage circuit
to said output stage.
10. (canceled)
11. (canceled)
12. (canceled)
13. (canceled)
14. A sample and hold circuit for an imager, comprising: a
selection circuit for selectively coupling a common node to an
imager column line and for sequentially coupling a first and second
storage element to said common node to sample and store respective
imager output signals, wherein said selection circuit further
comprises: a first switch, disposed between said common node and
said imager column line; a second switch, disposed between said
common node and said first storage element; a third switch,
disposed between said common node and said second storage element;
and a fourth switch for coupling said common node to a load
voltage.
15. The circuit of claim 14, wherein said first and fourth switches
being selected.
16. (canceled)
17. (canceled)
18. A sample and hold circuit for an imager, comprising: a
selection circuit for selectively coupling a common node to an
imager column line and for sequentially coupling a first and second
storage element to said common node to sample and store respective
imager output signals, wherein said selection circuit further
comprises: a first switch, disposed between said common node and
said imager column line; a second switch, disposed between said
common node and said first storage element; a third switch,
disposed between said common node and said second storage element;
a fourth switch for coupling said common node to a load voltage;
and wherein said second and third switches being sequentially
selected when said first switch being selected, said second and
third switches being substantially contemporaneously selected when
said first switch not being selected.
19. A sample and hold circuit for an imager, comprising: a
selection circuit for selectively coupling a common node to an
imager column line and for sequentially coupling a first and second
storage element to said common node to sample and store respective
imager output signals, wherein said selection circuit further
comprises: a first switch, disposed between said common node and
said imager; a second switch, disposed between said common node and
said first storage element; a third switch, disposed between said
common node and said second storage element; and a fourth switch
for coupling said common node to a load voltage.
20. The circuit of claim 19, wherein said first and fourth switches
being selected.
21. (canceled)
22. (canceled)
23. (canceled)
24. (canceled)
25. (canceled)
26. (canceled)
27. (canceled)
28. (canceled)
29. (canceled)
30. (canceled)
31. (canceled)
32. (canceled)
33. (canceled)
34. (canceled)
35. A semiconductor imaging device, comprising: a pixel array
imager comprising: a sample and hold circuit, comprising: a
selection circuit for selectively coupling a common node to a pixel
output and for sequentially coupling a first and second storage
element to said common node to sample and store respective pixel
output signals.
36. The semiconductor imaging device of claim 35, wherein said
selection circuit further comprises: a switch, disposed between
said common node and said pixel.
37. The semiconductor imaging device of claim 36, wherein said
selection circuit further comprises: a second switch, disposed
between said common node and said first storage element; and a
third switch, disposed between said common node and said second
storage element.
38. The semiconductor imaging device of claim 37, wherein said
selection circuit selectively couples said common node to a first
voltage.
39. The semiconductor imaging device of claim 38, wherein said
first voltage is a load voltage.
40. A processor system, comprising: a central processing unit;
array imager coupled to said central processing unit, said imager
comprising: a sample and hold circuit, comprising: a selection
circuit for selectively coupling a common node to a pixel output
column line and for sequentially coupling a first and second
storage element to said common node to sample and store respective
pixel output signals, said selection circuit for selectively
uncoupling said common node from said pixel output column line and
for selectively coupling said first and second storage elements
through said common node to transfer said stored respective pixel
output signals to an output stage.
41. The processor of claim 40, wherein said selection circuit
further comprises: a first switch, disposed between said common
node and said column line.
42. The processor of claim 41, wherein said selection circuit
further comprises: a second switch, disposed between said common
node and said first storage element; and a third switch, disposed
between said common node and said second storage element.
43. The processor of claim 42, wherein said selection circuit
selectively couples said common node to a first voltage.
44. The processor of claim 43, wherein said first voltage is a load
voltage.
45. (canceled)
46. (canceled)
47. A sample and hold circuit for an imager, comprising: a
switching circuit for selectively coupling a sample and hold
circuit to a pixel output column line and for sequentially coupling
first and second storage elements to said pixel output column line
through a first and second switch, respectively, to sample and
store respective pixel output signals, said switching circuit for
selectively uncoupling said sample and hold circuit from said pixel
output column line.
48. The sample and hold circuit of claim 47, wherein said switching
circuit further comprises a third switch, disposed between said
first and second switches and said pixel output column line.
49. The sample and hold circuit of claim 48, further comprising: a
fourth switch for selectively coupling a first voltage to said
first and second storage elements through said second and third
switches, respectively.
50. The sample and hold circuit of claim 49, wherein said first
voltage is a load voltage.
51. A method of operating a sample and hold circuit in an imaging
pixel array, said method comprising: selectively connecting a
selected imager array column line to said sample and hold circuit;
selectively coupling said first storage circuit to said selected
column line; storing a first signal from said selected column line
in said first storage circuit; selectively coupling said second
storage circuit to said selected column line; and storing a second
signal from said selected column line in said second storage
circuit.
52. The method of claim 51, further comprising: selectively
disconnecting said selected column line from said first storage
circuit, after said first signal is stored; and selectively
disconnecting said selected column line from said second storage
circuit, after said second signal is stored.
53. The method of claim 52, further comprising: selectively
disconnecting said sample and hold circuit from said selected
column line, after said first and second signals are stored.
54. The method of claim 53, further comprising: selectively
contemporaneously coupling input sides of said first and the input
side of said second storage circuits while selectively coupling
output sides of said first and second storage circuits to an output
stage.
55. The method of claim 54, wherein the selective coupling of the
said first and second storage circuits to said output stage is
controlled by a common signal.
56. The method of claim 55, further comprising the step of
initially coupling a clamp voltage to said first and second storage
circuits.
57. The method of claim 56, further comprising the step of coupling
a load voltage to said first and second storage circuits prior to
said storing of said first and said second signals.
Description
[0001] This application is a continuation application of U.S.
application Ser. No. 10/413,365, filed Apr. 15, 2003, and claims
domestic priority from the same. the complete disclosure of this
prior application is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The invention relates generally to semiconductor imaging
devices and in particular to an imaging device which can be
fabricated using a standard CMOS process. Particularly, the
invention relates to a CMOS active pixel sensor (APS) imager having
an array of pixel cells and to the column circuitry for reading the
cells.
BACKGROUND OF THE INVENTION
[0003] There is a current interest in CMOS active pixel imagers for
use as low cost imaging devices. An exemplary pixel circuit of a
CMOS active pixel sensor (APS) is described below with reference to
FIG. 1. Active pixel sensors can have one or more active
transistors within the pixel unit cell, can be made compatible with
CMOS technologies, and promise higher readout rates compared to
passive pixel sensors. The pixel circuit of FIG. 1, designated
generally by reference number 100, includes an exemplary pixel cell
150, which is a 3T APS cell, where the 3T is commonly used in the
art to designate use of three transistors to operate the pixel. The
3T pixel cell 150 includes a photodiode 162, reset transistor 184,
source follower transistor 186, and a row select transistor 188. It
should be understood that while FIG. 1 shows the circuitry for
operation of a single pixel, in practical use there will be an M by
N array of identical pixels arranged in rows and columns, with the
pixels of the array accessed using row and column select circuitry,
as described in more detail below.
[0004] The photodiode 162 of the 3T pixel cell 150 converts
incident photons to electrons which collect at node A. The source
follower transistor 186 has its gate connected to node A and thus
amplifies the signal appearing at node A. The signal amplified by
transistor 186 is passed on a column line 170 to the readout
circuitry when a particular row containing the cell 150 is selected
by the row selection transistor 188. The photodiode 162 accumulates
a photo-generated charge in a doped region of the substrate. It
should be understood that the CMOS imager might include a photogate
or other photoconversion device, in lieu of a photodiode, for
producing photo-generated charge.
[0005] A reset voltage source Vrst is selectively coupled through
reset transistor 184 to node A. The gate of the reset transistor
184 is coupled to a reset control line 191 which serves to control
the reset operation (i.e., Vrst is connected to node A). Vrst may
be Vdd. The row select control line 160 is coupled to all of the
pixels of the same row of the array. Voltage source Vdd is coupled
to a source follower transistor 186 and its output is selectively
coupled to a column line 170 through the row select transistor 188.
Although not shown in FIG. 1, the column line 170 is coupled to all
of the pixels of the same column of the array and typically has a
current load at its lower end. The gate of the row select
transistor 188 is coupled to the row select control line 160.
[0006] As known in the art, a two step process is used to read a
value from pixel 150. During a charge integration period, the
photodiode 162 converts photons to electrons which collect at the
node A. The charges at node A are amplified by source follower
transistor 186 and selectively passed to the column line 170 by the
row access transistor 188. During a reset period, node A is reset
by turning on the reset transistor 184, such that the reset voltage
Vrst is applied to node A and read out to the column line 170 by
the source follower transistor 186 through the activated row select
transistor 188. As a result, the two different values--the reset
voltage Vrst and the image signal voltage Vsig--are readout from
the pixel and sent by the column line 170 to the readout circuitry
where each is sampled and held for further processing as known in
the art.
[0007] All pixels in a row are read out simultaneously onto
respective column lines 170 and the column lines are activated in
sequence for reset and signal voltage read out. The rows of pixels
are also read out in sequence onto the respective column lines.
[0008] FIG. 2 shows a CMOS active pixel sensor integrated circuit
chip that includes a pixel array 230 and a controller 232 which
provides timing and control signals to enable the reading out of
signals stored in the pixels in a manner commonly known to those
skilled in the art. Exemplary arrays have dimensions of M.times.N
pixels, with the size of the array 230 depending on a particular
application. The imager is read out a row at a time using a column
parallel readout architecture. The controller 232 selects a
particular row of pixels in the array 230 by controlling the
operation of row addressing circuit 234 and row drivers 240. Charge
signals stored in the selected row of pixels are provided on the
column lines 170 (FIG. 1) to a readout circuit 242 in the manner
described above. The pixel signal read from each of the columns
then can be read out sequentially using a column addressing circuit
244. The differential signal, Vdiff=(Vrst-Vsig), corresponds to the
reset signal minus the integrated charge signal and is provided by
the outputs Vout2, Vout1 of the readout circuit 242.
[0009] FIG. 3 more clearly shows the rows and columns 349 of pixels
350. Each column includes multiple rows of pixels 350. Signals from
the pixels 350 in a particular column can be read out to a readout
circuit 351 associated with that column. The read out circuit 351
includes sample and hold circuitry for acquiring the pixel reset
(Vrst) and integrated charge signals (Vsig). Signals stored in the
readout circuits 351 can be read sequentially, column-by-column, to
an output stage 354 which is common to the entire array of pixels
330. The analog output signals can then be sent, for example, to a
differential analog circuit and which subtracts the reset and
integrated charge signals, (e.g., combines the two voltages and
determines the difference between the circuits) and sends them to
an analog-to-digital converter (ADC), or the reset and integrated
charge signals are each supplied to the analog-to-digital
converter.
[0010] FIG. 4 shows a sample and hold readout circuitry contained
in column readout circuit 351. The FIG. 4 circuit samples and holds
the Vsig and Vrst values for subsequent use by an output stage 354
(FIG. 3). For example, a Vsig from a desired pixel ("Vsig1")
coupled to a column line 470 is stored on capacitor 420 and a Vrst
from the desired pixel ("Vrst1") is stored on capacitor 418. Then
the Vrst and Vsig signals for the desired pixel are readout to an
output stage 354 (FIG. 3).
[0011] As seen in FIG. 4, the column line 470 is selectively
coupled through SH_R switch 410 to the front side of capacitor 418.
The backside of capacitor 418 is selectively coupled through switch
426 to a first input to output stage 354. The front side of
capacitor 418 is also selectively coupled through crowbar 411,
which includes a switch 413, to the front side of capacitor 420.
The column line 470 is also selectively coupled through SH_S switch
412 to the front side of capacitor 420. The backside of capacitor
420 is selectively coupled through switch 428 to a second input to
output stage 354. A clamp voltage Vcl (e.g., Vclamp) is selectively
coupled to the backside of capacitor 418. Vcl (e.g., Vclamp) is
selectively coupled through a switch 415 to the backside of
capacitor 418. Vcl is also selectively coupled through another
switch 417 to the backside of capacitor 420. A line voltage, e.g.,
a load voltage, Vln is selectively coupled through switch 436 and
switch 410 to the front side of capacitor 418. A line voltage Vln
is also selectively coupled through switch 436 and switch 412 to
the front side of capacitor 420. The line voltage Vln is typically
coupled to a current source for biasing the source follower
transistor of the selected pixel.
[0012] The operation of the FIG. 4 circuit is now described with
reference to the simplified signal timing diagram of FIG. 5
(assuming a readout from a 3T pixel). To store Vsig and Vrst from
the desired pixel, a pulse signal CLAMP is applied which
temporarily closes the switches 415, 417 and couples a Vclamp
voltage to the back of the capacitors 418, 420 placing a charge on
the respective back sides of respective capacitors. A pulse signal
Vln_en is also applied which couples the desired pixel to a Vln
voltage through the column line 470. To store Vsig on capacitor 420
while the pixel is in the signal sampling phase, a pulse signal
SH_S is applied which temporarily closes the switch 412 and couples
the desired pixel with the front side of capacitor 420 through the
column line 470. Thus, Vsig is stored on capacitor 420. After the
desired pixel is pulsed by a pixel reset signal, the pixel is in
reset signal sampling phase. To store Vrst on capacitor 418 pulse
signal SH_R is applied which temporarily closes the switch 410 and
couples the desired pixel with the front side of capacitor 418
through the column line 470. Thus, Vrst is stored on capacitor
418.
[0013] To transfer Vsig and Vrst through the output stage 354 (FIG.
3), pulse signals COLSEL and CB, are applied which temporarily
close switches 413, 426, and 428 and forces the signal stored on
the back side of the respective capacitor 418, 420 through output
stage 354. Thus, the amplified Vsig and Vrst signals are forced
downstream to output stage 354.
[0014] One issue associated with the APS CMOS imaging systems is
that of fixed pattern noise, which is type of distortion in the
image captured by the imaging system. One source of fixed pattern
noise is due to imperfections in the sample and hold circuit. The
layout of the sample and hold circuit contributes to the amount of
fixed pattern noise. In particular, the crowbar switch in the
sample and hold circuit, i.e., 413 in FIG. 4, introduces a
potential asymmetry in the cell with different coupling strengths
among the sampling capacitor nodes. Due to the delta sampling
nature of the timing scheme, floating capacitor plates are still
present in the circuit with a direct coupling to each other and
this presents a detrimental effect for any further improvement to
the sensor fixed pattern noise. Additionally, the crowbar switch
acts as a memory cell for the common mode voltage of the previously
read-pixel belonging to the earlier row.
[0015] A sample and hold circuit having a reduced fixed pattern
noise is desired.
SUMMARY OF THE INVENTION
[0016] The present invention provides an improved sample and hold
readout circuit and method of operation which reduces fixed pattern
noise during a read out operation. The circuit improves the
consistency of the pixel to pixel output of the pixel array and
increases the dynamic range of the pixel output. This is
accomplished by eliminating the crowbar switch between the storage
areas in the sample and hold circuit. Additionally, a switch is
added further isolating the sample and hold circuit from the column
line coupled to the pixel array. In this manner, the signals stored
in the sample and hold circuit are transferred downstream by
isolating the sample and hold circuit from the global column line
and then using the sampling switches SH_R and SH_S to short the
front plates of the capacitors together. This has the additional
advantage of creating a more symmetrical sample and hold
circuit.
[0017] These and other features and advantages of the invention
will be more readily understood from the following detailed
description of the invention which is provided in connection with
the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic diagram of a prior art active
pixel;
[0019] FIG. 2 is a block diagram of a prior art CMOS active sensor
chip;
[0020] FIG. 3 is a block diagram of a prior art array of active
pixels and an associated readout circuit;
[0021] FIG. 4 is a schematic diagram of a prior art sample and hold
circuit;
[0022] FIG. 5 is a simplified timing diagram associated with the
circuitry of FIG. 4;
[0023] FIG. 6 is a schematic diagram of a sample and hold circuit
in accordance with an exemplary embodiment of the invention;
[0024] FIG. 7 is a simplified timing diagram associated with the
circuitry of FIG. 6; and
[0025] FIG. 8 is a block diagram representation of a
processor-based system incorporating a CMOS imaging device in
accordance with an exemplary embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0026] In the following detailed description, reference is made to
the accompanying drawings, which form a part hereof, and in which
is shown by way of illustration specific embodiments in which the
invention may be practiced. These embodiments are described in
sufficient detail to enable those of ordinary skill in the art to
make and use the invention, and it is to be understood that
structural, logical or other changes may be made to the specific
embodiments disclosed without departing from the spirit and scope
of the present invention.
[0027] The present invention eliminates the crowbar switch and
utilizes the sampling switches to short the front plates of the
capacitors together when performing a read out from the sample and
hold circuit.
[0028] An embodiment of the invention is shown and described with
reference to FIGS. 6 and 7. The sample and hold circuit 351' of
FIG. 6 is different from the sample and hold circuit 351 of FIG. 4
in several respects: the crowbar 411 circuit including crowbar
switch 413 is eliminated and a COLSEL_global switch 652 is added.
Additionally, the SH_R switch 610 is controlled by either a SH_R or
a transfer control signal, e.g., the signal resulting from AND'ing
CB and COL_SEL signal. The SH_S switch 612 is controlled by either
a SH_S signal or a transfer control signal.
[0029] As seen in FIG. 6, a column line 670 is selectively coupled
through a COLSEL_global switch 652 to a node 611. Node 611 is
coupled through a switch 610 to the input side of capacitor 618.
The switch 610 is closed when either a SH_R or a CB and COL_SEL
pulse is enabled. The output side of capacitor 618 is selectively
coupled through switch 626 to a first input to output stage 354.
Node 611 is also selectively coupled through a switch 612 to the
input side of capacitor 620. The switch 612 is closed when either a
SH_S or a CB and COL_SEL pulse is. enabled. The output side of
capacitor 620 is selectively coupled through switch 628 to a second
input to output stage 354. A clamp voltage Vcl (e.g., Vclamp) is
selectively coupled to the output side of capacitor 618 through
switch 615. Vcl is also selectively coupled through switch 617 to
the output side of capacitor 620. A line voltage Vln is selectively
coupled through switch 636 and switch 610 to the input side of
capacitor 618. A line voltage Vln is also selectively coupled
through switch 636 and switch 612 to the input side of capacitor
620.
[0030] The operation of the FIG. 6 circuit is now described with
reference to the simplified signal timing diagram of FIG. 7
(assuming a readout from a 3T pixel). To store Vsig and Vrst from
the desired pixel, a pulse signal CLAMP is applied which
temporarily closes the switches 615, 617 and couples a Vclamp
voltage with the output side of the capacitors 618, 620 and places
a charge on the respective output side of respective capacitors. A
pulse signal COLSEL_global is also applied which closes switch 652
and couples node 611 to the column line 670. A pulse signal Vln_en
is also applied which couples node 611, and the desired pixel
through the column line 670 and node 611, to a Vln voltage.
[0031] To store Vsig on capacitor 620 while the pixel is in the
signal sampling phase, a pulse signal SH_S is applied which
temporarily closes the switch 612 and couples the desired pixel
with the input side of capacitor 620 through the column line 670.
The input side of capacitor 618 is also coupled to the Vln voltage
through switches 610 and 636. Thus, Vsig is stored on capacitor
620. After Vsig is stored, switch 610 is opened, thereby isolating
the input side of capacitor 618 from the desired pixel and the Vln
voltage.
[0032] After the desired pixel is pulsed by a pixel reset signal,
the pixel is in reset signal sampling phase. To store Vrst on
capacitor 618, pulse signal SH_R is applied, which temporarily
closes the switch 610 and couples the desired pixel with the front
side of capacitor 618 through the column line 670. The input side
of capacitor 620 is also coupled to the Vln voltage through
switches 612 and 636. Thus, Vrst is stored on capacitor 618. After
Vrst is stored, switch 612 is opened, thereby isolating the input
side of capacitor 620 from the desired pixel and the Vln voltage
and switch 652 and 636 are opened, isolating the common node 611
from the column line 670 and Vln voltage. Alternatively, switch 612
remains closed and switches 652 and 636 are opened, thereby
isolating the input side of capacitor 620 from the desired pixel
and the Vln voltage.
[0033] To transfer Vsig and Vrst through the output stage 354 (FIG.
3) with switches 652 and 636 open, a pulse signal COLSEL is applied
which temporarily closes switches 626 and 628. Then a pulse signal
CB is applied which temporarily closes SH_R/CB-COL_SEL,
SH_S/CB-COL_SEL switches 610 and 612, thereby shorting the input of
capacitor 618 to the input side of capacitor 620 and forcing the
signal stored on the output side of the respective capacitor 618,
620 through output stage 354. Thus, the amplified Vsig and Vrst
signals are forced downstream to output stage 354.
[0034] The method and apparatus aspects of the invention are
embodied in an image device 1140 shown in FIG. 8 which provides an
image output signal. The image output signal can also be applied to
a processor system 800, also illustrated in FIG. 8. A processor
based system, such as a computer system, for example, generally
comprises a central processing unit (CPU) 1110, for example, a
microprocessor, that communicates with one or more input/output
(I/O) devices 1150 over a bus 1170. The CPU 1110 also exchanges
data with random access memory (RAM) 1160 over bus 1170, typically
through a memory controller. The processor system may also include
peripheral devices such as a floppy disk drive 1120 and a compact
disk (CD) ROM drive 1130 which also communicate with CPU 1110 over
the bus 1170. Imager device 1140 is coupled to the processor system
and includes a pixel storage and readout circuit as described along
with respect to FIG. 6.
[0035] While the invention has been described and illustrated with
reference to specific exemplary embodiments, it should be
understood that many modifications and substitutions can be made
without departing from the spirit and scope of the invention.
Although the embodiments discussed above describe a specific
circuit layout with a specific number of transistors, photodiodes,
switches, conductive lines, the present invention is not so
limited. Furthermore, many of the above embodiments described are
shown with respect to the operation of the sample and hold of a
desired pixel that is a 3T pixel, the spirit of the invention is
not limited to 3T pixels. Accordingly, the invention is not to be
considered as limited by the foregoing description but is only
limited by the scope of the claims.
* * * * *