U.S. patent application number 12/018721 was filed with the patent office on 2008-07-24 for reduced electric field dmos using self-aligned trench isolation.
This patent application is currently assigned to Atmel Corporation. Invention is credited to Volker Dudek, Michael Graf, Gayle W. Miller.
Application Number | 20080173940 12/018721 |
Document ID | / |
Family ID | 37678302 |
Filed Date | 2008-07-24 |
United States Patent
Application |
20080173940 |
Kind Code |
A1 |
Miller; Gayle W. ; et
al. |
July 24, 2008 |
REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
Abstract
A method of fabricating an electronic device and the resulting
electronic device. The method includes forming a gate oxide on an
uppermost side of a silicon-on-insulator substrate; forming a first
polysilicon layer over the gate oxide; and forming a first silicon
dioxide layer over the first polysilicon layer. A first silicon
nitride layer is then formed over the first silicon dioxide layer
followed by a second silicon dioxide layer. Shallow trenches are
etched through all preceding dielectric layers and into the SOI
substrate. The etched trenches are filled with another dielectric
layer (e.g., silicon dioxide) and planarized. Each of the preceding
dielectric layers are removed, leaving an uppermost sidewall area
of the dielectric layer exposed for contact with a later-applied
polysilicon gate area. Formation of the sidewall area assures a
full-field oxide thickness thereby producing a device with a
reduced-electric field and a reduced capacitance between gate and
drift regions.
Inventors: |
Miller; Gayle W.; (Colorado
Springs, CO) ; Dudek; Volker; (Brackenheim, DE)
; Graf; Michael; (Leonberg, DE) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG & WOESSNER / ATMEL
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Atmel Corporation
San Jose
CA
|
Family ID: |
37678302 |
Appl. No.: |
12/018721 |
Filed: |
January 23, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11188921 |
Jul 25, 2005 |
7348256 |
|
|
12018721 |
|
|
|
|
Current U.S.
Class: |
257/339 ;
257/340; 257/E21.427; 257/E21.628; 257/E29.021; 257/E29.04;
257/E29.133; 257/E29.256; 257/E29.268 |
Current CPC
Class: |
H01L 29/086 20130101;
H01L 29/0847 20130101; H01L 21/823481 20130101; H01L 29/7835
20130101; H01L 29/0653 20130101; H01L 29/42368 20130101; H01L
29/66689 20130101; H01L 29/7824 20130101; H01L 29/66659
20130101 |
Class at
Publication: |
257/339 ;
257/340; 257/E29.256 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. An electronic device comprising: a gate area having a gate oxide
and a control gate; and a shallow trench isolation feature formed
proximate to the gate area and comprised of a trench-fill
dielectric having a full field oxide thickness and an uppermost
portion formed substantially parallel to and at a higher
cross-sectional elevation than an active portion of the gate oxide,
the shallow trench isolation feature being coupled to at least a
portion of the control gate.
2. The electronic device of claim 1 wherein the device is
characterized as lacking a gate wraparound.
3. The electronic device of claim 1 wherein the control gate is
comprised of a first and a second polysilicon layer, the first
polysilicon layer having a first face coupled to the gate oxide and
a second face coupled to the second polysilicon layer.
4. The electronic device of claim 3 wherein the second face of the
first polysilicon layer is substantially parallel to and at a lower
cross-sectional elevation than the uppermost portion of the shallow
trench isolation feature.
5. The electronic device of claim 1 wherein the shallow trench
isolation feature is formed in a silicon layer of a
silicon-on-insulator substrate.
6. A semiconductor electronic device comprising: a transistor
having a source, a drain, and a gate area, the gate area having a
control gate and a gate oxide, the gate area being characterized in
that a gate wraparound area is absent; and a shallow trench
isolation feature comprised of a trench-fill dielectric having a
full-field oxide thickness, the full-field oxide thickness having
an uppermost sidewall area of the trench-fill dielectric coupled to
at least a portion of the control gate.
7. The semiconductor electronic device of claim 6 wherein the
shallow trench isolation feature further comprises an uppermost
portion formed substantially parallel to and at a higher
cross-sectional elevation than an active portion of the gate
oxide.
8. The semiconductor electronic device of claim 6 wherein the
control gate is comprised of a first and a second polysilicon
layer, the first polysilicon layer having a first face located
proximate to the gate oxide and a second face located proximate to
the second polysilicon layer.
9. The semiconductor electronic device of claim 8 wherein the
second face of the first polysilicon layer is substantially
parallel to and at a lower cross-sectional elevation than an
uppermost portion of the shallow trench isolation feature.
10. The semiconductor electronic device of claim 6 wherein the
shallow trench isolation feature is formed in an n-well.
11. The semiconductor electronic device of claim 6 wherein the
shallow trench isolation feature is formed in a silicon layer of a
silicon-on-insulator substrate.
12. An MOS transistor comprising: a source, a drain, and a gate
area, the gate area having a control gate, a gate oxide, and
characterized such that a gate wraparound area is absent; and a
shallow trench isolation feature comprised of a trench-fill
dielectric having a full-field oxide thickness, the full-field
oxide thickness having an uppermost sidewall area of the
trench-fill dielectric coupled to at least a portion of the control
gate layer, the shallow trench isolation feature further having an
uppermost portion formed substantially parallel to and at a higher
cross-sectional elevation than an active portion of the gate
oxide.
13. The MOS transistor of claim 12 wherein the transistor has a
double-diffused dopant region.
14. The MOS transistor of claim 12 wherein the control gate is
comprised of a first and a second polysilicon layer, the first
polysilicon layer having a first face located proximate to the gate
oxide and a second face located proximate to the second polysilicon
layer.
15. The MOS transistor of claim 14 wherein the second face of the
first polysilicon layer is substantially parallel to and at a lower
cross-sectional elevation than an uppermost portion of the shallow
trench isolation feature.
16. The MOS transistor of claim 12 wherein the shallow trench
isolation feature is formed in an n-well.
17. The MOS transistor of claim 12 wherein the shallow trench
isolation feature is formed in a silicon layer of a
silicon-on-insulator substrate.
18. The MOS transistor of claim 12 wherein a lowermost portion of
the gate oxide is configured to be at least partially in electrical
communication with a threshold enhancing dopant region.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a divisional of pending application Ser. No.
11/188,921 filed Jul. 25, 2005.
TECHNICAL FIELD
[0002] The invention relates to electronic semiconductor devices
and methods of fabrication, and, more particularly, to
semiconductor devices and fabrication methods thereof for reducing
electric fields and other deleterious effects by using self-aligned
trench isolation techniques.
BACKGROUND ART
[0003] The electronics industry continues to rely upon advances in
semiconductor technology to realize higher-functioning devices in
more compact areas. For many applications, realizing
higher-functioning devices requires integrating a large number of
electronic devices into a single silicon die. As the number of
electronic devices per given area of a silicon wafer increases,
manufacturing processes employed become more difficult.
[0004] An important subject of ongoing research in the
semiconductor industry is a reduction in the dimensions of devices
used in integrated circuits. Planar transistors such as metal oxide
semiconductor (MOS) transistors are particularly suited to use in
high density integrated circuits. As a size of MOS transistors and
other active devices decreases, dimensions of the source/drain/gate
electrodes, and the channel region of each device, must decrease
commensurately.
[0005] When fabricating MOS transistors, source and drain
electrodes are typically heavily doped to reduce a parasitic
resistance of the device. While doping improves conductance, it
concurrently increases parasitic capacitance, and lowers breakdown
voltages. Many prior art devices interpose lightly doped drain
(LDD) regions on either side of the channel region, between the
channel region and the source/drain electrodes. LDD regions permit
MOS devices to develop adequate breakdown voltages. However, LDD
regions also increase the resistance between the source and drain
when the transistor is turned on. This increased parasitic
resistance degrades the switching speed and current carrying
capabilities of the transistor. The necessity of LDD regions also
adds process steps to fabrication which negatively affect both cost
and reliability.
[0006] A MOS transistor suitable to control the gating and
amplification of high speed signals must have a low parasitic
capacitance, low parasitic resistance, and a breakdown voltage
larger than the signals which are carried. These performance
parameters represent design trade-offs well known to those skilled
in the art of MOS transistor fabrication.
[0007] Most prior art MOS transistors have channel regions that are
substantially the same size as the overlying gate electrode. The
channel region size and shape is a direct result of implanting
dopants in the silicon underlying the gate electrode to form
source/drain electrodes and LDD regions, after the deposition of
the gate electrode. The wide channel region formed in such a
process contributes undesirable characteristics to a transistor's
performance. It is commonly acknowledged that the drain current is
inversely proportional to the length of the channel.
[0008] DMOS (double diffused metal oxide semiconductor) transistors
are well known as a type of MOSFET (metal on semiconductor field
effect transistor) using diffusions to form the transistor regions,
with a typical application being as a power transistor. Such
devices enjoy widespread use in such applications such as
automobile electrical systems, power supplies, and power management
applications.
[0009] In a DMOS transistor, a channel length is determined by the
higher rate of diffusion of the P body region dopant (typically
boron) compared to the N+ source region dopant (typically arsenic
or phosphorus). The channel as defined by the body region overlies
a lightly doped drift region. DMOS transistors can have very short
channels and typically do not depend on photolithography to
determine channel length. Such DMOS transistors have good
punch-through control because of the heavily doped P body shield.
The lightly doped drift region minimizes the voltage drop across
the channel region by maintaining a uniform field to achieve a
velocity saturation. The field near the drain region is the same as
in the drift region so that avalanche breakdown, multiplication,
and oxide charging are lessened as compared to conventional
MOSFETs.
[0010] In one type of DMOS transistor, a trench is used to form a
gate structure. These transistors are typically formed on
<100> oriented silicon substrates (wafers), using an
anisotropic etch to form the trench. When etched into <100>
silicon, the trench has 54.7 degree sidewall slopes. The doping
distribution is the same as the DMOS transistor described supra.
The two channels are located one on each side of the etched trench.
The device has a common drain contact at the bottom portion of the
substrate. Since many devices can be connected in parallel, DMOS
transistors can handle high current and high power so are suitable
for power switching applications as described previously.
[0011] Many different processes have been used for the fabrication
of power MOSFET devices over the years; these processes are
generally deep diffusion processes. It is well known to form such
transistors having a trench in the substrate, the trench being
lined with a thin oxide layer and filled with a conductive
polysilicon to form the transistor gate structure.
[0012] With reference to FIG. 1, a cross-sectional view of one
prior art MOS device 100 includes a silicon substrate 101, an nwell
103, a threshold implant 105, a gate oxide 107, a liner oxide 109,
a shallow-trench isolation (STI) oxide 111, a gate polysilicon
region 113, and a resultant gate wrap-around region 115. The gate
wrap-around region 115 is a result of contemporaneous MOS
processing techniques causing a "divot" at a periphery of the STI
oxide 111, as is well-known in the art. The gate wrap-around region
115, however, has at least the following detrimental affects to MOS
device performance: (1) isolation voltages between gate and drift
regions of a device are reduced; and (2) the divot produces a high
capacitance region between the gate and drift regions, thereby
creating a high local-electric field. Therefore, what is needed is
an economical method to produce a MOS device while eliminating the
deleterious effects of the gate wrap-around region by eliminating
the divot during processing.
SUMMARY OF THE INVENTION
[0013] The present invention is, in one embodiment, a semiconductor
electronic device fabricated using the method described herein. The
semiconductor electronic device is, for example, a reduced-electric
field DMOS having a source, a drain, and a gate with a shallow
trench isolation feature. The shallow trench isolation feature has
a trench-fill dielectric where the trench-fill dielectric maintains
an essentially full-field oxide thickness. The full-field oxide
thickness is partially formed by having an uppermost sidewall area
of the trench-fill dielectric in electrical communication with a
polysilicon gate layer, thereby eliminating a gate wraparound area
of the prior art.
[0014] The present invention is also a method of fabricating an
electronic device. The method includes, for example, forming a gate
oxide on an uppermost side of a silicon-on-insulator substrate;
forming a first polysilicon layer over the gate oxide; and forming
a first silicon dioxide layer over the first polysilicon layer. A
first silicon nitride layer is then formed over the first silicon
dioxide layer. The first nitride layer is chosen since a high
selectivity ratio etchant can be used in later processing steps to
etch the nitride at a different rate from the silicon dioxide
layer. A second silicon dioxide layer is then formed over the first
nitride. Shallow trenches are etched through all the preceding
dielectric layers and into the SOI substrate. The etched trenches
are filled with another dielectric layer (e.g., silicon dioxide).
The dielectric layer (i.e., the trench-fill) is planarized to be
substantially coplanar with an uppermost surface of the nitride
layer. Each of the preceding dielectric layers are then removed,
leaving an uppermost sidewall area of the dielectric layer. The
sidewall area assures a full-field oxide thickness thereby
producing a device with a reduced-electric field and a reduced
capacitance between gate and drift regions.
[0015] Due to the aforementioned attributes and processing methods,
the present invention is, inter alia, capable of attaining a higher
isolation voltage between gate and drift regions than the prior art
without degrading a trajectory of injected carriers or forcing them
deeper into the body of the device. Also, the structure of the
resulting device allows for a greatly reduced capacitance between
the device gate and drift region with an elimination of the "gate
wrap-around," thereby reducing a local electric field.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a cross-sectional view of a gate region in a prior
art MOS device.
[0017] FIGS. 2A-2P show various cross-sectional views of a reduced
electric field MOS device fabricated using exemplary fabrication
techniques of the present invention.
[0018] FIG. 3 is a portion of a gate region of the MOS device of
FIG. 2P.
DETAILED DESCRIPTION OF THE INVENTION
[0019] With reference to FIG. 2A, beginning exemplary processes of
the present invention utilize a silicon-on-insulator (SOI)
technique and include a substrate 201, an oxide isolation layer
203, and an SOI layer 205. A screen oxide 209 is either thermally
grown or deposited on the SOI layer 205. A patterned and etched
photoresist layer 211 provides a mask for an ion implantation step.
In a specific embodiment, a concentration of boron atoms 213 forms
a retrograde p-well 207, thus forming a body for an NMOS device. A
skilled artisan will recognize that other doping techniques, such
as diffusion, may also be readily employed to produce a similar
p-well area.
[0020] In this exemplary embodiment, the substrate 201 is a silicon
wafer. Alternatively, the substrate 201 could be another elemental
group IV semiconductor or a compound semiconductor (e.g., groups
III-V or II-VI). The substrate 201 may alternatively be a
non-semiconductor, such as a photomask blank.
[0021] In FIG. 2B, additional dopant areas have been added after
removal of the patterned and etched photoresist layer 211 and the
screen oxide 209 (neither of which is shown in FIG. 2B). The
additional dopant areas include an n-well 215 and a threshold
enhancing implant 208. Further, a gate oxide 217, a first
polysilicon layer 219, a first oxide layer 221, and a silicon
nitride layer 223 have been deposited by various techniques, all
known to a skilled artisan. The first polysilicon layer 219, the
first oxide layer 221, and the silicon nitride layer 223 comprise
an active stack.
[0022] In a specific embodiment, the gate oxide 217 is thermally
grown and/or etched to various thicknesses in different regions,
generally 20 .ANG. to 50 .ANG. thick. The first polysilicon layer
219 is deposited via chemical vapor deposition (CVD) to about 1200
.ANG. thick, and the first oxide layer 221 is thermally grown and
is about 90 .ANG. thick. The silicon nitride layer 223 is deposited
via a CVD process and is about 1200 .ANG. thick.
[0023] Over the active stack (i.e., the first polysilicon layer
219, the first oxide layer 221, and the silicon nitride layer 223),
a second oxide layer 225 and a photoresist layer 224 are patterned
and etched to act as a hardmask for subsequent shallow trench
isolation (STI) processes (described infra). The second oxide layer
225 may be a high density plasma (HDP)--enhanced CVD, with an
average thickness of approximately 2000 .ANG. that is dry-etched
(e.g., a reactive-ion etch) in preparation for the subsequent STI
processes.
[0024] In FIG. 2C, shallow trenches 227 have been etched through
the active stack and the gate oxide 217 and into the SOI layer 205
as part of the STI process. The photoresist layer 224 (not shown in
FIG. 2C) is subsequently removed. A liner oxide 235 (FIG. 2D) is
deposited or grown onto exposed sidewalls of the shallow trenches
227, followed by a third photoresist layer 229. The third
photoresist layer 229 is then patterned and etched (as shown in
FIG. 2D) and a second ion implant 231 is performed, producing a
p-field implant 233. The third photoresist layer 229 is then
stripped, and a second liner oxide 237 (FIG. 2E) is deposited. In a
specific embodiment, the second liner oxide 237 is silicon dioxide
grown by a pyrolitic oxidation of tetraethylorthosilane (TEOS) to a
thickness of approximately 200 .ANG.). A third oxide layer 239 is
then conformally deposited (e.g., by an HDP-CVD process to
approximately 9000 .ANG.) providing a shallow trench fill. The
third oxide layer 239 is etched (typically with an etchant which
has a high selectivity ratio between silicon dioxide and silicon
nitride), producing a first trench 241 and a second trench 243,
followed by a chemical mechanical planarization (CMP) process step.
The CMP process step stops at an uppermost portion of the silicon
nitride layer 223 (FIG. 2F).
[0025] With reference to FIG. 2G, the second trench 243 is etched
and extended at least partially through the p-field implant 233,
the p-well 207, and the SOI layer 205. In a specific embodiment,
the second trench 243 is extended to an uppermost surface of the
oxide isolation layer 203. A third liner oxide 245 (FIG. 2H) is
then thermally grown on exposed silicon sidewalls of a lower
portion of the extended second trench 243.
[0026] With reference to FIG. 2I, a conformal TEOS layer 247 is
deposited (e.g., to approximately 2000 .ANG. thick), followed by a
blanket polysilicon layer 249A. The blanket polysilicon layer 249A,
is deposited to a thickness of, for example, 5000 .ANG.. The
blanket polysilicon layer 249A is then etched (FIG. 2J), leaving a
deep trench fill plug 249B. A subsequent HDP-CVD oxide layer 251A
is deposited (FIG. 2K) to a depth of approximately 7000 .ANG.. An
additional CMP step planarizes the wafer, stopping on the silicon
nitride layer 223 (FIG. 2L). An oxide remainder 251B of the HDP-CVD
oxide layer 251A stays in the second trench 243 (now filled in)
above and in contact with the deep trench polysilicon plug
249B.
[0027] After CMP, the silicon nitride layer 223 is etched (e.g., by
hot phosphoric acid), leaving an upper portion of the shallow
trench isolation areas (comprised of the second liner oxide 237 and
the third oxide layer 239) partially exposed (FIG. 2M). A
buffered-oxide etch dip-back removes a remaining portion of the
first oxide layer 221 and provides a rounded area on an uppermost
edge of the STI corners 253 (FIG. 2N).
[0028] In FIG. 2O, a second polysilicon layer 255 is deposited
(e.g., to approximately a 2000 .ANG. thickness), patterned, and
etched. The second polysilicon layer 255 will form a gate area of
the MOS device.
[0029] With reference to FIG. 2P, fabrication of the MOS device
proceeds by adding an n-type lightly doped drain (NLDD) implant
265, a source area n-type source-drain (NSD) implant 267, and a
drain area NSD implant 269. An oxide-isolation layer 271 is added
to the second polysilicon layer 255, nitride sidewall spacers 257
are added to a periphery of the polysilicon layer 255, and a thick
dielectric 273 is deposited. Contact vias 259, 261, 263 are defined
for drain, gate, and source contacts respectively. Each of the vias
259, 261,263 is subsequently tungsten filled to complete the
contact. All of these final fabrication processes are known to one
of skill in the art.
[0030] With reference to FIG. 3, a portion 300 of the MOS device of
FIG. 2P indicates a first area 301 in which a capacitance between
the gate and drift regions of the MOS device is greatly reduced as
compared with a similar region of the prior art MOS device 100
(FIG. 1). Further, the gate wrap-around 115 of the prior art MOS
device 100 has been eliminated by utilizing the fabrication
techniques of the present invention. Additionally, a second area
303 of FIG. 3 indicates that a full field oxide thickness is
maintained. The full field thickness aids in optimizing performance
characteristics of the MOS device of the present invention.
[0031] In the foregoing specification, the present invention has
been described with reference to specific embodiments thereof. For
example, various doping processes are described in terms of
implants. A skilled practitioner will realize that another doping
process, such as diffusion, may be substituted for the implant
process. Also, various layers may be defined as being comprised of
a given material, for example, silicon dioxide. A skilled
practitioner will realize that another dielectric material may
often be substituted. For example, a silicon dioxide layer may be
interchanged with a silicon nitride layer as long as each adjacent
dielectric layer has a different etch rate (e.g., a high
selectivity wet-etch process will etch silicon dioxide more rapidly
than silicon nitride or vice versa). Also, various types of silicon
dioxide may be used even though the characteristics are all
somewhat similar to each other (e.g., dielectric breakdown or
permittivity). Thus, silicon dioxide layers formed by thermal
growth, chemical vapor deposition, or TEOS techniques may be
considered similar for an application of the present invention. It
will, therefore, be evident that various modifications and changes
can be made thereto without departing from the broader spirit and
scope of the present invention as set forth in the appended claims.
The specification and drawings are, accordingly, to be regarded in
an illustrative rather than a restrictive sense.
* * * * *