U.S. patent application number 11/619828 was filed with the patent office on 2008-07-10 for integrated complementary low voltage rf-ldmos.
Invention is credited to Jun Cai.
Application Number | 20080164537 11/619828 |
Document ID | / |
Family ID | 39593525 |
Filed Date | 2008-07-10 |
United States Patent
Application |
20080164537 |
Kind Code |
A1 |
Cai; Jun |
July 10, 2008 |
INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS
Abstract
Complementary RF LDMOS transistors have gate electrodes over
split gate oxides. A source spacer of a second conductivity type
extends laterally from the source tap of a first conductivity type
to approximately the edge of the gate electrode above the thinnest
gate oxide. A body of a first conductivity type extends from
approximately the bottom center of the source tap to the substrate
surface and lies under most of the thin section of the split gate
oxide. The source spacer is approximately the length of the gate
sidewall oxide and is self aligned with gate electrode. The body is
also self aligned with gate electrode. The drain is surrounded by
at least one buffer region which is self aligned to the other edge
of the gate electrode above the thickest gate oxide and extends to
the below the drain and extends laterally under the thickest gate
oxide. Both the source tap and drain are self aligned with the gate
side wall oxides and are thereby spaced apart laterally from the
gate electrode.
Inventors: |
Cai; Jun; (Scarborough,
ME) |
Correspondence
Address: |
HISCOCK & BARCLAY, LLP
2000 HSBC PLAZA, 100 Chestnut Street
ROCHESTER
NY
14604-2404
US
|
Family ID: |
39593525 |
Appl. No.: |
11/619828 |
Filed: |
January 4, 2007 |
Current U.S.
Class: |
257/408 ;
257/E21.427; 257/E21.435; 257/E29.04; 257/E29.063; 257/E29.064;
257/E29.119; 257/E29.133; 257/E29.146; 257/E29.156; 257/E29.266;
257/E29.268; 438/303 |
Current CPC
Class: |
H01L 29/4175 20130101;
H01L 29/1083 20130101; H01L 29/4933 20130101; H01L 29/0847
20130101; H01L 29/42368 20130101; H01L 29/1087 20130101; H01L
29/7835 20130101; H01L 29/456 20130101; H01L 29/66659 20130101 |
Class at
Publication: |
257/408 ;
438/303; 257/E29.266; 257/E21.435 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/336 20060101 H01L021/336 |
Claims
1. A lateral double diffused metal oxide semiconductor (LDMOS)
transistor comprising: a) a gate oxide having a plurality of
thicknesses under a gate electrode; b) a source tap region of a
first conductivity type; c) a lateral source spacer of a second
conductivity type lying substantially between a first edge of said
gate electrode and said source tap, said first conductivity type
being opposite to said second conductivity type; d) a drain region
of said second conductivity type on an opposite side of said gate
electrode; and e) at least one buffer region of that at least
partially surrounds said drain region and which extends under a
second edge of said gate electrode.
2. The LDMOS transistor set forth in claim 1 wherein said plurality
of thicknesses of said gate oxide is two.
3. The LDMOS transistor set forth in claim 2 wherein a thinner gate
oxide is under said first edge of said gate electrode and a thicker
gate oxide is under a second edge of said gate electrode.
4. The LDMOS transistor set forth in claim 3 wherein said at least
one buffer region extends laterally to below said thicker gate
oxide.
5. The LDMOS transistor set forth in claim 1 wherein said at least
one buffer region comprises two buffer regions, a first buffer
region of said second conductivity type lying below said drain
region and above a second buffer region of said second conductivity
type.
6. The LDMOS transistor set forth in claim 5 wherein said drain
region is of a higher dopant concentration than said first buffer
region which, in turn, has a higher dopant concentration than said
second buffer region.
7. The LDMOS transistor set forth in claim 1 further including a
body of said first conductivity type which lies below at least a
portion of said source tap region and under said lateral source
spacer and extends to said gate oxide.
8. The LDMOS transistor set forth in claim 7 wherein said body is
of a lower dopant concentration than said source tap region.
9. The LDMOS transistor set forth in claim 7 further including a
well of said first conductivity type under a least a portion of
said body.
10. The LDMOS transistor set forth in claim 9 further including a
first buried layer of said first conductivity type extending from
said well towards a substrate.
11. The LDMOS transistor set forth in claim 1 further including a
substrate laying below said gate electrode, said gate oxide, said
source tap region, said lateral source spacer, said drain region
and said at least one buffer region.
12. The LDMOS transistor set forth in claim 11 wherein said
substrate is of said second conductivity type.
13. The LDMOS transistor set forth in claim 11 wherein said
substrate is of said first conductivity type.
14. The LDMOS transistor set forth in claim 11 further including an
epi layer lying on said substrate.
15. The LDMOS transistor set forth in claim 14 further including a
well of said first conductive type lying on said epi layer.
16. The LDMOS transistor set forth in claim 3 wherein said at least
one buffer region comprises two buffer regions, a first buffer
region of said second conductivity type lying below said drain
region and above a second buffer region of said first conductivity
type.
17. The LDMOS transistor set forth in claim 16 wherein said second
buffer region extends latterly and deeply under all of the thick
section and part of the thin section of the split gate oxide to
overlap the body region.
18. The LDMOS transistor set forth in claim 1 wherein said at least
one buffer region consists of a single buffer region.
19. The LDMOS transistor set forth in claim 14 further including a
buried layer lying on said epi layer.
20. The LDMOS transistor set forth in claim 14 further including a
buried layer of said first conductivity type lying on said epi
layer.
21. The LDMOS transistor set forth in claim 20 further including a
buried layer of said second conductivity type lying on said buried
layer of said first conductivity type.
22. The LDMOS transistor set forth in claim 1 farther including an
isolation ring surrounding said transistor.
23. The LDMOS transistor set forth in claim 22 wherein said
isolation ring is connected to a region in said transistor which is
the same conductivity type as said isolation ring.
24. A high frequency lateral double diffused metal oxide
semiconductor (LDMOS) transistor comprising: a) a gate oxide having
a thinner section under a first edge of a gate electrode and a
thicker section under a second edge of said gate electrode; b) a
lateral source spacer of a second conductivity type lying between
said first edge of said gate electrode; c) a source tap region of a
first conductivity type, said first conductivity type being
opposite to said second conductivity type; d) a drain region of
said second conductivity type; e) a first buffer region of said
second conductivity type lying below said drain region and above a
second buffer region of said second conductivity type, both of
which at least partially surround said drain region and which
extend under said second edge of said gate electrode, said drain
region is of a higher dopant concentration than said first buffer
region which, in turn, has a higher dopant concentration than said
second buffer region; f) a body of said second conductivity type
which lies below at least a portion of said source tap region and
under said lateral source spacer and extends to said gate oxide,
said body being of a lower dopant concentration than said source
tap region; g) a well of said first conductivity type under a least
a portion of said body; h) a buried layer of said first
conductivity type extending from said well towards a substrate; and
i) a substrate laying below said gate electrode, said gate
electrode, said spacer, said source region, said drain region, said
first and second buffer regions, said body, said well, and said
buried layer; and j) an epi layer of said first conductivity type
lying on said substrate.
25. A method of making a LDMOS transistor comprising the steps of:
a) growing an epi layer on a substrate; b) forming a gate electrode
on a split gate oxide formed on said epi layer; c) forming a body
of said first conductivity type and a source spacer of said second
conductivity type which are self-aligned to first side of said
polysilicon gate electrode; said second conductivity type being
opposite to said first conductivity type; d) forming a first buffer
layer of said second conductivity type self-aligned to a second
edge of said polysilicon gate electrode; e) forming first and
second side wall oxides on said first edge and said second edge,
respectively, of said polysilicon gate electrode; and f) forming a
first drain region of said second conductivity type self-aligned to
said second side wall oxide g) forming a source tap layer of said
first conductivity type self-aligned to said first side wall oxide
such that said source tap layer and said body overlap in a region
spaced away from said first edge of said gate electrode, said
source spacer region extending from said source tap layer to under
at least said first edge of said polysilicon gate electrode.
26. The method set forth in claim 25 further including the step of
forming a well of said first conductivity type under a least a
portion of said body.
27. The method set forth in claim 26 further including the step of
forming a first buried layer of said first conductivity type
extending from said well towards a substrate.
28. The method set forth in claim 25 wherein said substrate is of
said first conductivity type.
29. The method set forth in claim 25 wherein said substrate is of
said second conductivity type.
30. The method set forth in claim 25 further including the step of
forming a second buffer layer of said second conductivity type
self-aligned to a second edge of said polysilicon gate electrode
and lying below said first buffer.
31. The method set forth in claim 30 wherein the steps of forming
said first buffer layer, said drain region, and said second buffer
layer includes forming said drain layer with a higher dopant
concentration than said first buffer layer which, in turn, is
formed with a higher dopant concentration than said second buffer
layer.
32. The method set forth in claim 25 further including the step of
forming a well of said second conductive type lying on said epi
layer.
33. The method set forth in claim 25 further including the step of
forming a second buffer layer of said first conductivity type
self-aligned to a second edge of said polysilicon gate electrode
and lying below said first buffer.
34. The method set forth in claim 33 wherein said second buffer
region extends latterly and deeply under all of the thick section
and part of the thin section of the split gate oxide to overlap the
body region.
35. The method set forth in claim 25 further including the step of
forming a buried layer lying on said epi layer.
36. The method set forth in claim 25 further including the step of
forming a buried layer of said first conductivity type lying on
said epi layer.
37. The method set forth in claim. 36 further including the step of
forming a buried layer of said second conductivity type lying on
said buried layer of said first conductivity type.
38. The method set forth in claim 25 further including the step of
forming an isolation ring surrounding said transistor.
39. The method set forth in claim 38 wherein said isolation ring is
connected to a region in said transistor which is the same
conductivity type as said isolation ring.
Description
FIELD OF THE INVENTION
[0001] This invention relates to power MOSFETs, and more
particularly, to low power lateral complementary power MOSFETs.
BACKGROUND OF THE INVENTION
[0002] The widespread use of personal communication products, such
as cell phones and wireless LANs, has created a demand for
semiconductor devices which can provide certain operational
characteristics specific to these devices. One of these operational
characteristics relates to the power dissipated in the
semiconductor devices. The conventional method to reduce the power
dissipation is to use a power supply voltage of three volts or
less. However, certain portions of the electronics, such as the RF
transmitters, require power devices that can handle higher voltages
and currents than are not present in the rest of the electronic
circuitry. This requirement is exacerbated by the demand for ever
smaller products thus providing a strong incentive for combining
complementary power devices on the same substrate as other portions
of the electronics. The lateral double diffused MOSFET (LDMOS)
transistor is virtually the only silicon device to meet these
requirements.
[0003] LDMOS transistors know in the art usually use a drift region
to provide the relatively high breakdown voltages required of these
devices. However such drift regions increase device resistance and
take up space on a semiconductor chip thus requiring a
significantly larger chip area than needed for convention
MOSFETs.
[0004] In addition, most of these prior art LDMOS transistors have
relatively low DC transconductance that also is significantly
degraded in the frequency ranges used in many of the personal
communication products, have power loss in the device due to
capacitances, junction leakage and substrate loss, and can have
reliability problems arising from the hot carrier effect.
[0005] Therefore, it can be appreciated that a LDMOS transistor
which can provide improvements in some or all of these areas over
the currently known LDMOS transistors is highly desirable
SUMMARY OF THE INVENTION
[0006] The invention comprises, in one form thereof, a lateral
double diffused metal oxide semiconductor (LDMOS) transistor
comprising a gate oxide having a plurality of thicknesses under a
gate electrode, a lateral spacer of a second conductivity type
lying between a first edge of the gate electrode and a source tap
region of a first conductivity type, the second conductivity type
being opposite to the first conductivity type, and a drain region
of the second conductivity type having a at least one buffer region
which at least partially surrounds the drain region and which
extends under a second edge of the gate electrode.
[0007] In another form, the invention includes a method for making
a LDMOS transistor. The method comprises the steps of growing an
epi layer on a substrate, forming a gate electrode on a split gate
oxide formed on the epi layer, forming a body of a first
conductivity type using a first side of the gate electrode as a
mask, forming a shallow source spacer region of a second
conductivity type using the first edge of the gate electrode as a
mask, the second conductivity type being opposite to the first
conductivity type, forming at least one buffer layer of the second
conductivity type using a second edge of the gate electrode as a
mask, forming first and second side wall oxides on the first and
second edges, respectively, of the gate electrode, and forming a
source tap layer of the first conductivity type using the first
side wall oxide as a mask such that the source tap layer and the
body overlap in a region spaced away from the first edge of the
gate electrode, the source spacer region extending from the source
tap layer to at least the first edge of the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The features and advantages of this invention, and the
manner of attaining them, will become apparent and be better
understood by reference to the following description of the various
embodiments of the invention in conjunction with the accompanying
drawings, wherein:
[0009] FIG. 1A is a diagrammatic view of an n channel integrated
low voltage RF-LDMOS transistor according to an embodiment of the
present invention;
[0010] FIG. 1B is a diagrammatic view of a complementary p channel
version of the integrated low voltage RF-LDMOS transistor shown in
FIG. 1A;
[0011] FIG. 2A is a diagrammatic view of an early stage in the
fabrication of the transistor shown in FIG. 1A;
[0012] FIG. 2B is a diagrammatic view of an early stage in the
fabrication of the transistor shown in FIG. 1B;
[0013] FIG. 3A is a diagrammatic view of al intermediate stage in
the fabrication of the transistor shown in FIG. 1A;
[0014] FIG, 3B is a diagrammatic view of an intermediate stage in
the fabrication of the transistor shown in FIG. 1B;
[0015] FIG. 4A is a diagrammatic view of a later intermediate stage
in the fabrication of the transistor shown in FIG. 1A;
[0016] FIG. 4B is a diagrammatic view of a later intermediate stage
in the fabrication of the transistor shown in FIG. 1B;
[0017] FIG. 5A is a diagrammatic view of an n channel integrated
low voltage RF-LDMOS transistor according to another embodiment of
the present invention;
[0018] FIG. 5B is a diagrammatic view of a complementary p channel
version of the integrated low voltage RF-LDMOS transistor shown in
FIG. 5A;
[0019] FIG. 6A is a diagrammatic view of an n channel integrated
low voltage RF-LDMOS transistor according to yet another embodiment
of the present invention;
[0020] FIG. 6B is a diagrammatic view of a complementary p channel
version of the integrated low voltage R(F-LDMOS transistor shown in
FIG. 6A;
[0021] FIG. 7A is a diagrammatic view of an n channel integrated
low voltage RF-LDMOS transistor according to still another
embodiment of the present invention;
[0022] FIG. 7B is a diagrammatic view of a complementary p channel
version of the integrated low voltage RF-LDMOS transistor shown in
FIG. 7A;
[0023] FIG. 8A is a graph of the drain characteristics versus drain
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.35 micron;
[0024] FIG. 8B is a graph of the drain characteristics versus drain
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.50 micron,
[0025] FIG. 5C is a graph of the drain characteristics versus drain
voltage simulation of a prior art transistor;
[0026] FIG. 9A is a graph of the frequency transition versus gate
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.35 micron;
[0027] FIG. 9B is a graph of the frequency transition versus gate
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.50 micron;
[0028] FIG. 9C is a graph of the frequency transition versus gate
voltage simulation of a prior art transistor;
[0029] FIG. 10A is a graph of the transconductance versus gate
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.35 micron;
[0030] FIG. 10B is a graph of the transconductance versus gate
voltage simulation of the transistor shown in FIG. 1A with a gate
length of 0.50 micron; and
[0031] FIG. 10C is a graph of the transconductance versus gate
voltage simulation of a prior art transistor.
[0032] It will be appreciated that for purposes of clarity, and
where deemed appropriate, reference numerals have been repeated in
the figures to indicate corresponding features. Also, the relative
size of various objects in the drawings has in some cases been
distorted to more clearly show the invention. The examples set out
herein illustrate several embodiments of the invention but should
not be construed as limiting the scope of the invention in any
manner.
DETAILED DESCRIPTION
[0033] Turning now to the drawings, FIG. 1A is a diagrammatic view
of an n channel integrated complementary low voltage RF-LDMOS
transistor 10 according to an embodiment of the present invention.
The transistor 10 has a source connection 12, a gate connection 14,
and a drain connection 16. The gate connection 14 is electrically
connected to a gate suicide 18 formed in a gate polysilicon 20. The
gate polysilicon 20 has a stepped bottom layer lying over a split
gate oxide 22 with a thin section 24 of length 26, and a thick
section 28 of length 30. A sidewall oxide 32 is shown on the left
side of the gate silicide 18, the gate polysilicon 20, and the thin
section 24 of the split gate oxide 22. Similarly, a sidewall oxide
34 is shown on the right side of the gate polysilicon 20 and the
thick section 28 of the split gate oxide 22.
[0034] The source connection 12 is electrically connected to a
source silicide 36 under which is a source P+ tap 38. A shallow and
short N+ source spacer 40 extends laterally from the right edge of
the source silicide 36 and top right of the P+ tap 38 to slightly
under the left side of the gate polysilicon 20. The length of the
N+ source spacer 40 in one embodiment of the invention is
approximately 0.08 microns, and can be between 0.04 and 0.3
microns. A P body 42 extends from the approximately the bottom
center of the P+ tap 38 to the substrate surface 44 and lies under
most of the thin section 24 of the split gate oxide 22. A P- well
46 extends from the top of an optional P- buried layer 48 from
approximately the downward projection of the middle of the bottom
of the P+ tap 38 to the bottom of the P body 42 at a point
approximately below the left edge of the gate polysilicon 20.
[0035] The drain connection 16 is electrically connected to a drain
silicide 50. A N+ drain 52 lies under and extends to the left of
the drain silicide 50. The left end of the N- drain is spaced
laterally apart from the gate polysilicon 20. A N buffer layer 54
lies under the N+ drain 52 and extends latterly to about the middle
of the thick section 28 of the split gate oxide 22. A N- buffer
layer 56 lies under the N buffer layer 54 and extends to under all
of the thick section 28 of the split gate oxide 22 near the
transition of the thin section 24 to the thick section 28 of the
split gate oxide 22.
[0036] The source silicide 36 and the drain silicide 50, and the
doped regions described above all lie in an epi layer 58 which in
turn is atop a P+ substrate 60.
[0037] The RF-LDMOS transistor 10 has a minimum device geometry for
power LDMOS transistors and is made by utilizing self-aligned
architecture design for high speed requirements. The self-aligned
architecture will be explained in more detail below with reference
to FIGS. 2A through 4B. The transistor 10 has a zero drift length
which helps to minimize the device geometry.
[0038] Besides miniaturization, the transistor 10 has several
characteristics arising from the geometry of the device which
provide important operating parameters. The shallow N+ source
spacer 40 with the P body 42 underneath and the P+ tap provide a
large Safe Operating Area (SOA), a small input capacitance, and
little junction leakage (which is important in battery powered
hand-held applications). The combination of the P body 42, the P-
well 46, the P- buried layer 48, and the P+ substrate 60 provide
reduced substrate self-heating which minimizes the substrate loss.
The split gate oxide 22 provides a lessened Miller feedback
capacitance since the gate-drain overlap is located at the thick
section 28 of the split gate oxide 22 thereby lowering the Crss.
The split gate oxide also provides a large transconductance and
lower Vt since the effective channel is located at the thin oxide
section 24 having all effective channel length shorter that the
width of the gate polysilicon 20. The thick gate oxide section 28
on the drain side lowers the E-field to thereby increase the
breakdown voltage of the transistor 10. The N buffer layer 54 and
the N- buffer layer 56 step drain buffers together with the P- epi
provide a large depletion width which lowers the drain to source
capacitance C.sub.ds. The step drain buffers lessen the degradation
of R.sub.on, g.sub.m and I.sub.Dsat since the N- buffer layer 56
with significant overlap with the thick gate oxide section 28
allows the channel electrons to spread out deep away from the gate
oxide 22 resulting in fewer filled traps in the gate oxide 22. the
lessening of the degradation of R.sub.on, g.sub.m and I.sub.Dsat
therefore increases the reliability of the transistor 10. Finally,
the zero drift length combined with the relatively highly doped N
buffer layer 54, which extends underneath the sidewall spacer 34,
provides a low R.sub.on and low conduction loss.
[0039] FIG. 1B is a diagrammatic view of a complementary p channel
version 70 of the integrated low voltage RF-LDMOS transistor shown
in FIG. 1A. Transistor 70 has a source connection 72, a gate
connection 74, and a drain connection 76. The gate connection 74 is
electrically connected to a gate silicide 78 formed in a gate
polysilicon 80. The gate polysilicon 80 has a stepped bottom layer
lying over a split gate oxide 82 with a thin section 84 and a thick
section 88. A sidewall oxide 92 is shown on the left side of the
gate silicide 78, the gate polysilicon 80, and the thin section 84
of the split gate oxide 82. Similarly, a sidewall oxide 94 is shown
on the right side of the gate polysilicon 80 and the thick section
88 of the split gate oxide 82.
[0040] The source connection 72 is electrically connected to a
source silicide 96 under which is a source N+ tap 98, a shallow and
short P+ source spacer 100 extends laterally from the right edge of
the source silicide 96 and top right of the N+ tap 98 to slightly
under the left side of the gate polysilicon 80. A N body 102
extends from the approximately the bottom center of the N+ tap 88
to the substrate surface 104 and lies under most of the thin
section 84 of the split gate oxide 82. A N- well 106 extends from
the top of an optional N- buried layer 108 from approximately the
downward projection of the middle of the bottom of the N+ tap 98 to
the bottom of the N body 102 at a point approximately below the
left edge of the gate polysilicon 80.
[0041] The drain connection 76 is electrically connected to a drain
silicide 110. A P+ drain 112 lies under and extends to the left of
the drain silicide 110. The left end of the P+ drain is spaced
laterally apart from the gate polysilicon 80. A P buffer layer 114
lies under the P+ drain 112 and extends latterly to about the
middle of the thick section 88 of the split gate oxide 82. A P-
buffer layer 116 lies under the P buffer layer 114 and extends
latterly to under all of the thick section 88 of the split gate
oxide 82 near the transition of the thin section 84 to the thick
section 88 of the split gate oxide 82.
[0042] The source silicide 96 and the drain silicide 10, and the
doped regions described above all lie in a high voltage N- well 18
which in turn is partially atop the N- buried layer 108, which are
in turn atop a P- epi 120 which is atop a P+ substrate 122.
[0043] The characteristics described above for the N channel
transistor 10 also apply to the P channel transistor 70.
[0044] FIGS. 2A and 2B are diagrammatic views of an early stage in
the fabrication of the transistors 10 and 70, respectively. In FIG.
2A a starting P- epi 130 is formed on the P+ substrate 60. A P-
buried layer 132 is formed in the P-epi 130. Similarly, in FIG. 2B
the starting P- epi 120 is formed on the P+ substrate 122, and a
buried layer 134 is formed in the P- epi 120.
[0045] FIGS. 3A and 3B are diagrammatic views of an intermediate
stage in the fabrication of the transistors 10 and 70,
respectively. In FIG. 3A an additional in-line P- epi is grown on
the P- buried layer 132 and P- epi 130 of FIG. 2A to form the P-
epi 58 shown in FIG. 1A. After field oxidation and masking, the P-
well 46 is implanted. In a subsequent diffusion operation the
P-buried layer 132 of FIG. 2A diffuses upward to form the P- buried
layer 48, and the P-well 46 diffuses downwardly and laterally. The
split gate oxide 22 is formed on the top of the P- epi 58 and the
gate polysilicon 20 is placed across the junction of the thick gate
oxide 28 and the thin gate oxide 24. In FIG. 313, similar to FIG.
3A, the high voltage N- well 118 is implanted and diffused in an
additional in-line P- epi 118. The N- well 106 is formed in the
same manner as the P- well 46 shown in FIG, 3A. In a subsequent
diffusion operation the N- buried layer 134 is diffused upward to
form the N- buried layer 108, and the N- well 106 diffuses
downwardly and laterally at the same time. The split gate oxide 82
and the gate polysilicon 80 are formed in the same manner as in the
n channel transistor shown in FIG. 3A.
[0046] FIGS. 4A and 4B are diagrammatic views of a later
intermediate stage in the fabrication of the transistors 10 and 70,
respectively. In FIG. 4A the P body 42 and the N+ source spacer 40
are implanted using the same mask and are self-aligned to the left
side of the gate polysilicon 20. Similarly, the step drain buffers
consisting of the N- buffer layer 56 and the N buffer layer 52 are
implanted using the same mask and are self-aligned to the right
side of the gate polysilicon 20. The same operations are performed
for the p channel transistor shown in FIG. 4B with complementary
dopant types, After bodies 42, 102 and source spacers 40, 100 are
formed, the sidewall oxide 32, 34, 92, and 94 are made using a
standard oxide spacer process.
[0047] The transistor 10 shown in FIG. 1A is completed by
implanting the P+ body tap 38, which is self-aligned to the left
side wall oxide, forming the source silicide 36 using the left side
wall oxide 32 as a mask, implanting the N+ drain 52, which is
self-aligned to the right side wall oxide, and forming the drain
silicide 50 using the right side wall oxide 34 as a mask. The
transistor 70 show in FIG. 1B is completed in the same manner using
complementary dopant types.
[0048] FIGS. 5A and 5B are diagrammatic views of integrated low
voltage RF-LDMOS transistors 130 and 132, respectively, according
to another embodiment of the present invention. Transistor I 30 is
transistor 10 with an enlarged N buffer layer 135 instead of the N
buffer layer 54, and a P- buffer layer 136 instead of the N- buffer
layer 56; and transistor 132 is transistor 70 with an enlarged P
buffer layer 137 instead of the P buffer layer 114, and a N- buffer
layer 138 instead of the P- buffer layer 116. In this embodiment
130 of the present invention, the N buffer 132 extends latterly to
under the thick section 28 of the split gate oxide 22 near the
transition of the thin section 24 to the thick section 28 of the
split gate oxide 22, and the P- buffer 134 extends latterly and
deeply under all of the thick section 28 and part of the thin
section 24 to overlap the P body 42. The transistor 132 shown in
FIG. 5B is formed in the same manner using complementary dopant
types. The change from N- buffer to P- buffer in transistor 130 or
from P- buffer to N- buffer in transistor 132 is to increase the
device drain to source punch-through voltage which can be a problem
with very short channel devices.
[0049] FIGS. 6A and 6B are diagrammatic views of integrated low
voltage RF-LDMOS transistors 140 and 142, respectively, according
to yet another embodiment of the present invention. Transistor 140
is transistor 10 without the N buffer layer 54, and transistor 142
is transistor 70 without the P buffer layer 114. The removal of
these layers 54, 114 allows a higher voltage rating for transistors
shown in FIGS. 6A and 6B compared with the transistors shown in
FIGS. 1A and 1B.
[0050] FIGS. 7A and 7B are diagrammatic views of integrated low
voltage RF-LDMOS transistors 150 and 152, respectively, according
to still another embodiment of the present invention in which the
transistors 150 and 152 are surrounded by N isolation rings for
isolated architectures. In FIG. 7A an N ring 154 has an isolation
connection 156. The N ring 154 is connected by an N bridge 158 to a
N- buried layer 160 which extends across the width of the
transistor 150. A P- buried layer 162, which also extends across
the width of the transistor 50, sits on top of the N- buried layer
160. In FIG. 713 an N ring 164 has an isolation connection 166. The
N ring 164 is connected by an N bridge 168 to a N- buried layer 170
which extends across the width of the transistor 152. A P- buried
layer 172 is built atop the N- buried layer 170 and connected to
the P- well 46 as indicated schematically by connection 174 from
the N- buried layer 172 to the source connection 72 which, in turn,
provides a connection through the source silicide 96, and the
source N+ tap 98 to the N- well 106.
[0051] FIGS. 8A-10C show 2-D simulated Si level operational
characteristics of the transistor 10 and a prior art power NMOS
transistor. FIGS. 8A, 9A, and 10A are simulations of transistor 10
with a thin gate width 26 of 0.20 .mu.m. FIGS. 8B, 9B, and 10B are
simulations of transistor 10 with a thin gate width 26 of 0.35
.mu.m. The simulations which generated the A and B graphs were for
the same thick gate width 30 of approximately 0.15 .mu.m. FIGS. 8C,
9C, and 10C are simulations of the prior art power NMOS
transistor.
[0052] FIGS. 8A, 8B, and 8C show the calculated drain
characteristics for the respective transistors using a 2-D model.
As can be seen transistor 10 with a 0.35 .mu.m gate poly length has
higher drain current densities than the 0.50 .mu.m gate poly length
transistor 10, which, in turn has higher drain current densities
than the prior art lateral transistor.
[0053] FIGS. 9A, 9B, and 9C show the calculated frequency
transitions (Ft) for the respective transistors. The peak Ft in
FIG. 9A is 67 GHz, while the peak Ft in FIG. 9B is 36 GHz, and the
peak Ft in FIG. 9C is 23 GHz.
[0054] FIGS. 10A, 10B, and 10C are the calculated transconductance
Gm for the respective transistors. The peak Gm in FIG. 10A is
3.times.10.sup.-4 siemens, while the peak Gm in FIG. 10B is
2.5.times.10.sup.-4 siemens, and the peak Gm in FIG. 10C is
1.3.times.10.sup.-4 siemens.
[0055] While the invention has been described with reference to
particular embodiments, it will be understood by those skilled in
the art that various changes may be made and equivalents may be
substituted for elements thereof without departing from the scope
of the invention. In addition, many modifications may be made to
adapt a particular situation or material to the teachings of the
invention without departing from the scope of the invention.
[0056] Therefore, it is intended that the invention not be limited
to the particular embodiments disclosed as the best mode
contemplated for carrying out this invention, but that the
invention will include all embodiments falling within the scope and
spirit of the appended claims.
* * * * *