U.S. patent application number 12/046240 was filed with the patent office on 2008-07-03 for method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs.
Invention is credited to RAJIT CHANDRA.
Application Number | 20080163135 12/046240 |
Document ID | / |
Family ID | 37728013 |
Filed Date | 2008-07-03 |
United States Patent
Application |
20080163135 |
Kind Code |
A1 |
CHANDRA; RAJIT |
July 3, 2008 |
METHOD AND APPARATUS FOR OPTIMIZING THERMAL MANAGEMENT SYSTEM
PERFORMANCE USING FULL-CHIP THERMAL ANALYSIS OF SEMICONDUCTOR CHIP
DESIGNS
Abstract
A method and apparatus for optimizing cooling system performance
using full-chip thermal analysis of semiconductor chip designs is
provided. One embodiment of a novel method for optimizing the
cooling of an electronic system incorporating at least one
semiconductor chip includes receiving full-chip temperature data
for the semiconductor chip(s) and configuring the cooling system
for dissipating heat from the electronic system in accordance with
the full-chip temperature data.
Inventors: |
CHANDRA; RAJIT; (Cupertino,
CA) |
Correspondence
Address: |
Moser, Patterson & Sheridan, LLP
Suite 100, 595 Shrewsbury Avenue
Shrewsbury
NJ
07702
US
|
Family ID: |
37728013 |
Appl. No.: |
12/046240 |
Filed: |
March 11, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11198467 |
Aug 5, 2005 |
|
|
|
12046240 |
|
|
|
|
10979957 |
Nov 3, 2004 |
7194711 |
|
|
11198467 |
|
|
|
|
60599278 |
Aug 5, 2004 |
|
|
|
Current U.S.
Class: |
716/111 ;
716/132; 716/136 |
Current CPC
Class: |
G06F 2111/06 20200101;
G06F 30/00 20200101; G06F 30/36 20200101; G06F 30/367 20200101;
G06F 2119/08 20200101; G06F 30/30 20200101; H05K 7/20209
20130101 |
Class at
Publication: |
716/2 |
International
Class: |
G06F 17/50 20060101
G06F017/50 |
Claims
1. A method for optimizing thermal management of an electronic
system, the method comprising: receiving full-chip temperature data
for a semiconductor chip incorporated in said electronic system;
configuring one or more thermal management resources of a thermal
management system in accordance with said full-chip temperature
data; and wherein said full-chip temperature data comprises a model
of a thermal gradient over said semiconductor chip in
operation.
2. The method of claim 1, wherein said model comprises a
three-dimensional thermal model of said semiconductor chip.
3. The method of claim 1, further comprising: computing said
full-chip temperature data.
4. The method of claim 3, wherein said computing is performed via a
transient analysis.
5. The method of claim 3, wherein said computing is performed in
accordance with a package of the semiconductor chip.
6. The method of claim 5, wherein said configuring comprises:
adjusting a design of said package.
7. The method of claim 6, wherein said adjusting provides
additional cooling to at least a portion of said semiconductor
chip.
8. The method of claim 5, wherein said computing is performed in
further accordance with a heat sink coupled to said package.
9. The method of claim 8, wherein said configuring comprises:
adjusting a design of said heat sink.
10. The method of claim 1, wherein said configuring is performed in
further accordance with full-chip temperature data for another
semiconductor chip mounted in a package with said semiconductor
chip.
11. The method of claim 10, further comprising: computing said
full-chip temperature data for said semiconductor chip in
accordance with said package.
12. The method of claim 10, further comprising: computing said
full-chip temperature data for said semiconductor chip in
accordance with said another semiconductor chip.
13. A computer readable medium containing an executable program for
optimizing thermal management of an electronic system, where the
program performs the steps of: receiving full-chip temperature data
for a semiconductor chip incorporated in said electronic system;
configuring one or more thermal management resources of a thermal
management system in accordance with said full-chip temperature
data; an wherein said full-chip temperature data comprises a model
of a thermal gradient over said semiconductor chip in
operation.
14. The computer readable medium of claim 13, wherein said model
comprises a three-dimensional thermal model of said semiconductor
chip.
15. The computer readable medium of claim 13, further comprising:
computing said full-chip temperature data.
16. The computer readable medium of claim 15, wherein said
computing is performed via a transient analysis.
17. The computer readable medium of claim 15, wherein said
computing is performed in accordance with a package of the
semiconductor chip.
18. The computer readable medium of claim 17, wherein said
configuring comprises: adjusting a design of said package.
19. The computer readable medium of claim 18, wherein said
adjusting provides additional cooling to at least a portion of said
semiconductor chip.
20. The computer readable medium of claim 17, wherein said
computing is performed in further accordance with a heat sink
coupled to said package.
21. The computer readable medium of claim 20, wherein said
configuring comprises: adjusting a design of said heat sink.
22. The computer readable medium of claim 13, wherein said
configuring is performed in further accordance with full-chip
temperature data for another semiconductor chip mounted in a
package with said semiconductor chip.
23. The computer readable medium of claim 22, further comprising:
computing said full-chip temperature data for said semiconductor
chip in accordance with said package.
24. The computer readable medium of claim 22, further comprising:
computing said full-chip temperature data for said semiconductor
chip in accordance with said another semiconductor chip.
25. Apparatus for optimizing thermal management of an electronic
system, the apparatus comprising: means for receiving full-chip
temperature data for a semiconductor chip incorporated in said
electronic system; means for configuring one or more thermal
management resources of a thermal management system in accordance
with said full-chip temperature data; and means for wherein said
full-chip temperature data comprises a model of a thermal gradient
over said semiconductor chip in operation.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/198,467, filed Aug. 5, 2005, which in turn
is a continuation-in-part of U.S. patent application Ser. No.
10/979,957, filed Nov. 3, 2004. In addition, application Ser. No.
11/198,467 claims the benefit of U.S. Provisional Patent
Application Ser. No. 60/599,278, filed Aug. 5, 2004. All of these
applications are herein incorporated by reference in their
entireties.
FIELD OF THE INVENTION
[0002] The present invention generally relates to computing
devices, and more particularly relates to systems for regulating
the temperatures of computing devices.
BACKGROUND OF THE INVENTION
[0003] Semiconductor chips typically comprise the bulk of the
components in an electronic system. These semiconductor chips are
also often the hottest part of the electronic system, and failure
of the system can often be traced back to thermal overload on the
chips. Thermal management of semiconductor chips is therefore a
critical parameter of electronic design, as it influences the
design of the cooling system for a computing device or system
incorporating the semiconductor chip.
[0004] FIG. 1 is a schematic diagram illustrating an exemplary
semiconductor chip 100. As illustrated, the semiconductor chip 100
comprises one or more semiconductor devices 102a-102n (hereinafter
collectively referred to as "semiconductor devices 102"), such as
transistors, resistors, capacitors, diodes and the like deposited
upon a substrate 104 and coupled via a plurality of wires or
interconnects 106a-106n (hereinafter collectively referred to as
"interconnects 106"). These semiconductor devices 102 and
interconnects 106 share power, thereby distributing a thermal
gradient over the chip 100 that may range from 100 to 180 degrees
Celsius in various regions of the chip 100.
[0005] Many methods currently exist for performing thermal analysis
of semiconductor chips designs, e.g., to ensure that a chip
constructed in accordance with a given design will not overheat and
trigger a failure when deployed within an intended system. Such
conventional methods, however, typically fail to provide a complete
or an entirely accurate picture of the chip's operating thermal
gradient. For example, typical thermal analysis models attempt to
solve the temperature on the chip substrate, but do not solve the
temperature in a full three dimensions, e.g., using industry
standards design, package and heat sink data. Moreover, most
typical methods do not account for the sharing of power among
semiconductor devices and interconnects, which distributes the heat
field within the chip, as discussed above. As a result, thermal
management systems designed manage internal temperatures and/or
thermal gradients in the chip (and/or system incorporating the
chip) in operation (e.g., by dissipating heat from the chip or
warming specific locations on the chip) are inefficiently designed.
In fact, typical thermal management systems are designed with
little or no knowledge of actual chip temperatures and gradients at
all. This often leads to chip and/or system failure due to
overheating or waste as excess cooling resources are directed to
regions in which they are not needed.
[0006] Therefore, there is a need in the art for a method and
apparatus for optimizing thermal management system performance
using full-chip thermal analysis of semiconductor chip designs.
SUMMARY OF THE INVENTION
[0007] A method and apparatus for optimizing thermal management
system performance using full-chip thermal analysis of
semiconductor chip designs is provided. One embodiment of a novel
method for optimizing the thermal management of an electronic
system incorporating at least one semiconductor chip includes
receiving full-chip temperature data for the semiconductor chip(s)
and configuring the thermal management system for managing heat in
the electronic system in accordance with the full-chip temperature
data.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above recited embodiments of
the invention are attained and can be understood in detail, a more
particular description of the invention, briefly summarized above,
may be had by reference to the embodiments thereof which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate only typical embodiments of
this invention and are therefore not to be considered limiting of
its scope, for the invention may admit to other equally effective
embodiments.
[0009] FIG. 1 is a schematic diagram illustrating an exemplary
semiconductor chip;
[0010] FIG. 2 is a schematic diagram illustrating one
implementation of a thermal analysis tool according to the present
invention;
[0011] FIG. 3 is a flow diagram illustrating one embodiment of a
method for performing three-dimensional thermal analysis of a
semiconductor chip design according to the present invention;
[0012] FIG. 4 is a graph illustrating the change in value of
transistor resistance for an exemplary negative channel metal oxide
semiconductor as a function of the output transition voltage;
[0013] FIG. 5 is a flow diagram illustrating one embodiment of a
method for optimizing the design of a thermal management system
based on knowledge of full-chip thermal gradients;
[0014] FIG. 6 is a flow diagram illustrating one embodiment of a
method 600 for processing semiconductor chip design and temperature
data to produce parameters for an optimal thermal management
configuration; and
[0015] FIG. 7 is a high level block diagram of the present thermal
management optimization method that is implemented using a general
purpose computing device.
[0016] To facilitate understanding, identical reference numerals
have been used, where possible, to designate identical elements
that are common to the figures.
DETAILED DESCRIPTION
[0017] Embodiments of the invention generally provide a method and
apparatus for optimizing the design of a thermal management system
in an electronic system (e.g., a computing device such as a desk
top computer, a laptop computer, a tablet computer, a personal
digital assistant, a cellular telephone, a gaming console or the
like) using full-chip temperature data for semiconductor chips
incorporated in the electronic system. One embodiment of the
inventive method analyzes a full, three-dimensional solution of
temperature values within a chip design, including power
dissipation values distributed over semiconductor devices (e.g.,
transistors, resistors, capacitors, diodes and the like) and wire
interconnects. This provides more a more accurate view of the
thermal conditions within the electronic device, thereby enabling a
thermal management system designer to configure the thermal
management system to manage heat in the electronic system in the
most efficient manner.
[0018] As used herein, the term "semiconductor chip" refers to any
type of semiconductor chip, which might employ analog and/or
digital design techniques and which might be fabricated in a
variety of fabrication methodologies including, but not limited to,
complementary metal-oxide semiconductor (CMOS), bipolar
complementary metal-oxide semiconductor (BiCMOS), and gallium
arsenide (GaAs) methodologies. Furthermore, as used herein, the
term "semiconductor device" refers to a potential active heat
dissipating device in a semiconductor chip, including, but not
limited to, transistors, resistors, capacitors, diodes and
inductors. The terms "wire", "interconnect" or "wire interconnect"
as used herein refer to any of various means of distributing
electrical signals (which may be analog or digital, static or
dynamic, logic signals or power/ground signals) from one place to
another. "Interconnects" may be on a semiconductor chip itself,
used in the packaging of the semiconductor chip, deployed between
the semiconductor chip and the packaging, or used in a variety of
other ways.
[0019] FIG. 2 is a schematic diagram illustrating one
implementation of a thermal analysis tool 200 according to the
present invention. As illustrated, the thermal analysis tool 200 is
adapted to receive a plurality of inputs 202a-202g (hereinafter
collectively referred to as "inputs 202") and process these inputs
202 to produce a full-chip (e.g., three-dimensional) thermal model
204 of a proposed semiconductor chip design.
[0020] In one embodiment, the plurality of inputs 202 includes
industry standard design data 202a-202f (e.g., pertaining to the
actual chip design or layout under consideration) and library data
202g (e.g., pertaining to the semiconductor devices and
interconnects incorporated in the design). In one embodiment, the
industry standard design data includes one or more of the following
types of data: electrical component extraction data and extracted
parasitic data (e.g., embodied in standard parasitic extraction
files, or SPEFs, 202a), design representations including layout
data (e.g., embodied in Library Exchange Format/Design Exchange
Format, or LEF/DEF files 202b, Graphical Design Format II, or
GDSII, files 202c and/or text files 202d), manufacturer-specific
techfiles 202e describing layer information and package models,
user-generated power tables 202f including design data (e.g.,
including a switching factor, E(sw)). In one embodiment, this
industry standard design data 202a-202f is stored in a design
database such as an open access database or a proprietary database.
In one embodiment, the library data 202g is embodied in a library
that is distributed by a semiconductor part manufacturer or a
library vendor. In another embodiment, the library incorporating
the library data 202g can be built in-house by a user.
[0021] In one embodiment, the library data 202g includes transistor
and diode models that are used to characterize the transistor
resistances (R.sub.dv) of the driver circuits, e.g., such as models
available through Berkeley short-channel Insulated Gate Field
Effect Transistor (IGFET) model (BSIM) models used by circuit
simulators including Simulation Program with Integrated Circuit
Emphasis (SPICE), HSPICE, commercially available from Synopsys,
Inc. of Mountain View, Calif. and Heterogeneous Simulation
Interoperability Mechanism (HSIM, commercially available from
Nassda Corporation of Santa Clara, Calif.), all developed at the
University of California at Berkeley.
[0022] As mentioned above, the plurality of inputs 202 are provided
to the thermal analysis tool 200, which processes the data in order
to produce a full-chip thermal model 204 of a proposed
semiconductor chip design. In one embodiment, the full-chip thermal
model is a three-dimensional thermal model.
[0023] Thus, as described above, embodiments of the present
invention rely on library data representing the electrical
properties of a semiconductor chip design (e.g., the resistance and
capacitance at various points) and the manners in which these
properties may vary with respect to each other and with respect to
other phenomena (e.g., temperature or fabrication variations).
Those skilled in the art will appreciate that these electrical
properties may be specified or calculated in any number of ways,
including, but not limited to, table-driven lookups, formulas based
on physical dimensions, and the like.
[0024] FIG. 3 is a flow diagram illustrating one embodiment of a
method 300 for performing full-chip thermal analysis of a
semiconductor chip design according to the present invention. The
method 300 may be implemented, for example, in the thermal analysis
tool 200 illustrated in FIG. 2. In one embodiment, the method 300
relies on the computation of power dissipated by various
semiconductor devices of the semiconductor chip design. As will be
apparent from the following discussion, this power computation may
be performed in any number of ways, including, but not limited to,
table-driven lookups, computations based on electrical properties,
circuit simulations, and the like. Moreover, those skilled in the
art will appreciate that although the following description
discusses the effects of resistance on power dissipation, power
dissipation computations could be based on any number of other
electrical properties or parameters, including, but not limited to,
capacitance, inductance and the like. Moreover, the computations
could be static or dynamic.
[0025] The method 300 is initialized at step 302 and proceeds to
step 304, where the method 300 determines the collection of
semiconductor devices (e.g., transistor, resistors, capacitors,
diodes inductors and the like) and their resistances. In one
embodiment, the method 300 determines this information by reading
one or more of the chip layout data (e.g., in GDS II, DEF and/or
text format), layer and package model data (e.g., from one or more
techfiles), and initial power and power versus temperature data for
the semiconductor devices (e.g., from the library data). In one
embodiment, initial power values and power values as a function of
temperature may be recorded within a common power table for
acceptable operating ranges for the driver circuits within the chip
design. The driver circuits may be at semiconductor device level or
at cell level, where cell level circuits represent an abstraction
of interconnected semiconductor devices making up a known
function.
[0026] In step 306, the method 300 uses the information collected
in step 304 to calculate the time average resistance values for
every semiconductor device in every driver circuit of the chip
design, as well as for every diode junction. These time-average
resistance values relate to changes in semiconductor device
dimensions (e.g., such as using higher power transistors in place
of lower power transistors in a chip design). In one embodiment,
the time average resistance value, R.sub.average for a
semiconductor device is calculated as:
R average = .intg. 0 t r R v ( t ) t t r ( EQN . 1 )
##EQU00001##
where t.sub.r is the output transition time of the driver circuit
under consideration, e.g., as specified by the library data.
[0027] FIG. 4 is a graph illustrating the change in value of
transistor resistance, R.sub.dv for an exemplary negative channel
metal oxide semiconductor (nMOS) as a function of the output
transition voltage, V.sub.driver.sub.--.sub.out. As illustrated,
the power dissipated by a transistor varies during switching. This
is also true for the power dissipated in other semiconductor
devices and in the interconnects coupled to the semiconductor
devices on the chip.
[0028] Referring back to FIG. 3, in step 308, the method 300
calculates the power dissipated by the semiconductor devices and
interconnects at a given temperature for the design under
consideration. In one embodiment of step 308, e.g., where a
steady-state analysis of the chip design is being performed, the
interdependence of temperature and average power is captured
through pre-characterized parameters of the semiconductor devices
and interconnects. In one embodiment, the power dissipated by a
semiconductor device (in this exemplary case, a transistor), P
transistor, is calculated as:
P.sub.transistor=(V.sub.d).sup.2/R.sub.average (EQN. 2)
where V.sub.d is the power supply voltage supplied to the
transistor. This voltage, V.sub.d, is less than the actual power
supply voltage, V.sub.dd, as the current drawn by the transistors
and flowing through the interconnects that connect the transistors
to a power supply causes a voltage drop. In another embodiment, the
power supply voltage to the transistor V.sub.d could be divided by
the maximum or minimum resistance value, R.sub.max or R.sub.min, in
order to calculate the power dissipated in the transistor. In one
embodiment, a decision as to whether to use an average, minimum or
maximum resistance value to calculate P.sub.transistor is based at
least in part on whether additional conditions, such as the
operation of the circuit, are to be evaluated.
[0029] While equations for calculating the power dissipation of
transistors have been provided herein by way of example, those
skilled in the art will appreciate that various methods of
calculating power dissipation for other semiconductor devices, such
as resistors, capacitors and diodes, are known in the art. For
example, equations for calculating the power dissipation of a
resistor are discussed in the Proceedings of the Fourth
International Symposium on Quality Electronic Design (ISQED 2003),
24-26 Mar. 2003, San Jose, Calif.
[0030] In one embodiment, the power dissipated by the interconnects
(e.g., power and signal lines), P interconnect is calculated
as:
P.sub.interconnect=P-P.sub.transistor (EQN. 3)
where P is the average electrical power dissipated per clock cycle
by a digital circuit (e.g., the chip design under consideration;
for the full chip, the total P is the sum of the power dissipated
by each circuit in the chip) and is available from the library data
202g. In the power lines, power is typically dissipated as Joule
heating, where the dissipated power P dissipated may be calculated
as:
P.sub.dissipated=I.sub.p.sup.2R.sub.power (EQN. 4)
where I.sub.p is the current through the power lines and
R.sub.power is the resistance of the power bus. The value of
I.sub.p may be calculated by commercially available tools, such as
Voltage Storm, available from Cadence Design Systems, Inc. of San
Jose, Calif.
[0031] Typically, the power drawn by a switching transistor may be
calculated as:
P=C.sub.loadV.sub.ddE(sw)(fclk) (EQN. 5)
where C.sub.load is the output capacitance as seen by the circuit,
E(sw) is the switching activity as defined by the average number of
output transitions per clock period, and fclk is the clock
frequency. The switching factor or activity, E(sw), is used for
evaluating the power table for the initial state of the design.
C.sub.load may be calculated by parasitic extraction tools, and
values for fclk and V.sub.dd are typically specified for a given
design. In general, half of the power, P, is stored in the
capacitance and the other half is dissipated in the transistors and
interconnects (e.g., the power and signal lines). Those skilled in
the art will appreciate that since R.sub.average varies with the
transition time of the circuits, and as the switching activity
changes for different modes of operation, E(sw) will also change,
thereby changing the value of P and the distribution of the amounts
of power dissipated in the transistors (e.g., see Equation 2) and
interconnects. This will, in turn, change the heat fields and
corresponding temperatures within the chip.
[0032] In another embodiment of step 308, a transient analysis is
performed, wherein the interdependence of temperature and average
power in the semiconductor devices and interconnects is based on
instantaneous values of power. In this case, power dissipated
values are calculated by dynamically simulating the circuit
embodied in the chip design under consideration. For example, the
circuit may be simulated using any commercially available circuit
simulator, such as HSPICE or HSIM, discussed above, or SPECTRE,
commercially available from Cadence Design Systems. In one
embodiment, the circuit is simulated by solving for values of
electrical attributes (e.g., current and voltages) at various
points in time. In the case of transient thermal analysis, the
thermal analysis system (e.g., thermal analysis tool 200 of FIG. 2)
drives the circuit simulator to calculate power at discrete points
whenever there is a sufficient change in the temperature of the
circuit. In one embodiment, the sufficiency of a temperature change
for these purposes is determined by a predefined threshold.
[0033] In step 310, the method 300 distributes the power consumed
in each of the interconnects. In one embodiment, power is
distributed based on the resistance of the wires used in the
interconnects, which is defined by the type, thickness and height
of the wires used in the interconnects. In one embodiment, the
resistance, R.sub.interconnect, of an interconnect segment is
calculated as:
R interconnected = .rho. L wt ( EQN . 6 ) ##EQU00002##
where L is the length of the interconnect segment, w is the width
of the segment, t is the thickness of the segment, and .rho. is a
resistivity constant dependent upon the type of wire used. The
resistivity constant, .rho., may be found in tables included in any
number of integrated circuits textbooks, including Rabaey et al.,
Digital Integrated Circuits, Second Edition, Prentice Hall
Electronic and VLSI Series, 2002.
[0034] In step 312, the method 300 uses the power dissipation and
distribution information calculated in steps 306-310 to model a
full-chip (e.g., three-dimensional) temperature gradient over the
chip design under consideration. In one embodiment, a full-chip
temperature gradient is modeled by adaptively partitioning the
volumes of steep temperature gradients over the chip design. In one
embodiment, partitioning is done in three dimensions; however, in
other embodiments, partitioning may be done in one or two
dimensions as well (for example, vertical partitioning may be
explicitly considered in how the temperature is modeled). In one
embodiment, "steep" temperature gradients are those portions of the
overall temperature gradient that are steep relative to other
regions of the overall temperature gradient. In one embodiment,
techfile data (e.g., pertaining to the dimensions and properties of
the chip design layers) and power density data are used to
partition the chip design. Power density data is typically
contained within the power table provided for a particular state of
operation of a chip design. The temperatures in each partition are
then determined and annotated accordingly in the three-dimensional
model.
[0035] In step 314, the method 300 determines whether the currently
computed temperature for the chip design falls within a previously
specified range. If the method 300 concludes that the currently
computed temperature does not fall within this range, the method
300 proceeds to step 318 and modifies the chip design (e.g., by
changing the resistances of the semiconductor devices and
interconnects, resizing the semiconductor devices and interconnect
wires, etc.). The method 300 then returns to step 308 and proceeds
as discussed above.
[0036] Alternatively, if the method 300 determines that the
currently computed temperature does fall within the specified
range, the method 300 proceeds to step 316 and terminates. Thus,
steps of the method 300 may be repeated in an iterative manner
until a steady state value is reached, within a specified
tolerance. In one embodiment, iteration of these steps may depend
on the particular implementation of the method 300. In further
embodiments, iteration could include convergence to an absolute
value, convergence to a relative value, or the passing of a fixed
number or iterations or a fixed amount of time.
[0037] Thus, the method 300 employs industry standard design,
package and heat sink data in order to produce a more complete and
more accurate profile of the temperature gradient created by a
semiconductor chip design. By accounting for the distribution of
power dissipated in the semiconductor devices and in the
interconnects, rather than simply characterizing dissipated power
as the power dissipated in the active semiconductor devices (which
does not consider simultaneous changes in the electrothermal
properties of the semiconductor devices and interconnects), more
accurate, full-chip thermal profiling can be achieved.
[0038] Chip designers may use the full-chip data produced by the
method 300 to design more robust semiconductor chips for particular
applications. For example, if the full-chip temperature gradient
produced by one iteration of the method 300 does not illustrate
acceptable results for a semiconductor chip design, a chip designer
may go back and modify the chip design (e.g., by changing the
resistances of the semiconductor devices and interconnects,
resizing the semiconductor devices and interconnect wires, etc.) in
an attempt to achieve more desirable results. The method 300 may
then be applied to the modified design to assess the resultant
temperature gradient. Those skilled in the art will appreciate that
while the method 300 illustrates a series of steps, the present
invention is not limited to the particular sequence illustrated,
and thus FIG. 3 should be considered only as one exemplary
embodiment of the present invention.
[0039] In one embodiment, the full-chip temperature data produced
by the method 300 may be implemented to optimize the design of a
thermal management system for managing heat in a semiconductor chip
and/or an electronic system or computing device incorporating the
semiconductor chip. That is, the full-chip temperature data may
guide a thermal management system or electronic system designer in
more precisely identifying those areas of the chip and/or
electronic system that require the most cooling or warming, or the
least cooling or warming, thereby enabling efficient design and use
of thermal management resources. Design of the thermal management
system may additionally include the design of an interface between
the thermal management system and the semiconductor chip or package
whose thermal characteristics are to be regulated by the thermal
management system. The thermal management system may comprise a
cooling system (e.g., a mechanical or fluid cooling system) for
dissipating heat from specific areas of the semiconductor chip
and/or a heating system for warming specific areas of the
semiconductor chip (e.g., in order to locally minimize thermal
gradients). Furthermore, the thermal management system may comprise
a plurality of components distributed over each semiconductor chip
and/or other components of the electronic system (e.g., each
semiconductor chip may have its own "mini" thermal management
system that is part of the thermal management system for the
overall electronic system). The full-chip temperature data may aid
in the optimization of substantially any thermal management system,
including external thermal management systems and internal or
on-chip thermal management systems.
[0040] FIG. 5 is a flow diagram illustrating one embodiment of a
method 500 for optimizing the design of a thermal management system
based on knowledge of full-chip thermal gradients. The method 500
is initialized at step 502 and proceeds to step 504, where the
method 500 receives full-chip temperature data for at least one
semiconductor chip incorporated within the electronic system to be
managed by the thermal management system. In one embodiment, the
system may be a single semiconductor chip itself, or a stack or
arrangement of multiple semiconductor chips. This full-chip
temperature data may be received, for example, from a thermal
analysis tool such as the thermal analysis tool 200.
[0041] In step 506, the method 500 receives thermal parameters for
the electronic system to be managed by the thermal management
system. In one embodiment, system thermal parameters include at
least one of: electrical and/or thermal constraints of the
electronic system, external chip conditions (e.g., conditions
within the electronic system but external to the semiconductor
chips incorporated therein), electronic system usage conditions,
thermal management system type (e.g., mechanical, fluid-based,
etc.), thermal management system materials, air or fluid flow
direction and/or orientation for the elements of the thermal
management system and semiconductor chip package materials.
[0042] In step 508, the method 500 determines the optimal thermal
management configuration for the system in accordance with the
full-chip temperature data and the system thermal parameters. That
is, the method 500 determines, based on a plurality of inputs
including the actual temperature gradients within the semiconductor
chip(s) and the thermal requirements of the electronic system, the
degree of thermal management required in each area of the
electronic system (e.g., the type, location and direction of
elements of the thermal management system). One embodiment of a
method for processing this plurality of inputs to determine the
optimal thermal management configuration is described in greater
detail in FIG. 6.
[0043] In one embodiment, the plurality of inputs specifically
includes at least one of: thermal characteristics of the cooling
and/or heating components of the thermal management system (e.g.,
thermal conductivity, heat transfer coefficient, thermal
resistances of junction-to-air, junction-to-case, case-to-spreader,
etc.), physical dimensions of the elements of the thermal
management system, constraints of the thermal management system
(e.g., switch on and off latency, zone of effectiveness, cost,
mechanical characteristics, electrical power consumed,
environmental factors such as noise, etc.).
[0044] The effectiveness of each of these inputs in equalizing
temperature and thermal gradient effects on the semiconductor
chip(s) is assessed. In particular, thermal characteristics of the
thermal management system enable the method 500 to assess the
temperature values in the semiconductor chip design(s) using
boundary conditions presented by the thermal management system.
Chip temperatures and their influence on the electrical
characteristics of the semiconductor chip design are computed using
these boundary conditions and then applied to optimize the
configuration of the thermal management system.
[0045] Because the temperature gradient may vary widely over a
semiconductor chip in operation, some areas of a semiconductor chip
may require a great deal of cooling or warming, while other areas
may require very little cooling or warming. Based on this
determination, thermal management resources may be allocated in the
most efficient manner among components in the electronic system, as
well as among components incorporated within the semiconductor
chip(s). In one embodiment, the optimal thermal management
configuration may involve directing thermal management resources
toward local "hot spots" on a semiconductor chip, e.g., by
repositioning elements a cooling system (e.g., to redirect air or
fluid flow), by adjusting the design of components of the thermal
management system (e.g., a heat sink) or by adjusting the
orientation of the semiconductor chip package to account for a
direction of cooling (e.g., air or fluid flow).
[0046] In one embodiment, the optimal thermal management
configuration specifies a plurality of parameters, including at
least one of: coordinates or positions of the thermal management
system components with respect to a reference point in the
semiconductor chip design(s) (e.g., Cartesian or spherical
coordinates), orientation of the thermal management system
components with respect to the semiconductor chip(s) whose
full-chip temperature data is received in step 504, and
state-dependent conditions for the thermal management system. For
example, in the case where on-chip control of the thermal
management system is enabled (e.g., such that the operating states
of the thermal management system are controllable in response to
thermal gradients associated with each operating state of the
semiconductor chip design(s)), the internal state of the
semiconductor chip (s) and the associated thermal gradient
computations are used to set the operating state of the thermal
management system. In one embodiment, the operating state of the
thermal management system includes mechanisms that influence the
heat transfer between the semiconductor chip(s) and the surrounding
environment, such as fan turn on and turn off, fan speed,
electrostatic airflow rate, heating components, injection of
coolants, evaporation rate control and ionization density.
[0047] In the case where on-chip control of the thermal management
system is not enabled, the positions of the thermal management
system are designed and implemented to alleviate the worst-case
temperature-dependent electrical failure conditions.
[0048] In step 510, the method 500 calculates the full-chip
temperature data for the semiconductor chip design(so incorporated
in the electronic system (e.g., in accordance with the method 300),
accounting for the optimal thermal management configuration as
determined in step 508.
[0049] In step 512, the method 500 determines whether the
electronic system requirements (which include individual
semiconductor chip requirements) are met, according to the newly
calculated full-chip temperature data. Thus, the method 500
determines whether the optimal thermal management configuration
determined in step 508 will sufficiently manage the temperatures
and thermal gradients of the electronic system as required. If the
system requirements are met, the method 500 terminates in step 514.
Alternatively, if the system requirements are not met, the method
500 returns to step 508 are proceeds as described above in order to
adjust the thermal management configuration for optimal performance
within the constraints of the system.
[0050] The method 500 thereby enables more efficient design of
thermal management systems for electronic systems by accounting for
the full-chip thermal gradients of the semiconductor chips
incorporated therein. Based on this information, thermal management
resources can be allocated to the various areas of the electronic
system and/or semiconductor chip(s) in the most efficient manner.
This provides better use of thermal management resources than
existing thermal management systems, which tend to manage the
temperatures and thermal gradients the electronic system in a more
general manner (e.g., based on the absolute temperature value, with
little or no regard to actual local variations in temperature).
Thus, electronic system failures and waste of thermal management
system resources can be significantly reduced.
[0051] In addition, the full-chip temperature data (e.g., as
computed by the method 300) may be implemented in designing the
heat transfer properties of a semiconductor chip package, thereby
also efficiently reducing the thermal gradients over the
semiconductor chip. For example, for packages incorporating
multiple semiconductor chips, the method 500, in conjunction with
the full-chip temperature data, may guide the arrangement of the
multiple semiconductor chips that offers the best thermal
management of the electrical or thermal constraints on the
electronic system design. Thus, semiconductor package design as
well as cooling system design may be enhanced by application of the
method 300 and/or the method 500.
[0052] FIG. 6 is a flow diagram illustrating one embodiment of a
method 600 for processing semiconductor chip design and temperature
data to produce parameters for an optimal thermal management
configuration. The method 600 may be implemented, for example, in
accordance with steps 508-512 of the method 500.
[0053] The method 600 is initialized at step 602 and proceeds to
step 604, where the method 600 receives the thermal inputs
described above (e.g., full-chip temperature data, thermal
characteristics of the cooling and/or heating components of the
thermal management system, physical dimensions of the elements of
the thermal management system and constraints of the thermal
management system) and the initial conditions for the electronic
system. In one embodiment, the initial conditions for the
electronic system include at least one of: starting temperatures
for the semiconductor chips incorporated therein, ambient
temperatures in which the electronic system is intended to work,
the position and efficiency of thermal management systems
incorporated therein (e.g., the thermal resistances of the heat
sinks, fans, etc.).
[0054] In step 606, the method 600 sorts the temperature gradients
within the semiconductor chip(s) incorporated in the electronic
system design. The temperature gradients are sorted in three
dimensions. In one embodiment, the temperature gradients are sorted
according to the magnitudes of the gradients (e.g., from smallest
gradient to largest gradient).
[0055] In step 608, the method 600 selects a weighting parameter in
three dimensions (e.g., x, y and z) based on the initial chip
boundary conditions. Essentially, the weighting parameter is a
specific parameter that aids in ranking those areas of the
semiconductor chip that can most efficiently dissipate heat. In one
embodiment, the weighting parameter is a thermal property of a
given location on the semiconductor chip, such as at least one of:
composite conductivity in the heat transfer direction, thermal
conductance in the heat transfer direction, thermal resistance from
a first location to a second location (e.g., from junction to
ambient) and heat transfer coefficient. The selection of the
weighting parameter may vary as a function of the semiconductor
chip's layout and/or material properties.
[0056] In step 610, the method 600 selects a set of trial
parameters with weighting functions for the boundary conditions
along the semiconductor chip/package interface. In one embodiment,
the set of trial parameters includes at least one of: thermal
resistance, heat transfer coefficients between the semiconductor
chip package and the thermal management system, and internal
conductivity factors of the semiconductor chips (e.g., to optimize
the paths that will lead to lower temperature gradients). In one
embodiment, the set of trial parameters is chosen such that the
thermal resistance is at a minimum in the location or region of the
maximum on-chip temperature. This implies that the direction of the
heat flow is taken into account in the choice of location for the
minimum thermal resistance, and that the magnitude of the
temperature is used to determine the value of the thermal
resistance achievable using the thermal management system.
[0057] In step 612, the method 600 solves the on-chip temperatures
in accordance with the selected trial parameters. In one
embodiment, step 612 may be performed in accordance with the method
300 described above.
[0058] In step 614, the method 600 determines for each
semiconductor chip incorporated in the electronic system, whether
the minimum temperature differentials (e.g., as defined by design
constraints on the semiconductor chip) are achieved in three
dimensions, based on the on-chip temperatures calculated in step
612.
[0059] If the method 600 determines in step 614 that the minimum
temperature differentials are not achieved in three directions for
all semiconductor chips, the method 600 returns to step 606 and
proceeds as described above in order to select a new set of trial
parameters for those chips.
[0060] Alternatively, if the method 600 determines in step 614 that
the minimum temperature differentials are achieved in three
directions for all semiconductor chips, the method 600 proceeds to
step 616 and determines for each semiconductor chip incorporated in
the electronic system, whether predefined design constraints on the
on-chip thermal gradients are met.
[0061] If the method 600 determines in step 616 that the thermal
gradients are not within the design constraints for all
semiconductor chips, the method 600 proceeds to step 618 and
assumes that a heating component of the thermal management system
is at least partially responsible for the oversized thermal
gradient(s). The method 600 then returns to step 606 and proceeds
as described above in order to select a new set of trial parameters
for those chips.
[0062] Alternatively, if the method 600 determines in step 616 that
the thermal gradients are within the design constraints for all
semiconductor chips, the method 600 proceeds to step 620 and
translates the selected trial parameters into a corresponding
thermal management system configuration (e.g., including
coordinates or positions of the thermal management system
components with respect to a reference point in the semiconductor
chip design, orientation of the thermal management system
components with respect to the semiconductor chip whose full-chip
temperature data is received in step 504, and state-dependent
conditions for the thermal management system, as described above
with respect to the method 500).
[0063] The method 600 then terminates in step 622.
[0064] FIG. 7 is a high level block diagram of the present thermal
management optimization method that is implemented using a general
purpose computing device 700. In one embodiment, a general purpose
computing device 700 comprises a processor 702, a memory 704, a
thermal management optimization module 705 and various input/output
(I/O) devices 706 such as a display, a keyboard, a mouse, a modem,
a network connection and the like. In one embodiment, at least one
I/O device is a storage device (e.g., a disk drive, an optical disk
drive, a floppy disk drive). It should be understood that the
thermal management optimization module 705 can be implemented as a
physical device or subsystem that is coupled to a processor through
a communication channel.
[0065] Alternatively, the thermal management optimization module
705 can be represented by one or more software applications (or
even a combination of software and hardware, e.g., using
Application Specific Integrated Circuits (ASIC)), where the
software is loaded from a storage medium (e.g., I/O devices 706)
and operated by the processor 702 in the memory 704 of the general
purpose computing device 700. Additionally, the software may run in
a distributed or partitioned fashion on two or more computing
devices similar to the general purpose computing device 700. Thus,
in one embodiment, the thermal management optimization module 705
for optimizing the design of a thermal management system for an
electronic system described herein with reference to the preceding
figures can be stored on a computer readable medium or carrier
(e.g., RAM, magnetic or optical drive or diskette, and the
like).
[0066] Thus, the present invention represents a significant
advancement in the field of thermal management system design.
Embodiments of the invention analyzes a full, three-dimensional
solution of temperature values within a design of a semiconductor
chip to be incorporated within an electronic system to be cooled,
including power dissipation values distributed over semiconductor
devices (e.g., transistors, resistors, capacitors, diodes and the
like) and wire interconnects. This provides more a more accurate
view of the thermal conditions within the electronic device,
thereby enabling a thermal management system designer to configure
the thermal management system to manage heat in the electronic
system in the most efficient manner. Specifically, by accounting
for actual or calculated semiconductor chip temperature data in the
initial design of the thermal management system (e.g., rather than
designing a generic thermal management system or a thermal
management system based on assumed chip temperatures), more
efficient use of thermal management resources and more effective
thermal management of an electronic system can be achieved.
[0067] While the foregoing is directed to embodiments of the
invention, other and further embodiments of the invention may be
devised without departing from the basic scope thereof, and the
scope thereof is determined by the claims that follow.
* * * * *