U.S. patent application number 12/038666 was filed with the patent office on 2008-07-03 for wear leveling techniques for flash eeprom systems.
Invention is credited to Anil Gupta, Karl M.J. Lofgren, Robert D. Norman, Gregory B. Thelin.
Application Number | 20080162798 12/038666 |
Document ID | / |
Family ID | 25054816 |
Filed Date | 2008-07-03 |
United States Patent
Application |
20080162798 |
Kind Code |
A1 |
Lofgren; Karl M.J. ; et
al. |
July 3, 2008 |
WEAR LEVELING TECHNIQUES FOR FLASH EEPROM SYSTEMS
Abstract
A mass storage system made of flash electrically erasable and
programmable read only memory ("EEPROM") cells organized into
blocks, the blocks in turn being grouped into memory banks, is
managed to even out the numbers of erase and rewrite cycles
experienced by the memory banks in order to extend the service
lifetime of the memory system. Since this type of memory cell
becomes unusable after a finite number of erase and rewrite cycles,
although in the tens of thousands of cycles, uneven use of the
memory banks is avoided so that the entire memory does not become
inoperative because one of its banks has reached its end of life
while others of the banks are little used. Relative use of the
memory banks is monitored and, in response to detection of uneven
use, have their physical addresses periodically swapped for each
other in order to even out their use over the lifetime of the
memory.
Inventors: |
Lofgren; Karl M.J.; (Newport
Beach, CA) ; Norman; Robert D.; (San Jose, CA)
; Thelin; Gregory B.; (Garden Grove, CA) ; Gupta;
Anil; (Irvine, CA) |
Correspondence
Address: |
DAVIS WRIGHT TREMAINE LLP - SANDISK CORPORATION
505 MONTGOMERY STREET, SUITE 800
SAN FRANCISCO
CA
94111
US
|
Family ID: |
25054816 |
Appl. No.: |
12/038666 |
Filed: |
February 27, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11028882 |
Jan 3, 2005 |
7353325 |
|
|
12038666 |
|
|
|
|
10428422 |
May 2, 2003 |
6850443 |
|
|
11028882 |
|
|
|
|
09108084 |
Jun 30, 1998 |
6594183 |
|
|
10428422 |
|
|
|
|
07759212 |
Sep 13, 1991 |
6230233 |
|
|
09108084 |
|
|
|
|
Current U.S.
Class: |
711/103 ;
711/E12.001 |
Current CPC
Class: |
G06F 12/0246 20130101;
G06F 2212/1036 20130101; G11C 16/3495 20130101; G11C 16/349
20130101; G06F 2212/7211 20130101; G11C 8/12 20130101 |
Class at
Publication: |
711/103 ;
711/E12.001 |
International
Class: |
G06F 12/00 20060101
G06F012/00 |
Claims
1. A method of operating a memory system having a non-volatile
array of memory cells with a controller thereof connected thereto,
wherein the array of memory cells is divided into distinct groups
of memory cells that are erasable together prior to re-writing data
therein, wherein: a plurality of quantities of a characteristic of
operation of the array of memory cells is monitored, a variable
related to differences in the monitored quantities is feed back to
the controller, and the controller uses the feedback variable to
change the characteristic of operation in a manner to reduce the
feed back variable during further operation of the memory system
but with a feedback gain that is limited by only changing the
characteristic of operation at intervals defined by a total of the
quantities of the characteristic.
2. The method of claim 1, wherein the characteristic includes
operational cycles experienced by individual groups of memory
cells, and the quantities include numbers of the operational cycles
experienced by the individual groups of memory cells.
3. The method of claim 2, wherein the feedback variable includes a
difference between the numbers of operational cycles of individual
groups of memory cells.
4. The method of claim 3, wherein the controller controls the
numbers of operational cycles experienced by the individual groups
of memory cells in a manner that tends to minimize the differences
between the numbers of operational cycles of individual groups of
memory cells.
5. The method of claim 4, wherein the controller controls the
numbers of operational cycles experienced by the individual groups
of memory cells by at least moving data stored in individual groups
of memory cells among identified groups of memory cells and
reassigning logical addresses of the identified groups of memory
cells that are recognized at an interface of the memory system to
physical addresses of different identified groups of memory cells.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of application Ser. No.
11/028,882, filed Jan. 3, 2005, which is a continuation of
application Ser. No. 10/428,422, filed May 2, 2003, now U.S. Pat.
No. 6,850,443, which is a continuation of application Ser. No.
09/108,084, filed Jun. 30, 1998, now U.S. Pat. No. 6,594,183, which
is a continuation of application Ser. No. 07/759,212, filed Sep.
13, 1991, now U.S. Pat. No. 6,230,233, which applications and
patents are incorporated herein in their entirety by this
reference.
BACKGROUND OF THE INVENTION
[0002] This invention relates generally to mass digital data
storage systems using flash electrically erasable and programmable
read only memory ("EEPROM") technology, and, more specifically, to
techniques of controlling the use of such systems in order to
improve their useful life.
[0003] An advantage of using EEPROM technology is that a
solid-state, non-volatile memory is provided, which can be
repetitively reprogrammed. Each EEPROM cell includes an
electrically floating gate positioned over a substrate channel
between source and drain regions. A thin gate oxide layer separates
the floating gate from the substrate. The threshold level of the
cell is controlled by an amount of charge that is placed on the
floating gate. If the charge level is above some threshold, the
cell is read to have one state, and if below that threshold, is
read to have another state.
[0004] The desired floating gate charge level is programmed by
applying an appropriate combination of voltages to the source,
drain, substrate and a separate control gate, for a designated
period of time, in order to cause electrons to move from the
substrate to the floating gate through the gate oxide layer.
Current leakage from the floating gate is very small over time,
thereby providing permanent storage. The charge level on the
floating gate can be reduced by an appropriate combination of
voltages applied to the elements described above, but it is
preferable to include a separate erase gate that is positioned
adjacent the floating gate with a thin layer of tunnel oxide
between them.
[0005] A large number of such cells form a memory. The cells are
preferably arranged on a semiconductor integrated circuit chip in a
two-dimensional array with a common control gate provided for a row
of such cells as a word line and the cells in each column having
either their drain or source connected to a common bit line. Each
cell is then individually addressable by applying the appropriate
voltages to the word and bit lines that intersect at the desired
cell. Rather than providing for such individual addressing for the
purpose of erasing the cells, however, the erase gates of a block
of cells are generally connected together in order to allow all of
the cells in the block to be erased at the same time, i.e., in a
"flash".
[0006] In operating such a memory system, cells can be rewritten
with data by either programming with electrons from the substrate
or erasing through their erase gates, depending upon the state in
which they are found and the state to which they are to be
rewritten. However, flash EEPROM systems are generally operated by
first erasing all of the cells in a erasable block to a common
level, and then reprogramming them to desired new states.
[0007] Flash EEPROM mass storage systems have many advantages for a
large number of applications. These advantages include their
non-volatility, speed, ease of erasure and reprogramming, small
physical size and similar factors. Because there are no mechanical
moving parts, such systems are not subject to failures of the type
most often encountered with hard and floppy disk mass storage
systems. However, EEPROM cells do have a limited lifetime in terms
of the number of times they can be reprogrammed or erased. As the
number of cycles to which a cell is subjected reaches a few tens of
thousands, it begins to take more voltage and/or time to both
program and erase the cell. This is believed due to electrons being
trapped in the respective gate and tunnel dielectric layers during
repetitive programming and erase cycles. After a certain number of
cycles, the number of electrons that are so trapped begin to change
the operating characteristics of the cell. At some point, after one
hundred thousand or more such cycles, so much voltage or time is
required to either program or erase the cell, or both, that it
becomes impractical to use it any further. The lifetime of the cell
has at that point ended. This characteristic of EEPROM cells is
described in European Patent Application Publication No.
349,775--Harari (1990).
[0008] Therefore, it is a principal object of the present
invention, given a finite lifetime of individual EEPROM cells, to
maximize the service lifetime of an entire mass storage EEPROM
system.
SUMMARY OF THE INVENTION
[0009] This and additional objects are accomplished by the present
invention, wherein, briefly and generally, the EEPROM array of
cells is divided into two or more interchangeable banks of cells,
each bank having one or more blocks of cells. A block is the
smallest group of cells that is erasable or programmable at one
time. A memory controller provides for interchanging such banks
over the lifetime of the memory at times when it is detected that
they are receiving significantly uneven use.
[0010] If such an interchange, or wear leveling, is not carried out
in the case where there is significantly uneven use among groups of
EEPROM cells, one group will reach its end of lifetime while other
groups have significant life left in them. When one group reaches
an end of lifetime, the entire memory may have to be replaced
unless extra groups of memory cells are included in the system for
replacing those that reach their lifetime. However, the techniques
of the present invention allow for extending overall memory system
lifetime without having to provide such replacement groups of
memory cells. The ability to interchange groups of cells to result
in more even wear among the groups is particularly advantageous in
computer system applications wherein flash EEPROM memory is used in
the nature of a disk drive. This is because the memory is subjected
to frequent erase and reprogramming cycles in some groups but not
others, and since the large capacity of the memory would require a
large number of spare groups in order to obtain a reasonable memory
system lifetime without use of the group interchange technique of
the present invention.
[0011] Additional objects, advantages and features of the various
aspects of the present invention will become apparent from the
following description of its preferred embodiments, which
description should be taken in conjunction with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 generally illustrates in block diagram form a
computer system with non-volatile solid state memory that utilizes
the various aspects of the present invention;
[0013] FIG. 2 schematically illustrates ways in which the solid
state memory in the system of FIG. 1 may be operated in accordance
with the present invention;
[0014] FIG. 3 shows in block diagram form a specific type of memory
system of FIG. 1 in which the present invention is utilized;
[0015] FIG. 4 shows a preferred organization of a block of memory
cells of the system of FIG. 3;
[0016] FIG. 5 is a flow diagram showing a preferred operation of
the memory system of FIGS. 3 and 4; and
[0017] FIGS. 6A, 6B and 6C illustrate certain operations set forth
in the flow diagram of FIG. 5.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] In order to set forth one environment in which the improved
memory system of the present invention may be utilized, FIG. 1
shows a general computer system that includes flash EEPROM memory
array 11 whose operation is controlled by a memory controller 13.
The memory system 11 and 13 is connected to a computer system bus
15, to which also are connected a system controlling microprocessor
17, random access memory ("RAM") 19, input/output circuits ("I/O")
21, and various other components as appropriate for a specific
computer system. In the improvements being described, the memory
controller 13 manages operation of the EEPROM memory 11 in a way to
maximize the lifetime of the memory system by avoiding uneven use
of any one part of it.
[0019] FIG. 2 is a diagram which conceptually and generally
illustrates such a memory operation technique as well as showing
various alternatives for specific implementations of the technique.
The EEPROM memory 11 is organized into a large number of blocks of
flash EEPROM cells, each block being the smallest unit of cells
that is flash erasable. In the case where separate erase gates are
provided as part of the EEPROM cells, all the erase gates of the
cells in each block are connected together. The blocks of memory
cells are further organized into banks. Each of the n banks in this
illustration contain m blocks. The quantity n must be at least two,
and the quantity m is one or more.
[0020] In a specific form, each block is designed to contain a
standard computer sector's worth of data plus some overhead fields.
Blocks of data, indicated in dashed outline by a block 23, are
received from the computer system over the bus 15, indicated to
travel along a path 25. A logical address of a memory location for
a block 23 to be written into is also sent by the computer system.
This logical address is converted by an address translation table
27 into a physical memory address. A path 29 indicates the block
within the memory 11 into which the data is to be written. The
address translation table 27 simply converts a given logical
address from the computer system into a corresponding physical
address of a block within the memory 11 that is to receive that
data. As explained later, the translation table 27 is
reprogrammable by signals in a path 31 from a processing unit 33 to
redirect data blocks of given logical addresses into different
physical banks of the memory 11 in order to even out use of the
banks.
[0021] In preparation for the processing circuits 33 to decide
whether such redirection is required, information is first gathered
of memory characteristics and usage. A running record 35 tabulates
information from logical addresses of data blocks being directed to
the memory system from the computer system. Another running record
37 tabulates information of physical block usage within the memory
array 11 itself. The processing circuits 33 take this data from
either or both of the records 35 and 37 and determine whether any
data shifting among banks in the memory is required. Depending upon
specific applications, some of the information available from
monitoring the logical or physical addresses of data blocks being
programmed is used, and sometimes both. The purpose of the
conceptual diagram of FIG. 2 is to explain a wide range of options
for specific implementations of wear leveling. In this example, it
is assumed that the banks are the smallest units of memory which
may be swapped in response to utilization of this information.
[0022] Among the types of information that may beneficially be
acquired by the records 35 and 37 are the following:
[0023] (a) The total number of blocks of memory with which the
computer system is working at the moment. The number of logical
blocks recognized by the host computer operating system, noted in
the record 35, will obviously be no more than the number of
available physical blocks within interchangeable banks, noted in
the record 37, and will likely be fewer. The physical specification
obviously can be no higher than the number of physical blocks of
memory available for data storage, and generally will be less in
order to allow for some memory blocks becoming defective.
[0024] (b) For each of the available blocks, a record may be
maintained of the number of times that the block was written since
operation of the memory array 11 was first started. This number for
physical blocks maintained by the record 37 will be higher than the
logical number in record 35 because of overhead writes which the
memory controller 13 may cause to occur.
[0025] (c) A total number of block writing cycles that have been
initiated since the memory array 11 was first put into operation,
the logical number in record 35 and the physical number in record
37.
[0026] (d) The total number of cycles experienced by the
interchangeable banks, either by way of a total of all the blocks
of each bank, or by way of an average number per bank. Both a
logical record 35 and a physical record 37 of this may be
maintained.
[0027] (e) Related to (d) is to maintain an identification of the
banks having the minimum and the maximum number of cycles. The
minimum and maximum numbers can than be quickly ascertained.
[0028] This provides a great deal of information from which the
processing 33 can determine whether there is uneven wear among the
various banks of memory cells. The records 35 or 37 may be stored
in separate tables or, to the extent possible, maintained as part
of the blocks to which the data pertains in an overhead section or
the information stored in the block. Where an accumulation of
numbers must be made, it is preferable to keep running totals in
order to minimize the amount of processing that is necessary when
the wear leveling operation is performed. The processing 33 can use
this information in a number of different ways to detect when one
or more of the memory banks is being used considerably more
frequently than one or more of the other memory banks.
[0029] As an example of one alternative, the maximum usage of any
of the banks is first noted and a calculation made of the total
number of block writes which could have been accomplished if each
bank of the memory 11 was used to the exactly the same amount. This
is the ideal, perfect even wear of the memory that is a goal of the
wear leveling process. This is then compared with the total number
of erase and write cycles that have occurred in the memory, the
arithmetical difference being indicative of how far the system is
operating from that ideal. A high difference value indicates a
large imbalance in usage among the blocks. It may be calculated
either from data acquired from the logical address records 35 or
from the physical address records 37. In order to save memory, the
logical address records 35 may be omitted entirely if the system
speed is not unduly limited by the omission.
[0030] A wear leveling operation can be triggered by that
difference exceeding a certain magnitude. Alternatively, that
difference can be used in conjunction with other data before a wear
leveling event is initiated. That other data includes static
information of the ideal number of blocks that could be written
during the life of the memory system if the wear is perfectly
evenly distributed. A target for a total actual number of blocks to
be stored over the lifetime of the memory is then determined,
taking into account that perfectly even wear is not going to occur
under any circumstances. This static difference between the ideal
and target number of total block writes during the lifetime of the
system is then compared with the actual difference number described
above. When that calculated difference is about the same or less
than the static target difference, the memory is operating within
its target parameters and no action is taken. However, when the
calculated difference number exceeds the static target difference,
the memory is not operating up to expectations. If continued to
operate in that manner, one or more blocks of the memory will reach
their end of lifetime before the targeted number of user writes has
been reached. Therefore, when the calculated difference exceeds the
target difference by some amount, the wear leveling process 33 is
then initiated.
[0031] When wear leveling is accomplished, two main events occur.
First, as indicated by a path 39 of FIG. 2, data is transferred
between the most heavily used and least used banks. For example, if
bank 0 has a very large number of erase and rewrite cycles when
compared to that of bank 1, that data in each of these banks can be
swapped. The second thing that happens is that the address
translation table is updated to result in directing data blocks
formerly directed to bank 0 to bank 1, and vice versa. Logical
addresses from the computer system that previously caused its
associated data block to be written into a block having a physical
address within bank 0 will now cause the block to be written within
bank 1. Similarly, data blocks previously directed to bank 1 are
directed to bank 0.
[0032] As can be visualized from FIG. 2, the wear leveling
processing is accomplished in a feedback system. Adjustments are
made in the memory bank assignments in order to minimize a selected
one of the above described differences. Those differences are
calculated from data which results from those memory bank
assignments. The differences can be viewed as feedback control
variables. Adjustments in operation of the memory are made to
minimize the selected feedback variable.
[0033] Some limitation should be imposed on how often the wear
leveling process is allowed to take place. If done again before
there have been many operational cycles experienced by the memory,
the process will undesirably swap operation of the system back to
the previous condition of promoting maximum uneven wear. If the
process is allowed to be immediately performed a further time,
operation will swap back to the low wear level case, and so on.
Unnecessary use of the wear leveling process simply adds to wear of
the memory, and shortening its life, rather than extending it.
Therefore, some limitation is preferably imposed on how often the
wear leveling process is performed, such as by allowing it only
after many thousands of cycles have occurred since the last time.
This is, in effect, a limitation upon the feedback system loop
gain.
[0034] Another example of a way of determining when wear leveling
is necessary is to compare the number of block writes which have
occurred to the present time in each of the memory banks, either by
total number of block writes or some type of average of cycles of
blocks within the bank, by monitoring the physical memory usage
record 37. When those bank usage numbers are significantly
different from each other, uneven wear among the banks is apparent.
When these numbers become skewed in excess of a set threshold
amount, then the wear leveling processing 33 is initiated.
[0035] It is this latter technique that is used in a specific
implementation which will be described with respect to FIGS. 3-6.
FIG. 3 provides an outline of a specific system in which this wear
leveling technique is employed. The memory controller 13 includes
appropriate circuits 43 for interfacing with the computer system
bus 15, a controller microprocessor 45, volatile buffer memory 47
for temporarily storing data being written to or read from the
memory, and control logic circuitry 49. These circuit units are
interconnected and under the control of the microprocessor 45. The
control logic circuitry 49 includes the memory system address
translation table 27', corresponding to the table 27 described with
respect to FIG. 2. The EEPROM banks 111 are formed of a number of
individual integrated circuit chips, such as circuit chips 51 and
53, which are connected to the controller logic 49 over circuits
55. The number of EEPROM circuit chips employed depends upon the
storage capacity desired for the memory system. Further details of
the system illustrated in FIG. 3 can be had by reference to a
co-pending patent application entitled "Device and Method for
Controlling Solid-State Memory System", Ser. No. 07/736,733, filed
Jul. 26, 1991, naming Robert D. Norman, Karl M. J. Lofgren, Jeffrey
Donald Stai, Anil Gupta, and Sanjay Mehrotra as inventors, now U.S.
Pat. No. 5,430,859.
[0036] The EEPROM cells are arranged on each of the integrated
circuit chips 51, 53, etc., in four separate two-dimensional arrays
of rows and columns of such cells. Referring to the circuit chip
51, for example, a small area 57 contains interfacing circuits,
while four areas 59, 61, 63 and 65 provide separate arrays of rows
and columns of memory cells arranged as quadrants of the chip. In
this specific example, each of the quadrants 59, 61, 53 and 65 is
designated as a memory bank, the smallest unit of memory that is
swapped in order to improve wear leveling. A large number of such
banks are provided in a typical memory system that can employ from
a few to many EEPROM integrated circuit chips, with four such banks
per chip. Each bank is, in turn, subdivided into memory blocks,
such as the block 67 illustrated in the bank 61. Each bank can
contain from several to hundreds of such blocks, depending, of
course, on the density of the EEPROM cell formations on the chip,
its size, and similar factors. Alternatively, but usually not
preferred, each bank can have a single block.
[0037] The nature of each block is illustrated in FIG. 4. Each
block contains, in this example, four rows of memory cells. Most of
the cells in each row form a portion 69 devoted to storing a sector
of data. Such a data sector will typically conform to existing
computer standards, such as having a capacity of 512 bytes.
Accompanying each such data sector is header information, which is
stored in another portion of each of the four rows of the block.
Each such block is the smallest unit of the memory system which can
be separately erased. That is, all of the erase gates of each
memory block are connected together for simultaneous erasure when
appropriately addressed. Although multiple blocks may be erased at
one time, portions of memory smaller than a block size are not
separately erasable.
[0038] A field 73 is included in the header 71 to maintain a count
of the number of times that the block has been erased and
rewritten. As part of an erasure and rewrite cycle, this count is
updated by one. When data is swapped among memory banks in order to
accomplish wear leveling, it is the data stored in the portion 69
of each block of a bank that is swapped. The header 71, including
the cycle count field 73, remains with its physical block. The
cycle count 73 starts with one the first time its respective block
of a new memory is erased and written, and is incremented by one
upon the occurrence of each subsequent cycle during the lifetime of
the memory. It is the count field 73 of each block that is read and
processed periodically throughout the lifetime of the memory in
order to determine whether there is uneven wear among the various
memory banks and, if so, how a leveling of that uneven use can be
accomplished.
[0039] A process flow diagram of FIG. 5 provides an example of wear
leveling control of the memory system described above with respect
to FIGS. 3 and 4. In this example, the process can be begun either
automatically upon each initialization of the computer system, as
indicated by a step 75, or upon the memory controller 13 receiving
a command from the host computer system microprocessor 17, as
indicated by a step 77. Whether the process is begun automatically
upon system initialization at step 75 depends upon how the memory
controller is set by a hard wire connection. A process path 79
indicates the controller being set to commence a review of the wear
leveling each time the system is initialized, such as each time
power is turned on to the system. In either event, the process is
controllable by the host computer system, generally as part of an
operating software system that periodically causes the wear
leveling review to begin.
[0040] Once begun, as indicated by a step 81, the cycle count field
73 of each data storage block in the system is read. An average
block cycle count for each bank is then calculated from these
numbers. The average cycle counts for each bank, as indicated by a
step 83, are then compared to determine whether there is such an
imbalance of use of the various banks that a wear leveling
operation should take place.
[0041] Even though the steps 75 and 77 provide a limitation and
control on how often this process is accomplished, a step 85 shows
a further limitation, which references the average bank usage count
numbers. As will be explained more fully below, the system includes
a spare bank of memory which is used in the wear leveling process.
During each implementation of the process, the bank having the
highest average block usage count is designated as the current
spare bank. Thus, in order to prevent banks from being
unnecessarily swapped back and forth, the count of the current
spare bank, which has not been used for data storage purposes since
the last wear leveling operation, provides a benchmark. Only if the
usage of some other bank exceeds the previous record use carried by
the current spare bank, then the process continues.
[0042] A next step 87, in that case, compares the maximum and
minimum bank usage numbers to determine whether they differ by more
than some present number A. If not, the wear leveling process
reverts back to the step 77 wherein it awaits another command from
the host computer system. If the difference does exceed A, however,
then a swapping of banks of memory is accomplished in subsequent
steps in order to even out the bank usage during future cycles. An
example of the difference number A is 15,000 erase and write
cycles. That number can vary considerably, however, depending upon
the desired memory system operation. If the number is made too
small, wear leveling cycles will occur too frequently, thus adding
to the wear of the system since some overhead erase and rewrite
cycles are required each time the wear leveling process in
accomplished. If the number A is too large, on the other hand, the
lifetime of the memory system is likely to be cut short by one or
more banks reaching its lifetime limit of erase and rewrite cycles
long prior to other banks approaching such a limit.
[0043] Before proceeding with other steps of the process of FIG. 5,
an example of the translation table 27' and its use is indicated in
FIG. 6A. This state of the translation table 27' assumes a
simplistic correspondence between logical and physical memory
addresses. Data blocks having logical addresses within bank 0 are
mapped by the translation table 27' into physical bank 0, those of
logical bank 1 to physical bank 1, and so forth.
[0044] As a first step 89 of a leveling procedure, data stored in
the bank with the minimum count is written into the current spare
memory bank. This is illustrated in FIG. 6B. Assuming the average
block counts for each of the banks are set forth for purposes of
explanation in FIG. 6A, bank 0 at this point in time has the
highest average count, and bank (n-1) has the lowest. Bank n is the
current spare bank. Therefore, in step 89 of FIG. 5, data is moved
from bank (n-1) to bank n, as indicated at 91. Next, as indicated
by a step 93 of FIG. 5, the minimum count bank (n-1) is erased. In
a next step 93, the data of the maximum bank 0 is written into the
former minimum usage bank (n-1), as indicated at 97 of FIG. 6B. A
next step 99 then erases the maximum used bank 0 and it is
designated as a new spare bank.
[0045] Finally, as indicated by a step 101, the translation table
27' is updated so that blocks of data within the swapped banks are
redirected to those new physical bank locations. FIG. 6C shows an
example of that, where the translation table 27' is changed from
what it was in FIG. 6A to level out the wear of the various banks
during future erase and rewrite cycles. Accordingly, the most
heavily used bank having a logical address 0 is remapped into the
bank (n-1), the same bank into which the physical bank 0 data
blocks were written earlier in the process. Similarly, the least
used logical bank n address is remapped into physical bank n, the
previous spare bank in the state shown in FIG. 6A. The most heavily
used bank 0, as shown in FIG. 6C, has no logical banks mapped into
it. Bank 0 is now the new current spare bank. It has the maximum
use of any bank to-date. It will now rest and the wear leveling
process will not be accomplished again until the usage of some
other bank exceeds that of bank 0, as determined in step 85 of FIG.
5.
[0046] Alternatively, a spare bank of EEPROM memory need not be
designated for the wear leveling process, thus freeing up another
bank for storing data. Data can simply be swapped between the banks
experiencing the maximum and minimum cycles to-date, and the
translation table 27' then being updated to redirect data
accordingly. The controller buffer memory 47 can be used for
temporary storage of data from the maximum and minimum use banks as
data is being swapped between them. The count of the most heavily
used bank is then remembered and used in the comparison step 35
when determining whether the imbalance is sufficient to justify the
wear leveling process being performed. However, since the buffer
memory 47 is usually preferred to be RAM, any power failure or
significant power glitches occurring during the wear leveling
process will cause data to be lost. The use of the spare bank in
the manner described above will prevent such a data loss since the
data of each block being swapped will remain in EEPROM memory at
all times.
[0047] Although the various aspects of the present invention have
been described to its preferred embodiments, it will be understood
that the invention is entitled to protection within the full scope
of the appended claims.
* * * * *