U.S. patent application number 11/646064 was filed with the patent office on 2008-07-03 for temperature calculation based on non-uniform leakage power.
Invention is credited to Dhananjay Adhikari, Zhong-Ning George Cai, Jacob Schneider.
Application Number | 20080159352 11/646064 |
Document ID | / |
Family ID | 39583931 |
Filed Date | 2008-07-03 |
United States Patent
Application |
20080159352 |
Kind Code |
A1 |
Adhikari; Dhananjay ; et
al. |
July 3, 2008 |
Temperature calculation based on non-uniform leakage power
Abstract
A system may include determination of a spatial power map
associated with an integrated circuit based on an architecture of
the circuit, generation of a spatial thermal map associated with
the integrated circuit based on the spatial power map, and
determination of a spatial leakage power map based on the spatial
thermal map. In some aspects, a system includes determination of a
temperature of an integrated circuit, comparison of the temperature
with a thermal divergence temperature, determination that the
temperature of the integrated circuit is primarily due to leakage
power, and disabling of power to the integrated circuit.
Inventors: |
Adhikari; Dhananjay;
(Austin, TX) ; Cai; Zhong-Ning George; (Lake
Oswego, OR) ; Schneider; Jacob; (Austin, TX) |
Correspondence
Address: |
BUCKLEY, MASCHOFF & TALWALKAR LLC
50 LOCUST AVENUE
NEW CANAAN
CT
06840
US
|
Family ID: |
39583931 |
Appl. No.: |
11/646064 |
Filed: |
December 27, 2006 |
Current U.S.
Class: |
374/4 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 23/34 20130101; H01L 2924/0002 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
374/4 |
International
Class: |
G01N 25/72 20060101
G01N025/72 |
Claims
1. A method comprising: determining a spatial power map associated
with an integrated circuit based on an architecture of the circuit;
generating a spatial thermal map associated with the integrated
circuit based on the spatial power map; and determining a spatial
leakage power map based on the spatial thermal map.
2. A method according to claim 1, wherein determining the spatial
leakage power map comprises: modeling spatial leakage power based
on a fabrication process of the integrated circuit.
3. A method according to claim 1, further comprising: determining a
second spatial power map associated with the integrated circuit
based on the spatial leakage power map; generating a second spatial
thermal map associated with the integrated circuit based on the
second spatial power map; and determining a second spatial leakage
power map based on the second spatial thermal map.
4. A method according to claim 3, further comprising: determining
whether the second spatial thermal map is substantially similar to
the spatial thermal map.
5. A method according to claim 1, further comprising: determining a
leakage power shutdown temperature based on the spatial leakage
power map.
6. A method comprising: determining a temperature of an integrated
circuit; comparing the temperature with a thermal divergence
temperature; determining that the temperature of the integrated
circuit is primarily due to leakage power; and disabling power to
the integrated circuit.
7. A method according to claim 6, wherein determining that the
temperature of the integrated circuit is primarily due to leakage
power comprises: determining that the integrated circuit is
inactive.
8. A method according to claim 6, wherein comparing the temperature
with the thermal divergence temperature comprises: determining that
the temperature is proximate to the thermal divergence temperature
of the integrated circuit, and further comprising: after
determining that the temperature of the integrated circuit is
primarily due to leakage power, measuring a second temperature of
the integrated circuit; and determining that the second temperature
is greater than the thermal divergence temperature of the
integrated circuit.
9. A method according to claim 6, further comprising: determining
the thermal divergence temperature of the integrated circuit based
on a plurality of stored temperatures.
10. An apparatus comprising: an integrated circuit; a temperature
sensor to measure a temperature of the integrated circuit; and a
comparator to compare the temperature with a thermal divergence
temperature; wherein the integrated circuit is to determine that
the temperature of the integrated circuit is primarily due to
leakage power, and disable power to the integrated circuit.
11. An apparatus according to claim 10, wherein the determination
that the temperature of the integrated circuit is primarily due to
leakage power comprises: a determination that the integrated
circuit is inactive.
12. An apparatus according to claim 10, wherein the comparator is
to determine that the temperature is proximate to the thermal
divergence temperature of the integrated circuit, wherein
temperature sensor is to measure a second temperature of the
integrated circuit after it is determined that the temperature of
the integrated circuit is primarily due to leakage power, and
wherein the integrated circuit is further to determine that the
second temperature is greater than the thermal divergence
temperature of the integrated circuit.
13. An apparatus according to claim 10, further comprising: a
memory comprising a plurality of stored temperatures including the
thermal divergence temperature.
14. A system comprising: a double data rate memory; an integrated
circuit; a temperature sensor to measure a temperature of the
integrated circuit; and a comparator to compare the temperature
with a thermal divergence temperature; wherein the integrated
circuit is to determine that the temperature of the integrated
circuit is primarily due to leakage power, and disable power to the
integrated circuit.
15. A system according to claim 14, wherein the determination that
the temperature of the integrated circuit is primarily due to
leakage power comprises: a determination that the integrated
circuit is inactive.
16. A system according to claim 14, wherein the comparator is to
determine that the temperature is proximate to the thermal
divergence temperature of the integrated circuit, wherein
temperature sensor is to measure a second temperature of the
integrated circuit after it is determined that the temperature of
the integrated circuit is primarily due to leakage power, and
wherein the integrated circuit is further to determine that the
second temperature is greater than the thermal divergence
temperature of the integrated circuit.
Description
BACKGROUND
[0001] Power dissipation directly affects the performance and
reliability of modern integrated circuits. A microprocessor
designer, for example, may model this power dissipation with
respect to a high level micro-architecture, a register transfer
level, and an actual implementation of the microprocessor.
According to conventional methods for modeling power dissipation,
source-to-drain leakage power is characterized as a constant
depending only on a process corner of the subject integrated
circuit. These methods typically neglect any dependence of leakage
power on temperature as insignificant.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] FIG. 1 is a block diagram illustrating an apparatus
according to some embodiments.
[0003] FIG. 2 is a flow diagram of a process according to some
embodiments.
[0004] FIG. 3 illustrates a thermal divergence temperature
determined according to some embodiments.
[0005] FIG. 4 is a flow diagram of a process according to some
embodiments.
DETAILED DESCRIPTION
[0006] FIG. 1 is a block diagram of integrated circuit 100
according to some embodiments. Integrated circuit 100 may comprise
any type of semiconductor-based device having electrical devices
integrated therein. Integrated circuit 100 may be fabricated
according to any number of fabrication techniques that are or
become known. In some embodiments, integrated circuit 100 comprises
a silicon-based general-purpose microprocessor.
[0007] Integrated circuit 110 comprises core 110, temperature
sensor 120, lookup table 130, power regulation circuit 140 and
comparator 150. The positions and relative sizes of functional
blocks 110 through 150 do not necessarily reflect any particular
implementation. According to some embodiments, one or more of
functional blocks 110 through 150 may share active or passive
electrical elements amongst each other.
[0008] Core 110 may comprise an execution engine to execute
processor-executable program code. Such execution may illicit
desired behavior from circuit 100, which may include internal state
changes as well the driving of desired signals to external pins
(not shown) of circuit 100. Circuit 100 may store program code
"on-chip" for low-level operations such as one or more processes
described herein.
[0009] Memory 160 may be in communication with one or more external
pins and may provide processor-executable program code to
integrated circuit 100 according to some embodiments. Memory 160
may comprise any type of memory for storing data, including but not
limited to a Single Data Rate Random Access Memory (SDR-RAM), a
Double Data Rate Random Access Memory (DDR-RAM), or a Programmable
Read Only Memory (PROM).
[0010] FIG. 2 is a diagram of process 200 according to some
embodiments. Process 200 may be executed by any combination of
hardware, software and/or firmware, and some elements may be
executed manually. Process 200 may be executed during testing
and/or other quality assurance activities after manufacture of an
integrated circuit.
[0011] Initially, at 210, a spatial power map associated with an
integrated circuit is determined. The spatial power map is based on
an architecture of the circuit. Determination of the spatial power
map at 210 may proceed according to any suitable system that is or
becomes known. For example, some conventional systems receive an
electronic "floorplan" of the integrated circuit, statistical
historic studies of prior integrated circuits, and process data,
and generate a three-dimensional map illustrating power consumption
at various locations throughout the integrated circuit. The map
typically reflects active power, gate power, and source-to-drain
leakage power.
[0012] Next, at 220, a spatial thermal map associated with an
integrated circuit is generated based on the spatial power map
generated at 210. The spatial thermal map may indicate average
operational temperatures at various points of the integrated
circuit. Again, current or future conventional methods for
generating such a thermal map may be employed at 220.
[0013] A spatial leakage power map is determined at 230 based on
the spatial thermal map generated at 220. According to some
embodiments, the spatial leakage power map reflects source-to-drain
leakage power at various locations of the integrated circuit. The
leakage power may be modeled as follows:
P.sub.sdleak2=P.sub.sdleak1e.sup.(.beta.(T2-T1),
[0014] where .beta. is obtained from process data simulations. The
following table illustrates values of .beta. generated by SPICE
measurements using a minimum square fit method, with V.sub.dd=1.1V,
T=25 to 150 degrees C., and a PTTTT skew on conventional
microprocessor fabrication process.
TABLE-US-00001 TTTT FFFF LV.sub.T NMOS 1.48E-02 9.35E-02 HV.sub.T
NMOS 1.94E-02 1.68E-02 LV.sub.T PMOS 1.76E-02 1.06E-02 HV.sub.T
PMOS 2.01E-02 1.74E-02
[0015] As shown, .beta. may vary depending on process corner.
Accordingly, several spatial leakage power maps corresponding to
respective process corners may be generated at 230.
[0016] At 240, it is determined whether the spatial leakage power
map is substantially convergent. Convergence in this context may
indicate that a difference between the most-recently determined
spatial thermal map and a previously-determined thermal map is less
than a predetermined threshold. Some embodiments therefore require
flow to return to 220 and continue as described above to generate a
second spatial thermal map for comparison against a first spatial
thermal map at 240. Flow continues to cycle between 220, 230 and
240 until the most-recently determined spatial thermal map is
determined to be substantially convergent.
[0017] One or more leakage power shutdown temperatures are
determined at 250 based on the spatial leakage power map. The
determination at 250 may be based on the direct proportionality of
temperature to total power, written as T.sub.j=T.sub.a+.THETA.
(Source-Drain Leakage Power+Gate Leakage Power+Active Power).
Assuming that Y.sub.1=T.sub.j and Y.sub.2=T.sub.a+.THETA., the
function Y=Y.sub.1-Y.sub.2 may be defined. The function Y has one
minimum and no maximums. Moreover, if the minimum is less than 0,
either one solution (i.e., a converging case) or two solutions
(i.e., a diverging case) exists.
[0018] FIG. 3 is a graph illustrating a plot of Y according to some
embodiments. The plot is associated with a particular process
corner based on which the associated spatial leakage power map was
determined at 230. Also shown is solution A of the function Y,
which may represent a leakage power shutdown temperature according
to some embodiments. The leakage power shutdown temperature may be
a temperature at which, for the given process corner, temperature
and leakage power become self-reinforcing and cause a runaway
condition.
[0019] FIG. 4 is a flow diagram of process 400 according to some
embodiments. Process 400 may be executed by any combination of
hardware, software and/or firmware. Process 400 may be executed by
circuit 100 according to some embodiments.
[0020] A temperature of an integrated circuit is determined at 410.
The temperature may be determined by an on-chip temperature sensor
such as temperature sensor 120, which may comprise a digital
thermometer or any other type of sensor that is or becomes known.
The sensor may measure the temperature at a particular location of
the integrated circuit at which temperature and leakage power are
of concern.
[0021] At 420, it is determined whether the temperature is
proximate to a thermal divergence temperature. As described above
with respect to the leakage power shutdown temperature, the thermal
divergence temperature may be a temperature at which the continued
application of supply power may cause a runaway temperature
condition. Accordingly, the thermal divergence temperature may be
determined for a particular location of the integrated circuit as
described above with respect to the leakage power shutdown
temperature.
[0022] The thermal divergence temperature may be stored on-chip
(e.g., in lookup table 130) after manufacture of the integrated
circuit. In some embodiments, several thermal divergence
temperatures are stored on-chip and one of the stored temperatures
is flagged to indicate its applicability to the particular
integrated circuit. Such an arrangement may allow a manufacturer to
customize process 400 in view of a process corner or intended use
of the integrated circuit.
[0023] Comparator 130 may compare the determined temperature to the
thermal divergence temperature at 420. Comparator 130 may indicate
TRUE if the measured temperature is less than but sufficiently
proximate to the thermal divergence temperature. Comparator 130 may
be an element of core 110. Flow returns to 410 if the determined
temperature is not proximate to the thermal divergence
temperature.
[0024] Flow proceeds to 430 if the determination at 420 is
affirmative. At 430, it is determined if the integrated circuit is
active. The determination at 430 may be intended to determine if
the measured temperature is primarily due to active power or
leakage power. The determination may be based on communication with
the operating system, internal performance counters of the
integrated circuit, etc. If the integrated circuit is active, flow
continues to 440 to hand control to other temperature control
processes. Such control may comprise reducing operational
frequency, supply power, workload, etc.
[0025] If it is determined that the integrated circuit is not
active, a temperature of the integrated circuit is again determined
at 450, and this temperature is compared against the thermal
divergence point at 460. If the measured temperature is less than
the thermal divergence point, flow returns to 420 to determine
whether to determine whether the temperature of the integrated
circuit is still proximate to the thermal divergence temperature
and flow continues as described above.
[0026] If the measured temperature is greater than the thermal
divergence point at 460, power to the integrated circuit is
disabled at 470. Disabling the power is intended to prevent a
runaway temperature condition. The power may be disabled by
operating power regulation circuit 140 to reduce or eliminate power
supplied to all or a portion of integrated circuit 100. The power
may be disabled at 470 by instructing an off-chip voltage regulator
(not shown) to stop power delivery to integrated circuit 100.
[0027] The several embodiments described herein are solely for the
purpose of illustration. Therefore, persons in the art will
recognize from this description that other embodiments may be
practiced with various modifications and alterations.
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