U.S. patent application number 11/755390 was filed with the patent office on 2008-07-03 for multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same.
Invention is credited to Dong Ha JUNG, Baek Mann KIM, Jeong Tae KIM, Soo Hyun KIM, Young Jin LEE.
Application Number | 20080157367 11/755390 |
Document ID | / |
Family ID | 39582746 |
Filed Date | 2008-07-03 |
United States Patent
Application |
20080157367 |
Kind Code |
A1 |
KIM; Soo Hyun ; et
al. |
July 3, 2008 |
MULTI-LAYER METAL WIRING OF SEMICONDUCTOR DEVICE PREVENTING MUTUAL
METAL DIFFUSION BETWEEN METAL WIRINGS AND METHOD FOR FORMING THE
SAME
Abstract
A multi-layer metal wiring of a semiconductor device and a
method for forming the same are disclosed. The multi-layer metal
wiring of the semiconductor device includes a lower Cu wiring, and
an upper Al wiring formed to be contacted with the lower Cu wiring,
and a diffusion barrier layer interposed between the lower Cu
wiring and the upper Al wiring. The diffusion barrier layer is
formed of a W-based layer.
Inventors: |
KIM; Soo Hyun; (Seoul,
KR) ; KIM; Baek Mann; (Kyoungki-do, KR) ; LEE;
Young Jin; (Kyoungki-do, KR) ; JUNG; Dong Ha;
(Kyoungki-do, KR) ; KIM; Jeong Tae; (Kyoungki-do,
KR) |
Correspondence
Address: |
LADAS & PARRY LLP
224 SOUTH MICHIGAN AVENUE, SUITE 1600
CHICAGO
IL
60604
US
|
Family ID: |
39582746 |
Appl. No.: |
11/755390 |
Filed: |
May 30, 2007 |
Current U.S.
Class: |
257/751 ;
257/E21.17; 257/E21.171; 257/E21.495; 257/E23.141; 257/E23.16;
438/627 |
Current CPC
Class: |
H01L 21/76846 20130101;
H01L 21/76856 20130101; H01L 23/53223 20130101; H01L 21/28562
20130101; H01L 21/76843 20130101; H01L 21/28556 20130101; H01L
2924/0002 20130101; H01L 2924/0002 20130101; H01L 23/53238
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/751 ;
438/627; 257/E21.495; 257/E23.141 |
International
Class: |
H01L 23/52 20060101
H01L023/52; H01L 21/4763 20060101 H01L021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 28, 2006 |
KR |
10-2006-0137204 |
Claims
1. A multi-layer metal wiring of a semiconductor device comprising:
a lower Cu wiring; an upper Al wiring formed over the lower Cu
wiring and electrically contacting the lower Cu wiring; and a
W-based diffusion barrier layer formed between the lower Cu wiring
and the upper Al wiring.
2. The multi-layer metal wiring of the semiconductor according to
claim 1, wherein the W-based diffusion barrier layer comprises a WN
layer.
3. The multi-layer metal wiring of the semiconductor according to
claim 2, wherein the WN layer has a thickness of 50 to 200
.ANG..
4. The multi-layer metal wiring of the semiconductor according to
claim 1, wherein the W-based diffusion barrier layer comprises a
stacked layer of a W layer and a WN layer.
5. The multi-layer metal wiring of the semiconductor according to
claim 4, wherein the stacked layer of the W layer and the WN layer
has a thickness of 50 to 300 .ANG..
6. The multi-layer metal wiring of the semiconductor according to
claim 1, wherein the W-based diffusion barrier layer comprises a
WSiNy layer.
7. The multi-layer metal wiring of the semiconductor according to
claim 6, wherein the WSiNy layer has a thickness of 50 to 200
.ANG..
8. The multi-layer metal wiring of the semiconductor according to
claim 1, wherein the W-based diffusion barrier layer comprises a
stacked layer of a WSix layer and a WSixNy layer.
9. The multi-layer metal wiring of the semiconductor according to
claim 8, wherein the stacked layer of the WSix layer and the WSixNy
layer has a thickness of 50 to 300 .ANG..
10. The multi-layer metal wiring of the semiconductor according to
claim 1, wherein the upper Al wiring comprises an Al nucleation
growth layer formed on the diffusion barrier layer.
11. The multi-layer metal wiring of the semiconductor according to
claim 10, wherein the Al nucleation growth layer has a thickness of
50 to 500 .ANG..
12. A method for forming a multi-layer metal wiring of a
semiconductor device including: forming a lower Cu wiring over a
semiconductor substrate; forming a w-based diffusion barrier layer
on the lower Cu wiring; and forming an upper Al wiring over the
lower Cu wiring including the W-based diffusion barrier layer.
13. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12, wherein the W-based
diffusion barrier layer comprises a WN layer.
14. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 13, wherein the WN layer
has a thickness of 50 to 200 .ANG..
15. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 13, wherein the WN layer is
formed in an ALD or CVD method.
16. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 13, wherein the WN layer is
formed under a temperature in the range of 200 to 400.degree. C.
and a pressure in the range of 1 to 40 Torr.
17. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12, wherein the W-based
diffusion barrier layer comprises a stacked layer of a W layer and
a WN layer.
18. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 17, wherein the stacked
layer of the W layer and the WN layer has a thickness of 50 to 300
.ANG..
19. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 17, wherein the stacked
layer of the W layer and the WN layer is formed by depositing the W
layer and nitrifying the surface of the W layer.
20. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 17, wherein the W layer is
deposited in an ALD or CVD method.
21. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 17, wherein the W layer is
deposited under a temperature in the range of 200 to 400.degree. C.
and a pressure in the range of 1 to 40 Torr.
22. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 19, wherein the
nitrification on the surface of the W layer is performed by a heat
treatment or a plasma treatment under the atmosphere of any one of
NH.sub.3, N.sub.2H.sub.4, N.sub.2, and N.sub.2/H.sub.2.
23. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12, wherein the W-based
layer is formed of a WSiNy layer.
24. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 23, wherein the WSiNy layer
has a thickness of 50 to 200 .ANG..
25. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 23, wherein the WSiNy layer
is formed in an ALD or CVD method.
26. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 23, wherein the WSiNy layer
is formed under a temperature in the range of 300 to 500.degree. C.
and a pressure in the range of 0.01 to 10 Torr.
27. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12, wherein the W-based
diffusion barrier layer comprises a stacked layer of a WSix layer
and a WSiNy layer.
28. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 27, wherein the stacked
layer of the WSix layer and the WSiNy layer has a thickness of 50
to 300 .ANG..
29. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 27, wherein the stacked
layer of the WSix layer and the WSiNy layer is formed by depositing
the WSix layer and nitrifying the surface of the WSix layer.
30. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 27, wherein the WSix layer
is deposited in an ALD or CVD method.
31. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 29, wherein the WSix layer
is deposited under a temperature in the range of 300 to 500.degree.
C. and a pressure in the range of 0.01 to 10 Torr.
32. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 29, wherein the
nitrification on the surface of the WSix layer is performed by a
heat treatment or a plasma treatment under the atmosphere of any
one of NH.sub.3, N.sub.2H.sub.4, N.sub.2, and N.sub.2/H.sub.2.
33. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12 further comprising
forming a Al nucleation growth layer on the diffusion barrier layer
prior to forming the upper Al wiring.
34. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 33, wherein the Al
nucleation growth layer has a thickness of 50 to 500 .ANG. based on
a CVD method.
35. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12 comprising: the method
for forming the upper Al wiring includes the steps of depositing
the Al layer over the diffusion barrier layer based on a PVD method
at a temperature in the range of 200 to 400.degree. C.; and
performing a heat treatment on the Al layer at a temperature in the
range of 400 to 500.degree. C.
36. The method for forming the multi-layer metal wiring of the
semiconductor device according to claim 12 further comprising:
depositing a first Al layer over the diffusion barrier layer in a
PVD method at a temperature in the range of 150 to 200.degree. C.;
and depositing a second Al layer over the first Al layer in a PVD
method at a temperature in the range of 200 to 450.degree. C.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to Korean patent
application number 10-2006-0137204 filed on Dec. 28, 2006, which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a method for forming a
multi-layer metal wiring of a semiconductor device, and more
particularly to a multi-layer metal wiring of a semiconductor
device including a diffusion barrier layer for preventing mutual
metal diffusion between upper and lower metal wirings mutually
contacted and a method for forming the same.
[0003] For highly integrated semiconductor devices, high speed
device components are required such that the memory cells are
formed in a stack structure. Further, the metal wirings carrying
electrical signals to each cell are also formed in a multi-layer
structure. The metal wiring laid out in a multi-layer structure
provides advantageous design flexibility and allows more leeway in
setting the margins for the metal wiring resistance, the current
capacity, etc.
[0004] Generally, aluminum (Al) has been the choice of metal wiring
for its superior electric conductivity and the ease of being
applied in a fabrication process. However, copper (Cu) is preferred
over Al in products operating in faster speeds and requiring lower
operational voltages due to high integration of semiconductor
devices, because Cu has relatively lower resistance than Al.
[0005] However, it is not preferable to apply only Cu as the
material for all metal wirings formed in a multi-layer structure
due to increased manufacturing expenses and certain unsuitable
characteristics that could be present in the highly integrated
device components. Along these lines, Cu were used as the metal
wiring material in a multi-layer structure when high speed is
important, and Al were used when the speed is relatively less
important.
[0006] Meanwhile, when Cu is used as the lower metal wiring and Al
is used as the upper metal wiring in a multi-layer metal wiring
structure, a diffusion barrier layer between the lower and upper
metal wirings is necessary to prevent metal diffusion between the
metal wirings.
[0007] Generally, in a multi-layer metal wiring structure having a
lower wiring of Cu and an upper wiring of Al, a Ti layer and/or a
TiN layer (i.e., either individually or as a stacked layer) were
used as the diffusion barrier layer between the lower and upper
metal wirings. However, the diffusion barrier layer made of stacked
Ti and TiN layers cannot secure the thickness needed to
sufficiently suppress the metal diffusion between the metal
wirings.
[0008] It is not impossible to increase the thickness of the Ti
and/or TiN layers to suppress the metal diffusion between the lower
Cu wiring and the upper Al wiring; however, this only leads to
reduction of the sectional area of the Al upper wiring, which is
formed in a damascene pattern, and thereby causes the undesirable
increase of the metal wiring resistance.
[0009] Also, when the thickness of the stacked Ti and TiN layers is
increased, filling Al in a via hole in the damascene pattern to
form a upper metal wiring would become more difficult such that
voids may be generated in the via hole leading to the significantly
increased metal wiring resistance.
[0010] Therefore, increasing the thickness of the stacked Ti and
TiN layers for purposes of suppressing the metal diffusion between
the lower Cu wiring and the upper Al wiring is impractical for
use.
BRIEF SUMMARY OF THE INVENTION
[0011] Embodiments of the present invention provide a multi-layer
metal wiring of a semiconductor device preventing the mutual metal
diffusion between an upper and a lower metal wirings mutually
contacted, and a method forming the same.
[0012] In one embodiment, a multi-layer metal wiring of a
semiconductor device includes; a lower Cu wiring; an upper Al
wiring formed to be contacted with the lower Cu wiring; and a
diffusion barrier layer interposed between the lower Cu wiring and
the upper Al wiring and formed of a W-based layer.
[0013] The W-based layer is formed of a WN layer.
[0014] The WN layer has a thickness of 50 to 200 .ANG..
[0015] The W-based layer is formed of a stacked layer of a W layer
and a WN layer.
[0016] The stacked layer of the W layer and the WN layer has a
thickness of 50 to 300 .ANG..
[0017] The W-based layer is formed of a WSiNy layer.
[0018] The WSiNy layer has a thickness of 50 to 200 .ANG..
[0019] The W-based layer is formed of a stacked layer of a WSix
layer and a WSixNy layer.
[0020] The stacked layer of the WSix layer and the WSixNy layer has
a thickness of 50 to 300 .ANG..
[0021] In the multi-layer metal wiring of the semiconductor device,
the upper Al wiring includes an Al nucleation growth layer formed
on the diffusion barrier layer.
[0022] The Al nucleation growth layer has a thickness of 50 to 500
.ANG..
[0023] In the other embodiment, a method for forming a multi-layer
metal wiring of a semiconductor device include: forming a lower Cu
wiring over the upper of the semiconductor substrate on which an
underlayer is formed; and forming an upper Al wiring by interposing
a diffusion barrier layer over the lower Cu metal wiring, wherein
the diffusion barrier layer is formed of a W-based layer.
[0024] The W-based layer is formed of a WN layer.
[0025] The WN layer has a thickness of 50 to 200 .ANG..
[0026] The WN layer is formed in an ALD method or a CVD method.
[0027] The WN layer is formed under the conditions of the
temperature of 200 to 400.degree. C. and the pressure of 1 to 40
Torr.
[0028] The W-based layer is formed of a stacked layer of a W layer
and a WN layer.
[0029] The stacked layer of the W layer and the WN layer has a
thickness of 50 to 300 .ANG..
[0030] The formation of the stacked layer of the W layer and the WN
layer includes the steps of depositing the W layer and nitrifying
the surface of the W layer.
[0031] The W layer is deposited based on a ALD method or a CVD
method.
[0032] The W layer is deposited under the conditions of the
temperature of 200 to 400.degree. C. and the pressure of 1 to 40
Torr.
[0033] The nitrification on the surface of the W layer is performed
by a heat treatment or a plasma treatment under the atmosphere of
any one of NH.sub.3, N.sub.2H.sub.4, N.sub.2, and
N.sub.2/H.sub.2.
[0034] The W-based layer is formed of a WSiNy layer.
[0035] The WSiNy layer has a thickness of 50 to 200 .ANG..
[0036] The WSiNy layer is formed based on an ALD method or a CVD
method.
[0037] The WSiNy layer is formed under the conditions of the
temperature of 300 to 500.degree. C. and the pressure of 0.01 to 10
Torr.
[0038] The W-based layer is formed of a stacked layer of a WSix
layer and a WSiNy layer.
[0039] The stacked layer of the WSix layer and the WSiNy layer has
a thickness of 50 to 300 .ANG..
[0040] The formation of the stacked layer of the WSix layer and the
WSiNy layer includes the steps of depositing the WSix layer and
nitrifying the surface of the WSix layer.
[0041] The WSix layer is deposited in a ALD method or a CVD
method.
[0042] The WSix layer is deposited under the conditions of the
temperature of 300 to 500.degree. C. and the pressure of 0.01 to 10
Torr.
[0043] The nitrification on the surface of the WSix layer is
performed by a heat treatment or a plasma treatment under the
atmosphere of any one of NH.sub.3, N.sub.2H.sub.4, N.sub.2, and
N.sub.2/H.sub.2.
[0044] The method for forming the multi-layer metal wiring of the
semiconductor device includes forming a Al nucleation growth layer
on the diffusion barrier layer prior to forming the upper Al
wiring.
[0045] The Al nucleation growth layer has a thickness of 50 to 500
.ANG. based on a CVD method.
[0046] The method for forming the upper Al wiring includes the
steps of depositing the Al layer over the diffusion barrier layer
based on a PVD method at the temperature of 200 to 400.degree. C.,
and performing a heat treatment on the Al layer at the temperature
of 400 to 500.degree. C.
[0047] The method for forming the upper Al wiring includes the
steps of depositing a first Al layer over the diffusion barrier
layer based on a PVD method at the temperature of 150 to
200.degree. C., and depositing a second Al layer over the first Al
layer based on a PVD method at the temperature of 200 to
450.degree. C.
BRIEF DESCRIPTION OF THE DRAWINGS
[0048] FIGS. 1A through 1E are cross-sectional views for explaining
a method for forming a multi-layer metal wiring of a semiconductor
device in accordance with an embodiment of the present
invention.
[0049] FIG. 2 is a cross-sectional view for explaining a method for
forming a WN layer as a diffusion barrier layer in accordance with
a first embodiment of the present invention.
[0050] FIG. 3 is a cross-sectional view for explaining a method for
forming a stacked layer of a W layer and a WN layer as a diffusion
barrier layer in accordance with a second embodiment of the present
invention.
[0051] FIG. 4 is a cross-sectional view for explaining a method for
forming a WSix layer as a diffusion barrier layer in accordance
with a third embodiment of the present invention.
[0052] FIG. 5 is a cross-sectional view for explaining a method for
forming a stacked layer of a WSix layer and a WSixNy layer as a
diffusion barrier layer in accordance with a fourth embodiment of
the present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0053] The present invention forms a diffusion barrier layer of a
W-based layer. The W-based diffusion barrier layer is inserted in
the contact interface between a lower Cu wiring and an upper Al
wiring. Preferably, the W-based layer is formed of a WN layer, a
stacked layer of a W layer and the WN layer, a WSiNy layer, or a
stacked layer of the WSix layer and a WSiNy layer.
[0054] The W-based layer has very excellent diffusion barrier
characteristics as compared to a Ti layer and TiN layer, which are
conventional diffusion barrier layers. The W-based diffusion
barrier layer has excellent capability to suppress the metal
diffusion between the lower Cu wiring and the upper Al wiring.
Therefore, when forming a multi-layer metal wiring to which the
lower Cu wiring and the upper Al wiring is formed in an ultra high
integration device, the present invention provides an excellent
diffusion barrier layer capable of suppressing the metal diffusion
between the upper and lower metal wirings as well as suppressing
the generation of metal compounds with high resistance due to the
metal diffusion mutually between the metal wirings.
[0055] Therefore, the present invention can suppress the generation
of the metal compounds with high resistance due to the metal
diffusion between the metal wirings, making it possible to improve
the device performance characteristics and reliability. Also, the
present invention provides a diffusion barrier layer of thinner
thickness than the conventional barrier layer of the stacked Ti and
TiN layers, thereby reducing the contact resistance.
[0056] Hereinafter, the method for forming a multi-layer metal
wiring of a semiconductor device according to an embodiment of the
present invention will be described in detail with reference to
FIGS. 1A through 1E.
[0057] Referring to FIG. 1A, a first interlayer insulating layer
110 is formed over the a semiconductor substrate 100 on which an
underlayer (not shown) is formed and then etched to form a trench
120 defining a region for forming a lower metal wiring 140. A first
diffusion barrier layer 130 is formed over the first interlayer
insulating layer 110 including the trench 120. The first diffusion
barrier layer 130 is formed of a stacked layer of a Ta layer 130a
and a TaN layer 130b.
[0058] A Cu seed layer is deposited over the first diffusion
barrier layer 130. The Cu layer is deposited over the Cu seed layer
with an electroplating method so that the trench 120 is filled. The
lower Cu wiring 140 is formed in the trench 120 by etching the Cu
layer and the first diffusion barrier layer 130 so that the first
interlayer insulating layer 110 outside the trench 120 is
exposed.
[0059] Referring to FIG. 1B, a second interlayer insulating layer
150 is formed over the first interlayer insulating layer 120
including the lower Cu wiring 140, and then the second interlayer
insulating layer 150 is etched to form a contact hole 160 exposing
the lower Cu wiring 140.
[0060] Referring to FIG. 1C, a second diffusion barrier layer 170
for preventing the mutual metal diffusion between the lower Cu
wiring 140 and a upper metal wiring (to be formed in the contact
hole 160) is formed over the second interlayer insulating layer 150
including the contact hole 160. The second diffusion barrier layer
170 is formed of a tungsten-based (or W-based) layer. For example,
the W-based layer would include a WN layer or a stacked layer of W
and WN layers or a WSiNy layer or a stacked layer of WSix and WSiNy
layers or the like.
[0061] Referring to FIG. 1D, an Al nucleation growth layer 181 is
formed over the W-based second diffusion barrier layer 170 by a
deposition method such as a chemical vapor deposition (CVD). The Al
nucleation growth layer 181 is formed to have a thickness of 50 to
500 .ANG..
[0062] A wiring 182 of Al layer is formed on the Al nucleation
growth layer 181 such that the contact hole 160 is filled. For
example, the Al layer for wiring 182 is formed by depositing Al at
a temperature in the range of 200 to 400.degree. C. by a deposition
method such as a physical vapor deposition (PVD) and by performing
a heat treatment on the Al layer at a temperature in the range of
400 to 500.degree. C.
[0063] Similarly, for example, the Al layer for wiring 182 can be
formed as a stacked layer of a fist Al layer and a second Al layer
by depositing the first Al layer at a temperature in the range of
150 to 200.degree. C. by a PVD method and depositing the second Al
layer over the first Al layer at a temperature in the range of 200
to 450.degree. C. also by a PVD method.
[0064] Referring to FIG. 1E, the Al layer for upper wiring 182 and
the W-based second diffusion barrier layer 170 are etched to form a
upper Al wiring 180 contacting the lower Cu wiring 140, thereby
forming a multi-layer metal wiring of a semiconductor device
according to an embodiment of the present invention.
[0065] FIG. 2 is a cross-sectional view for explaining a method for
forming a WN layer as a second diffusion barrier layer in
accordance with a first embodiment of the present invention. As
shown, a WN layer 270 is formed to a thickness of 50 to 200 .ANG.
over a second interlayer insulating layer 250 having the contact
hole 260 by an atomic layer deposition (ALD) or CVD method.
[0066] For example, the WN layer 270 is formed by supplying one or
more gases in combinations of B.sub.2H.sub.6, WF.sub.6, and
NH.sub.3 under a temperature in the range of 200 to 400.degree. C.
and a pressure in the range of 1 to 40 Torr. One or more gases in
combination of B.sub.10H.sub.14, SiH.sub.4, and Si.sub.2H.sub.6,
besides or in addition to B.sub.2H.sub.6, can be used when forming
the WN layer 270.
[0067] Further, the WN layer 270 can also be formed by depositing a
W layer to a thickness of 10 to 100 .ANG. by supplying the gases of
B.sub.2H.sub.6 and WF.sub.6, and then changing the W layer into the
WN layer by supplying the gases of B.sub.2H.sub.6 and NH.sub.3,
thereby depositing the WN layer. The W layer can be formed by using
any one of gas B.sub.10H.sub.14, SiH.sub.4, and Si.sub.2H.sub.6,
besides the gas of B.sub.2H.sub.6.
[0068] In FIG. 2, the reference numeral 200 represents a
semiconductor substrate; 210 represents a first interlayer
insulating layer; 230a represents a Ta layer; 230b represents a TaN
layer; 230 represents a first diffusion barrier layer; and 240
represents a lower Cu wiring.
[0069] FIG. 3 is a cross-sectional view for explaining a method for
forming a stacked layer of a W layer and a WN layer as a second
diffusion barrier layer in accordance with a second embodiment of
the present invention. As shown, a stacked layer 370 of a W layer
371 and a WN layer 372 is formed to a thickness of 50 to 300 .ANG.
by first depositing the W layer 371 over the second interlayer
insulating layer 350 having the contact hole 360 by an ALD or CVD
method, and then nitrifying the surface of the W layer 371.
[0070] For example, the method for forming the stacked layer 370 of
the W layer 371 and WN layer 372 is formed by forming the WN layer
372 on the surface of the W layer 371 by first supplying the gas of
WF.sub.6 and B.sub.2H.sub.6 under a temperature in the range of 200
to 400.degree. C. and a pressure in the range of 1 to 40 Torr to
deposit the W layer 371 and then nitrifying the surface of the W
layer 371 under the atmosphere of NH.sub.3.
[0071] The W layer 371 can be deposited by using any one of gas of
B.sub.10H.sub.14, SiH.sub.4, and Si.sub.2H.sub.6 besides the gas of
B.sub.2H.sub.6. The nitrification on the surface of the W layer 371
can be performed by using the gas of N.sub.2H.sub.4 besides the gas
of NH.sub.3, and further the nitrification can be performed by
supplying a radical including N by forming N.sub.2 and
N.sub.2/H.sub.2 plasma.
[0072] Meanwhile, the nitrification on the surface of the W layer
371 may be performed by raising the temperature of the
semiconductor substrate or may be performed by a heat treating
process for an efficient nitrification processing.
[0073] In FIG. 3, the reference numeral 300 represents a
semiconductor substrate; 310 represents a first interlayer
insulating layer; 330a represents a Ta layer; 330b represents a TaN
layer; 330 represents a first diffusion barrier layer; and 340
represents a lower Cu wiring.
[0074] FIG. 4 is a cross-sectional view for explaining a method for
forming a WSixNy layer as a second diffusion barrier layer in
accordance with a third embodiment of the present invention. As
shown, the WSixNy layer 470 is formed to a thickness of 50 to 300
.ANG. over the second interlayer insulating layer 450 having the
contact hole 460 by an ALD or CVD method.
[0075] For example, the WSixNy layer 470 is formed by supplying one
or more gases in combination of WF.sub.6, B.sub.2H.sub.6,
SiH.sub.4, and NH.sub.3 under a temperature in the range of 300 to
500.degree. C. and a pressure of 0.01 to 10 Torr. The WSixNy layer
470 can be formed in a cycle of B.sub.2H.sub.6
supply-B.sub.2H.sub.6 purge-WF.sub.6 supply-WF.sub.6
purge-SiH.sub.4 supply-SiH.sub.4 purge-NH.sub.3 supply-NH.sub.3
purge or in a cycle of WF.sub.6 supply-WF.sub.6
purge-B.sub.2H.sub.6 supply-B.sub.2H.sub.6 purge-SiH.sub.4
supply-SiH.sub.4 purge-NH.sub.3 supply-NH.sub.3 purge.
[0076] The WSixNy layer 470 can be formed by using one or more
gases of BH.sub.3 and B.sub.10H.sub.14 besides the gas of
B.sub.2H.sub.6, and can be formed by using one or more gases of
Si.sub.2H.sub.6 and SiH.sub.2Cl.sub.2 besides the gas of
SiH.sub.4.
[0077] In FIG. 4, the reference numeral 400 represents a
semiconductor substrate; 410 represents a first interlayer
insulating layer; 430a represents a Ta layer; 430b represents a TaN
layer; 430 represents a first diffusion barrier layer; and 440
represents a lower Cu wiring.
[0078] FIG. 5 is a cross-sectional view for explaining a method for
forming a stacked layer of a WSix layer and a WSixNy layer as a
second diffusion barrier layer in accordance with a fourth
embodiment of the present invention. As shown, a stacked layer 570
of the WSix layer 571 and the WSixNy layer 572 is formed to a
thickness of 50 to 300 .ANG. by depositing the WSix layer 571 over
the second interlayer insulating layer 550 having the contact hole
560 by an ALD or CVD method and nitrifying the surface of the WSix
layer 571.
[0079] For example, the method for forming the stacked layer 570 of
the WSix layer 571 and WSixNy layer 572 is formed by forming the
WSixNy layer 572 on the surface of the WSix layer 571 by first
supplying one or more gases in combination of WF.sub.6,
B.sub.2H.sub.6 and SiH.sub.4 to deposit the WSix layer 571 under a
temperature in the range of 300 to 500.degree. C. and a pressure in
the range of 0.01 to 10 Torr and then nitrifying the surface of the
WSix layer 571 under the atmosphere of NH.sub.3.
[0080] The WSix layer 571 can be deposited by using a gas of
BH.sub.3 or B.sub.10H.sub.14 besides the gas of B.sub.2H.sub.6 and
using a gas of Si.sub.2H.sub.6 or SiH.sub.2Cl.sub.2 besides the gas
of SiH.sub.4. The nitrification on the surface of the WSix layer
571 can be performed by using the gas of N.sub.2H.sub.4 besides the
gas of NH.sub.3 and can be performed by supplying a radical
including N by forming N.sub.2 and N.sub.2/H.sub.2 plasma.
[0081] Meanwhile, the nitrification on the surface of the WSix
layer 571 can be performed by raising the temperature of the
semiconductor substrate 500 and can be performed by a heat treating
process for an efficient nitrification processing.
[0082] In FIG. 5, the reference numeral 510 represents a first
interlayer insulating layer; 530a represents a Ta layer; 530b
represents a TaN layer; 530 represents a first diffusion barrier
layer; and 540 represents a lower Cu wiring.
[0083] As described above, the present invention uses the W-based
layer as the diffusion barrier layer between the lower Cu wiring
and the upper Al wiring. The W-based layer has excellent diffusion
barrier characteristics as compared to the conventional diffusion
barrier such as the stacked layer of the Ti layer and the TiN
layer, effectively suppressing the metal diffusion between the
lower Cu wiring contacting the upper Al wiring.
[0084] As described above, when forming a multi-layer metal wiring
structure having the lower Cu wiring contacting the upper Al wiring
in an ultra high integration device, the present invention provides
an excellent diffusion barrier for effectively suppressing the
metal diffusion between the upper and lower metal wirings. The
present invention also suppresses the high resistance metal
compounds from being generated through the metal diffusion between
the metal wirings, thereby improving the device reliability and
performance characteristics.
[0085] Also, the present invention provides a thinner diffusion
barrier than the conventional diffusion barrier layer of the
stacked Ti and TiN layers, thereby lowering the contact
resistance.
[0086] Although a specific embodiments of the present invention has
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
the spirit of the invention as disclosed in the accompanying
claims.
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