U.S. patent application number 11/964239 was filed with the patent office on 2008-07-03 for transistor, fabricating method thereof and flat panel display therewith.
This patent application is currently assigned to Samsung SDI Co., Ltd.. Invention is credited to SEIHWAN JUNG, KIYONG LEE, MAXIM LISACHENKO, BYOUNGKEON PARK, JINWOOK SEO, TAEHOON YANG.
Application Number | 20080157083 11/964239 |
Document ID | / |
Family ID | 39580475 |
Filed Date | 2008-07-03 |
United States Patent
Application |
20080157083 |
Kind Code |
A1 |
PARK; BYOUNGKEON ; et
al. |
July 3, 2008 |
TRANSISTOR, FABRICATING METHOD THEREOF AND FLAT PANEL DISPLAY
THEREWITH
Abstract
A transistor includes a substrate, an active region including a
source region, a channel region, and a drain region which are
crystallized using an SGS crystallization method and are formed on
the substrate so that a grain size of a first annealed portion and
a second annealed portion are different from each other, a gate
insulating layer formed on the active region, and a gate electrode
formed on the gate insulating layer.
Inventors: |
PARK; BYOUNGKEON;
(Yongin-si, KR) ; YANG; TAEHOON; (Yongin-si,
KR) ; SEO; JINWOOK; (Yongin-si, KR) ; JUNG;
SEIHWAN; (Yongin-si, KR) ; LEE; KIYONG;
(Yongin-si, KR) ; LISACHENKO; MAXIM; (Yongin-si,
KR) |
Correspondence
Address: |
STEIN, MCEWEN & BUI, LLP
1400 EYE STREET, NW, SUITE 300
WASHINGTON
DC
20005
US
|
Assignee: |
Samsung SDI Co., Ltd.
Suwon-si
KR
|
Family ID: |
39580475 |
Appl. No.: |
11/964239 |
Filed: |
December 26, 2007 |
Current U.S.
Class: |
257/59 ;
257/E21.001; 257/E21.133; 257/E21.413; 257/E29.003; 257/E29.293;
438/166 |
Current CPC
Class: |
H01L 21/02488 20130101;
H01L 29/78675 20130101; H01L 29/78696 20130101; H01L 21/02672
20130101; H01L 27/1277 20130101; H01L 29/66757 20130101; H01L
21/02532 20130101; H01L 29/04 20130101; H01L 27/3244 20130101 |
Class at
Publication: |
257/59 ; 438/166;
257/E21.001; 257/E29.003 |
International
Class: |
H01L 29/04 20060101
H01L029/04; H01L 21/00 20060101 H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 29, 2006 |
KR |
2006-138322 |
Claims
1. A transistor, comprising: a substrate; an active region
including a source region, a channel region, and a drain region,
which are crystallized using an SGS (Super Grain Silicon)
crystallization method and are formed on the substrate so that a
grain size of a first annealed portion and a second annealed
portion are different from each other; a gate insulating layer
formed on the active region; and a gate electrode formed on the
gate insulating layer.
2. The transistor as claimed in claim 1, wherein a grain boundary
size of the first annealed portion is smaller than that of the
second annealed portion.
3. The transistor as claimed in claim 1, wherein the active region
includes metal catalysts.
4. The transistor as claimed in claim 3, wherein the concentration
of the metal catalysts in the first annealed portion is higher than
that of the second annealed portion.
5. The transistor as claimed in claim 3, wherein the metal catalyst
is one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh,
Cd, Pt, or any combinations thereof.
6. The transistor as claimed in claim 1, wherein the source region
and the drain region are doped with a P-type dopant.
7. The transistor as claimed in claim 1, wherein the source region
and the drain region are doped with an N-type dopant.
8. The transistor as claimed in claim 1, wherein the gate electrode
is one of MoW, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy,
or any combinations thereof.
9. The transistor as claimed in claim 1, further comprising a
buffer layer formed between the substrate and the active
region.
10. The transistor as claimed in claim 1, further comprising: an
inter-layer dielectric layer formed on a surface of the gate
insulating layer and the gate electrode; a source electrode
connected to the source region and penetrating through the
inter-layer dielectric layer and gate insulating layer; and a drain
electrode connected to the drain region and penetrating through the
inter-layer dielectric layer and the gate insulating layer.
11. The transistor as claimed in claim 1, wherein a grain boundary
does not exist in the active region.
12. The transistor as claimed in claim 1, wherein at least one
grain boundary exists in the active region.
13. A fabricating method of the transistor, comprising: preparing a
substrate, forming an amorphous silicon layer on the substrate;
forming a capping layer on the amorphous silicon layer; forming a
metal catalyst layer on the capping layer; performing a first
annealing process to crystallize amorphous silicon of the amorphous
silicon layer into first annealed polycrystalline silicon using an
SGS (Super Grain Silicon) crystallization method wherein metal
catalysts of the metal catalyst layer diffuse as far as the
amorphous silicon by penetrating through the capping layer;
removing the metal catalyst layer and the capping layer; and
performing a second annealing process wherein the metal catalyst
crystallizes the amorphous silicon into second annealed
polycrystalline silicon using the SGS crystallization method to
form a polycrystalline silicon layer.
14. The fabricating method of the transistor as claimed in claim
13, further comprising: forming a semiconductor layer by patterning
the polycrystalline silicon layer; and forming a gate insulating
layer, a gate electrode, an inter-layer dielectric layer, and a
source/drain electrode on the substrate.
15. The fabricating method of the transistor as claimed in claim
13, wherein during the removing of the metal catalyst layer and the
capping layer, the metal catalyst layer and the capping layer are
removed once the amorphous silicon is crystallized so that a
respective grain boundary size is smaller than half of an average
distance between the metal catalysts.
16. The fabricating method of the transistor as claimed in claim
13, further comprising: forming a buffer layer before forming of
the amorphous silicon layer on the substrate.
17. The fabricating method of the transistor as claimed in claim
13, wherein crystallinity of the polycrystalline silicon formed by
the first annealing process is different from that of the
polycrystalline silicon formed by the second annealing process.
18. The fabricating method of the transistor as claimed in claim
13, wherein a grain boundary size of the polycrystalline silicon
formed by the first annealing process is smaller than that of the
polycrystalline silicon formed by the second annealing process.
19. The fabricating method of the transistor as claimed in claim
13, wherein the concentration of the metal catalyst of the
polycrystalline silicon formed by the first annealing process is
higher than that of the metal catalyst of the polycrystalline
silicon formed by the second annealing process.
20. The fabricating method of the transistor as claimed in claim
13, wherein a grain boundary does not exist in the second annealed
polycrystalline silicon.
21. The fabricating method of the transistor as claimed in claim
13, wherein at least one grain boundary exists in the second
annealed polycrystalline silicon.
22. The fabricating method of the transistor as claimed in claim
13, wherein the metal catalyst layer is one of Ni, Pd, Ti, Ag, Au,
Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or any combinations
thereof.
23. The fabricating method of the transistor as claimed in claim
13, wherein the capping layer is an insulating layer.
24. The fabricating method of the transistor as claimed in claim
13, wherein the capping layer is one of an oxide film, a nitride
film, or any combinations thereof.
25. The fabricating method of the transistor as claimed in claim
13, wherein the oxide film is one of silicon dioxide (SiO.sub.2),
aluminum oxide (alumina, Al.sub.2O.sub.3), hafnium oxide
(HfO.sub.2), zirconium oxide (zirconia, ZrO.sub.2), or any
combinations thereof.
26. A flat panel display device, comprising: the transistor
manufactured by the method of claim 13.
27. The method of claim 13, wherein the first annealing process
occurs between about 500.degree. C. to about 650.degree. C. and the
second annealing process occurs between about 550.degree. C. to
about 800.degree. C.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of Korean Application
No. 2006-138322 filed on Dec. 29, 2006, in the Korean Intellectual
Property Office, the disclosure of which is incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] Aspects of the present invention relate to a transistor, a
fabricating method thereof, and a flat panel display device
therewith. More particularly, aspects of the present invention
relate to a transistor, a fabricating method, and a flat panel
display device, wherein an amorphous silicon layer formed on an
insulating substrate is crystallized into a polycrystalline silicon
layer using an SGS (Super Grain Silicon) crystallization method,
whereby the substrate undergoes a first annealing process by
absorbing or diffusing an extremely small amount of metal catalysts
into a capping layer as the substrate undergoes a first heat
treatment in order to control the concentration of the metal
catalyst left in the polycrystalline silicon layer, then the
substrate undergoes a second annealing process, that is, a
remaining crystallization as the substrate undergoes a second heat
treatment after the capping layer and the metal catalyst layer are
removed.
[0004] 2. Description of the Related Art
[0005] In general, a thin film transistor (TFT) is a semiconductor
device wherein a channel region, where a hole or an electron can
flow, can be formed by doping a P-type or an N-type dopant on a
source region and a drain region, and then applying a predetermined
voltage to a gate electrode. The thin film transistor can be
classified into a PMOS (P-type metal-oxide semiconductor)
transistor and an NMOS (N-type metal-oxide semiconductor)
transistor. If the source region and the drain region are doped
with the P-type dopant, and the hole flows when a channel region is
formed, the transistor is called the PMOS transistor. On the
contrary, if the source region and the drain region are doped with
the N-type dopant, and the electron flows when a channel region is
formed, the transistor is called the NMOS transistor.
[0006] The thin film transistor is used widely as a switching
transistor or a driving transistor of a variety of flat panel
display devices, such as an active matrix liquid crystal display
device and an organic light emitting diode display device. In
general, in the thin film transistor as described above, amorphous
silicon is deposited on a substrate made of glass, quartz, plastic
or steel. Then, a semiconductor layer is formed by crystallizing
the amorphous silicon after the amorphous silicon is
dehydrogenated. Specifically, the semiconductor layer is formed by
depositing an amorphous silicon layer on the substrate using a
chemical vapor deposition method, and processed to include a source
region, a drain region and a channel region (referred to as an
active region as a whole).
[0007] However, if the amorphous silicon is deposited directly on a
substrate by the chemical vapor deposition method and the like, the
amorphous silicon layer containing about 12% of hydrogen is formed,
which has low electron mobility. In addition, if the amorphous
silicon layer of low electron mobility is crystallized into a
silicon layer with a crystalline structure having high electron
mobility, the silicon layer can be damaged by an explosion of the
hydrogen contained therein. Accordingly, a dehydrogenation process
is executed in order to prevent the explosion of the hydrogen
during the course of the crystallization process.
[0008] In general, an amorphous silicon layer is dehydrogenated by
heat-treating the amorphous silicon layer for dozens of minutes to
a few hours at temperatures over 400.degree. C. in a furnace.
Subsequently, a crystallization process to crystallize the
dehydrogenated amorphous silicon layer is carried out.
[0009] A few methods used to crystallize the amorphous silicon into
polycrystalline silicon include solid phase crystallization,
excimer laser crystallization, metal induced crystallization, and
metal induced lateral crystallization. The solid phase
crystallization is a method wherein an amorphous silicon layer is
annealed for a few hours to dozens of hours below about 700.degree.
C. 700.degree. C. is a deflection temperature of glass which forms
a substrate of a display device to which a thin film transistor is
applied. An excimer laser crystallization is a method wherein an
amorphous silicon layer is heated locally to a high temperature by
injecting a light beam from an excimer laser into the amorphous
silicon layer so that the amorphous silicon layer is
crystallized.
[0010] A metal induced crystallization is a method wherein a metal
such as nickel, palladium, gold, aluminum, and so on, is brought
into contact with an amorphous silicon layer or injected into the
amorphous silicon layer. Consequently, a phase transition is
induced during which the amorphous silicon changes into
polycrystalline silicon. A metal induced lateral crystallization is
a method wherein silicide generated from the reaction of a metal
and silicon continuously propagates laterally. Consequently, metal
induced lateral crystallization induces the crystallization of an
amorphous silicon layer in sequence.
[0011] However, the solid phase crystallization has disadvantages
in that the process time is too long, and the substrate can be
deformed easily due to the high temperature heat treatment
occurring over a long time. The excimer laser crystallization has
disadvantages in that the process requires an expensive laser
device, and the interfacial property between a semiconductor layer
and a gate insulating layer is poor because extrusions are
generated on a polycrystallized surface. The metal induced
crystallization or the metal induced lateral crystallization have
disadvantages in that a leak (or leakage) current of a
semiconductor layer of a thin film transistor increases because
metal catalysts are left in the polycrystalline silicon layer.
Consequently, the characteristics of various flat panel display
devices using the silicon layer as a switching transistor or a
driving transistor of the above processes are poor.
SUMMARY OF THE INVENTION
[0012] Aspects of the present invention are directed to controlling
the concentration of the metal catalyst left in a polycrystalline
silicon layer when an amorphous silicon layer formed on an
insulating substrate is crystallized into a polycrystalline silicon
layer using an SGS (Super Grain Silicon) crystallization
method.
[0013] An aspect of the present invention is to provide a
transistor, a fabricating method, and a flat panel display device,
wherein a substrate is crystallized by absorbing or diffusing an
extremely small amount of metal catalysts into a capping layer as
the substrate undergoes a first heat treatment. Subsequently, the
substrate undergoes a remaining (or further) crystallization as the
substrate undergoes a second heat treatment after the capping layer
and the metal catalyst are removed. Accordingly, a leak (or
leakage) current can be minimized because the concentration of the
metal catalyst left in the polycrystalline silicon layer can be
minimized.
[0014] A transistor according to an aspect of the present invention
minimizes a leak (or leakage) current can include a substrate; an
active region including a source region, a channel region, and a
drain region which are crystallized using an SGS (Super Grain
Silicon) crystallization method and are formed on the substrate so
that a crystal grain size of a first annealed portion and a second
annealed portion are different from each other; a gate insulating
layer formed on the active region; and a gate electrode formed on
the gate insulating layer.
[0015] According to aspects of the present invention, a grain
boundary size of the first annealed portion can be smaller than
that of the second annealed portion. The concentration of metal
catalysts of the first annealed portion can be higher than that of
the second annealed portion. The source region and the drain region
of the active region can be doped with either a P-type dopant or an
N-type dopant. The gate electrode can be one of MoW, Ti, Cu, AiNd,
Al, Cr, Mo alloy, Cu alloy, Al alloy, or any combinations thereof.
The transistor can also include a buffer layer formed between the
substrate and the active region. The metal catalyst can be one of
Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or
any combination thereof.
[0016] The transistor according to an aspect of the present
invention can also include an inter-layer dielectric layer formed
on a surface of the gate insulating layer and the gate electrode, a
source electrode connected to the source region and penetrating
through the inter-layer dielectric layer and the gate insulating
firm, and a drain electrode connected to the drain region and
penetrating through the inter-layer dielectric layer and the gate
insulating layer.
[0017] A fabricating method of the transistor according to an
aspect of the present invention includes preparing a substrate;
forming an amorphous silicon layer on the substrate; forming a
capping layer on the amorphous silicon layer; forming a metal
catalyst layer on the capping layer; performing a first annealing
process to crystallize amorphous silicon of the amorphous silicon
layer into first annealed polycrystalline silicon using an SGS
(Super Grain Silicon) crystallization method wherein metal
catalysts of the metal catalyst layer diffuse as far as the
amorphous silicon by penetrating through the capping layer;
removing the metal catalyst layer and the capping layer; and
performing a second annealing process wherein the metal catalyst
crystallizes the amorphous silicon into second annealed
polycrystalline silicon using an SGS crystallization method to form
a polycrystalline silicon layer.
[0018] In aspects of the present invention, after the second
annealing process, the method can include forming a semiconductor
layer (an active region) by patterning the polycrystalline silicon
layer and forming a gate insulating layer, a gate electrode, an
inter-layer dielectric layer, and a source/drain electrode on the
substrate. During removing of the metal catalyst layer and the
capping layer, the metal catalyst layer and the capping layer may
be removed once the size of the respective grain boundary size is
smaller than half of an average distance between the metal
catalysts as the amorphous silicon is crystallized.
[0019] In aspects of the present invention, the method can also
include forming a buffer layer prior to the forming of the
amorphous silicon layer on the substrate. The crystallinity of the
polycrystalline silicon formed by the first annealing process is
different from that of the polycrystalline silicon formed by the
second annealing process. A grain boundary size of the
polycrystalline silicon formed by the first annealing process is
smaller than that of the polycrystalline silicon formed by the
second annealing process.
[0020] According to aspects of the present invention, the
concentration of the metal catalyst of the polycrystalline silicon
formed by the second annealing process is lower than that of the
metal catalyst of the polycrystalline silicon formed by the first
annealing process. The metal catalyst layer can be one of Ni, Pd,
Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or any
combinations thereof. The capping layer can be an insulating layer
and be one of an oxide film, a nitride film, or any combinations
thereof. The oxide film can be one of silicon dioxide (SiO.sub.2),
aluminum oxide (alumina, Al.sub.2O.sub.3), hafnium oxide
(HfO.sub.2) and zirconium oxide (zirconia, ZrO.sub.2).
[0021] As described above, in aspects of the present invention, a
leak (or leakage) current can be reduced by minimizing the
concentration of the metal catalyst that is unnecessarily left in a
polycrystalline silicon layer. In addition, a polycrystalline
silicon layer of excellent (or improved) crystallinity can be
obtained by reducing unnecessary crystallization by remaining metal
catalysts.
[0022] Additional aspects and/or advantages of the invention will
be set forth in part in the description which follows and, in part,
will be obvious from the description, or may be learned by practice
of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] These and/or other aspects and advantages of the invention
will become apparent and more readily appreciated from the
following description of the aspects, taken in conjunction with the
accompanying drawings of which:
[0024] FIGS. 1A to 1F are cross-sectional views depicting a
fabricating process wherein an amorphous silicon layer is
crystallized into a polycrystalline silicon layer using an SGS
(Super Grain Silicon) crystallization method according to an aspect
of the present invention;
[0025] FIG. 2 is a cross-sectional view depicting a polycrystalline
silicon layer formed according to an aspect the present invention
after the polycrystalline silicon layer is etched lightly;
[0026] FIG. 3 is a cross-sectional view of a thin film transistor
adopting the polycrystalline silicon layer formed according to an
aspect of the present invention;
[0027] FIG. 4 is a block diagram illustrating an example of a flat
panel display device to which the transistor according to an aspect
of the present invention can be applied; and
[0028] FIG. 5 is an equivalent circuit diagram depicting a pixel
circuit of a flat panel display device to which the transistor
according to an aspect of the present invention can be applied.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] Reference will now be made in detail to aspects of the
present invention, examples of which are illustrated in the
accompanying drawings, wherein like reference numerals refer to the
like elements throughout. The aspects are described below in order
to explain the present invention by referring to the figures.
[0030] FIGS. 1A to 1F are cross-sectional views depicting a
fabricating process wherein an amorphous silicon layer is
crystallized into a polycrystalline silicon layer using an SGS
(Super Grain Silicon) crystallization method according to an aspect
the present invention. First, FIG. 1A is a cross-sectional view
depicting a process during which a buffer layer 102 is formed on a
substrate 101, and an amorphous silicon layer 103 is formed on the
buffer layer 102. As shown in FIG. 1A, the buffer layer 102 is
formed as a single layer or a double layer of a silicon oxide layer
or a silicon nitride layer by use of a chemical vapor deposition
technique or process or a physical vapor deposition technique or
process on the substrate 101. In various aspects, the substrate 101
is made of plastic, glass or steel. As shown, the buffer layer 102
prevents (or reduces) the diffusion of water or impurities
generated from the bottom substrate 101. The buffer layer 102 also
controls the velocity of heat transfer so that a semiconductor
layer can be crystallized properly.
[0031] Subsequently, the amorphous silicon layer 103 is formed on
the buffer layer 102. In the aspect shown, the amorphous silicon
layer 103 is formed by the chemical vapor deposition technique in
general, though not required. The amorphous silicon layer 103
formed by the chemical vapor deposition technique contains gases
such as hydrogen, and the gases cause problems such as a decrease
in mobility of electrons, and so on. Accordingly, a dehydrogenation
process is executed (or performed) so that hydrogen is not left in
(or is removed from) the amorphous silicon layer 103.
[0032] FIG. 1B is a cross-sectional view depicting a process during
which a capping layer 104 is formed on the substrate 101. As shown
in FIG. 1B, the capping layer 104 is formed on the substrate 101 on
which the amorphous silicon layer 103 is formed. As shown, the
capping layer 104 is formed of an oxide film or a nitride film by
the chemical vapor deposition technique. The oxide film is made of
a material such as silicon dioxide (SiO.sub.2), aluminum oxide
(such as alumina, Al.sub.2O.sub.3), hafnium oxide (such as
HfO.sub.2), and zirconium oxide (such as zirconia, ZrO.sub.2), and
the nitride film is made of a material such as silicon nitride
(such as SiNx). In other aspects, the capping layer 104 may be any
combinations of the oxide or nitride films.
[0033] As shown, the characteristics of the capping layer 104 can
be changed by a variety of processing conditions during the course
of the chemical vapor deposition process, and such characteristics
change of the capping layer 104 can influence the diffusion or the
infiltration of metal catalysts during the course of subsequent
processes and the crystallization of the amorphous silicon layer
103 significantly. That is, when the capping layer 104 is formed by
the chemical vapor deposition process, the characteristics of the
capping layer 104 can be changed by changes in key variables such
as an amount of silane gas, and/or an amount and power (or
pressure) of ammonia gas.
[0034] As shown, the capping layer 104 is defined as an insulating
layer which contributes to the crystallization of the amorphous
silicon layer 103. The capping layer 104 controls the concentration
or the amount of the metal catalyst by controlling the diffusion
and the infiltration of the metal catalyst during the course of one
or more heat treatment processes. The capping layer 104 can be made
of an oxide such as silicon dioxide (SiO.sub.2), aluminum oxide
(such as alumina, Al.sub.2O.sub.3), hafnium oxide (such as
HfO.sub.2), zirconium oxide (such as zirconia, ZrO.sub.2), or a
nitride such as silicon nitride (SiNx), or any combinations
thereof.
[0035] FIG. 1C is a cross-sectional view depicting a process during
which a metal catalyst layer 105 is formed on the capping layer
104. As shown in FIG. 1C, the metal catalyst layer 105 is formed by
depositing metal catalysts on the capping layer 104. As shown, the
metal catalyst layer 105 is formed by depositing one, or more than
one metal catalysts of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo,
Tr, Ru, Rh, Cd, Pt, or any combinations thereof. It is preferable,
but not required, to form the metal catalyst layer 105 with Ni
because Ni can crystallize the amorphous silicon layer 103 into a
polycrystalline silicon layer 110 more easily.
[0036] FIG. 1D is a cross-sectional view depicting a process during
which metal catalysts 108c are absorbed or diffused into the
capping layer 104 by carrying out of a first annealing process
(depicted as) 106 while the substrate 101 undergoes a first heat
treatment.
[0037] Subsequently, a process during which the amorphous silicon
layer 103 is crystallized as the substrate 101 undergoes the first
annealing process 106, is carried out. During the first annealing
process 106, the metal catalyst 108c contained in the metal
catalyst layer 105 diffuses or infiltrates (depicted as) 107 into
the capping layer 104, and moves to an interface 104a between the
capping layer 104 and the amorphous silicon layer 103 (shown in
FIG. 1C). Consequently, a crystallization seed 108a is formed. As
shown, metal catalysts 108b, which cannot reach the amorphous
silicon layer 103, do not influence the crystallization of the
amorphous silicon layer 103 at all. Preferably, the temperature for
the heat treatment during the first annealing process 106 is
500.degree. C. to 650.degree. C., though not required. If the
substrate 101 is heat-treated below 500.degree. C., the
crystallization cannot be accomplished as properly (or
efficiently). On the contrary, in case that the substrate is
heat-treated over 650.degree. C., a seed 108a cannot be formed (or
dispersed) as uniformly.
[0038] As shown, during the first annealing process 106, the metal
catalyst 108c moves to the interface 104a between the amorphous
silicon layer 103 and the capping layer 104 as the substrate 101
undergoes the first heat treatment. Subsequently, the
crystallization seed (or the seed) 108a is formed. The amorphous
silicon layer 103 is crystallized into a grain 110a of a
polycrystalline silicon layer 110 using the seed 108a by adopting
the SGS (Super Grain Silicon) crystallization method.
[0039] FIG. 1E is a cross-sectional view depicting a process during
which a polycrystalline silicon layer 110 having low concentration
of a remaining metal catalyst 108c is formed by removing the metal
catalyst layer 105 and the capping layer 104. As shown in FIG. 1E,
the polycrystalline silicon layer 110 having low concentration of
the remaining metal catalyst 108c is formed by removing the capping
layer 104. When the capping layer 104 is removed, the seed 108a
formed at the interface 104a between the capping layer 104 and the
polycrystalline silicon layer 110 should be removed together in
order to form an immaculate (or a clean) interface 104a.
[0040] As shown, a time when the metal catalyst layer 105 and the
capping layer 104 should be removed is calculated by the following
equation 1.
V * t < L 2 [ Formula 1 ] ##EQU00001##
[0041] Here, V is the average crystallization velocity, L is the
distance between the seeds 108a, and t is the crystallization
time.
[0042] That is, it is preferable, but not required, to remove the
metal catalyst layer 105 and the capping layer 104 when a
respective grain 110a distance (shown in FIG. 1F) is smaller than
half of the average distance between the metal catalysts after the
amorphous silicon layer 103 is crystallized.
[0043] For instance, if the grain boundary 110c grows at the rate
of 0.83 .mu.m per minute at 600.degree. C., and the distance
between the metal catalysts is 20 .mu.m,
t < 20 .mu. m 2 1 0.83 .mu. m / min t < 12.05 min [ Formula 2
] ##EQU00002##
[0044] That is, it is preferable, but not required, to remove the
metal catalyst layer 105 and the capping layer 104 after the
substrate 101 undergoes the first heat treatment for about 12
minutes, in this example.
[0045] FIG. 1F is a drawing depicting a process during which a
remaining amorphous silicon layer 103a is crystallized as the
substrate 101 undergoes a second annealing process (depicted as)
108 while the substrate 101 undergoes a second heat treatment.
During the second annealing process 108, the amorphous silicon
layer 103 is crystallized beginning with (or starting at) the
polycrystalline silicon layer grain 110a formed after the first
annealing process 106.
[0046] One grain 110a of polycrystalline silicon layer 110 grows
from one seed 108a formed by the metal catalyst 108c, and when the
grains which grow from a plurality of different seeds (such as
108a) come in contact with one another, the grain boundary 110c is
formed. Therefore, if the amount of the metal catalysts 108c which
reaches the interface 104a is controlled properly (that is, after
the first annealing process 106, the diffusion of the metal
catalyst 108c is controlled by removing the unnecessary metal
catalysts 108c and the capping layer 104, consequently, the number
of the seed 108a for grain growth at the interface 104a can be
controlled), the grain 110a of the polycrystalline silicon layer
110 becomes larger, and the number of the grain boundary 110c
becomes smaller. Preferably, though not required, the temperature
for the second annealing process 108 is 550.degree. C. to
800.degree. C. If the substrate 101 is heat-treated below
550.degree. C., the crystallization cannot be accomplished as
properly (or efficiently). On the contrary, in case that the
substrate is heat-treated over 800.degree. C., the substrate can be
deformed.
[0047] As shown, during the second annealing process 108, the
remaining amorphous silicon layer 103a is crystallized into the
polycrystalline silicon layer 110 formed after the first annealing
process 106 (using the SGS (Super Grain Silicon) crystallization
method) as the substrate 101 undergoes the second annealing process
108.
[0048] In the polycrystalline silicon layer 110 formed by the SGS
crystallization method, the diffusion of the metal catalyst 108c is
controlled by removing the unnecessary metal catalyst 108c and the
capping layer 104 after the first annealing process 106. Therefore,
the second annealing process 108 is carried out when the number of
the seed 108a for grain growth at the interface 104a is controlled
or removed. Consequently, the grain 110a of the polycrystalline
silicon layer 110 becomes larger, and the number of the grain
boundary 110c becomes smaller.
[0049] FIG. 2 is a microscopic image depicting the polycrystalline
silicon layer 110 formed using the SGS crystallization method
according to aspects of the present invention after the
polycrystalline silicon layer 110 is etched lightly. In the case of
the polycrystalline silicon portion 110b formed by the second
annealing process 108, the concentration of the metal catalyst 108c
is lower, or the crystallinity is better than when the
polycrystalline silicon portion (or grain) 110c formed by the first
annealing process 106. This is because the diffusion and
infiltration of the unnecessary metal catalyst 108c is reduced as
the metal catalyst layer 105 and the capping layer 104 are removed
after the first annealing process 106. As the amount of unnecessary
metal catalyst 108c is reduced, the crystallinity becomes excellent
(or improved) because the grain (such as 110a) can be formed
uniformly. In various aspects, the first heat treatment may
nucleate and/or grow the grain 110a and the subsequent second heat
treatment further grows the grain 110a into a larger grain 110b,
which includes grain 110a. In other aspects, further independent
nucleation of grains is prevented or minimized during the second
heat treatment so that the grain 110a simply grows into the larger
grain 110b.
[0050] FIG. 3 is a cross-sectional view of a thin film transistor
using the polycrystalline silicon layer 110 formed using the SGS
crystallization method according to aspects of the present
invention. As shown in FIG. 3, the buffer layer 102 is formed on
the substrate 101 made of glass, quartz, plastic, or steel.
Subsequently, a silicon layer 111 (an active region) is formed by
patterning the polycrystalline silicon layer 110 after the
polycrystalline silicon layer 110 is formed as described in FIGS.
1A to 1F. In the active region 111, the diffusion of the metal
catalyst 108c is controlled by removing the unnecessary metal
catalyst 108c and the capping layer 104 after the first annealing
process 106. Accordingly, the second annealing process 108 is
carried out when the number of the seeds 108a for grain growth at
the interface 104a is controlled. Therefore, the grain 110a of the
polycrystalline silicon layer 110 becomes larger, and the number of
the grain boundary 110c becomes smaller. Consequently, even an
active region 111 including no grain boundary or at least one grain
boundary can be formed.
[0051] Subsequently, after a gate insulating layer 112 is formed by
forming an insulating layer (such as a silicon oxide film, a
silicon nitride film, or any combination thereof) in a single layer
or a double layer, a gate electrode 113 is formed by depositing and
patterning a gate electrode forming material. As shown, a
source/drain region and a channel region (in the active layer 111)
can be defined by carrying out an impurity injection process on the
silicon layer 111 (an active region) using the gate electrode 113
as a mask. The gate electrode 113 can be any one selected from MoW,
Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or any
combinations thereof.
[0052] Subsequently, a contact hole exposing one or more portions
of layers is formed by etching a predetermined region of an
inter-layer dielectric layer 114 and the gate electrode 113, after
the inter-layer dielectric layer 114 is formed by forming an
insulating layer (such as a silicon oxide film, a silicon nitride
film, or any combinations thereof) in a single layer or a in a
double layer on the entire surface of the substrate 101. Then, a
thin film transistor 100 is completed as a source/drain electrode
(such as 115) is formed by depositing and patterning a source/drain
electrode forming material on the entire surface of the substrate
101.
[0053] The thin film transistor 100 manufactured by the fabricating
method so as to have the structure described above can be used
widely as a switching transistor and a driving transistor of a
variety of flat panel display devices (such as an active matrix
liquid crystal display device and an organic light emitting diode
display device). Hereinafter, an organic light emitting diode
display device 400 will be described as an example of the flat
panel display device equipped with the transistor 100. However, the
transistor 100 according to an aspect of the present invention is
not limited simply to the organic light emitting diode display
device 400.
[0054] Referring to FIG. 4, an active matrix liquid crystal display
device is shown as an example of a flat panel display device to
which the transistor 100 according to an aspect of the present
invention can be applied. As shown in FIG. 4, an organic light
emitting diode display device 400 can be integrated and formed
including a scan driver 410, a data driver 420, and a pixel portion
430 driven by the scan driver 410 and the data driver 420.
[0055] Referring to FIG. 5, a pixel portion or a pixel circuit 430
of a flat panel display device to which the transistor 100
according to an aspect of the present invention can be applied is
shown. As shown in FIG. 5, in the pixel circuit 430, a sub-pixel
consists of a scan line (Scan) to select which pixel 431 should be
driven; a data line (Data) to apply a controlled amount of voltage
to the pixel 431 according to a controlled selection; a switching
transistor (T1) to control the data flow according to a signal of
the scan line (Scan); a power source line (VDD) to supply power; a
storage capacitor (Cs) to store an electric charge as much as (or
in the amount of the voltage difference between the voltage applied
from the data line (Data) and the voltage supplied from the power
source line (VDD); a driving transistor (T2) to send an electric
current as an electric current is supplied with (or in the amount
of the voltage stored in the storage capacitor (Cs); and an organic
light emitting diode to emit light according to the electric
current that flows through the driving transistor (T2).
[0056] In addition, the switching transistor (T1) and the driving
transistor (T2) are formed with one PMOS thin film transistor
respectively, for example. The switching transistor (T1) and the
driving transistor (T2) can include more than one PMOS and/or NMOS
thin film transistors respectively according to the characteristics
of the function desired.
[0057] The switching transistor (T1) and the driving transistor
(T2) have the same structure as the structure of the transistor 100
according to an aspect of the present invention. A leak (or
leakage) current can be reduced by minimizing the concentration of
the metal catalyst 108c left in the silicon layer 111 (an active
region) of the transistor 100. In addition, a silicon layer 111 of
excellent (or improved) crystallinity can be obtained by reducing
the unnecessary crystallization by metal catalysts 108c.
[0058] Accordingly, the characteristics of a display can be
improved by applying the transistor 100 according to aspects of the
present invention to a flat panel display device 400 such as an
organic light emitting diode display device and a liquid crystal
display device.
[0059] As described above, the object of the transistor, the
fabricating method thereof and the flat panel display device
therewith according to aspects of the present invention is to
control the concentration of the metal catalyst left in the
polycrystalline silicon layer when an amorphous silicon layer is
crystallized using the SGS crystallization method. The substrate
undergoes the first annealing process by absorbing or diffusing an
extremely small amount of the metal catalyst into the capping layer
as the substrate undergoes the first annealing process. Then the
substrate undergoes the second annealing process after the capping
layer and the metal catalyst layer are removed. Consequently, the
concentration of the metal catalyst left in the polycrystalline
silicon layer can be minimized and a leak (or leakage) current can
also be minimized.
[0060] The above detailed description is one aspect of the
transistor which can prevent or reduce a leak (or a leakage)
current, the fabricating process thereof and the flat panel display
device therewith according to aspects the present invention, and
the aspects of the present invention is not limited to these
aspects. It will also be understood that when a layer or element is
referred to as being "on" or "over" another layer or substrate, it
can be directly on the other layer or substrate, or intervening
layers may also be present. Further, it will be understood that
when a layer is referred to as being "under" or "below" another
layer, it can be directly under, or one or more intervening layers
may also be present.
[0061] Although a few aspects of the present invention have been
shown and described, it would be appreciated by those skilled in
the art that changes may be made in the aspects without departing
from the principles and spirit of the invention, the scope of which
is defined in the claims and their equivalents.
* * * * *