U.S. patent application number 12/043146 was filed with the patent office on 2008-06-26 for operating method of non-volatile memory.
This patent application is currently assigned to POWERCHIP SEMICONDUCTOR CORP.. Invention is credited to Wei-Zhe Wong, Ching-Sung Yang.
Application Number | 20080151645 12/043146 |
Document ID | / |
Family ID | 37566323 |
Filed Date | 2008-06-26 |
United States Patent
Application |
20080151645 |
Kind Code |
A1 |
Wong; Wei-Zhe ; et
al. |
June 26, 2008 |
OPERATING METHOD OF NON-VOLATILE MEMORY
Abstract
A non-volatile memory including at least a substrate, a memory
cell and source/drain regions is provided. The memory cell is
disposed on the substrate and includes at least a first memory unit
and a second memory unit. Wherein, the first memory unit, from the
substrate up, includes a floating gate and a first control gate.
The second memory unit is disposed on a sidewall of the first
memory unit and includes a charge trapping layer and a second
control gate. The two source/drain regions are disposed in the
substrate at both sides of the memory cell.
Inventors: |
Wong; Wei-Zhe; (Tainan City,
TW) ; Yang; Ching-Sung; (Hsinchu City, TW) |
Correspondence
Address: |
JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
7 FLOOR-1, NO. 100, ROOSEVELT ROAD, SECTION 2
TAIPEI
100
omitted
|
Assignee: |
POWERCHIP SEMICONDUCTOR
CORP.
Hsinchu
TW
|
Family ID: |
37566323 |
Appl. No.: |
12/043146 |
Filed: |
March 6, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11306093 |
Dec 15, 2005 |
|
|
|
12043146 |
|
|
|
|
Current U.S.
Class: |
365/185.29 ;
257/E21.209; 257/E21.21; 257/E21.422; 257/E21.423; 257/E29.128;
257/E29.129; 257/E29.308; 365/185.18 |
Current CPC
Class: |
H01L 29/40117 20190801;
H01L 29/7923 20130101; H01L 29/42324 20130101; H01L 29/40114
20190801; H01L 29/4232 20130101; H01L 29/7887 20130101; H01L
29/42328 20130101; H01L 29/66833 20130101; H01L 29/66825 20130101;
H01L 29/42344 20130101; H01L 27/115 20130101 |
Class at
Publication: |
365/185.29 ;
365/185.18 |
International
Class: |
G11C 16/06 20060101
G11C016/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 27, 2005 |
TW |
94121378 |
Claims
1. An operating method of a P-type channel memory, the P-type
channel memory comprising: an N-type well region disposed in a
substrate, a memory cell disposed on the N-type well region and
comprising a first memory unit and a second memory unit disposed on
a sidewall of the first memory unit, the first memory unit, form
the substrate up, at least comprising a floating gate suitable for
storing a first bit and a first control gate, and the second memory
unit, from the substrate up, at least comprising a charge trapping
layer suitable for storing a second bit and a second control gate,
a first source/drain region and a second source/drain region
disposed in the N-type well regions at both sides of the memory
cell; the operating method comprising: performing a programming
operation by applying a first voltage to the first source/drain
region, applying a second voltage to the second source/drain
region, applying a third voltage to the first control gate,
applying a fourth voltage to the second control gate, applying a
fifth voltage to the N-type well region, wherein the third voltage
is larger than the first voltage, so that the band gap between
valance band and conduction band is used to induce a hot-electron
injection effect, by which the electrons are injected to the
floating gate where a first bit is stored.
2. The method of claim 1, wherein the first voltage is a negative
voltage and the third voltage is a positive voltage.
3. The method of claim 1, wherein the first voltage is about -5V,
the second voltage is about 0V, the third voltage is about 6V, the
fourth voltage is about 0V and the fifth voltage is about 0V.
4. The method of claim 1, further comprising performing a
programming operation by applying the first voltage to the first
source/drain region, applying the second voltage to the second
source/drain region, applying a sixth voltage to the first control
gate, applying a seventh voltage to the second control gate and
applying the fifth voltage to the N-type well region, wherein the
seventh voltage is larger than the first voltage, the first voltage
is larger than the sixth voltage, so that the channel hot-holes are
used to induce hot-electron injection effect, by which the
electrons are injected to the charge trapping layer where a second
bit is stored.
5. The method of claim 4, wherein the sixth voltage is about -12V
and the seventh voltage is about -1V.
6. The method of claim 1, further comprising performing an erasing
operation by applying an eighth voltage to the second source/drain
region, applying a ninth voltage to the first control gate,
applying a tenth voltage to the second control gate, applying a
eleventh voltage to the N-type well region and floating the first
source/drain region, wherein the ninth voltage and the tenth
voltage are less than the eleventh voltage, so that a FN tunneling
effect is used for inducing the electrons stored in the floating
gate and the electrons stored in the charge trapping structure into
the N-type well region.
7. The method of claim 6, wherein the eighth voltage is about 0V,
the ninth voltage is about -15V, the tenth voltage is about -15V
and the eleventh voltage is about 0V.
8. The method of claim 1, further comprising performing a reading
operation by applying a twelfth voltage to the first source/drain
region, applying a thirteenth voltage to the second source/drain
region, applying a fourteenth voltage to the first control gate,
applying a fifteenth voltage to the second control gate and
applying a sixteenth voltage to the N-type well region, wherein the
fifteenth voltage is less than the fourteenth voltage and the
fourteenth voltage is less than the thirteenth voltage, so as to
open a channel below the second memory unit for reading the first
bit stored in the floating gate.
9. The method of claim 8, wherein the twelfth voltage is about 0V,
the thirteenth voltage is about -1.5V, the fourteenth voltage is
about -3V, the fifteenth voltage is about -6V and the sixteenth
voltage is about 0V.
10. The method of claim 8, further comprising performing a reading
operation by applying the twelfth voltage to the first source/drain
region, applying the thirteenth voltage to the second source/drain
region, applying a seventeenth voltage to the first control gate,
applying an eighteenth voltage to the second control gate and
applying the sixteenth voltage to the N-type well region, wherein
the seventeenth voltage is less than the eighteenth voltage and the
eighteenth voltage is less than the thirteenth voltage, so as to
open a channel below the first memory unit for reading the second
bit stored in the charge trapping layer.
11. The method of claim 10, wherein the seventeenth voltage is
about -6V and the eighteenth voltage is about -3V.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of an application Ser. No.
11/306,093, filed on Dec. 15, 2005, now allowed, which claims the
priority benefit of Taiwan application serial no. 94121378, filed
on Jun. 27, 2005. The entirety of each of the above-mentioned
patent applications is hereby incorporated by reference herein and
made a part of this specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates to a semiconductor device, and
particularly to a non-volatile memory (NVM), a manufacturing method
and an operating method thereof.
[0004] 2. Description of the Related Art
[0005] Among various types of non-volatile memory products,
electrically erasable programmable read only memory (EEPROM) is a
memory device that has been widely used in personal computers and
electronic equipment. Data can be stored, read out or erased from
the EEPROM many times and stored data are retained even after power
supplying the devices is cut off.
[0006] The floating gate and the control gate in a typical EEPROM
are made of doped polysilicon. By applying bias voltages to the
control gate and a source/drain region thereof, the EEPROM
operates. When erasing data in the EEPROM however, it is likely to
over-erase, which leads to misjudgment of data. In addition, to
follow the trend of high integrity in the current semiconductor
industry, the memory size becomes smaller, with shorter channel
length. Therefore, when programming the memory cell, an abnormal
punch-through phenomenon occurs between a drain region and a source
region, which has an adverse impact on the electrical performance
of the memory.
[0007] For other non-volatile memories of the prior art, a silicon
nitride layer, instead of a polysilicon floating gate, is used to
form an ONO composite layer (oxide-nitride-oxide composite layer).
Such a device is referred to as a SONOS device
(silicon-oxide-nitride-oxide-silicon device). Since the silicon
nitride is able to capture electrons, the electrons injected in the
silicon nitride layer would not be evenly distributed in the whole
layer. Instead, the injected electrons concentrate on local regions
of the silicon nitride layer. By changing the applied voltages on
the control gate and the source/drain regions at both sides of the
control gate, at the left side and the right side of a memory in a
layer made of single silicon nitride material, 1-bit is stored,
respectively. In this way, the non-volatile memory for storing 2
bits/cell is formed.
[0008] The memory cells still face the challenge of higher
integrity of memory cell and shorter channel length. Under such
situation, the two 1-bits of a memory cell would affect each other,
so that two charge-distribution curves corresponding to the two
1-bits get broader, even merge together to generate a so-called
second bit effect. As a result, when erasing data, the distribution
curve formed by injected hot holes in the silicon nitride layer is
not able to overlap with the electron-distribution curve, which
leads to incomplete erasing and longer erasing time. This problem
results in a slow operating speed and poor efficiency, even lower
reliability.
[0009] It can be concluded that a non-volatile memory capable of
storing multiple bits in a single memory cell without the second
bit effect, over-erase and punch-through is desired in the related
semiconductor manufactures.
SUMMARY OF THE INVENTION
[0010] In view of the above described, an object of the present
invention is to provide a non-volatile memory capable of storing
multi-bit data in a single memory cell without the second bit
effect.
[0011] Another object of the present invention is to provide a
manufacturing method of the non-volatile memory suitable for
fabricating memories with simple process and without punch-through
problems.
[0012] Still another object of the present invention is to provide
an operating method with higher operation efficiency, lower applied
voltage, less power consumption and faster operation speed.
[0013] The present invention provides a non-volatile memory, which
includes at least a substrate, memory cells and source/drain
regions. The memory cell is disposed on the substrate and includes
a first memory unit and a second memory unit. Wherein, the first
memory unit, from the substrate up, includes at least a floating
gate and a first control gate. The second memory unit is disposed
on one sidewall of the first memory unit and, from the substrate
up, includes a charge trapping layer and a second control gate. The
source/drain region is disposed on the substrate at both sides of
memory cells.
[0014] According to the non-volatile memory described in the
embodiment of the present invention, the second memory unit
includes a charge trapping structure containing a charge trapping
layer. The charge trapping structure is disposed between the second
control gate and the substrate and extends between the second
control gate and the first memory unit.
[0015] According to the non-volatile memory described in the
embodiment of the present invention, the charge trapping structure,
from the substrate up, includes, for example, a tunneling
dielectric layer, a charge trapping layer and a barrier dielectric
layer. Wherein, the charge trapping layer is made of, for example,
silicon nitride.
[0016] According to the non-volatile memory described in the
embodiment of the present invention, a dielectric layer is between
the floating gate and the substrate. An inter-gate dielectric layer
is between the first control gate and the floating gate. The
inter-gate dielectric layer is made of, for example,
oxide-nitride-oxide (ONO, i.e. a composite of silicon oxide-silicon
nitride-silicon oxide).
[0017] According to the non-volatile memory described in the
embodiment of the present invention, the floating gate is made of,
for example, doped polysilicon; the first control gate and the
second control gate are made of, for example, doped
polysilicon.
[0018] The non-volatile memory of the present invention combining a
first memory unit and a second memory unit is able to avoid second
bit effect in the conventional EEPROMs and capable of storing two
bits in a single memory cell.
[0019] The present invention provides a manufacturing method of the
non-volatile memory. At first, a substrate is provided. Next, a
first memory unit is formed on the substrate, wherein the first
memory unit, from the substrate up, includes a dielectric layer, a
floating gate, an inter-gate dielectric layer and a first control
gate. Further, a charge trapping structure is formed on the
substrate and a conductive layer is then formed on the substrate.
Furthermore, the partial conductive layer is removed to form a
second control gate on a sidewall of the first memory unit. The
second control gate and the charge trapping structure together form
a second memory unit. Then, at a side of the first memory not
adjacent to the second memory unit and at a side of the second
memory unit not adjacent to the first memory unit, two doping
regions are formed, respectively.
[0020] According to the manufacturing method of the non-volatile
memory in the embodiment of the present invention, prior to the
step of forming a first memory unit, an N-type well region can be
further formed in the substrate. To match the N-type well region,
the above-mentioned two doping regions are P-type doping
regions.
[0021] According to the manufacturing method of the non-volatile
memory in the embodiment of the present invention, the
above-mentioned charge trapping structure, from the substrate up,
includes a tunneling dielectric layer, a charge trapping layer and
a barrier dielectric layer. The charge trapping layer is made of,
for example, silicon nitride.
[0022] According to the manufacturing method of the non-volatile
memory in the embodiment of the present invention, the
above-mentioned step for removing the partial conductive layer
includes, for example, the sub-steps as follows. First, the charge
trapping layer is used as an etching stop layer first to
self-aligned etch the conductive layer to form the side wall
spacers on both sides of the first memory unit. Next, a patterned
photoresist layer is formed on the substrate for covering the
conductive layer on the one sidewall of the first memory unit.
Further, the patterned photoresist layer is used as a mask to
remove the exposed part of the conductive layer. The method for
removing the exposed part of the conductive layer includes
non-isotropic etching process.
[0023] In the manufacturing method of the non-volatile memory, due
to different etching selection ratios between the charge trapping
structure and the conductive layer, the charge trapping structure
can serve as a self-alignment mask to remove the conductive layer
on the first memory unit, which simplifies the process and prevents
the memory from punch-through.
[0024] The present invention provides an operating method of P-type
channel memories. The P-type channel memory includes an N-type well
region, memory cells, a first source/drain region and a second
source/drain region. The N-type well region is disposed in the
substrate. The memory cells are disposed on the N-type well region.
Each of the memory cells includes a first memory unit and a second
memory unit disposed on a sidewall of the first memory unit. The
first memory unit, from the substrate up, includes at least a
floating gate suitable for storing a first bit and a first control
gate. The second memory unit, from the substrate up, includes at
least a charge trapping layer suitable for storing a second bit and
a second control gate. The first source/drain region and the second
source/drain region are disposed at both sides of the N-type well
region, respectively. The operating method includes following
operations.
[0025] In the programming operations, a first voltage and a second
voltage are applied to the first source/drain region and the second
source/drain region, respectively and a third voltage and a fourth
voltage are applied to the first control gate and the second
control gate, respectively. In addition, a fifth voltage is applied
to the N-type well region. Wherein, the third voltage is larger
than the first voltage, so that the band gap between valance band
and conduction band is used to induce a hot-electron injection
effect, by which the electrons are injected to the floating gate
where a first bit is stored.
[0026] According to the operating method of the non-volatile memory
in the embodiment of the present invention, the first voltage is a
negative voltage, while the third voltage is a positive voltage.
The first volt is about -5V, the second voltage is about 0V, the
third voltage is about 6V, the fourth voltage is about 0V and the
fifth voltage is about 0V.
[0027] According to the operating method of the non-volatile memory
in the embodiment of the present invention, during the
above-mentioned programming operations, the method further includes
applying the first voltage to the first source/drain region,
applying the second voltage to the second source/drain region,
applying a sixth voltage to the first control gate, applying a
seventh voltage to the second control gate and applying the fifth
voltage to the N-type well region. Wherein, the seventh voltage is
larger than the first voltage and the first voltage is larger than
the sixth voltage, so that channel hot-holes are used to induce
hot-electron injection effect, by which the electrons are injected
to the charge trapping layer where a second bit is stored.
[0028] According to the operating method of the non-volatile memory
in the embodiment of the present invention, the above-mentioned
sixth voltage is about -12V and the seventh voltage is about
-1V.
[0029] According to the operating method of the non-volatile memory
in the embodiment of the present invention, during the
above-mentioned erasing operations, an eighth voltage is applied to
the second source/drain region, a ninth voltage and a tenth voltage
are applied to the first control gate and the second control gate,
respectively, and an eleventh voltage is applied to the N-type well
region for floating the first source/drain region. Wherein, the
ninth voltage and the tenth voltage are less than the eleventh
voltage, so that a FN tunneling effect is used for inducing the
electrons stored in the floating gate and the charge trapping layer
into the N-type well region.
[0030] According to the operating method of the non-volatile memory
in the embodiment of the present invention, the above-mentioned
eighth voltage is about 0V, the ninth voltage is about -15V, the
tenth voltage is about -15V, and the eleventh voltage is about
0V.
[0031] According to the operating method of the non-volatile memory
in the embodiment of the present invention, during the
above-mentioned reading operations, a twelfth voltage and a
thirteenth voltage are applied to the first source/drain region and
the second source/drain region, respectively, a fourteenth voltage
and a fifteenth voltage are applied to the first control gate and
the second control gate, respectively and a sixteenth voltage is
applied to the N-type well region. Wherein, the fifteenth voltage
is less than the fourteenth voltage, the fourteenth voltage is less
than the thirteenth voltage, so as to open a channel below the
second memory unit for reading the first bit in the floating
gate.
[0032] According to the operating method of the non-volatile memory
in the embodiment of the present invention, the above-mentioned
twelfth voltage is about 0V, the thirteenth voltage is about -1.5V,
the fourteenth voltage is about -3V, the fifteenth voltage is about
-6V and the sixteenth voltage is about 0V.
[0033] According to the operating method of the non-volatile memory
in the embodiment of the present invention, during the
above-mentioned reading operations, the method further includes,
applying the twelfth voltage and the thirteenth voltage to the
first source/drain region and the second source/drain region,
respectively, applying a seventeenth voltage and an eighteenth
voltage to the first control gate and the second control gate,
respectively and applying the sixteenth voltage to the N-type well
region. Wherein, the seventeenth voltage is less than the
eighteenth voltage and the eighteenth voltage is less than the
thirteenth voltage, so as to open a channel below the first memory
unit for reading the second bit in the charge trapping layer.
[0034] According to the operating method of the non-volatile memory
in the embodiment of the present invention, the above-mentioned
seventeenth voltage is about -6V and the eighteenth voltage is
about -3V.
[0035] In the operating method of the non-volatile memory, the
adopted operation mode for programming and erasing has a higher
efficiency and is capable of injecting and pulling out the
electrons more quickly. Therefore, the operation voltage on the
memory is reduced, the power consumption is lowered and the device
operation speed is advanced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve for explaining the principles of the invention.
[0037] FIG. 1 is a schematic structural cross-sectional view of a
non-volatile memory in an embodiment of the present invention.
[0038] FIG. 2A through FIG. 2E are schematic cross-sectional views
showing a flowchart of fabricating a non-volatile memory in an
embodiment of the present invention.
[0039] FIG. 3A is a diagram illustrating the programming operation
of a left bit in a P-type channel memory.
[0040] FIG. 3B is a diagram illustrating the programming operation
of a right bit in a P-type channel memory.
[0041] FIG. 3C is a diagram illustrating the reading operation of a
left bit in a P-type channel memory.
[0042] FIG. 3D is a diagram illustrating the reading operation of a
right bit in a P-type channel memory.
[0043] FIG. 3E is a diagram illustrating the erasing operation of a
P-type channel memory.
DESCRIPTION OF THE EMBODIMENTS
[0044] FIG. 1 is a schematic structural cross-sectional view of a
non-volatile memory in an embodiment of the present invention.
[0045] Referring to FIG. 1, the non-volatile memory includes at
least a substrate 100, memory cells 110 and source/drain regions
120a and 120b. The memory cell 110 is disposed on the substrate 100
and includes at least a memory unit 130 and another memory unit
140. Wherein, the memory unit 130, from the substrate 100 up,
includes at least a tunneling dielectric layer 131, a floating gate
133, an inter-gate dielectric layer 135 and a control gate 137. The
memory unit 140 is disposed on a sidewall of the memory unit 130.
The memory unit 140 includes, for example, a control gate 143 and a
charge trapping structure 141. The control gate 143 is disposed on
a sidewall of the memory unit 130 and the charge trapping structure
141 is disposed between the control gate 143 and the memory unit
130, and between the control gate 143 and the substrate 100. The
source/drain regions 120a and 120b are disposed in the substrate at
both sides of the memory cell 110.
[0046] The substrate 100 is, for example, a P-type substrate,
wherein an N-type well region 103 is further disposed and together
with the P-type doped source/drain regions 120a and 120b forms a
P-type channel non-volatile memory.
[0047] The tunneling dielectric layer 131 in the memory unit 130 is
made of, for example, silicon oxide. The floating gate 133 is made
of, for example, doped polysilicon or other conductive materials.
The control gate 137 is made of, for example, doped polysilicon,
metal, metal silicide, or other conductive materials. Wherein, the
inter-gate dielectric layer 135 can be a composite dielectric layer
including, from down to up, a silicon oxide layer 135a, a silicon
nitride layer 135b and a silicon oxide layer 135c. Certainly, the
inter-gate dielectric layer 135 can only include the silicon oxide
layer 135a and the silicon nitride layer 135b, even only include
the single silicon oxide layer 135a. That is, as long as the
material of the inter-gate dielectric layer 135 is a proper
dielectric material capable of preventing the electrons stored in
the floating gate 133 from entering the control gate 137, it is
proper. The floating gate 133 of the memory unit 130 is used for
storing charges and saving 1-bit data.
[0048] The control gate 143 of the memory unit 140 is made of, for
example, doped polysilicon, metal, metal silicide, or other
conductive materials. The charge trapping structure 141 in the
memory unit 140, from the substrate up, includes, for example, a
tunneling dielectric layer 141a, a charge trapping layer 141b and a
barrier dielectric layer 141c. The tunneling dielectric layer 141a
is made of, for example, silicon oxide. The charge trapping layer
141b is made of, for example, silicon nitride. The barrier
dielectric layer 141c is made of, for example, silicon oxide.
Alternatively, the tunneling dielectric layer 141a and the barrier
dielectric layer 141c can be made of other similar materials. While
the charge trapping layer 141b can be made of other materials
capable of trapping charges hereinto, such as tantalum oxide
(Ta.sub.2O.sub.5), strontium titanate (SrTiO.sub.3), hafnium oxide
(HfO.sub.2), and so on, not limited to the above-mentioned silicon
nitride. The charge trapping layer 141b has the characteristic of
trapping charges hereinto, so that the memory unit 140 in the
memory cell 110 can be used for storing 1-bit data as well.
[0049] In the non-volatile memory, the memory unit 130 and the
memory 140 are connected in series to each other and any one of the
memory units can be used for selecting the gate. By opening or
closing a channel under the chosen memory unit, the punch through
problem in a conventional EEPROM can be solved. Besides, the memory
unit 130 and the memory unit 140 can store 1-bit data,
respectively, such that the non-volatile memory of the present
invention is the 2 bits/cell structure. Furthermore, different from
the silicon nitride ROM (read-only memory) having a conventional 2
bits/cell structure, in the present invention, two bits are stored
in two different structures, respectively. Hence, the second bit
effect would not occur, which leads to enhanced efficiency and
higher reliability.
[0050] For the manufacturing method of the non-volatile memory,
please refer to FIGS. 2A-2E, schematic cross-sectional views
showing a flowchart of fabricating a non-volatile memory in an
embodiment of the present invention.
[0051] Referring to FIG. 2A, first, a substrate 100 is provided and
the substrate 100 is, for example, a P-type substrate. Next, an
isolation structure (not shown) is formed on the substrate 100.
After that, an N-type well region 103 is formed on the substrate
100. The method for forming the N-type well region 103 is, for
example, by doping N-type dopant into the substrate 100 in a dopant
diffusion process or dopant implanting process.
[0052] Further, on the substrate 100, a dielectric material layer
131', a conductive material layer 133', a dielectric material layer
135' and a conductive material layer 137' are formed sequentially.
The dielectric material layer 131' is made of, for example, silicon
oxide and formed, for example, in a thermal oxidizing process. The
conductive material layer 133' is made of, for example, doped
polysilicon and formed, for example, in a chemical vapor deposition
(CVD) process. Since the conductive material layer 133' is used as
the floating gate 133 afterwards, after forming the conductive
material layer 133', a patterning step is performed, then the
dielectric material layer 135' and the conductive material layer
137' are formed.
[0053] The conductive material layer 137' is made of, for example,
doped polysilicon and formed in a chemical vapor deposition (CVD)
process. Certainly, the conductive material layers 133' and 137'
can also be made of metal, metal silicide or other proper
conductive materials and are formed, for example, in a physical
vapor deposition (PVD) process. The dielectric material layer 135',
from the bottom to the top, includes, for example, a silicon oxide
layer 135a', a silicon nitride layer 135b' and a silicon oxide
layer 135c'. The silicon oxide layers 135a' and 135c' are formed,
for example, in a chemical vapor deposition (CVD) process, and the
silicon nitride layer 135b' is also formed, for example, in a
chemical vapor deposition (CVD) process. The dielectric material
layer 135' in the embodiment is made of composite dielectric layer
for an explanatory purpose only. Since the dielectric material
layer 135' is as an intermediate layer for forming an inter-gate
dielectric layer 135 in the following step, the dielectric material
layer 135' can also be other proper dielectric materials, such as
silicon oxide or oxide-nitride, depending on design
requirements.
[0054] Furthermore, referring to FIG. 2B, the dielectric material
layer 131', the conductive material layer 133', the dielectric
material layer 135' and the conductive material layer 137' are
patterned to form the memory unit 130. The method for patterning
the above-mentioned layers is described, for example, as follows.
On the conductive material layer 137', a patterned photoresist
layer is formed (not shown). Taking the patterned photoresist layer
as a mask, a non-isotropic etching process is performed, so that a
control gate 137, an inter-gate dielectric layer 135 (a silicon
oxide layer 135c, a silicon nitride layer 135b and a silicon oxide
layer 135a), a floating gate 133 and a tunneling dielectric layer
131 are defined. Wherein, after conducting two lithography etching
processes, the conductive material layer 133' becomes a block-like
floating gate 133. The floating gate 133 in the memory unit 130
serves for storing charges.
[0055] Then, referring to FIG. 2C, a charge trapping structure 141
is formed on the memory unit 130. The charge trapping structure
141, from the substrate 100 up, includes, for example, a tunneling
dielectric layer 141a, a charge trapping layer 141b and a barrier
dielectric layer 141c. The tunneling dielectric layer 141a is made
of, for example, silicon oxide and formed, for example, in a
chemical vapor deposition (CVD) process. The charge trapping layer
141b is made of, for example, silicon nitride and formed, for
example, in a chemical vapor deposition (CVD) process. The barrier
dielectric layer 141c is made of, for example, silicon oxide and
formed, for example, in a chemical vapor deposition (CVD) process.
In addition, the tunneling dielectric layer 141a and the barrier
dielectric layer 141c can be made of other similar materials. The
charge trapping layer 141b is made of, but not limited to, silicon
nitride and can be other materials capable of trapping charges
hereinto, such as tantalum oxide (Ta2O5), strontium titanate
(SrTiO3) or hafnium oxide (HfO2).
[0056] Afterwards, referring to FIG. 2D, a conductive material
layer 143' is formed on the substrate 100. The conductive material
layer 143' is made of, for example, doped polysilicon. To form the
conductive material layer 143', for example, an undoped polysilicon
layer is formed in a chemical vapor deposition (CVD) process,
followed by an ion implanting process. Alternatively, the
conductive material layer can be formed in an in-situ doped method
and chemical vapor deposition (CVD) process. The conductive
material layer 143' can be made of other proper conductive
materials, such as metal as well, and formed in other different
methods, depending on the materials. Then, the charge trapping
layer 141 is used as an etching stop layer first to self-aligned
etch the conductive material layer 143' to form the side wall
spacers on both sides of the memory unit 130. Since the charge
trapping structure 141 has an etching selection ratio different
from that of the conductive material layer 143', the charge
trapping structure 141 can be taken as an etching stop layer for
etching the conductive material layer 143'.
[0057] Thereafter, referring to FIG. 2E, the conductive material
layer 143' is patterned to form a control gate 143 on a sidewall of
the memory unit 130. To pattern the conductive material layer 143',
for example, a patterned photoresist layer (not shown) is formed on
the conductive material layer 143', and the patterned photoresist
layer covers the partial conductive material layer 143' disposed on
a sidewall of the memory unit 130 and the charge trapping structure
141. Then, taking the patterned photoresist layer as a mask, a
non-isotropic etching process is conducted, so that the partial
conductive material layer 143' disposed on another sidewall of the
memory unit 130 is removed. During the etching, the partial charge
trapping structure 141 disposed on the other sidewall is removed.
The control gate 143 and the charge trapping structure 141 form a
memory unit 140, and a charge trapping layer 141b included in the
memory unit 140 serves for storing charges. Further, the memory
unit 130 and the memory unit 140 form a memory cell 110.
Afterwards, two source/drain regions 120a and 120b are formed at
both sides of the memory cell 110, respectively. The dopant in the
source/drain regions 120a and 120b is, for example, P-type dopant.
The source/drain regions 120a and 120b are formed, for example, in
a dopant implanting process. The formed non-volatile memory is a
P-type channel memory.
[0058] According to the manufacturing method of the non-volatile
memory, due to different etching selection ratios of the charge
trapping structure 141 and the conductive material layer 143', the
charge trapping structure 141 can be used as a self-alignment mask
for removing the conductive material layer 143' on the memory unit
130, which results in an increasing process window. In addition,
the process has simple steps, and a 2 bits/cell structure can be
formed by combing the memory unit 130 and the memory unit 140
together. Therefore, the process has considerable value in the
semiconductor industry.
[0059] An operating method of the non-volatile memory according to
the present invention is further described hereafter. Referring to
FIGS. 3A-3E, FIG. 3A is a diagram illustrating the programming
operation of a left bit in a P-type channel memory; FIG. 3B is a
diagram illustrating the programming operation of a right bit in a
P-type channel memory; FIG. 3C is a diagram illustrating the
reading operation of a left bit in a P-type channel memory; FIG. 3D
is a diagram illustrating the reading operation of a right bit in a
P-type channel memory; and FIG. 3E is a diagram illustrating the
erasing operation of a P-type channel memory.
[0060] Referring to FIG. 3A, during a programming operation, a
voltage V.sub.P1, for example, about -5V is applied to the
source/drain region 120a, a voltage V.sub.P2, for example, about 0V
is applied to the source/drain region 120b, a voltage V.sub.PG1,
for example, about 6V is applied to the control gate 137, a voltage
V.sub.PC1, for example, about 0V is applied to the control gate 143
and a voltage V.sub.NW, for example, about 0V is applied to the
N-type well region 103. Wherein, the voltage V.sub.PC1 of the
control gate 137 is larger than the voltage V.sub.P1 of the
source/drain region 120a and the voltage V.sub.P2 of the
source/drain region 120b is larger than the voltage V.sub.P1 of the
source/drain region 120a, so that the band gap between valance band
and conduction band is used to induce a hot-electron injection
effect, by which the electrons are injected to the floating gate
133 of the memory unit 130 where a left bit is stored.
[0061] Referring to FIG. 3B, also during a programming operation, a
voltage V.sub.P1, for example, about -5V is applied to the
source/drain region 120a, a voltage V.sub.P2, for example, about 0V
is applied to the source/drain region 120b, a voltage V.sub.PG2,
for example, about -12V is applied to the control gate 137, a
voltage V.sub.PC2, for example, about -1V is applied to the control
gate 143 and a voltage V.sub.NW, for example, about 0V is applied
to the N-type well region 103. Wherein, the voltage V.sub.PC2 of
the control gate 143 is larger than the voltage V.sub.P1 of the
source/drain region 120a, the voltage V.sub.P1 of the source/drain
region 120a is larger than the voltage V.sub.PG2 of the control
gate 137 and the voltage V.sub.P2 of the source/drain region 120b
is larger than the voltage V.sub.P1 of the source/drain region
120a, so that the channel hot-holes are used to induce hot-electron
injection effect, by which the electrons are injected to the charge
trapping layer 141 of the memory unit 140 where a right bit is
stored.
[0062] Referring to FIG. 3C, during a reading operation, a voltage
V.sub.R1, for example, about 0V is applied to the source/drain
region 120a, a voltage V.sub.R2, for example, about -1.5V is
applied to the source/drain region 120b, a voltage V.sub.RG1, for
example, about -3V is applied to the control gate 137, a voltage
V.sub.RC1, for example, about -6V is applied to the control gate
143 and a voltage V.sub.NW, for example, about 0V is applied to the
N-type well region 103. Wherein, the voltage V.sub.RC1 of the
control gate 143 is less than the voltage V.sub.RG1 of the control
gate 137, the voltage V.sub.RG1 of the control gate 137 is less
than the voltage V.sub.R2 of the source/drain region 120b and the
voltage V.sub.R2 of the source/drain region 120b is less than the
voltage V.sub.R1 of the source/drain region 120a, so that a channel
below the memory unit 140 is opened for reading the left bit in the
memory unit 130.
[0063] Referring to FIG. 3D, also during a reading operation, a
voltage V.sub.R1, for example, about 0V is applied to the
source/drain region 120a, a voltage V.sub.R2, for example, about
-1.5V is applied to the source/drain region 120b, a voltage
V.sub.RG2, for example, about -6V is applied to the control gate
137, a voltage V.sub.RC2, for example, about -3V is applied to the
control gate 143 and a voltage V.sub.NW, for example, about 0V is
applied to the N-type well region 103. Wherein, the voltage
V.sub.RG2 of the control gate 137 is less than the voltage
V.sub.RC2 of the control gate 143, the voltage V.sub.RC2 of the
control gate 143 is less than the voltage V.sub.R2 of the
source/drain region 120b and the voltage V.sub.R2 of the
source/drain region 120b is less than the voltage V.sub.R1 of the
source/drain region 120a, so that a channel below the memory unit
130 is opened for reading the right bit in the memory unit 140.
[0064] Referring to FIG. 3E, during an erasing operation, a voltage
V.sub.E2, for example, about 0V is applied to the source/drain
region 120b, a voltage V.sub.EG, for example, about -15V is applied
to the control gate 137, a voltage V.sub.EC, for example, about
-15V is applied to the control gate 143 and a voltage V.sub.NW, for
example, about 0V is applied to the N-type well region 103.
Wherein, both the voltage V.sub.EG of the control gate 137 and the
voltage V.sub.EC of the control gate 143 are less than the voltage
V.sub.NW of the N-type well region 103, so that a FN tunneling
effect is used for inducing the electrons stored in the floating
gate 133 of the memory unit 130 and the electrons stored in the
charge trapping structure 141 of the memory unit 149 into the
N-type well region 103. Thus, the left bit and the right bit
previously stored in the memory unit 130 and the memory unit 140
respectively are erased.
[0065] According to the operating method of the non-volatile memory
in the present invention, the band gap between valance band and
conduction band is used to induce a hot-electron injection effect,
by which the electrons are injected to the floating gate 133 of the
memory unit 130; the channel hot-holes are used to induce
hot-electron injection effect, by which the electrons are injected
to the charge trapping layer 141 of the memory unit 140. These
electron injection mechanisms feature a high efficiency, a faster
speed to operate the non-volatile memory, a lower voltage required
and power consumption.
[0066] From the above described, in the non-volatile memory of the
present invention, two memory units are connected in series to each
other, which not only enables a single memory cell to store 2-bits
data, but also avoids the second bit effect problems in the prior
art. In addition, the provided operating mode of the non-volatile
memory features high efficiency, lower voltage required by
programming operation on the memories, reduced power consumption
and enhanced speed to operate the device. Therefore, the invention
has a great value in the semiconductor industry.
[0067] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
specification and examples to be considered as exemplary only, with
a true scope and spirit of the invention being indicated by the
following claims and their equivalents.
* * * * *