U.S. patent application number 11/962126 was filed with the patent office on 2008-06-12 for manufacturing method of semiconductor device.
This patent application is currently assigned to EMEMORY TECHNOLOGY INC.. Invention is credited to Hsin-Ming Chen, Ming-Chou Ho, Ching-Hsiang Hsu, Chun-Hung Lu, Shih-Jye Shen, Shih-Chen Wang.
Application Number | 20080138956 11/962126 |
Document ID | / |
Family ID | 38204834 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080138956 |
Kind Code |
A1 |
Wang; Shih-Chen ; et
al. |
June 12, 2008 |
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Abstract
A semiconductor device formed on a first conductive type
substrate is provided. The device includes a gate, a second
conductive type drain region, a second conductive type source
region, and a second conductive type first lightly doped region.
The gate is formed on the first conductive type substrate. The
second conductive type drain region and the second conductive type
source region are formed in the first conductive type substrate at
both sides of the gate. The second conductive type first lightly
doped region is formed in the first conductive type substrate
between the gate and the second conductive type source region.
Inventors: |
Wang; Shih-Chen; (Taipei
City, TW) ; Chen; Hsin-Ming; (Tainan County, TW)
; Lu; Chun-Hung; (Yunlin, TW) ; Ho; Ming-Chou;
(Hsinchu City, TW) ; Shen; Shih-Jye; (Hsinchu,
TW) ; Hsu; Ching-Hsiang; (Hsinchu City, TW) |
Correspondence
Address: |
JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
7 FLOOR-1, NO. 100, ROOSEVELT ROAD, SECTION 2
TAIPEI
100
omitted
|
Assignee: |
EMEMORY TECHNOLOGY INC.
Hsin-Chu
TW
|
Family ID: |
38204834 |
Appl. No.: |
11/962126 |
Filed: |
December 21, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11557112 |
Nov 7, 2006 |
|
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11962126 |
|
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|
|
60597210 |
Nov 17, 2005 |
|
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60743630 |
Mar 22, 2006 |
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Current U.S.
Class: |
438/305 ;
257/E21.427; 257/E21.433; 257/E29.133; 257/E29.268 |
Current CPC
Class: |
H01L 27/115 20130101;
G11C 16/0466 20130101; H01L 29/40117 20190801; H01L 29/7923
20130101; H01L 29/792 20130101; H01L 27/11568 20130101; H01L
29/6656 20130101; H01L 29/7887 20130101; H01L 27/11521 20130101;
H01L 29/4234 20130101; H01L 29/42324 20130101; G11C 16/0475
20130101; H01L 29/66833 20130101; H01L 29/66659 20130101; H01L
27/105 20130101; H01L 29/40114 20190801; H01L 29/66825 20130101;
G11C 16/0425 20130101; H01L 29/7835 20130101; H01L 29/513 20130101;
H01L 29/42368 20130101 |
Class at
Publication: |
438/305 ;
257/E21.433 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A method of fabricating a semiconductor device, comprising:
providing a first conductive type substrate; forming a gate on the
first conductive type substrate; forming a second conductive type
first lightly doped region in the substrate at a first side of the
gate; and forming a second conductive type source region in the
substrate at the first side of the gate, and forming a second
conductive type drain region at a second side of the gate, wherein
the second conductive type first lightly doped region is formed in
the first conductive type substrate between the second conductive
type source region and the gate.
2. The method of fabricating the semiconductor device of claim 1,
wherein the first conductive type is a P-type while the second
conductive type is an N-type; or the first conductive type is an
N-type while the second conductive type is a P-type.
3. The method of fabricating the semiconductor device of claim 1,
further comprising forming a first dielectric layer on the first
conductive type substrate before the step of forming the gate on
the first conductive type substrate.
4. The method of fabricating the semiconductor device of claim 3,
wherein the first dielectric layer has a first thickness at the
first side and a second thickness at the second side, and the
second thickness is larger than the first thickness.
5. The method of fabricating the semiconductor device of claim 1,
wherein the steps of forming the second conductive type first
lightly doped region in the first conductive type substrate at the
first side of the gate comprise: forming a patterned photoresist
layer exposing the first conductive type substrate at the first
side of the gate on the substrate; performing an ion implantation
process to form the second conductive type first lightly doped
region; and removing the patterned photoresist layer.
6. The method of fabricating the semiconductor device of claim 1,
further comprising forming a first conductive type lightly doped
region in the substrate at the second side of the gate, wherein the
first conductive type lightly doped region is formed between the
second conductive type drain region and the gate.
7. The method of fabricating the semiconductor device of claim 6,
wherein the steps of forming the second conductive type first
lightly doped region in the first conductive type substrate at the
first side of the gate and forming the first conductive type
lightly doped region in the substrate at the second side of the
gate comprise: forming a first patterned photoresist layer exposing
the first conductive type substrate at the first side of the gate
on the substrate; performing a first ion implantation process to
form the second conductive type first lightly doped region;
removing the first patterned photoresist layer; forming a second
patterned photoresist layer exposing the first conductive type
substrate at the second side of the gate on the substrate;
performing a second ion implantation process to form the first
conductive type lightly doped region; and removing the second
patterned photoresist layer.
8. The method of fabricating the semiconductor device of claim 6,
further comprising: forming a second conductive type second lightly
doped region in the substrate at the second side of the gate,
wherein the second conductive type second lightly doped region is
formed between the second conductive type drain region and the
gate.
9. The method of fabricating the semiconductor device of claim 8,
wherein the steps of forming the second conductive type first
lightly doped region and the second conductive type second lightly
doped region in the first conductive type substrate at the first
side and the second side of the gate and forming the first
conductive type lightly doped region in the substrate at the second
side of the gate comprise: performing a first ion implantation
process to form the second conductive type first lightly doped
region and the second conductive type second lightly doped region;
forming a patterned photoresist layer exposing the first conductive
type substrate at the second side of the gate on the substrate;
performing a second ion implantation process to form the first
conductive type lightly doped region; and removing the patterned
photoresist layer.
10. The method of fabricating the semiconductor device of claim 1,
further comprising forming insulating spacers at the side walls of
the gate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of an application Ser. No.
11/557,112, filed on Nov. 7, 2006, now pending, which claims the
priority benefit of U.S. provisional applications Ser. No.
60/597,210, filed on Nov. 17, 2005 and 60/743,630, filed on Mar.
22, 2006. The entirety of each of the above-mentioned patent
applications are hereby incorporated by reference herein and made a
part of this specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to a manufacturing method of a
semiconductor device, and more particularly to a manufacturing
method of a semiconductor device which raises the limit of
high-voltage stress.
[0004] 2. Description of Related Art
[0005] A Metal Oxide Semiconductor (MOS) transistor device is one
of the most important and fundamental electronic units among
various electronic products. Since the invention of MOS transistor
devices, people are constantly aiming for reducing the size of
semiconductors; namely, more semiconductor devices are squeezed in
a specific area so as to enhance and accelerate the performance of
computation.
[0006] As the level of integration of integrated circuits
increases, the dimensions of semiconductor devices decrease
correspondingly. Accordingly, as the dimension of a Metal Oxide
Semiconductor (MOS) transistor is reduced, the channel length also
reduces. However, the dimension of the channel of a MOS transistor
cannot be unlimitedly reduced. As the channel length of a
semiconductor device reduces to a certain degree, various problems
gradually emerge, which are generally so-called "short channel
effects". More specifically, when the channel length is decreased
and the voltage applied remains unchanged, not only the operation
speed of the transistor but also the lateral electric field in the
channel is increased. Thereby, the energy of the channel electrons
is increased, especially for the channel electrons near the drain
region. The energy of these electrons is greater than the band gap
of the semiconductor. Therefore, after colliding with valence-band
electrons near the drain region, the channel electrons easily
excite the valence-band electrons thereat to the conductive band
and hot electrons are then formed. Parts of the hot electrons enter
a gate oxide layer and cause damages, so that the reliability and
the lifetime of the device are reduced. Especially when the
dimension of a MOS transistor device is further reduced to a
nanometer scale, the short channel effect and the punch through
effect would become more serious, and a further size reduction of
the semiconductor device is then hindered. Therefore, it is a
common objective in the industry to produce a semiconductor device
with small size, high integration, and high quality.
SUMMARY OF THE INVENTION
[0007] This invention is to provide a semiconductor device and the
method of fabricating the same. The semiconductor device has a
simple structure and a high breakdown voltage so as to raise the
limit of high-voltage stress and to be operated under high
voltage.
[0008] This invention provides a semiconductor device, including a
gate, a second conductive type drain region, a second conductive
type source region, and a second conductive type first lightly
doped region. The gate is formed on a first conductive type
substrate. The second conductive type drain region and the second
conductive type source region are formed in the first conductive
type substrate at both sides of the gate. The second conductive
type first lightly doped region is formed between the gate and the
second conductive type source region.
[0009] According to an embodiment of the present invention, the
first conductive type is a P-type while a second conductive type is
an N-type. Conversely, the second conductive type is a P-type while
the first conductive type is an N-type.
[0010] According to an embodiment of the present invention, the
semiconductor device further includes a first dielectric layer. The
first dielectric layer is formed between the gate and the first
conductive type substrate, wherein the first dielectric layer has a
first thickness at a side of the second conductive type source
region and a second thickness at a side of the second conductive
type drain region. The first thickness is larger than the
second.
[0011] According to an embodiment of the present invention, the
semiconductor device further includes a first conductive type
lightly doped region. The first conductive type lightly doped
region is formed between the gate and the second conductive type
drain region.
[0012] According to an embodiment of the present invention, the
semiconductor device further includes a second conductive type
second lightly doped region. The second conductive type second
lightly doped region is formed between the gate and the second
conductive type drain region. The second conductive type first
lightly doped region contains a different dopant concentration from
the second conductive type second lightly doped region.
[0013] According to an embodiment of the present invention, the
semiconductor device further includes insulating spacers. The
insulating spacers are formed on the side walls of the gate.
[0014] According to an embodiment of the present invention, the
material of the insulating spacers includes silicon nitride or
silicon oxide.
[0015] Inasmuch as a lightly doped region having a same conductive
type as the source region is formed between the source region and
the gate, but no lightly doped region is formed between the drain
region and the gate. Even forming a neutral substrate at the sides
of the drain region or forming a lightly doped region with an
opposite conductive type to the drain region at the sides of the
drain region are two other alternatives for the semiconductor
device of the present invention.
[0016] Thus, a high breakdown voltage is then provided to raise the
limit of high-voltage stress of the MOS device and to operate the
semiconductor device of the present invention under a high
voltage.
[0017] The invention provides a method for fabricating a
semiconductor device. The fabricating process is described below.
First, a first conductive type substrate is provided, and a gate is
formed on the first conductive type substrate. Then, a second
conductive type first lightly doped region is formed in the
substrate at a first side of the gate. Thereafter, a second
conductive type source region is formed in the substrate at the
first side of the gate, and a second conductive type drain region
is formed at a second side of the gate, wherein the second
conductive type first lightly doped region is formed in the first
conductive type substrate between the second conductive type source
region and the gate.
[0018] According to an embodiment of the present invention, the
first conductive type is a P-type while a second conductive type is
an N-type. Conversely, the first conductive type is an N-type while
the second conductive type is a P-type.
[0019] According to an embodiment of the present invention, the
method further includes a step of forming a first dielectric layer
on the first conductive type substrate before the step of forming
the gate on the first conductive type substrate.
[0020] According to an embodiment of the present invention, the
first dielectric layer has a first thickness at a first side and a
second thickness at a second side. The second thickness is larger
than the first.
[0021] According to an embodiment of the present invention, the
steps of forming the second conductive type first lightly doped
region in the first conductive type substrate at the first side of
the gate are provided as following. First, a patterned photoresist
layer exposing the first conductive type substrate at the first
side of the gate is formed on the substrate. An ion implantation
process is then performed to form the second conductive type first
lightly doped region. Afterward, the patterned photoresist layer is
removed.
[0022] According to an embodiment of the present invention, the
method further includes a step of forming a first conductive type
lightly doped region in the substrate at the second side of the
gate. The first conductive type lightly doped region is formed
between the second conductive type drain region and the gate.
[0023] According to an embodiment of the present invention, the
steps of forming the second conductive type first lightly doped
region in the first conductive type substrate at the first side of
the gate, and forming the first conductive type lightly doped
region in the substrate at the second side of the gate are provided
as following. First, a first patterned photoresist layer exposing
the first conductive type substrate at the first side of the gate
is formed on the substrate. A first ion implantation process is
then performed to form the second conductive type first lightly
doped region. After the first patterned photoresist layer is
removed, a second patterned photoresist layer exposing the first
conductive type substrate at the second side of the gate is formed
on the substrate. A second ion implantation process is then
performed to form the first conductive type lightly doped region,
and the second patterned photoresist layer is removed.
[0024] According to an embodiment of the present invention, the
method further includes forming a second conductive type second
lightly doped region in the substrate at the second side of the
gate. The second conductive type second lightly doped region is
formed between the second conductive type drain region and the
gate.
[0025] According to an embodiment of the present invention, the
steps of forming the second conductive type first lightly doped
region and the second conductive type second lightly doped region
in the first conductive type substrate at the first and the second
sides of the gate, and forming the first conductive type lightly
doped region in the substrate at the second side of the gate are
provided as following. First, a first ion implantation process is
performed to form the second conductive type first lightly doped
region and the second conductive type second lightly doped region.
A patterned photoresist layer exposing the first conductive type
substrate at the second side of the gate is then formed on the
substrate. After a second ion implantation process is performed to
form the first conductive type lightly doped region, the patterned
photoresist layer is removed.
[0026] According to an embodiment of the present invention, the
method further includes forming insulating spaces at the side walls
of the gate.
[0027] The method of fabricating the semiconductor device of the
present invention has a simple fabricating process which can be
integrated with the fabricating process of a conventional
Complementary Metal Oxide Semiconductor (CMOS) so as to reduce the
time of fabricating the device. Various specific embodiments of the
present invention are disclosed below, illustrating examples of
various possible implementations of the concepts of the present
invention. The following description is made for the purpose of
illustrating the general principles of the invention and should not
be taken in a limiting sense. The scope of the invention is best
determined by reference to the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIG. 1A is a schematic cross-sectional view showing a
preferred embodiment of the semiconductor device of the present
invention.
[0029] FIG. 1B is a schematic cross-sectional view showing a
preferred embodiment of the semiconductor device of the present
invention.
[0030] FIG. 1C is a schematic cross-sectional view showing another
preferred embodiment of the semiconductor device of the present
invention.
[0031] FIG. 1D is a schematic cross-sectional view showing yet
another preferred embodiment of the semiconductor device of the
present invention.
[0032] FIGS. 2A through 2E are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to a preferred embodiment of the present invention.
[0033] FIGS. 3A through 3B are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to a preferred embodiment of the present invention.
[0034] FIGS. 4A through 4C are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to another preferred embodiment of the present invention.
[0035] FIGS. 5A through 5D are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to a preferred embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0036] FIG. 1A is a schematic cross-sectional view showing a
preferred embodiment of the semiconductor device of the present
invention.
[0037] Please refer to FIG. 1A. The semiconductor device of the
present invention is, for example, formed on a first conductive
type substrate 100. The first conductive type substrate 100 is a
silicon substrate, for example. The semiconductor device includes a
gate dielectric layer 102, a gate 104, a dielectric layer 106,
insulating spacers 108, a second conductive type source region 110,
a second conductive type drain region 112, and a second conductive
type lightly doped region 114, for example.
[0038] The gate 104 is, for example, formed on the first conductive
type substrate 100. The material of the gate 104 is, for example,
doped polysilicon.
[0039] The gate dielectric layer 102 is, for example, formed
between the gate 104 and the first conductive type substrate 100.
The material of the gate dielectric layer 102 is, for example,
silicon oxide.
[0040] The second conductive type source region 110 and the second
conductive type drain region 112 are formed in the first conductive
type substrate 100 at both sides of the gate 104, for example.
[0041] The insulating spacers 108 are, for example, formed on the
side walls of the gate 104. The material of the insulating spacers
108 is silicon oxide or silicon nitride, for example.
[0042] The second conductive type lightly doped region 114 is, for
example, formed in the first conductive type substrate 100 between
the gate 104 and the second conductive type source region 110.
Namely, it is positioned under the insulating spacers 108.
[0043] In the above-mentioned embodiment, if the first conductive
type is a P-type and the second conductive type is an N-type, the
semiconductor device is an N-channel semiconductor device. On the
other hand, if the first conductive type is an N-type and the
second conductive type is a P-type, the semiconductor device is
then a P-channel semiconductor device.
[0044] According to the semiconductor device of the present
invention, inasmuch as the second conductive type lightly doped
region is not formed at the sides of the second conductive type
drain region 112, the limit of high-voltage stress of the MOS
device can be raised, so that the semiconductor device of the
present invention can be operated under a high voltage.
[0045] FIG. 1B is a schematic cross-sectional view showing another
preferred embodiment of the semiconductor device of the present
invention. In FIG. 1B, the same reference numbers are used to refer
to the same parts in FIG. 1A. Here, only the differences are
described.
[0046] Please refer to FIG. 1B. The semiconductor device includes a
first conductive type lightly doped region 116 formed at the sides
of the second conductive type drain region 112. The first
conductive type lightly doped region 116 is, for example, formed in
the first conductive type substrate 100 between the gate 104 and
the second conductive type drain region 112. Namely, it is
positioned under the insulating spacers 108.
[0047] According to the semiconductor device shown in FIG. 1B,
inasmuch as a lightly doped region with an opposite conductive type
to the source/drain region is formed at the sides of the drain
region, thereby the limit of high-voltage stress of the MOS device
can be raised, so that the semiconductor device of the present
invention can be operated under a high voltage.
[0048] FIG. 1C is a schematic cross-sectional view showing yet
another preferred embodiment of the semiconductor device of the
present invention. In FIG. 1C, the same reference numbers are used
to refer to the same parts in FIG. 1A. Here, only the differences
are described.
[0049] Please refer to FIG. 1C. The semiconductor device includes
the first conductive type lightly doped region 116 and a second
conductive type lightly doped region 114a formed at the sides of
the second conductive type drain region 112. The first conductive
type lightly doped region 116 is, for example, formed in the first
conductive type substrate 100 between the gate 104 and the second
conductive type drain region 112. Namely, it is positioned under
the insulating spacers 108. The second conductive type lightly
doped region 114a is, for example, formed in the first conductive
type substrate 100 between the gate 104 and the second conductive
type drain region 112. Namely, it is positioned under the
insulating spacers 108.
[0050] According to the semiconductor device shown in FIG. 1C,
inasmuch as a second conductive type lightly doped region 114a and
the first conductive type lightly doped region 116 are formed at
the sides of the drain and have an opposite conductive type, the
substrate 100 between the second conductive type drain region 112
and the gate stays at the first conductive type, thereby the limit
of high-voltage stress of the MOS device can be raised, so that the
semiconductor device of the present invention under a high
voltage.
[0051] FIG. 1D is a schematic cross-sectional view showing yet
another preferred embodiment of the semiconductor device of the
present invention. In FIG. 1D, the same reference numbers are used
to refer to the same parts in FIG. 1A. Here, only the differences
are described.
[0052] Please refer to FIG. 1D. The gate dielectric layer 102a
between the gate 104 and the first conductive type substrate 100 is
provided with a different thickness near the second conductive type
drain region 112 and near the second conductive type source region
110. For example, the gate dielectric layer 102a is provided with a
thickness d1 near the second conductive type source region 110 and
a thickness d2 near the second conductive type drain 112. The
thickness d2 is larger than thickness d1.
[0053] According to the semiconductor device shown in FIG. 1D,
inasmuch as the gate dielectric layer 102a is relatively thick near
the second conductive type drain region 112, high voltage
durability is thereby achieved. Consequently, the gate dielectric
layer is exempted from being damaged while a high voltage is
applied to the drain region.
[0054] According to the semiconductor device shown in FIG. 1D, the
lightly doped region with the same conductive type as the source
region formed between the source region and the gate and the
lightly doped region with a different conductive type from the
drain region formed between the drain region and the gate are taken
as an example to describe herein. Other alternatives are as shown
in FIG. 1B and FIG. 1C. The lightly doped region with an opposite
conductive type to the drain region is formed between the drain
region and the gate, or two lightly doped regions having opposite
conductive types are formed in the substrate between the drain
region and the gate so as to neutralize the substrate between the
drain region and the gate.
[0055] Inasmuch as the lightly doped region having a same
conductive type as the source region is formed between the source
region and the gate, but no lightly doped region is formed between
the drain region and the gate. Even forming a neutral substrate at
the sides of the drain region or forming a lightly doped region
with an opposite conductive type to the drain region at the sides
of the drain region are two other alternatives for the
semiconductor device of the present invention. Accordingly, a high
breakdown voltage can be provided to raise the limit of the
high-voltage stress of the MOS device and to operate the
semiconductor device of the present invention under a high
voltage.
[0056] The method of fabricating the semiconductor device in the
present invention is explained thereupon. FIGS. 2A through 2E are
schematic cross-sectional views showing the steps for fabricating a
semiconductor device according to a preferred embodiment of the
present invention.
[0057] Please refer to FIG. 2A. First, a first conductive type
substrate 200 is provided. A dielectric layer 202 and a conductive
layer 204 are formed on the substrate 200 sequentially. The first
conductive type substrate 200 is a silicon substrate, for example.
The material of the dielectric layer 202 is, for example, silicon
oxide. The dielectric layer is formed, for example, by thermal
oxidation. The material of the conductive layer 204 is, for
example, doped polysilicon. The method for forming conductive layer
204 includes forming a layer of undoped polysilicon by chemical
vapor deposition, and then performing an ion-implantation process;
or adopting an in-situ implanting operation in a chemical vapor
deposition process.
[0058] Please refer to FIG. 2B. The conductive layer 204 and the
dielectric layer 202 are patterned to form the gate 204a and the
gate dielectric layer 202a. The patterned conductive layer 204 and
the dielectric layer 202 are formed, for example, by performing
photolithographic and etching processes. Then, a dielectric layer
206 is formed on the substrate 200. The material of the dielectric
layer 206 is, for example, silicon oxide. The dielectric layer 206
is formed by thermal oxidation or chemical vapor deposition, for
example.
[0059] Please refer to FIG. 2C. A patterned photoresist layer 208
exposing the substrate 200 at one side of the gate 204a is formed
on the substrate 200. The patterned photoresist layer 208 is formed
by performing a photolithographic process, for example. A dopant
implantation process 210 is performed by using the patterned
photoresist layer 208 as a mask to form a second conductive type
lightly doped region 212 in the substrate 200. The dopant
implantation process 210 is, for example, to implant dopants in the
substrate 200 through an ion implantation process.
[0060] Please refer to FIG. 2D. After the patterned photoresist
layer 208 is removed, insulating spacers 214 are formed at the side
walls of the gate 204. The material of the insulating spacers 214
is silicon oxide, silicon nitride, or SiON, for example. The
insulating spacers 214 are, for example, formed by performing a
chemical vapor deposition process at first to form an insulating
material layer, and removing a part of the insulating material
layer through an anisotropic etching operation.
[0061] Please refer to FIG. 2E. Subsequently, a dopant implantation
process 216 is performed by using the gate 204a with insulating
spacers 214 as a mask to form a second conductive type source
region 218a and a second conductive type drain region 218b in the
substrate 200. The dopant implantation process 216 is, for example,
to implant dopants in the substrate 200 through an ion implantation
process.
[0062] FIGS. 3A through 3B are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to a preferred embodiment of the present invention. In FIGS. 3A and
3B, the same reference numbers are used to refer to the same parts
in FIGS. 2A through 2E. Same descriptions are as well omitted.
[0063] Please refer to FIG. 3A. The steps depicted in FIG. 3A
follow FIG. 2C. Namely, the patterned photoresist layer 208 is
removed after the second conductive type lightly doped region 212
is formed in the substrate 200. Afterward, another patterned
photoresist layer 220 exposing the substrate 200 at another side
(the side in opposition to the second conductive type lightly doped
region 212) of the gate 204a is formed on the substrate 200. The
patterned photoresist layer 220 is formed by performing a
photolithographic process, for example. A dopant implantation
process 222 is performed by using the patterned photoresist layer
220 as a mask to form a first conductive type lightly doped region
224 in the substrate 200. The dopant implantation process 222 is,
for example, to implant dopants in the substrate 200 through an ion
implantation process.
[0064] Please refer to FIG. 3B. After the patterned photoresist
layer 220 is removed, insulating spacers 214 are formed at the side
walls of the gate 204. Subsequently, a dopant implantation process
216 is performed by using the gate 204a with the insulating spacers
214 as a mask to form a second conductive type source region 218a
and a second conductive type drain region 218b in the substrate
200.
[0065] FIGS. 4A through 4C are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to another preferred embodiment of the present invention. In FIGS.
4A through 4C, the same reference numbers are used to refer to the
same parts in FIGS. 2A through 2E. Same descriptions are as well
omitted.
[0066] Please refer to FIG. 4A. The steps depicted in FIG. 4A
follow FIG. 2B. Namely, after the gate 204a, the gate dielectric
layer 202a, and the dielectric layer 206 are formed on the
substrate 200. A dopant implantation process 224 is performed by
using the gate 204a as a mask so as to form the second conductive
type lightly doped regions 212a and 212b on the substrate 200 at
both sides of the gate 204a. The dopant implantation process 224
is, for example, to implant dopants in the substrate 200 through an
ion implantation process.
[0067] Please refer to FIG. 4B. A patterned photoresist layer 226
exposing the substrate 200 at one side of the gate 204a is formed
on the substrate 200. The patterned photoresist layer 226 is formed
by performing a photolithographic process, for example. Then, a
dopant implantation process 228 is performed by using the patterned
photoresist layer 226 as a mask to form a first conductive type
lightly doped region 230 in the substrate 200. The dopant
implantation process 228 is, for example, to implant dopants in the
substrate 200 through an ion implantation process.
[0068] Please refer to FIG. 4C. After the patterned photoresist
layer 226 is removed, insulating spacers 214 are formed at the side
walls of the gate 204. Subsequently, a dopant implantation process
216 is performed by using the gate 204a with the insulating spacers
214 as a mask to form the second conductive type source region 218a
and the second conductive type drain region 218b in the substrate
200.
[0069] FIGS. 5A through 5D are schematic cross-sectional views
showing the steps for fabricating a semiconductor device according
to a preferred embodiment of the present invention. In FIGS. 5A
through 5E, the same reference numbers are used to refer to the
same parts in FIGS. 2A through 2E. Same descriptions are as well
omitted.
[0070] Please refer to FIG. 5A. First, the first conductive type
substrate 200 is provided. Then a dielectric layer 202 and a
conductive layer 204 are formed on the substrate 200 sequentially.
The first conductive type substrate 200 is a silicon substrate, for
example. The dielectric layer 202, for example, constitutes the
dielectric layers 201a and 201b. Hence, the dielectric layer 202
has two types of thicknesses. The material of the dielectric layer
202 is, for example, silicon oxide. The method of fabricating the
dielectric layer 202 is, for example, to form a dielectric layer on
the substrate 200 at first. Afterward, the dielectric layer is
patterned to form the dielectric layer 201a and the dielectric
layer 201b is then formed on the substrate 200. The material of the
conductive layer 204 is, for example, doped polysilicon. The method
for forming the conductive layer 204 includes forming a layer of
undoped polysilicon by chemical vapor deposition and then
performing a process of ion-implantation; or adopting an in-situ
implanting operation in a chemical vapor deposition process.
[0071] Please refer to FIG. 5B. The conducting layer 204 and the
dielectric layer 202 are patterned to form the gate 204a and the
gate dielectric layer 202a. The patterned conductive layer 204 and
the dielectric layer 202 are formed, for example, by performing
photolithographic and etching processes. Then, the dielectric layer
206 is formed on the substrate 200. The material of the dielectric
layer 206 is, for example, silicon oxide. The dielectric layer 206
is formed by thermal oxidation or chemical vapor deposition, for
instance.
[0072] Please refer to FIG. 5C. A patterned photoresist layer 208
exposing the substrate 200 at one side of the gate 204a is formed
on the substrate 200. The patterned photoresist layer 208 is formed
by performing a photolithographic process, for example. A dopant
implantation process 210 is performed by using the patterned
photoresist layer 208 as a mask to form a second conductive type
lightly doped region 212 in the substrate 200. The second
conductive type lightly doped region 212 is formed at the thinner
side of the dielectric layer 202a. The dopant implantation process
210 is, for example, to implant dopants in the substrate 200
through an ion implantation process.
[0073] Please refer to FIG. 5D. After the patterned photoresist
layer 208 is removed, insulating spacers 214 are formed at the side
walls of the gate 204. Subsequently, a dopant implantation process
216 is performed by using the gate 204a with insulating spacers 214
as a mask to form the second conductive type source region 218a and
the second conductive type drain region 218b in the substrate 200.
The dopant implantation process 216 is, for example, to implant
dopants in the substrate 200 through an ion implantation process.
As stated in the method of fabricating the semiconductor device
shown in FIGS. 5A through 5D, the fabricating method disclosed in
FIGS. 3A through 3B and FIGS. 4A through 4C can be likewise applied
to the method of fabricating the lightly doped region.
[0074] According to the method of fabricating the semiconductor
device shown in FIGS. 5A through 5D, the lightly doped region with
the same conductive type as the source region formed between the
source region and the gate and the lightly doped region with a
different conductive type from the drain region formed between the
drain region and the gate are taken as an example to describe
herein. Other alternatives are as shown in FIGS. 3A through 3B and
FIGS. 4A through 4C. The lightly doped region with an opposite
conductive type to the drain region is formed between the drain
region and the gate, or two lightly doped regions having opposite
conductive types are formed in the substrate between the drain
region and the gate so as to neutralize the substrate between the
drain region and the gate.
[0075] As stated above, the method of fabricating the semiconductor
device of the present invention has a simple fabricating process
which can be integrated with the process of fabricating a
conventional Complementary Metal Oxide Semiconductor (CMOS) so as
to reduce the time of fabricating the device.
[0076] In conclusion, inasmuch as a lightly doped region having a
same conductive type as the source region is formed between the
source region and the gate, but on lightly doped region is formed
between the drain region and the gate. Even forming a neutral
substrate at the sides of the drain region or forming a lightly
doped region with an opposite conductive type to the drain region
at the sides of the drain region are two other alternatives for the
semiconductor device of the present invention. If the semiconductor
device is operated under a smaller turned-on current, a better
device performance can be then achieved and the limit of
high-voltage stress can be raised so as to operate the
semiconductor device of the present invention under a high
voltage.
[0077] Furthermore, since the method of fabricating the
semiconductor device of the present invention can be integrated
with the process of fabricating a conventional Bipolar
Complementary Metal Oxide Semiconductor (CMOS), the time of
fabricating the device can be reduced without performing the
photolithographic and etching processes.
[0078] The above description provides a full and complete
description of the preferred embodiments of the present invention.
Various modifications, alternate construction, and equivalent may
be made by those skilled in the art without changing the scope or
spirit of the invention. Accordingly, the above description and
illustrations should not be construed as limiting the scope of the
invention which is defined by the following claims.
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