U.S. patent application number 12/031121 was filed with the patent office on 2008-06-12 for thin film transistor array panel and method for manufacturing the same.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Yang-Ho BAE, Beom-Seok CHO, Chang-Oh JEONG, Je-Hun LEE.
Application Number | 20080138942 12/031121 |
Document ID | / |
Family ID | 36260786 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080138942 |
Kind Code |
A1 |
LEE; Je-Hun ; et
al. |
June 12, 2008 |
THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE
SAME
Abstract
The invention provides a thin film transistor (TFT) array panel
that includes an insulating substrate; a gate line formed on the
insulating substrate and having a first layer of an Al containing
metal, a second layer of a Cu containing metal that is thicker than
the first layer, and a gate electrode; a gate insulating layer
arranged on the gate line; a semiconductor arranged on the gate
insulating layer; a data line having a source electrode and
arranged on the gate insulating layer and the semiconductor; a
drain electrode arranged on the gate insulating layer and the
semiconductor and facing the source electrode; a passivation layer
having a contact hole and arranged on the data line and the drain
electrode; and a pixel electrode arranged on the passivation layer
and coupled with the drain electrode through the contact hole.
Inventors: |
LEE; Je-Hun; (Seoul, KR)
; BAE; Yang-Ho; (Suwon-si, KR) ; CHO;
Beom-Seok; (Seoul, KR) ; JEONG; Chang-Oh;
(Suwon-si, KR) |
Correspondence
Address: |
CANTOR COLBURN, LLP
20 Church Street, 22nd Floor
Hartford
CT
06103
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Suwon-si
KR
|
Family ID: |
36260786 |
Appl. No.: |
12/031121 |
Filed: |
February 14, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11249500 |
Oct 14, 2005 |
7352004 |
|
|
12031121 |
|
|
|
|
Current U.S.
Class: |
438/160 ;
257/E21.414 |
Current CPC
Class: |
H01L 27/1288 20130101;
H01L 27/124 20130101; H01L 51/0023 20130101; H01L 27/3279 20130101;
H01L 51/56 20130101 |
Class at
Publication: |
438/160 ;
257/E21.414 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 26, 2004 |
KR |
10-2004-0085683 |
Claims
1-8. (canceled)
9. A method for manufacturing a thin film transistor array (TFT)
panel, comprising: forming a gate line on an insulating substrate,
the gate line having a first layer including Al, a second layer
including Cu and is thicker than the first layer, and a gate
electrode; sequentially depositing a gate insulating layer, a
semiconductor layer, and a ohmic contact layer on the gate line;
patterning the semiconductor layer and the ohmic contact layer;
forming a drain electrode and a data line having a source electrode
on the gate insulating layer and the ohmic contact layer, the drain
electrode facing the source electrode with a gap formed
therebetween; forming a passivation layer having a contact hole
that exposes the drain electrode, the passivation layer being
formed on the data line and the drain electrode; and forming a
pixel electrode on the passivation layer, the pixel electrode being
coupled with the drain electrode through the contact hole.
10. The method of claim 9, wherein forming the gate line on the
insulating substrate comprises: sequentially depositing the first
layer and the second layer on the insulating substrate; and
simultaneously patterning the first layer and the second layer via
an etching process.
11. The method of claim 10, wherein the first layer the second
layer are etched by an etchant including H.sub.2O.sub.2.
12. The method of claim 11, wherein the etchant further contains at
least one of phosphoric acid (H.sub.3PO.sub.4), nitric acid
(HNO.sub.3), and acetic acid (CH.sub.3COOH).
13. The method of claim 10, wherein the first layer and the second
layer are etched using an etchant containing phosphoric acid
(H.sub.3PO.sub.4), nitric acid (HNO.sub.3), and acetic acid
(CH.sub.3COOH).
14. The method of claim 13, wherein the etchant includes about 50%
to about 80% of phosphoric acid, about 2% to about 10% of nitric
acid, and about 2% to about 15% of acetic acid.
15. The method of claim 9, wherein forming the gate line on the
insulating substrate comprises: sequentially depositing the first
layer and the second layer on a insulating substrate in sequence;
and sequentially patterning the first layer and the second layer
using a wet etching and a dry etching process.
16. The method of claim 9, wherein the data line and the
semiconductor layer are formed by a photo-etching process using a
photoresist pattern having a first portion, a second portion that
is thicker than the first portion, and a third portion that is
thinner than the first portion.
17. The method of claim 16, wherein the first portion is arranged
between the source electrode and the drain electrode, and the
second portion is arranged on the data line and the drain
electrode.
18. The method of claim 9, further comprising: forming a color
filter on the insulating substrate before forming the passivation
layer.
19-23. (canceled)
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to and the benefit of
Korean Patent Application No. 10-2004-0085683, filed on Oct. 26,
2004, which is hereby incorporated by reference for all purposes as
if fully set forth herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present description relates to a thin film transistor
(TFT) array panel for a liquid crystal display (LCD) or an organic
light emitting display (OLED), and a method for manufacturing the
same.
[0004] 2. Description of the Related Art
[0005] Liquid crystal displays (LCDs) are a popular type of flat
panel display. An LCD includes a liquid crystal (LC) layer
positioned between two panels provided with field-generating
electrodes. The LCD displays images by applying voltages to the
field-generating electrodes to generate an electric field in the LC
layer that determines orientations of LC molecules in the LC layer
to adjust polarization of incident light.
[0006] A common type of LCD includes two panels provided with
field-generating electrodes respectively, wherein one panel has a
plurality of pixel electrodes in a matrix and the other panel has a
common electrode covering the entire surface of the panel.
[0007] The LCD displays images by applying a different voltage to
each pixel electrode. The TFTs, which have three terminals to
switch voltages applied to the pixel electrodes, are connected with
the pixel electrodes, and gate lines transmitting signals to
control the TFTs and data lines transmitting voltages applied to
the pixel electrodes are formed on a TFT array panel.
[0008] The TFT is applied to an active matrix organic light
emitting display and operates as a switching element to control
respective light emitting elements.
[0009] Molybdenum (Mo), chromium (Cr), and titanium (Ti) are the
materials conventionally used for forming the gate lines of a TFT
array panel.
[0010] When a size of an LCD is increased, a material having low
resistivity is required since the lengths of the gate and data
lines are increased. Accordingly, there are limitations when
applying Mo, Cr, and Ti to a large size LCD.
[0011] Copper (Cu) is a well known material used as a substitute
for Mo, Cr, and Ti because it has low resistivity. However, bad
adhesiveness of Cu with a glass substrate is problemsome when
applying Cu to a gate line. Therefore, there is a need for a
material having low resistivity and sufficient adhesive properties
to be used for the gate lines of the TFT and signal lines.
SUMMARY OF THE INVENTION
[0012] The present invention provides a TFT array panel that has
signal lines having low resistivity that is sufficiently with a
substrate. Additional features of the invention will be set forth
in the description which follows, and in part will be apparent from
the description, or may be learned by practice of the
invention.
[0013] The present invention discloses a thin film transistor (TFT)
array panel, including an insulating substrate; a gate line formed
on the insulating substrate, the gate line having a first layer
that includes Al, a second layer that includes Cu containing metal
and is thicker than the first layer, and a gate electrode; a gate
insulating layer arranged on the gate line; a semiconductor
arranged on the gate insulating layer; a data line having a source
electrode, the data line being arranged on the gate insulating
layer and the semiconductor; a drain electrode arranged on the gate
insulating layer and the semiconductor and facing the source
electrode; a passivation layer having a contact hole, the
passivation layer arranged on the data line and the drain
electrode; and a pixel electrode arranged on the passivation layer
and coupled with the drain electrode.
[0014] The present invention also discloses a method for
manufacturing a thin film transistor array (TFT) panel, including
forming a gate line on an insulating substrate, the gate line
having a first layer including Al, a second layer including Cu and
is thicker than the first layer, and a gate electrode; sequentially
depositing a gate insulating layer, a semiconductor layer, and a
ohmic contact layer on the gate line; patterning the semiconductor
layer and the ohmic contact layer; forming a drain electrode and a
data line having a source electrode on the gate insulating layer
and the ohmic contact layer, the drain electrode facing the source
electrode with a gap formed therebetween; forming a passivation
layer having a contact hole that exposes the drain electrode, the
passivation layer being formed on the data line and the drain
electrode; and forming a pixel electrode on the passivation layer,
the pixel electrode being coupled with the drain electrode through
the contact hole.
[0015] The present invention also discloses an organic light
emitting display (OLED), including: a first semiconductor member
and a second semiconductor member including a first intrinsic
portion and a second intrinsic portion, respectively, and formed of
an amorphous silicon or a polysilicon material; a gate conductor
having a first layer that includes Al, a second layer that includes
Cu and is thicker than the first layer, and a gate line having a
first gate electrode that overlaps the first intrinsic portion and
a second gate electrode that overlaps the second intrinsic portion;
a gate insulating layer arranged between the first semiconductor
member, the second semiconductor member, and the gate conductor; a
data conductor that includes a data line having a first source
electrode coupled with the first semiconductor member, a first
drain electrode opposing the first source electrode with respect to
the first intrinsic portion and coupled with the first
semiconductor member, a voltage transmission line that includes a
second source electrode coupled with the second semiconductor
member, and a second drain electrode opposing the second source
electrode with respect to the second intrinsic portion and coupled
with the second semiconductor member; a pixel electrode coupled
with the second drain electrode; a partition having an opening
exposing the pixel electrode; an auxiliary electrode arranged on
the partition and having substantially the same planar shape as the
partition; an organic light emitting member arranged on the pixel
electrode and positioned substantially in the opening; and a common
electrode arranged on the light emitting member and the auxiliary
electrode.
[0016] The present invention also discloses a thin film transistor
(TFT) array panel for an LCD device, including: a lower layer
formed of an Al containing metal; and an upper layer formed of a Cu
containing metal that is at least about four times thicker than the
lower layer, wherein the upper layer and the lower layer are
patterned to form a plurality of gate lines.
[0017] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are intended to provide further explanation of
the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are included to provide a
further understanding of the invention and are incorporated in and
constitute a part of this specification, illustrate embodiments of
the invention and together with the description serve to explain
the principles of the invention.
[0019] FIG. 1 is a layout view of a TFT array panel for an LCD
according to an embodiment of the invention.
[0020] FIG. 2 is a sectional view of the TFT array panel shown in
FIG. 1 taken along the line II-II.
[0021] FIGS. 3A, 4A, 5A, and 6A are layout views sequentially
illustrating the intermediate operations of a method of
manufacturing a TFT array panel for an LCD according to the
embodiment shown in FIG. 1 and FIG. 2.
[0022] FIG. 3B is a sectional view of the TFT array panel shown in
FIG. 3A taken along the line IIIb-IIIb'.
[0023] FIG. 3C is an enlarged view of the "A" portion of FIG.
3B.
[0024] FIG. 4B is a sectional view of the TFT array panel shown in
FIG. 4A taken along the line IVb-IVb' in the operation following
the operation shown in FIG. 3B.
[0025] FIG. 5B is a sectional view of the TFT array panel shown in
FIG. 5A taken along the line Vb-Vb' in the operation following the
operation shown in FIG. 4B.
[0026] FIG. 6B is a sectional view of the TFT array panel shown in
FIG. 6A taken along the line VIb-VIb' in the operation following
the operation shown in FIG. 5B.
[0027] FIG. 7 is a layout view of a TFT array panel for an LCD
according to another embodiment of the invention.
[0028] FIG. 8 is a sectional view of the TFT array panel shown in
FIG. 7 taken along the line VIII-VIII'.
[0029] FIGS. 9A, 12A, and 13A are layout views of the TFT array
panel shown in FIG. 7 and FIG. 8 during intermediate operations of
a manufacturing method according to an embodiment of the
invention.
[0030] FIGS. 9B, 10, 11, 12B, and 13B are sectional views of the
TFT array panel shown in FIG. 7 and FIG. 8 during intermediate
operations of a manufacturing method according to an embodiment of
the invention.
[0031] FIG. 9C is an enlarged view of the "B" portion of FIG.
9B.
[0032] FIG. 14A is a layout view of a TFT array panel for an LCD
according to another embodiment of the invention.
[0033] FIG. 14B is a sectional view of the TFT array panel shown in
FIG. 14A taken along the line XIVB-XIVB'.
[0034] FIG. 15A and FIG. 16A are layout views of the TFT array
panel shown in FIG. 14A and FIG. 14B during intermediate operations
of a manufacturing method according to an embodiment of the
invention.
[0035] FIG. 15B is a sectional view of the TFT array panel shown in
FIG. 15A taken along the line XVB-XVB'.
[0036] FIG. 16B is a sectional view of the TFT array panel shown in
FIG. 16A taken along the line XVIB-XVIB'.
[0037] FIG. 17 is a layout view of a TFT array panel for an OLED
according to another embodiment of the invention.
[0038] FIG. 18 and FIG. 19 are sectional views of the TFT array
panel shown in FIG. 17 taken along the line XVIII-XVIII' and the
line XIX-XIX', respectively.
[0039] FIG. 20 and FIG. 21 are sectional views of the TFT array
panel shown in FIG. 17 taken along the line XX-XX' and the line
XXI-XXI', respectively.
[0040] FIGS. 22, 24, 26, 28, 30, 32, and 34 are layout views of the
TFT array panel shown in FIGS. 17, 18, 19, 20, and 21 during
intermediate operations of a manufacturing method according to an
embodiment of the invention.
[0041] FIGS. 23A, 23B, and 23C are sectional views of the TFT array
panel shown in FIG. 22 taken along the lines XXIIIa-XXIIIa',
XXIIIb-XXIIIb', and XXIIIc-XXIIIc'.
[0042] FIGS. 25A, 25B, and 25C are sectional views of the TFT array
panel shown in FIG. 24 taken along the lines XXVa-XXVa',
XXVb-XXVb', and XXVc-XXVc'.
[0043] FIGS. 27A, 27B, 27C, and 27D are sectional views of the TFT
array panel shown in FIG. 26 taken along the lines XXVIIa-XXVIIa',
XXVIIb-XXVIIb', XXVIIc-XXVIIc', and XXVIId-XXVIId'.
[0044] FIGS. 29A, 29B, 29C, and 29D are sectional views of the TFT
array panel shown in FIG. 28 taken along the lines XXIXa-XXIXa',
XXIXb-XXIXb', XXIXc-XXIXc', and XXIXd-XXIXd'.
[0045] FIGS. 31A, 31B, 31C, and 31D are sectional views of the TFT
array panel shown in FIG. 30 taken along the lines XXXIa-XXXIa',
XXXIb-XXXIb', XXXIc-XXXIc', and XXXId-XXXId'.
[0046] FIGS. 33A and 33B are sectional views of the TFT array panel
shown in FIG. 32 taken along the lines XXXIIIa-XXXIIIa' and
XXXIIIb-XXXIIIb'.
[0047] FIGS. 35 and 36 are sectional views of the TFT array panel
shown in FIG. 34 taken along the lines XXXV-XXXV' and
XXXVI-XXXVI'.
DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
[0048] Embodiments of the present invention are described more
fully below with reference to the accompanying drawings in which
preferred embodiments of the invention are shown. The present
invention may, however, be embodied in different forms and should
not be construed as being limited to the embodiments set forth
herein. Rather, these embodiments are provided so that this
disclosure fully conveys the scope of the invention to those
skilled in the art.
[0049] In the drawings, the thickness of layers, films, and regions
are exaggerated for clarity. Like numerals refer to like elements
throughout. It will be understood that when an element such as a
layer, film, region, or substrate is referred to as being "on"
another element, it can be directly on the other element or
intervening elements may also be present.
[0050] TFT array panels and manufacturing methods thereof according
to embodiments of this invention are described below.
[0051] A TFT array panel for an LCD according to a first embodiment
of the invention is described below with reference to FIG. 1 and
FIG. 2.
[0052] FIG. 1 is a layout view of a TFT array panel for an LCD and
FIG. 2 is a sectional view of the TFT array panel shown in FIG. 1
taken along the line II-II.
[0053] A plurality of gate lines 121 for transmitting gate signals
are provided, e.g., formed, on an insulating substrate 110. The
gate lines 121 are mostly formed in a horizontal direction and
partial portions thereof become a plurality of gate electrodes 124.
Different partial portions thereof, which extend in a lower
direction, become a plurality of expansions 127.
[0054] The gate line 121 has lower layers 124p and 127p and upper
layers 124q and 127q. The lower layers 124p and 127p may be made of
an Al-like metal such as aluminum (Al) or aluminum-neodymium
(Al--Nd). The upper layers 124q and 127q may be made of a Cu-like
metal such as pure Cu or a Cu alloy. As shown in FIG. 1, the upper
layers 124q and 127q are thicker than the lower layers 124p and
127p.
[0055] Signal lines of a large LCD may be made with Cu since Cu has
a low resistivity. Accordingly, problems such as signal delay,
which arise when the signal lines are lengthened, are reduced.
However, Cu is not sufficiently adhesive with a glass substrate,
which is problemsome when applying Cu to gate lines that are
directly formed on the glass substrate.
[0056] To solve the problem of Cu having insufficient adhesiveness,
an additional metal layer of Mo, Cr, or Ti may be formed under the
Cu layer. However, since Mo, Cr, and Ti each have high resistivity,
such materials increase resistance in the signal lines.
[0057] Thus, according to the present invention, an Al containing
metal layer is applied under the Cu containing metal layer to
improve adhesion with the substrate without increasing resistance.
For example, Al has a much lower resistivity than Mo, Cr, and Ti,
and is also sufficiently adhesive with the substrate, therefore,
the combination of an Al containing metal layer and a Cu containing
metal layer compliments Cu, which has low resistance.
[0058] The Cu containing metal layer is thicker than the Al
containing metal layer, which assures low resistance of the signal
lines. The Cu containing metal layer may be more than four times
thicker than the Al containing metal layer. When the thickness of
the Al containing metal layer is not sufficiently thick, the Cu
containing metal layer may partially contact the substrate and/or
may partially peel. When the Al containing metal layer is too
thick; the signal lines may have high resistance. Therefore,
according to an embodiment of the invention, the upper layers 124q
and 127q of the Cu containing metal are formed to be more than four
times thicker than the lower layers 124p and 127p of the Al
containing metal. For example, when the upper layers 124q and 127q
approximately 2000 .ANG. thick, the lower layers 124p and 127p are
approximately of 5 .ANG.-500 .ANG. thick.
[0059] When the lower layers 124p and 127p and the upper layers
124q and 127q are formed having the above-described thickness
ratio, the upper and lower layers may be patterned with one etching
step.
[0060] Generally, since Al and Cu have very different etching
conditions, double layers of Al and Cu cannot be patterned together
using a normal etching method. Accordingly, two etching operations
with different etching conditions must be applied when patterning
the double layer of Al and Cu. For instance, Cu may be rapidly
etched by wet etching with an etchant of H.sub.2O.sub.2, and Al may
be scarcely etched by wet etching with an etchant of
H.sub.2O.sub.2. Alternatively, Al may be etched by dry etching with
plasma and the Cu is scarcely etched by dry etching. Accordingly,
when patterning the lower layers 124p and 127p of the Al containing
metal and the upper layers 124q and 127q of the Cu containing
metal, the upper layers 124q and 127q may be first etched by a wet
etching and then the lower layers 124p and 127p may be etched by
dry etching using the upper layer pattern as an etching mask.
[0061] According to the embodiment of the present invention, when
the lower layers 124p and 127p are significantly thinner than the
upper layers 124q and 127q, the two layers may be patterned
together with an etchant by using a galvanic effect. The galvanic
effect is a tendency for metals having different electrical
potentials in an electrolyte solution to oxidize and reduce. For
example, when two metals having different electrical potentials are
disposed in an electrolyte solution, a metal having a relatively
positive potential works as a cathode and tends to reduced and the
other metal having a relatively negative potential works as an
anode and tends to oxidize. In this case, the etching speed
(eroding speed) of the cathode metal is slower than when the
cathode metal is used alone. The etching speed (eroding speed) of
the anode metal is faster than when the anode metal is used alone.
Since the degree of galvanic effect is largely dependent on the
area ratio of the cathode and anode, the etching rate of the upper
layers and the lower layers may be controlled by adjusting the
thickness of the two layers.
[0062] Al and Cu respectively have electromotive forces of about
-1.66V and about +0.337V. Accordingly, Al operates as the anode and
Cu operates as the cathode. The gap between the electromotive
forces between Al and Cu is about 1.997V. This is a larger value
than 1.86V, which is the gap between the electromotive forces
between Al and Mo. Therefore, the galvanic effect may be more
efficiently applied between Al and Cu than between Al and Mo.
[0063] According to the invention, the lower layers 124p and 127p
of the Al containing metal and the upper layers 124q and 127q of
the Cu containing metal, which are thicker than the lower layers
124p and 127p, are sequentially deposited and etched together with
an etchant such as H.sub.2O.sub.2. The lower layers 124p and 127p
work as an anode and are etched with an increased etching speed and
the upper layers 124q and 1271 work as a cathode and are etched
with a decreased etching speed, or vice-versa. Accordingly, the
etching speeds of the Al layers and Cu layers may be balanced so
that lateral surfaces of the lower layers 124p and 127p and the
upper layers 124q and 127q have substantially the same slope.
[0064] The lateral sides of the upper layers 124q and 127q and
lower layers 124p and 127q are inclined relative to a surface of
the substrate 110, and the inclination angle thereof ranges about
30 to about 80 degrees.
[0065] A gate insulating layer 140 which may be made of silicon
nitride (SiNx), is formed on the gate lines 121.
[0066] A plurality of semiconductor stripes 151, which may be made
of hydrogenated amorphous silicon (abbreviated to "a-Si"), are
formed on the gate insulating layer 140. Each semiconductor stripe
151 extends substantially in the longitudinal direction and is
curved periodically. Each semiconductor stripe 151 has a plurality
of projections 154 branched out or extending toward the gate
electrodes 124. Each semiconductor stripe 151 widens near the gate
lines 121 so that the semiconductor stripe 151 cover a sufficiently
large areas of the gate lines 121.
[0067] A plurality of ohmic contact stripes 161 and islands 165,
which may be made of silicide or n+ hydrogenated a-Si heavily doped
with n type impurity, are formed on the semiconductor stripes 151.
Each ohmic contact stripe 161 has a plurality of projections 163,
and the projections 163 and the ohmic contact islands 165 are
located in pairs on the projections 154 of the semiconductor
stripes 151.
[0068] The edge surfaces of the semiconductor stripes 151 and the
ohmic contacts 161 and 165 are tapered, and the inclination angles
of the edge surfaces of the semiconductor stripes 151 and the ohmic
contacts 161 and 165 may be in a range of about 30 to about 80
degrees.
[0069] A plurality of data lines 171, a plurality of drain
electrodes 175, and a plurality of storage capacitor conductors 177
are formed on the ohmic contacts 161 and 165 and the gate
insulating layer 140.
[0070] The data lines 171 for transmitting data voltages extend
substantially in the longitudinal direction and intersect the gate
lines 121 and define pixel areas substantially arranged in a
matrix. A plurality of branches of each data line 171, which
project toward the drain electrodes 175, form a plurality of source
electrodes 173. Each pair of the source electrodes 173 and the
drain electrodes 175 are separated from each other and are
positioned opposite to each other with respect to a gate electrode
124.
[0071] The data line 171 and drain electrode 175 are made of one or
more of Chromium (Cr), Molybdenum (Mo), Aluminum (Al), Cooper (Cu),
and Tungsten (W). The data line 171 and drain electrode 175 have
double layers 173p, 173q, 175p, and 175q that are made of two
metals selected from among Cr, Mo, Al, Cu, and W. The data metals
are selected according to resistance and contact
characteristics.
[0072] A gate electrode 124, a source electrode 173, a drain
electrode 175, and a projection 154 of a semiconductor stripe 151,
form a TFT having a channel formed in the projection 154 disposed
between the source electrode 173 and the drain electrode 175. The
storage capacitor conductor 177 overlaps with the expansion 127 of
the gate line 121.
[0073] The data lines 171, the drain electrodes 175, and the
storage capacitor conductor 177 have tapered edge surfaces, and the
inclination angles of the edge surfaces are in a range of about
30-80 degrees.
[0074] The ohmic contacts 161 and 165 are provided between the
semiconductor stripe 151 and the data line 171 and between the
drain electrode 175 and the projection 154 of the semiconductor
stripe 151 to reduce contact resistance therebetween. The
semiconductor stripe 151 is exposed between the source electrode
173 and the drain electrode 175 and at other places not covered
with the data line 171 and the drain electrode 175. Most of the
semiconductor stripe 151 is narrower than the data line 171 but the
semiconductor stripe 151 widens near where the semiconductor stripe
151 and the gate line 121 meet to prevent disconnection of the data
line 171, as discussed above.
[0075] A passivation lawyer 180 is provided on the data line 171,
the drain electrode 175, the storage capacitor conductor 177, and
the exposed region of the semiconductor stripe 151. The passivation
layer 180 may be made of an organic material having substantial
planarization properties and photosensibility, or an insulating
material having a low dielectric constant such as a-Si:C:O, a
Si:O:F, etc. This passivation layer 180 may be formed by plasma
enhanced chemical vapor deposition (PECVD). To prevent the organic
material of the passivation layer 180 from contacting with the
semiconductor stripes 151 exposed between the data line 171 and the
drain electrode 175, the passivation layer 180 may include an
insulating layer made of SiNx or SiO.sub.2 formed under the organic
material layer.
[0076] A plurality of contact holes 185, 187, and 182 are formed in
the passivation layer 180 to expose the drain electrode 175, the
storage capacitor conductor 177, and an end portion of the data
line 171, respectively.
[0077] A plurality of pixel electrodes 190 and a plurality of
contact assistants 82, which are made of IZO or ITO, are arranged
on the passivation layer 180.
[0078] Since the pixel electrode 190 is physically and electrically
coupled with the drain electrode 175 and the storage capacitor
conductor 177 through the contact holes 185 and 187, respectively,
the pixel electrode 190 receives the data voltage from the drain
electrodes 175 and transmits the data voltage to the storage
capacitor conductor 177.
[0079] The pixel electrode 190 to which the data voltage is applied
generates an electric field with a common electrode (not
illustrated) of the opposite panel (not illustrated) to which a
common voltage is applied, thereby rearranging the liquid crystal
molecules in the liquid crystal layer.
[0080] As discussed above, the pixel electrode 190 and the common
electrode form a capacitor to store and preserve the received
voltage after the TFT is turned off. The capacitor is referred to
hereinafter as a "liquid crystal capacitor." To enhance the voltage
storage ability, another capacitor is provided, which is coupled
with the liquid crystal capacitor in parallel and is referred to
hereinafter as a "storage capacitor." The storage capacitor is
formed at an overlap portion of the pixel electrode 190 and the
adjacent gate line 121, which is referred to hereinafter as
"previous gate line." The expansion 127 of the gate line 121
ensures the largest possible overlap dimension and increases
storage capacity of the storage capacitor. The storage capacitor
conductor 177 is connected, e.g., coupled, with the pixel electrode
190 and overlaps with the expansion 127. The storage capacitor is
positioned at the bottom of the passivation layer 180 so that the
pixel electrode 190 is near the previous gate line 121.
[0081] The pixel electrode 190 may overlap with the adjacent gate
line 121 and the adjacent data line 171 to improve the aperture
ratio. It is understood that the pixel electrode 190 may not
overlap the adjacent gate line 121 and the adjacent data line
171.
[0082] The contact assistant 82 supplements and improves adhesion
between the end portion of the data line 171 and the exterior
devices, such as the driving integrated circuit, and protects them.
The contact assistant 82 is an optional feature.
[0083] A method for manufacturing a TFT array panel is described
below with reference to FIGS. 1, 2, 3A, 3B, 3C, 4A, 4B, 5A, 5B, 6A,
and 6B.
[0084] FIGS. 3A, 4A, 5A, and 6A are layout views sequentially
illustrating the intermediate operations of a method for
manufacturing a TFT array panel for an LCD according to the
embodiment shown in FIG. 1 and FIG. 2. FIG. 3B is a sectional view
of the TFT array panel shown in FIG. 3A taken along the line
IIIb-IIIb'. FIG. 4B is a sectional view of the TFT array panel
shown in FIG. 4A taken along the line IVb-IVb' in the operation
following the operation shown in FIG. 3B. FIG. 5B is a sectional
view of the TFT array panel shown in FIG. 5A taken along the line
Vb-Vb' in the operation following the step shown in FIG. 4B. FIG.
6B is a sectional view of the TFT array panel shown in FIG. 6A
taken along the line VIb-VIb' in the operation following the
operation shown in FIG. 5B.
[0085] As shown in FIG. 3A and FIG. 3B, a metal layer is formed on
an insulating substrate 110.
[0086] The metal layer is deposited by a Co-sputtering. Two targets
are used in a same sputtering chamber for the Co-sputtering. One
target is made of Al or Al--Nd. The other target is made of Cu.
Here, the Al--Nd target preferably includes 2 wt % of Nd.
[0087] The Co-sputtering may be performed according to the
following method.
[0088] Power is applied to the Al (or Al--Nd) target while no power
is applied to the Cu target to deposit a lower layer of Al (or
Al--Nd). The lower layer is preferably about 5 .ANG. to about 500
.ANG. thick.
[0089] Power is then switched to be applied to the Cu target and
not to be applied to the Al (or Al--Nd) target to deposit an upper
layer. The upper layer is preferably about 2,000 .ANG. thick.
[0090] The upper layer and the lower layer are simultaneously
etched to form a plurality of gate lines 121 having a plurality of
gate electrodes 124 and expansions 127. For example, the upper
layer and the lower layers may be etched using an etchant of
H.sub.2O.sub.2 or an etchant containing H.sub.2O.sub.2, phosphoric
acid (H.sub.3PO.sub.4), nitric acid (HNO.sub.3), acetic acid
(CH.sub.3COOH), and deionized water. The etchant may include 50% to
80% of phosphoric acid, 2% to 10% of nitric acid, 2% to 15% of
acetic acid, and deionized water to fill the residual quantity.
[0091] The etchants discussed above etch Al and Cu at different
etching speeds during normal conditions. However, according to the
present invention, the lower layer of Al and the upper layer of Cu
are deposited with different thickness and are etched together with
the etchant such that lateral sides of the lower layers 124p and
127p and the upper layers 124q and 127q have substantially the same
slope.
[0092] In the present invention, the lower layer of Al is thinner
thickness than the upper layer of Cu because of the etching
conditions. Therefore, since Al and Cu have very different etching
conditions, double layers of Al and Cu cannot be patterned together
under normal etching conditions. Accordingly, two etching
operations with different etching conditions should be applied to
pattern the double layer of Al and Cu. For example, Cu may be
rapidly etched by a wet etching with an etchant of H.sub.2O.sub.2
and Al may be scarcely etched by wet etching with an etchant of
H.sub.2O.sub.2. To the contrary, Al is etched by a dry etching with
plasma and Cu may be scarcely etched by dry etching. Accordingly,
when patterning the lower layers 124p and 127p of the Al containing
metal and the upper layers 124q and 127q of the Cu containing
metal, the upper layers 124q and 127q are first etched by wet
etching and then the lower layers 124p and 127p are etched by dry
etching using the upper layer pattern as an etching mask.
[0093] However, according to the embodiment of the invention, when
the lower layers 124p and 127p are significantly thinner than the
upper layers 124q and 127q, the two layers may be patterned
together with an etchant by using a galvanic effect. The galvanic
effect refers to an oxidation and a reduction tendency of metals
having different electrical potentials in an electrolyte solution.
For example, when two metals having different electrical potentials
are disposed in an electrolyte solution, a metal having a
relatively positive potential operates as a cathode and may be
reduced and the other metal having a relatively negative potential
works as an anode and tends to be oxidized. In this case, the
etching speed (eroding speed) of the cathode metal is slower when
the cathode metal is disposed alone. The etching speed (eroding
speed) of the anode metal is faster than when the anode metal is
disposed alone. Since the degree of galvanic effect is highly
dependent on the area ratio of the cathode and anode, the etching
rate of the upper layers and the lower layers may be controlled by
adjusting the thickness of the two layers.
[0094] Al and Cu have electromotive forces of about -1.66V and
about +0.337V, respectively. Accordingly, Al operates as the anode
and Cu operates as the cathode. The gap between the electromotive
forces between Al and Cu is about 1.997V, which is larger than
1.86V, which is the difference between the electromotive forces of
Al and Mo. This indicates that the galvanic effect may be more
efficiently applied between Al and Cu than between Al and Mo.
[0095] Accordingly, in the present invention, the lower layers 124p
and 127p of the Al containing metal and the upper layers 124q and
127q of the Cu containing metal, which are thicker than the lower
layers 124p and 127p, are sequentially deposited and are etched
together with an etchant, such as H.sub.2O.sub.2. Here, the lower
layers 124p and 127p operates as an anode and are etched with an
increased etching speed. The upper layers 124q and 1271 operates as
a cathode and are etched with a decreased etching speed.
Accordingly, the etching speeds of the Al layers and Cu layers may
be balanced to simultaneously etch the lower layers 124p and 127p
and the upper layers 124q and 127q.
[0096] Here, as shown in FIG. 3C, when the upper layers 124q and
127q are about four times thicker than the lower layers 124p and
127p, the etching speeds of the upper layers 124q and 127q and the
lower layers 124p and 127p may be balanced due to the galvanic
effect. For example, when the upper layers 124q and 127q are about
2,000 .ANG. thick, the lower layers are less than or equal to about
500 .ANG. thick.
[0097] Referring to FIG. 4A and FIG. 4B, SiNx or SiO.sub.2 is
deposited on the gate line 121 to form a gate insulating layer 140.
The gate insulating layer 140 may be about 2,000 .ANG. to 5,000
.ANG. thick, and the deposition temperature may be between about
250.degree. C. and about 500.degree. C.
[0098] After sequential deposition of an intrinsic a-Si layer and
an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic
a-Si layer are photo-etched to form a plurality of extrinsic
semiconductor stripes 161 and a plurality of intrinsic
semiconductor stripes 151, respectively, having projections 164 and
154.
[0099] Referring to FIG. 5A and FIG. 5B, a lower metal layer and an
upper metal layer are deposited on the extrinsic semiconductor
stripes 161 by a deposition method such as sputtering. The lower
metal layer and the upper metal layer are made of two metals
selected from among Cr, Mo, Al, Cu, and W. The two layers may be
about 3,000 .ANG. thick. The sputtering temperature may be about
15.degree. C.
[0100] The two layers are then simultaneously patterned to form
data lines 171, drain electrodes 175, and storage conductors 177 by
an etchant. The two layers may be etched using an etchant
containing phosphoric acid, nitric acid, acetic acid, and deionized
water. The etchant may include about 63% to about 70% of phosphoric
acid, about 4% to about 8% of nitric acid, about 8% to about 11% of
acetic acid, and deionized water to fill the residual quantity. The
etchant may include more acetic acid by about 4% to about 8%.
[0101] Portions of the extrinsic semiconductor stripes 161, which
are not covered with the data lines 171 and the drain electrodes
175, are then removed by etching to complete a plurality of ohmic
contacts 163 and 165 and to expose portions of the intrinsic
semiconductor stripes 151. Oxygen plasma treatment may then be
performed to stabilize the exposed surfaces of the semiconductor
stripes 151.
[0102] Referring to FIG. 6A and FIG. 6B, a passivation layer 180 is
deposited and dry etched along with the gate insulating layer 140
to form a plurality of contact holes 185, 187, and 182. The gate
insulating layer 140 and the passivation layer 180 may be etched
using an etch condition having substantially the same etch ratio
for both the gate insulating layer 140 and the passivation layer
180.
[0103] As shown in FIG. 1 and FIG. 2, a plurality of pixel
electrodes 190 and a plurality of contact assistants 82 may be
formed by sputtering and photo-etching an IZO layer or an ITO
layer.
[0104] According to another embodiment of the invention, the data
lines and the semiconductors are formed using different photo
etching processes having different photo masks than was described
in the first embodiment. However, the data lines and the
semiconductors may be simultaneously formed by a photo etching
process using a same photo mask to reduce production cost. Such an
embodiment is described below with reference to the drawings.
[0105] FIG. 7 is a layout view of a TFT array panel for an LCD
according to another embodiment of the invention. FIG. 8 is a
sectional view of the TFT array panel shown in FIG. 7 taken along
the line VIII-VIII'.
[0106] Referring to FIG. 7 and FIG. 8, a plurality of gate lines
121 including a plurality of gate electrodes 124 and a plurality of
storage electrode lines 131, which are electrically separated from
the gate lines 121, are formed on a substrate 110.
[0107] The gate line 121 and the storage lines 131 have lower
layers 121p and 131p and upper layers 121q and 131q. The lower
layers 121p and 131p may be made of an Al containing metal, such as
aluminum (Al) or aluminum-neodymium (Al--Nd). The upper layers 121q
and 131q may be made of Cu.
[0108] In addition, the lateral sides of the lower layers 121p and
131p and the upper layers 121q and 131q are inclined relative to a
surface of the substrate 110, and the inclination angle thereof
ranges from about 30 to about 80 degrees.
[0109] A gate insulating layer 140, which may be made of silicon
nitride (SiNx), is formed on the gate lines 121 and the storage
electrode lines 131.
[0110] A plurality of semiconductor stripes 151, which may be made
of hydrogenated amorphous silicon (abbreviated to "a-Si"), are
formed on the gate insulating layer 140. Each semiconductor stripe
151, may extend substantially in the longitudinal direction and may
include a plurality of projections 154 extending toward the gate
electrodes 124. The projections 154 have portions overlapping the
storage electrode line 131.
[0111] A plurality of ohmic contact stripes 161 and islands 165,
which may be made of silicide or n+ hydrogenated a-Si heavily doped
with n type impurity, are formed on the semiconductor stripes 151.
Each ohmic contact stripe 161 may include a plurality of
projections 163, and the projections 163 and the ohmic contact
islands 165 are located in pairs on the projections 154 of the
semiconductor stripes 151.
[0112] The lateral sides of the semiconductors 151 and the ohmic
contacts 161 and 165 are inclined relative to a surface of the
substrate 110, and the inclination angles thereof may range from
about 30 to about 80 degrees.
[0113] A plurality of data lines 171 and a plurality of drain
electrodes 175 are formed on the ohmic contacts 161 and 165 and the
gate insulating layer 140.
[0114] The data lines 171 for transmitting data voltages extend
substantially in the longitudinal direction and intersect the gate
lines 121 to define pixel regions arranged in a matrix. A plurality
of branches of each data line 171, which project toward the drain
electrodes 175, form a plurality of source electrodes 173. Each
pair of the source electrodes 173 and the drain electrodes 175 are
separated from each other, and are opposite to each other, with
respect to a gate electrode 124.
[0115] The data line 171 and drain electrode 175 are made of one or
more of Cr, Mo, Al, Cu, and tungsten (W). The data line 171 and
drain electrode 175 have multiple layers; e.g., double layers 173p,
173q, 175p, and 175q, which may be made of two metals selected from
among Cr, Mo, Al, Cu, and tungsten (W). The data metals are
selected under considering such properties as resistance and
contact characteristics.
[0116] The ohmic contacts 161 and 165 are only arranged or
interposed between the underlying semiconductors 151 and the
overlying data lines 171 and drain electrodes 175, and the ohmic
contacts 161 and 165 reduce the contact resistance therebetween.
The semiconductor stripes 151 include a plurality of exposed
portions, which are not covered with the data lines 171 and the
drain electrodes 175, such as portions located between the source
electrodes 173 and the drain electrodes 175.
[0117] A passivation layer 180 is formed on the data lines 171, the
drain electrodes 175, and portions of the semiconductor stripes 151
that are not covered with the data lines 171 and the drain
electrodes 175. The passivation layer 180 may be made of a
photosensitive organic material having a good flatness
characteristic, a dielectric insulating material having a
dielectric constant less than 4.0, such as a-Si:C:O and a-Si:O:F,
formed by plasma enhanced chemical vapor deposition (PECVD), or an
inorganic material such as silicon nitride and silicon oxide.
[0118] The passivation layer 180 includes a plurality of contact
holes 182 and 185.
[0119] A plurality of pixel electrodes 190 and a plurality of
contact assistants 82 are formed on the passivation layer 180.
[0120] The pixel electrodes 190 are physically and electrically
connected, e.g., coupled, with the drain electrodes 175 through the
contact holes 185, such that the pixel electrodes 190 receive the
data voltages from the drain electrodes 175. The pixel electrodes
190 supplied with the data voltages generate electric fields, in
cooperation with a common electrode (not shown) provided on another
panel (not shown), which reorient liquid crystal molecules in a
liquid crystal layer (not shown) disposed therebetween.
[0121] A pixel electrode 190 and a common electrode form a liquid
crystal capacitor, which stores applied voltages when the TFT is
turned off. An additional capacitor referred to as a "storage
capacitor" is connected in parallel to the liquid crystal
capacitor. The storage capacitors are implemented by overlapping
the pixel electrodes 190 with the storage lines 131. The storage
electrode lines 131 are supplied with a predetermined voltage such
as the common voltage. The storage electrode lines 131 may be
omitted when the storage capacitance generated by the overlapping
of the gate lines 121 and the pixel electrodes 190 is sufficient.
The storage electrode lines 131 may be formed along a boundary of
the pixels to enhance aperture ratio.
[0122] A method of manufacturing the TFT array panel illustrated in
FIG. 7 and FIG. 8 is described below with reference to FIGS. 7, 8,
9A, 9B, 9C, 10, 11, 12A, 12B, 13A, 13B, and 13C.
[0123] A lower metal layer, which may be formed of Al or Al alloy
and an upper metal layer of Cu, which is thicker than the lower
metal layer, are formed on an insulating substrate 110. The
insulating substrate 110 may be formed of glass and the lower and
upper metal layers may be formed thereon by sputtering.
[0124] The upper metal layer and the lower metal layer are then
simultaneously patterned to form a plurality of gate lines 121
having gate electrodes 124 and storage electrode lines 131. For
example, the lower metal layer and the upper metal layer may have a
thickness ratio of about 1:4. The upper and lower layers may be
etched using an etchant of H.sub.2O.sub.2 or an etchant containing
H.sub.2O.sub.2, phosphoric acid (H.sub.3PO.sub.4), nitric acid
(HNO.sub.3), acetic acid (CH.sub.3COOH), and deionized water. The
etchant may include about 50% to about 80% of phosphoric acid,
about 2% to about 10% of nitric acid, about 2% to about 15% of
acetic acid, and deionized water to fill the residual quantity.
[0125] The etchants listed above etch Al and Cu at very different
etching speeds during normal conditions. However, in the present
invention, the lower layer of Al and the upper layer of Cu have
different thickness and are etched together with the etchants such
that lateral sides of the lower layers 121p and 131p and the upper
layers 121q and 131q have substantially the same slope.
[0126] The upper layers 121q and 131q of the Cu containing metal
are preferably more than four times thicker than the lower layers
121p and 131p of the Al containing metal. For example, when the
upper layers 121q and 131q are about 2000 .ANG. thick, the lower
layers 121p and 131p are about 5 .ANG. to about 500 .ANG.
thick.
[0127] The thickness ratio between the upper layers 121q and 131q
and the lower layers 121p and 131p determined by considering such
things as etching conditions for low resistance, adhesiveness to
the substrate, and simultaneous etching. When the lower layers 121p
and 131p are less than about 5 .ANG. thick, the upper layers 121q
and 131q may contact the substrate 110 and may be partially peeled.
To the contrary, when the thickness of the lower layers 121p and
131p is too thick, high resistance of signal lines may be
problemsome and the two layers 121p, 131p, 121q, and 131q cannot be
simultaneously.
[0128] Referring to FIG. 10, a gate insulating layer 140 made of
SiNx, an intrinsic semiconductor layer 150, and an extrinsic
semiconductor layer 160 are sequentially deposited. The intrinsic
semiconductor layer 150 may be made of hydrogenated amorphous
silicon (abbreviated to "a-Si") and the extrinsic semiconductor
layer 160 may be made of silicide or n+ hydrogenated a-Si heavily
doped with n type impurity.
[0129] A lower metal layer and an upper metal layer are deposited
on the extrinsic semiconductor stripes 161. This may be performed
using a deposition method such as sputtering. The lower metal layer
and the upper metal layer are made of two metals selected from
among Cr, Mo, Al, Cu, and W. The two layers are then simultaneously
patterned to form data lines 171 and drain electrodes 175 by an
etchant. The etchant may include about 63% to about 70% of
phosphoric acid, about 4% to about 8% of nitric acid, about 8% to
about 11% of acetic acid, and deionized water to fill the residual
quantity. The etchant may include more acetic acid by about 4% to
about 8%.
[0130] A photoresist film is applied on the upper layer 170q. The
photoresist film is exposed to light through an exposure mask (not
shown), and developed such that the developed photoresist has a
positional dependent thickness as shown in FIG. 10. The developed
photoresist includes a plurality of first portions 54, second
portion 52, and third portions. The first portions 54 are located
on channel areas B, the second portions 52 are located on the data
line areas A, and no reference numeral is assigned to the third
portions that are located on remaining areas C since they have
substantially no thickness. As shown in FIG. 10, the thickness
ratio of the first portions 54 to the second portions 52 is
adjusted depending upon the process conditions in the subsequent
process steps. For example, the thickness of the first portions 54
is preferable equal to or less than half of the thickness of the
second portions 52; e.g., the second portion 52 is at least twice
as thick as the first portion 54.
[0131] The position-dependent thickness of the photoresist may be
obtained using several techniques, for example, by providing
translucent areas on the exposure mask as well as transparent areas
and light blocking opaque areas. The translucent areas may have a
slit-like pattern, a lattice-like pattern, or a thin film(s) having
an intermediate transmittance or an intermediate thickness. When
using a slit pattern, the width of the slits or the distance
between the slits is preferably less than the resolution of a light
exposer used for the photolithography. When using a reflowable
photoresist, after forming a photoresist pattern made of a
reflowable material using a normal exposure mask with only
transparent areas and opaque areas, the reflowable material may
reflow onto areas without the photoresist, thereby forming thin
portions.
[0132] Next, the photoresist film 52 and 54 and the underlying
layers are etched such that the data lines 171, drain electrodes
175, and the underlying layers remain on the data areas A, only the
intrinsic semiconductor layer remains on the channel areas B, and
the gate insulating layer 140 is exposed on the remaining areas
C.
[0133] A method for forming at least the above described structure
is discussed below.
[0134] Referring to FIG. 11, the exposed portions of the first
layer and the second layers 170p on the other areas C are removed
to expose the underlying portions of the extrinsic semiconductor
layer 160.
[0135] The exposed portions of the extrinsic semiconductor layer
160 and the underlying portions of the intrinsic semiconductor
layer 150 on the areas C as well as the photoresist pattern 54 and
52 are then removed by dry etching to expose source and drain (S/D)
metals 174 of the area B.
[0136] The photoresist pattern 54 of the channel areas B may be
removed by an etching process that simultaneously removes the
extrinsic semiconductor 160 and the intrinsic semiconductor 150, or
by separate etching processes. Residual photoresist of the
photoresist pattern 54 in the channel area B may be removed by
using an ashing procedure. In this operation, the semiconductor
stripes 151 are completely formed.
[0137] When the S/D metals are able to be etched by dry etching,
the S/D metals may be sequentially etched along with the extrinsic
semiconductor layer 161 and the intrinsic semiconductor layer 150
to simplify the manufacturing process. In this case, the three
layers 170, 160, and 150 (not specifically shown) may be
sequentially etched in a dry etching chamber, which is referred to
as an "in-situ" method.
[0138] As shown in FIG. 12A and FIG. 12B, portions of the S/D
metals 174 and the underlying portions of the extrinsic
semiconductor layer 164 on the channel areas B are then removed by
etching. The exposed portions of the semiconductor 154 may be
etched to reduce the thickness of the semiconductor 154 and to
partially remove and the second portion 52 of the photoresist
pattern.
[0139] Accordingly, the source electrodes 173 and the drain
electrodes 175 are separated from each other, and, simultaneously,
the data lines 171 and the ohmic contacts 163 and 165 thereunder
are completed.
[0140] The residual second portions 52 of the photoresist pattern
left on the data areas A are then removed.
[0141] As shown in FIG. 13A and FIG. 13B, a passivation layer 180
is formed to cover the data lines 171, the drain electrodes 175,
and the portions of the semiconductor stripes 151 are not covered
with the data lines 171 and the drain electrodes 175. The
passivation layer 180 may be formed of a photosensitive organic
material having properties such as a good flatness characteristic,
a dielectric insulating material having a low dielectric constant
less than 4.0, such as a-Si:C:O and a-Si:O:F, formed by plasma
enhanced chemical vapor deposition (PECVD), or an inorganic
material such as silicon nitride and silicon oxide.
[0142] The passivation layer 180 is then photo-etched to form a
plurality of contact holes 185 and 182. When the passivation layer
180 is formed with a photosensitive material, the contact holes 185
and 182 may only be formed by photolithography.
[0143] As shown in FIG. 7 and FIG. 8, a plurality of pixel
electrodes 190 and a plurality of contact assistants 82 are then
formed by sputtering and photo-etching an IZO layer or an ITO
layer. The pixel electrodes 190 and the contact assistants 82 are
respectively connected, e.g., coupled, with the drain electrodes
175 and an end of the data lines 171 through the contact holes 185
and 182.
[0144] The present embodiment illustrates a TFT array panel having
color filters, however, it is understood that the color fillers are
not always necessary.
[0145] FIG. 14A is a layout view of a TFT array panel for an LCD
according to another embodiment of the invention. FIG. 14B is a
sectional view of the TFT array panel shown in FIG. 14A taken along
the line XIVB-XIVB'.
[0146] A plurality of gate lines 121 for transmitting gate signals
are formed on an insulating substrate 110. As shown, the gate lines
121 are mostly formed in the substantially horizontal direction and
partial portions thereof form a plurality of gate electrodes 124.
Also, different partial portions of the gate lines 121, which
extend in a downward direction, become a plurality of expansions
127.
[0147] The gate line 121 has lower layers 124p and 127p and upper
layers 124q and 127q. The lower layers 124p and 127p may be made of
an Al containing metal such as aluminum (Al) or aluminum-neodymium
(Al--Nd). The upper layers 124q and 127q may be of a Cu containing
metal such as pure Cu or a Cu alloy. For example, the upper layers
124q and 127q may be thicker than the lower layers 124p and 127p,
e.g., the upper layers 124q and 127q are preferably more than four
times thicker than the lower layers 124p and 127p
[0148] When the Al containing metal layer is too thin, the Cu
containing metal layer may contact the substrate and/or may be
partially peeled. To the contrary, when the Al containing metal
layer is too thick, high resistance of signal lines is problemsome.
Accordingly, it is preferable that the upper layers 124q and 127q
of the Cu containing metal are more than four times thicker than
the lower layers 124p and 127p of the Al containing metal.
[0149] The lateral sides of the upper layers 124q and 127q and
lower layers 124p and 127q are inclined relative to a surface of
the substrate 110, and the inclination angle thereof ranges from
about 30 to about 80 degrees.
[0150] A gate insulating layer 140, which may be made of silicon
nitride (SiNx), is formed on the gate lines 121.
[0151] A plurality of semiconductor stripes 151, which may be made
of hydrogenated amorphous silicon (abbreviated to "a-Si"), are
formed on the gate insulating layer 140. Each semiconductor stripe
151 extends substantially in the longitudinal direction and is
curved at various portions thereof. Each semiconductor stripe 151
has a plurality of projections 154 extending toward the gate
electrodes 124. The width of each semiconductor stripe 151
increases near the gate lines 121 such that the semiconductor
stripe 151 covers sufficient areas of the gate lines 121.
[0152] A plurality of ohmic contact stripes 161 and islands 165,
which may be made of silicide or n+ hydrogenated a-Si heavily doped
with n type impurity, are formed on the semiconductor stripes 151.
Each ohmic contact stripe 161 has a plurality of projections 163,
and the projections 163 and the ohmic contact islands 165 are
located in pairs on the projections 154 of the semiconductor
stripes 151.
[0153] The edge surfaces of the semiconductor stripes 151 and the
ohmic contacts 161 and 165 are tapered. The inclination angles of
the tapered edge surfaces of the semiconductor stripes 151 and the
ohmic contacts 161 and 165 are preferably in a range of about 30 to
about 80 degrees.
[0154] A plurality of data lines 171, a plurality of drain
electrodes 175, and a plurality of storage capacitor conductors 177
are formed on the ohmic contacts 161 and 165 and the gate
insulating layer 140.
[0155] The data lines 171 for transmitting data voltages extend
substantially in the longitudinal direction and intersect the gate
lines 121 to define pixel regions arranged in a matrix. A plurality
of branches of each data line 171, which extend toward the drain
electrodes 175, form a plurality of source electrodes 173. Each
pair of the source electrodes 173 and the drain electrodes 175 are
separated from each other, and are opposite to each other with
respect to a gate electrode 124.
[0156] A gate electrode 124, a source electrode 173, a drain
electrode 175, and a projection 154 of a semiconductor stripe 151,
together form a TFT having a channel formed in the projection 154
that is disposed between the source electrode 173 and the drain
electrode 175. The storage capacitor conductor 177 is overlapped
with the expansion 127 of the gate line 121.
[0157] The data lines 171, the drain electrode 175, and the storage
capacitor conductor 177 may be made of a metal such as Cr, Ti, Ag,
Mo, Ta, and an Al containing metal (Al, or Al-alloy). When the data
lines 171, the drain electrode 175, and the storage capacitor
conductor 177 include an Al containing metal layer, the data lines
171, the drain electrode 175, and the storage capacitor conductor
177 may further include another layer made of Cr, Ti, Ta, Mo, or an
alloy thereof having good physical, chemical, and electrical
contact characteristics with other materials such as indium tin
oxide (ITO) and indium zinc oxide (IZO).
[0158] The data lines 171, the drain electrodes 175, the storage
capacitor conductor 177 have tapered edge surfaces, and the
inclination angles of the edge surfaces are in a range of about 30
to about 80 degrees.
[0159] The ohmic contacts 161 and 165 are only arranged between the
semiconductor stripe 151 and the data line 171 and between the
drain electrode 175 and the projection 154 of the semiconductor
stripe 151 to reduce contact resistance therebetween. The
semiconductor stripe 151 is exposed at an area between the source
electrode 173 and the drain electrode 175 and at other areas not
covered with the data line 171 and the drain electrode 175. Most of
the semiconductor stripe 151 is narrower than the data line 171,
however, the semiconductor stripe 151 widens near an area where the
semiconductor stripe 151 and the gate line 121 meet each other in
order to prevent disconnection of the data line 171, as discussed
above.
[0160] According to an embodiment of the invention, the color
filters 230R, 230G, and 230B are formed on the data line 171, the
drain electrode 175, and the storage capacitor conductor 177. The
color filters 230R, 230G, and 230B are formed along pixel columns
that are partitioned by data lines 171. The red, green, and blue
color filters 230R, 230G, and 230B are activated in turn.
[0161] The color filters 230R, 230G, and 230B are not formed on the
end portions of the gate lines 121 and the data lines 171, which
are connected; e.g., coupled, with external circuits. Two adjacent
color filters 230R, 230G, and 230B overlap each other on the data
lines 171. Accordingly, the overlapped color fillers 230R, 230G,
and 230B prevents or substantially prevents light leakage that may
arise around a pixel area. All of the red, green, and blue color
filters 230R, 230G, and 230B may be arranged on the data line 171
to overlap each other.
[0162] A first interlayer insulating layer 801 is formed under the
color filters 230R, 230G, and 230B to prevent pigments of the color
filters 230R, 230G, and 230B from flowing or permeating into the
semiconductor protrusion 154. A second interlayer insulating layer
802 may be formed on the color filters 230R, 230G, and 230B to
prevent pigments of the color filters 230R, 230G, and 230B from
flowing into a liquid crystal layer (not illustrated).
[0163] The interlayer insulating layer 801 and 802 may be made of
an insulating material having a low dielectric constant such as
a-Si:C:O and a Si:O:F or SiNx.
[0164] As discussed above, when the color filters 230R, 230G, and
230B are arranged on the TFT array panel and overlap each other on
the data line 171, the opposite panel may only have a common
electrode. Accordingly, assembling of the TFT panel and opposite
panel is easy and the such arrangement increase aperture ratio.
[0165] In the second interlayer insulating layer 802, a plurality
of contact holes 185, 187, and 182 are formed to expose the drain
electrode 175, the storage capacitor conductor 177, and an end
portion of the data line 171, respectively.
[0166] A plurality of pixel electrodes 190 and a plurality of
contact assistants 82, which are made of IZO or ITO, are formed on
the second interlayer insulating layer 802.
[0167] Since the pixel electrode 190 is physically and electrically
connected; e.g., coupled, with the drain electrode 175 and the
storage capacitor conductor 177 through the contact holes 185 and
187, respectively, the pixel electrode 190 receives the data
voltage from the drain electrodes 175 and transmits the data
voltage to the storage capacitor conductor 177.
[0168] The pixel electrode 190 where the data voltage is applied
generates an electric field with a common electrode (not
illustrated) of the opposite panel (not illustrated) to which a
common voltage is applied, so that the liquid crystal molecules in
the liquid crystal layer are rearranged according to the applied
voltage.
[0169] The contact assistant 82 supplements adhesion between the
end portion of the data line 171 and the exterior devices, such as
the driving integrated circuit, and provides protection. The
contact assistant 82 is optional.
[0170] A method for manufacturing a TFT array panel is described
below with reference to FIGS. 15A, 16A, and 16B as well as FIG. 14A
and FIG. 14B.
[0171] Referring to FIG. 15A and FIG. 15B, a lower metal layer of
Al or Al alloy and an upper metal layer of Cu, which is thicker
than the lower metal layer, are formed on an insulating substrate
110 of glass by sputtering.
[0172] The upper metal layer and the lower metal layer are
simultaneously patterned to form a plurality of gate lines 121
having gate electrodes 124 and storage electrode lines 131. For
example, the lower metal layer and the upper metal layer may have a
thickness ratio of about 1:4. The upper and lower layers are
preferably etched using an etchant of H.sub.2O.sub.2 or an etchant
containing H.sub.2O.sub.2, phosphoric acid (H.sub.3PO.sub.4),
nitric acid (HNO.sub.3), acetic acid (CH.sub.3COOH), and deionized
water. The etchant may include about 50% to about 80% of phosphoric
acid, about 2% to about 10% of nitric acid, about 2% to about 15%
of acetic acid, and deionized water to fill the residual
quantity.
[0173] A gate insulating layer 140, a plurality of semiconductor
stripes 151, a plurality of ohmic contact assistants 161 and 165, a
plurality of data lines 171, and drain electrodes 175 are
sequentially formed on the gate lines 121.
[0174] Organic photo-resist materials respectively including
pigments of red, green, and blue are applied and patterned using a
photo process to sequentially form a plurality of color filters
230R, 230G, and 230B. For example, a first interlayer insulating
layer 801 made of an inorganic insulating material, such as SiNx or
SiO.sub.2, is formed on the data lines 171 and drain electrodes 175
before the color filters 230R, 230G, and 230B are formed. The first
interlayer insulating layer 801 prevents pigments of the color
filters 230R, 230G, and 230B from permeating or flowing into the
semiconductor protrusion 154. At this time, openings 235 and 237
exposing the drain electrode 175 and the storage capacitor
conductor 177 are simultaneously formed.
[0175] Referring to FIG. 16A and FIG. 16B, a second interlayer
insulating layer 802 is formed by coating an organic insulating
film having a low dielectric constant and a good flatness
characteristic, or by coating the PECVD of a low dielectric
insulating material, such as a-Si:C:O and a-Si:O:F, having a
dielectric constant less than about 4.0
[0176] The first interlayer insulating layer 801 and the second
interlayer insulating layer 802 are photo-etched to form a
plurality of contact holes 182, 185, and 187. The contact holes 185
and 187 exposing the drain electrodes 175 and the storage capacitor
conductor 177 are formed in the openings 235 and 237 of the color
filters 230R, 230G, and 230B
[0177] As shown in FIG. 14B, a plurality of pixel electrodes 190
and a plurality of contact assistants 82 are then formed thereon,
e.g., by sputtering and photo-etching an IZO layer or an ITO layer.
The pixel electrodes 190 are connected; e.g., coupled, with the
drain electrodes 175 and the storage capacitor conductor 177
through the contact holes 185 and 187.
[0178] A TFT panel for an active matrix organic light emitting
display (AM-OLED) according to another embodiment of the invention
is described below.
[0179] FIG. 17 is a layout view of a TFT array panel for an LCD
according to another embodiment of the invention. FIG. 18 and FIG.
19 are sectional views of the TFT array panel shown in FIG. 17
taken along the line XVIII-XVIII' and the line XIX-XIX',
respectively. FIG. 20 and FIG. 21 are sectional views of the TFT
array panel shown in FIG. 17 taken along the line XX-XX' and the
line XXI-XXI', respectively.
[0180] A plurality of gate conductors that include a plurality of
gate lines 121 including first gate electrodes 124a and a plurality
of second gate electrodes 124b are formed on an insulating
substrate 110, such as transparent glass.
[0181] The gate lines 121, transmitting gate signals, extend
substantially in a transverse direction and are separated from each
other. As shown, the first gate electrodes 124a extends upward. The
gate line 121 may extend to be connected; e.g., coupled, with a
driving circuit (not shown) integrated on the substrate 110, or the
gate line 121 may have an end portion (not shown) having a
sufficient area for connection with another layer or an external
driving circuit mounted or attached on the substrate 110 or on
another device, such as a flexible printed circuit film (not
shown), that may be attached with the substrate 110.
[0182] Each of the second gate electrodes 124b is separated from
the gate lines 121 and include a storage electrode 133 extending
substantially in a transverse direction between two adjacent gate
lines 121.
[0183] The gate lines 121, the first gate electrode 124a and the
second gate electrode 124b, and the storage electrode 133 have
lower layers 124ap and 124bp and upper layers 124aq and 124bq. The
lower layers 124ap and 124bp may be made of an Al containing metal
such as aluminum (Al) or aluminum-neodymium (Al--Nd). The upper
layers 124aq and 124bq may be made of Cu.
[0184] The upper layers 124aq and 124bq are thicker than the lower
layers 124ap and 124bp. For example, the upper layers 124aq and
124bq are preferably more than four times thicker than the lower
layers 124ap and 124bp when considering such properties as low
resistance, adhesiveness, and simultaneous etching.
[0185] The lateral sides of the gate conductors 121 and 124b are
inclined relative to a surface of the substrate 110 and the
inclination angle thereof ranges from about 30 degrees to about 80
degrees.
[0186] A gate insulating layer 140, which may be made of silicon
nitride (SiNx), is formed on the gate conductors 121 and 124b.
[0187] A plurality of semiconductor stripes 151 and islands 154b,
which may be made of hydrogenated amorphous silicon (abbreviated to
"a-Si") or polysilicon, are formed on the gate insulating layer
140. Each semiconductor stripe 151 extends substantially in the
longitudinal direction and has a plurality of projections 154a
extending toward the first gate electrodes 124a. Each semiconductor
island 154b crosses a second gate electrode 124b and includes a
portion 157 that overlaps the storage electrode 133 of the second
gate electrode 124b.
[0188] A plurality of ohmic contact stripes 161 and ohmic contact
islands 163b, 165a, and 165b, which may be made of silicide or n+
hydrogenated a-Si heavily doped with n type impurity such as
phosphorous, are formed on the semiconductor stripes 151 and
islands 154b. Each ohmic contact stripe 161 includes a plurality of
projections 163a, and the projections 163a and the ohmic contact
islands 165a are located in pairs on the projections 154a of the
semiconductor stripes 151. The ohmic contact islands 163b and 165b
are located in pairs on the semiconductor islands 154b and the
semiconductor islands 154b includes a portion 167 that overlaps the
storage electrode 133 of the second gate electrode 124b.
[0189] The lateral sides of the semiconductor stripes and islands
151 and 154b and the ohmic contacts 161, 163b, 165a, and 165b are
inclined relative to a surface of the substrate, and the
inclination angles thereof are preferably between about 30 degrees
to about 80 degrees.
[0190] A plurality of data conductors including a plurality of data
lines 171, a plurality of voltage transmission lines 172, and a
plurality of first drain electrodes 175a and second drain
electrodes 175b are formed on the ohmic contacts 161, 163b, 165b,
and 165b and the gate insulating layer 140.
[0191] The data lines 171 extend substantially in the longitudinal
direction and intersect the gate lines 121. Each data line 171
includes a plurality of first source electrodes 173a, an end
portion thereof having a sufficient area for contact with another
layer or an external device. The data lines 171 may be directly
connected; e.g., coupled, with a data driving circuit for
generating the gate signals, which may be integrated on the
substrate 110.
[0192] The voltage transmission lines 172 for transmitting driving
voltages extend substantially in the longitudinal direction and
intersect the gate lines 121. Each voltage transmission line 172
includes a plurality of second source electrodes 173b. The voltage
transmission lines 172 may be connected; e.g., coupled, with each
other. The voltage transmission lines 172 overlap the storage
region 157 of the semiconductor islands 154b.
[0193] The first drain electrode 175a and the second drain
electrode 175b are separated from the data lines 171 and the
voltage transmission lines 172 and from each other. Each pair of
the first source electrodes 173a and the first drain electrodes
175a are arranged opposite to each other with respect to a first
gate electrode 124a, and each pair of the second source electrodes
173b and the second drain electrodes 175b are arranged opposite to
each other with respect to a second gate electrode 124b.
[0194] A first gate electrode 124a, a first source electrode 173a,
a first drain electrode 175a, and a projection 154a of a
semiconductor stripe 151, together form a switching TFT having a
channel formed in the projection 154a arranged between the first
source electrode 173a and the first drain electrode 175a.
Meanwhile, a second gate electrode 124b, a second source electrode
173b, a second drain electrode 175b, and a semiconductor island
154b, together form a driving TFT having a channel formed in the
semiconductor island 154b arranged between the second source
electrode 173b and the second drain electrode 175b.
[0195] The data conductors 171, 172, 175a, and 175b are made of a
metal such as Cr, Mo, Al, Cu, and W. The data conductors 171, 172,
175a, and 175b have tapered lateral sides relative to the surface
of the substrate 110, and the inclination angles of the tapered
lateral sides range from about 30 degrees to about 80 degrees.
[0196] The ohmic contacts 161, 163b, 165b, and 165b are only
arranged between the underlying semiconductor stripes 151 and
islands 154b and the overlying data conductors 171, 172, 175a, and
175b thereon and reduce the contact resistance therebetween. The
semiconductor stripes 151 include a plurality of portions that are
not covered with the data conductors 171, 172, 175a, and 175b.
[0197] Most of the semiconductor stripe 151 is narrower than the
data line 171; however, the semiconductor stripe 151 widens near
where the semiconductor stripe 151 and the gate line 121 meet each
other in order to prevent disconnection of the data line 171, as
discussed above.
[0198] A passivation layer 180 may be formed on the data conductors
171, 172, 175a, and 175b and the exposed portions of the
semiconductor stripes 151 and islands 154b. The passivation layer
180 may preferably be made of an inorganic material, such as
silicon nitride or silicon oxide, a photosensitive organic material
having a good flatness characteristic, or a low dielectric
insulating material having a dielectric constant less than 4.0,
such as a-Si:C:O and a-Si:O:F, formed by plasma enhanced chemical
vapor deposition (PECVD). The passivation layer 180 may include a
lower layer of an inorganic insulator and an upper layer of an
organic insulator.
[0199] The passivation layer 180 includes a plurality of contact
holes 185, 183, 181, 182, and 189 exposing portions of the first
drain electrode 175a, a second gate electrode 124b, the second
drain electrodes 175b, and end portions 125 and 179 of the gate
line 121 and the data line 171, respectively.
[0200] The contact holes 182 and 189 expose the end portions 125
and 179 of the gate line 121 and the data line 171 to connect them
with external driving circuits. Anisotropic conductive films are
arranged between the output terminals of the external driving
circuit and the end portions 125 and 175 to assist with electrical
connection and physical adhesion. However, when driving circuits
are directly formed on the substrate 110, contact holes are not
formed. When gate driving circuits are directly formed on the
substrate 110 and data driving circuits are formed as separate
chips, only a contact hole 189 exposing the end portion 179 of the
data line 171 is formed.
[0201] A plurality of pixel electrodes 190, a plurality of
connecting members 192, and a plurality of contact assistants 196
and 198 are formed on the passivation layer 180.
[0202] The pixel electrodes 190 are connected; e.g., coupled, with
the second drain electrodes 175b through the contact holes 185. The
connecting member 192 connects the first drain electrode 175a with
the second gate electrode 124b through the contact holes 181 and
183. The contact assistants 196 and 198 are connected; e.g.,
coupled, with the end portions 196 and 198 of the gate line 121 and
the data line 171 through the contact holes 182 and 189,
respectively.
[0203] The pixel electrode 190, the connecting member 192, and the
contact assistants 196 and 198 may be made of a transparent
conductor material such as ITO or IZO.
[0204] A partition 803, an auxiliary electrode 272, a plurality of
light emitting members 70, and a common electrode 270 may be formed
on the passivation layer 180 and the pixel electrodes 190.
[0205] The partition 803 may be made of an organic or inorganic
insulating material and forms frames of organic light emitting
cells. The partition 803 may be formed along boundaries of the
pixel electrodes 190 and defines space for filling with an organic
light emitting material.
[0206] The light emitting member 70 is arranged on the pixel
electrode 190 and surrounded by the partition 803. The light
emitting member 70 may be made of one light emitting material that
emits a red light, a green light or a blue light. Red, green, and
blue light emitting members 70 are sequentially and repeatedly
disposed on the substrate.
[0207] The auxiliary electrode 272 has substantially the same
planar pattern as the partition 803. The auxiliary electrode 272
contacts the common electrode 270 to reduce resistance of the
common electrode 270.
[0208] The common electrode 270 is formed on the partition 803, the
auxiliary electrode 272, and the light emitting member 70. The
common electrode 270 is made of a metal having low resistance, such
as Al. This embodiment illustrates a back emitting OLED. However,
when a front emitting OLED or both sides emitting OLED is used, the
common electrode 270 may be made of a transparent conductor such as
ITO or IZO.
[0209] A method for manufacturing the TFT array panel shown in
FIGS. 17, 18, 19, 20, and 21 according to an embodiment of the
invention is described below, with reference to FIGS. 17-33B.
[0210] FIGS. 22, 24, 26, 28, 30, 32, and 34 are layout views of the
TFT array panel shown in FIGS. 17, 18, 19, 20, and 21 during
intermediate operations of a manufacturing method according to an
embodiment of the invention.
[0211] FIGS. 23A, 23B, and 23C are sectional views of the TFT array
panel shown in FIG. 22 taken along the lines XXIIIa-XXIIIa',
XXIIIb-XXIIIb', and XXIIIc-XXIIIc'. FIGS. 25A, 25B, and 25C are
sectional views of the TFT array panel shown in FIG. 24 taken along
the lines XXVa-XXVa', XXVb-XXVb', and XXVc-XXVc'. FIGS. 27A, 27B,
27C, and 27D are sectional views of the TFT array panel shown in
FIG. 26 taken along the lines XXVIIa-XXVIIa', XXVIIb-XXVIIb',
XXVIIc-XXVIIc', and XXVIId-XXVIId'. FIGS. 29A, 29B, 29C, and 29D
are sectional views of the TFT array panel shown in FIG. 28 taken
along the lines XXIXa-XXIXa', XXIXb-XXIXb', XXIXc-XXIXc', and
XXIXd-XXIXd'. FIGS. 31A, 31B, 31C, and 31D are sectional views of
the TFT array panel shown in FIG. 30 taken along the lines
XXXIa-XXXIa', XXXIb-XXXIb', XXXIc-XXXIc', and XXXId-XXXId'. FIGS.
33A and 33B are sectional views of the TFT array panel shown in
FIG. 32 taken along the lines XXXIIIa-XXXIIIa' and
XXXIIIb-XXXIIIb'.
[0212] As shown in FIGS. 22, 23A, 23B, and 23C, gate metal layers
are deposited on a substrate. The metal layers may be deposited
using a Co-sputtering technique, wherein two targets may be
installed in a same sputtering chamber. One of the targets may be
made of Al or Al--Nd, and the other target is made of Cu.
[0213] A lower metal layer, which may be made of Al or an Al alloy,
and an upper metal layer, which may be made of Cu and is thicker
than the lower metal layer, are formed on an insulating substrate
110, which may be made of glass, by a Co-sputtering technique. For
example, the upper metal layer may be about 2,000 .ANG. thick and
the lower metal layer may be about 300 .ANG. thick.
[0214] The upper metal layer and lower metal layer are then
simultaneously patterned to form a plurality of gate lines 121
having a plurality of first gate electrodes 124a, a plurality
second electrodes 124b, and storage electrodes 133. For example,
the upper layer and the lower layer are preferably etched by an
etchant of H.sub.2O.sub.2 or an etchant containing H.sub.2O.sub.2,
phosphoric acid (H.sub.3PO.sub.4), nitric acid (HNO.sub.3), acetic
acid (CH.sub.3COOH), and deionized water. Specially, the etchant
may include about 50% to about 80% of phosphoric acid, about 2% to
about 10% of nitric acid, about 2% to about 15% of acetic acid, and
deionized water to fill the residual quantity.
[0215] Referring to FIGS. 25, 26A, 26B, and 26C, after sequential
deposition of a gate insulating layer 140, an intrinsic a-Si layer,
and an extrinsic a-Si layer, the extrinsic a-Si layer and the
intrinsic a-Si layer are photo-etched to form a plurality of
extrinsic semiconductor stripes 164 and a plurality of intrinsic
semiconductor stripes 151 and islands 154b including projections
154a on the gate insulating layer 140. For example, the gate
insulating layer 140 is preferably made of silicon nitride with a
thickness of about 2,000 .ANG. to about 5,000 .ANG., and the
deposition temperature is preferably in a range of about
250.degree. C. to about 500.degree. C.
[0216] Referring to FIGS. 26, 27A, 27B, 27C, and 27D, a first layer
of Mo-alloy, a second layer of Al (or Al-alloy), and a third layer
of Mo-alloy are sequentially deposited on the extrinsic
semiconductor stripes 164 by a Co-sputtering technique. The first
and third layers may be made of a molybdenum alloy (Mo-alloy),
which is composed of molybdenum (Mo) and at least one of niobium
(Nb), vanadium (V), and titanium (Ti). The three layers are etched
using a photoresist (not shown) to form a plurality of data
conductors that include a plurality of data lines 171 including
first source electrodes 173a, a plurality of voltage transmission
lines 172 including second source electrodes 173b, and a plurality
of first and second drain electrodes 175a and 175b.
[0217] Before or after removing the photoresist, portions of the
extrinsic semiconductor stripes 164, which are not covered with the
data conductors 171, 172, 175a, and 175b, are removed by etching to
complete a plurality of ohmic contact stripes 161 including
projections 163a and a plurality of ohmic contact islands 163b,
165a, and 165b, and to expose portions of the intrinsic
semiconductor stripes 151 and islands 154b.
[0218] Oxygen plasma treatment may then be performed to stabilize
the exposed surfaces of the semiconductor stripes 151.
[0219] Referring to FIGS. 28, 29A, 29B, 29C, and 29D, a passivation
layer 180 is deposited and patterned to form a plurality of contact
holes 189, 185, 183, 181, and 182 exposing the first drain
electrode 175A and the second drain electrode 175b, the second gate
electrodes 124b, and the end portion 179 of the data line 171.
[0220] Referring to FIGS. 31, 32a, 32b, 32c, and 32d, a plurality
of pixel electrodes 190, a plurality of connecting members 192, and
contact assistants 196 and 198 are formed on the passivation layer
180 with ITO or IZO.
[0221] Referring to FIGS. 33a, 33b, 34, 35, and 36, a partition 803
and an auxiliary electrode 272 are formed by using a single
photolithography operation.
[0222] A plurality of organic light emitting members 70, preferably
including multiple layers, may then be formed in the openings by
deposition or inkjet printing following a masking, and a common
electrode 270 may then be formed as shown in FIGS. 22, 23A, 23B,
23C, and 24.
[0223] As discussed above, the invention provides TFT array panels
having gate lines that include a lower layer of an Al containing
metal and an upper layer of a Cu containing metal that is thicker
than the lower layer. Such gate lines have low resistance and
strong adhesiveness to the substrate. Since the lower layer of the
Al containing metal and the upper layer of the Cu containing metal
may be simultaneously etched by an etching process, a manufacturing
process of the TFT array panel is simplified.
[0224] It will be apparent to those skilled in the art that various
modifications and variation can be made in the present invention
without departing from the spirit or scope of the invention. Thus,
it is intended that the present invention cover the modifications
and variations of this invention provided they come within the
scope of the appended claims and their equivalents.
* * * * *