U.S. patent application number 11/949515 was filed with the patent office on 2008-06-12 for liquid crystal display.
Invention is credited to Dong-Gyu Kim.
Application Number | 20080136759 11/949515 |
Document ID | / |
Family ID | 39497390 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080136759 |
Kind Code |
A1 |
Kim; Dong-Gyu |
June 12, 2008 |
LIQUID CRYSTAL DISPLAY
Abstract
A liquid crystal display includes: a plurality of pixel
electrodes each having a first sub-pixel electrode and a second
sub-pixel electrode that face each other in a diagonal direction; a
plurality of gate lines; and a plurality of data lines that
intersect the plurality of gate lines and at least partially
overlap the pixel electrodes.
Inventors: |
Kim; Dong-Gyu; (Yongin-si,
KR) |
Correspondence
Address: |
MACPHERSON KWOK CHEN & HEID LLP
2033 GATEWAY PLACE, SUITE 400
SAN JOSE
CA
95110
US
|
Family ID: |
39497390 |
Appl. No.: |
11/949515 |
Filed: |
December 3, 2007 |
Current U.S.
Class: |
345/87 |
Current CPC
Class: |
G09G 2300/0417 20130101;
G02F 1/134345 20210101; G02F 1/134309 20130101; G09G 2300/0491
20130101; G02F 1/1395 20130101; G09G 3/3614 20130101; G09G 3/3651
20130101; G02F 1/136286 20130101 |
Class at
Publication: |
345/87 |
International
Class: |
G09G 3/36 20060101
G09G003/36 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 11, 2006 |
KR |
10-2006-0125428 |
Claims
1. A liquid crystal display comprising: a plurality of pixel
electrodes each having a first sub-pixel electrode and a second
sub-pixel electrode that face each other in a diagonal direction
and are connected to each other; a plurality of gate lines; and a
plurality of data lines that intersect the plurality of gate lines
and at least partially overlap the pixel electrodes.
2. The liquid crystal display of claim 1, wherein each of the first
and second sub-pixel electrodes comprises first and second edges
that are parallel to the gate line and third and fourth edges that
are parallel to the data line.
3. The liquid crystal display of claim 1, further comprising a
plurality of thin film transistors connected to the gate lines, the
data lines, and the pixel electrodes.
4. The liquid crystal display of claim 3, wherein each data line
comprises a first data line connected to the pixel electrodes
through the thin film transistors, and second and third data lines
that are adjacent to the first data line, respectively.
5. The liquid crystal display of claim 4, wherein the pixel
electrode overlaps the first to third data lines.
6. The liquid crystal display of claim 5, wherein the first data
line overlaps both the first and second sub-pixel electrodes, the
second data line overlaps the first sub-pixel electrodes, and the
third data line overlaps the second sub-pixel electrodes.
7. The liquid crystal display of claim 6, wherein data voltages
having the same polarity are applied to the second and third data
lines, and the polarity of the data voltage applied to the first
data line is opposite to that applied to the second and third data
lines.
8. The liquid crystal display of claim 3, wherein the plurality of
thin film transistors connected to the pixel electrodes that are
adjacent in the column direction are alternately disposed at both
sides of the data line.
9. The liquid crystal display of claim 1, further comprising an
organic film formed between the pixel electrodes and the data
lines.
10. The liquid crystal display of claim 3, further comprising
storage electrode lines that overlap the pixel electrodes.
11. The liquid crystal display of claim 10, wherein an opening is
formed in the organic film at a position where the storage
electrode line overlaps the pixel electrode.
12. The liquid crystal display of claim 10, wherein the thin film
transistor comprises a drain electrode connected to the pixel
electrode, and at least a portion of the drain electrode overlaps
the storage electrode line.
13. The liquid crystal display of claim 1, further comprising a
plurality of color filters that are formed between the pixel
electrodes and the data lines.
14. The liquid crystal display of claim 10, wherein an opening is
formed in the color filter at a position where the storage
electrode line overlaps the pixel electrode.
15. The liquid crystal display of claim 1, further comprising: a
common electrode that faces the pixel electrodes; and a liquid
crystal layer interposed between the pixel electrodes and the
common electrode, wherein liquid crystal molecules in the liquid
crystal layer are aligned in parallel with the pixel electrodes and
the common electrode when no electric field is applied.
16. The liquid crystal display of claim 1, further comprising: a
common electrode that faces the pixel electrodes; and a liquid
crystal layer interposed between the pixel electrodes and the
common electrode, wherein liquid crystal molecules in the liquid
crystal layer are aligned in a splay alignment mode when no
electric field is applied, and are aligned in a bend alignment mode
when the electric field is applied.
17. A liquid crystal display comprising: a plurality of pixel
electrodes; a plurality of gate lines that transmit gate signals to
the pixel electrodes; and a plurality of data lines that intersect
the gate lines and transmit data voltages to the pixel electrodes,
wherein the data line overlaps the pixel electrodes and comprises a
first portion that lies on a first imaginary straight line and a
second portion that lies on a second imaginary straight line
separated from and parallel to the first imaginary straight
line.
18. The liquid crystal display of claim 17, wherein the first and
second portions overlap different pixel electrodes.
19. The liquid crystal display of claim 17, wherein each pixel
electrode comprises first and second edges that are parallel to the
gate lines and third and fourth edges that are parallel to the data
lines.
20. The liquid crystal display of claim 17, further comprising a
plurality of storage electrode lines that overlap the pixel
electrodes.
21. The liquid crystal display of claim 20, further comprising a
light blocking member disposed between adjacent pixel
electrodes.
22. The liquid crystal display of claim 21, wherein the light
blocking member comprises a first light blocking member that is
adjacent to the first portion of the data line and a second light
blocking member that is adjacent to the second portion of the data
line.
23. The liquid crystal display of claim 22, wherein the first light
blocking member is separated from the second light blocking member,
and the first light blocking member is connected to the storage
electrode line.
24. The liquid crystal display of claim 20, wherein the light
blocking member is formed of the same material as the storage
electrode line.
25. The liquid crystal display of claim 17, further comprising an
organic film formed between the pixel electrodes and the data
lines.
26. The liquid crystal display of claim 25, wherein an opening is
formed in the organic film at a position where the storage
electrode line overlaps the pixel electrode.
27. The liquid crystal display of claim 17, further comprising a
plurality of color filters that are formed between the pixel
electrodes and the data lines.
28. The liquid crystal display of claim 27, wherein an opening is
formed in the color filter at a position where the storage
electrode line overlaps the pixel electrode.
29. The liquid crystal display of claim 17, further comprising a
plurality of thin film transistors connected to the gate lines, the
data lines, and the pixel electrodes, wherein the plurality of thin
film transistors connected to the pixel electrodes that are
adjacent in the column direction are alternately disposed at both
sides of the data line.
30. The liquid crystal display of claim 17, wherein data voltages
having opposite polarities are applied to the two adjacent data
lines.
31. The liquid crystal display of claim 17, further comprising: a
common electrode that faces the pixel electrodes; and a liquid
crystal layer interposed between the pixel electrodes and the
common electrode, wherein liquid crystal molecules in the liquid
crystal layer are aligned in parallel with the pixel electrodes and
the common electrodes when no electric field is applied.
32. The liquid crystal display of claim 17, further comprising: a
common electrode that faces the pixel electrodes; and a liquid
crystal layer interposed between the pixel electrodes and the
common electrode, wherein liquid crystal molecules in the liquid
crystal layer are aligned in a splay alignment mode when no
electric field is applied, and are aligned in a bend alignment mode
when the electric field is applied.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to and the benefit of
Korean Patent Application No. 10-2006-0125428 filed in the Korean
Intellectual Property Office on Dec. 11, 2006, the entire contents
of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a liquid crystal
display.
[0004] 2. Description of the Related Art
[0005] Liquid crystal displays are now the most widely used of the
flat panel displays. The liquid crystal displays have two display
panels on which electric field generating electrodes such as pixel
electrodes and a common electrode are formed, and a liquid crystal
layer interposed between the panels. In the liquid crystal
displays, a voltage is applied to the electric field generating
electrodes so as to generate an electric field in the liquid
crystal layer. The alignment of liquid crystal molecules of the
liquid crystal layer is determined by the electric field.
Accordingly, the polarization of incident light is controlled,
thereby providing image display.
[0006] The liquid crystal displays also include switching elements
connected to the individual pixel electrodes and a plurality of
signal lines, such as gate lines and data lines, for controlling
the switching elements so as to apply voltages to the pixel
electrodes.
[0007] In order to prevent a degradation phenomenon that occurs
when the electric field is applied in the liquid crystal layer in
one direction for a long time, polarities of the data voltage with
respect to a common voltage are inverted for every frame, every
row, or every pixel.
[0008] In these liquid crystal displays, a high-speed driving
method is used so as to improve a motion picture display
characteristic. However, because high-speed driving requires a
larger amount of electric power as the frame speed increases,
column inversion is used once per frame to minimize power
consumption.
[0009] However, the column inversion causes a coupling defect and a
stripe defect. Parasitic capacitance arising from an overlap
between the data lines and the pixel electrodes causes a data
voltage having the same polarity to be continuously applied
throughout a frame, thereby generating a coupling defect that
causes the upper and lower parts of the display panel of the liquid
crystal panel assembly to display images with different luminances.
In particular, if a box having a high grayscale level is displayed
on a background image having a low grayscale level, a vertical
crosstalk phenomenon may occur such that the upper portion and the
lower portion of the box have grayscales different from the
background image.
[0010] The stripe defect refers to a phenomenon in which stripes
appear when a data voltage having the same polarity is applied in a
vertical direction so that a data voltage having a positive
polarity creates an image that is different from a data voltage
having a negative polarity.
SUMMARY OF THE INVENTION
[0011] An exemplary embodiment of the present invention provides a
liquid crystal display that prevents the coupling defect and the
stripe defect comprising: a plurality of pixel electrodes each
having a first sub-pixel electrode and a second sub-pixel electrode
that face each other in a diagonal direction and are connected to
each other; a plurality of gate lines; and a plurality of data
lines that intersect the plurality of gate lines and at least
partially overlap the pixel electrodes.
[0012] Each of the first and second sub-pixel electrodes may
include first and second edges that are parallel to the gate line,
and third and fourth edges that are parallel to the data line.
[0013] The liquid crystal display may further include a plurality
of thin film transistors connected to the gate lines, the data
lines, and the pixel electrodes.
[0014] The data lines may include a first data line connected to
the pixel electrodes through the thin film transistors and second
and third data lines that are adjacent to the first data line, and
the pixel electrodes may overlap all of the first to third data
lines.
[0015] The first data line may overlap both the first and second
sub-pixel electrodes, the second data line may overlap the first
sub-pixel electrodes, and the third data line may overlap the
second sub-pixel electrodes.
[0016] Data voltages having the same polarity may be applied to the
second and third data lines, and the polarity of the data voltage
applied to the first data line may be opposite to that of the data
voltage applied the second and third data lines.
[0017] The plurality of thin film transistors connected to the
pixel electrodes that are adjacent in the column direction may be
alternately disposed at both sides of the data line.
[0018] The liquid crystal display may further include an organic
film formed between the pixel electrodes and the data lines.
[0019] The liquid crystal display may further include storage
electrode lines that overlap the pixel electrodes.
[0020] An opening may be formed in the organic film at a position
where each storage electrode line overlaps a pixel electrode.
[0021] Each thin film transistor may include a drain electrode
connected to the pixel electrode, and at least a portion of the
drain electrode may overlap the storage electrode line.
[0022] The liquid crystal display may further include a plurality
of color filters that are formed between the pixel electrodes and
the data lines.
[0023] An opening may be formed in each color filter at a position
where the storage electrode line overlaps the pixel electrode.
[0024] The liquid crystal display may further include a common
electrode that faces the pixel electrodes, and a liquid crystal
layer interposed between the common electrode and the pixel
electrodes. The liquid crystal molecules in the liquid crystal
layer may be arranged in parallel with the pixel electrodes and the
common electrodes when no electric field is applied.
[0025] The liquid crystal display may further include a common
electrode that faces the pixel electrodes, and a liquid crystal
layer interposed between the common electrode and the pixel
electrodes. The liquid crystal molecules in the liquid crystal
layer may be aligned in a splay alignment mode when no electric
field is applied, and aligned in a bend alignment mode when the
electric field is generated.
[0026] Another embodiment of the present invention provides a
liquid crystal display including: a plurality of pixel electrodes;
a plurality of gate lines that transmit gate signals to the pixel
electrodes; and a plurality of data lines that intersect the gate
lines and transmit data voltages to the pixel electrodes. Each data
line overlaps a pixel electrode and includes a first portion that
lies on a first imaginary straight line and a second portion that
lies on a second imaginary straight line which is separated from
and parallel to the first imaginary straight line.
[0027] The first and second portions of the data lines may overlap
different pixel electrodes.
[0028] The pixel electrode may include first and second edges that
are parallel to the gate lines, and third and fourth edges that are
parallel to the data lines.
[0029] The liquid crystal display may further include a plurality
of storage electrode lines that overlap the pixel electrodes.
[0030] The liquid crystal display may further include a light
blocking member disposed between adjacent pixel electrodes.
[0031] The light blocking member may include a first light blocking
member that is adjacent to the first portion of the data line and a
second light blocking member that is adjacent to the second portion
of the data line.
[0032] The first light blocking member may be separated from the
second light blocking member, and the first light blocking member
may be connected to the storage electrode line.
[0033] The light blocking member may be formed of the same material
as the storage electrode line.
[0034] The liquid crystal display may further include an organic
film formed between the pixel electrodes and the data lines.
[0035] An opening may be formed in the organic film at a position
where the storage electrode line overlaps the pixel electrode.
[0036] The liquid crystal display may further include a plurality
of color filters that are formed between the pixel electrodes and
the data lines.
[0037] An opening may be formed in the color filter at a position
where the storage electrode line overlaps the pixel electrode.
[0038] The liquid crystal display may further include a plurality
of thin film transistors connected to the gate lines, the data
lines, and the pixel electrodes. The plurality of thin film
transistors connected to the pixel electrodes that are adjacent in
the column direction may be alternately disposed at both sides of
the data line.
[0039] Data voltages having opposite polarities may be applied to
the two adjacent data lines.
[0040] The liquid crystal display may further include a common
electrode that faces the pixel electrodes, and a liquid crystal
layer interposed between the common electrode and the pixel
electrodes. The liquid crystal molecules in the liquid crystal
layer may be arranged in parallel with the pixel electrodes and the
common electrodes when no electric field is applied.
[0041] The liquid crystal display may further include a common
electrode that faces the pixel electrodes, and a liquid crystal
layer interposed between the common electrode and the pixel
electrodes. The liquid crystal molecules in the liquid crystal
layer may be aligned in a splay alignment mode when no electric
field is applied, and aligned in a bend alignment mode when the
electric field is generated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] FIG. 1 is a block diagram of a liquid crystal display
according to an exemplary embodiment of the present invention.
[0043] FIG. 2 is an equivalent circuit diagram of one pixel in the
liquid crystal display according to the exemplary embodiment of the
present invention.
[0044] FIG. 3 is a view illustrating the spatial alignment of the
pixels and signal lines of the liquid crystal panel assembly
according to the exemplary embodiment of the present invention.
[0045] FIG. 4 is a layout view of the liquid crystal panel assembly
according to the exemplary embodiment of the present invention.
[0046] FIGS. 5 and 6 are cross-sectional views of the liquid
crystal panel assembly of FIG. 4 taken along the lines V-V and
VI-VI.
[0047] FIG. 7 is a layout view illustrating an alignment error
occurring in the manufacturing process of the liquid crystal
display shown in FIG. 4.
[0048] FIG. 8 is a layout view of a liquid crystal panel assembly
according to another exemplary embodiment of the present
invention.
[0049] FIG. 9 is a layout view of a liquid crystal panel assembly
according to another exemplary embodiment of the present
invention.
[0050] FIG. 10 is a cross-sectional view of the liquid crystal
panel assembly shown in FIG. 9 taken along the line IX-IX.
[0051] FIG. 11 is a view illustrating an alignment state of the
liquid crystal molecules of a liquid crystal display according to
another exemplary embodiment of the present invention before a
predetermined voltage is applied.
[0052] FIG. 12 is a view illustrating an alignment state of the
liquid crystal molecules of a liquid crystal display according to
another exemplary embodiment of the present invention after the
predetermined voltage is applied.
[0053] FIG. 13 is a layout view illustrating an alignment error
occurring in the liquid crystal panel assembly shown in FIG. 9.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0054] In the drawings, the thickness of layers, films, panels,
regions, etc., are exaggerated for clarity. It will be understood
that when an element such as a layer, film, region, or substrate is
referred to as being "on" another element, it can be directly on
the other element or intervening elements may also be present. In
contrast, when an element is referred to as being "directly on"
another element, there are no intervening elements present.
[0055] First, a liquid crystal display according to an exemplary
embodiment of the present invention will be described in detail
with reference to FIGS. 1 and 2.
[0056] FIG. 1 is a block diagram of a liquid crystal display
according to an exemplary embodiment of the present invention, and
FIG. 2 is an equivalent circuit diagram of one pixel in a liquid
crystal display according to an exemplary embodiment of the present
invention.
[0057] Referring to FIG. 1, a liquid crystal display according to
an exemplary embodiment of the present invention includes a liquid
crystal panel assembly 300, a gate driver 400, a data driver 500, a
gray voltage generator 800, and a signal controller 600.
[0058] In an equivalent circuit, the liquid crystal panel assembly
300 includes a plurality of signal lines G.sub.1 to G.sub.n and
D.sub.1 to D.sub.m, and a plurality of pixels PX that are connected
to the plurality of signal lines and are arranged approximately in
a matrix. Referring to the structure shown in FIG. 2, the liquid
crystal panel assembly 300 includes lower and upper display panels
100 and 200 that face each other, and a liquid crystal layer 3 that
is interposed between the lower and upper display panels 100 and
200.
[0059] The signal lines G.sub.1 to G.sub.n and D.sub.1 to D.sub.m
include a plurality of gate lines G.sub.1 to G.sub.n that transmit
gate signals (also referred to as "scanning signals"), and a
plurality of data lines D.sub.1 to D.sub.m that transmit data
signals. The gate lines G.sub.1 to G.sub.n substantially extend in
a row direction and are in parallel with one another, and the data
lines D.sub.1 to D.sub.m substantially extend in a column direction
and are in parallel with one another.
[0060] For example, the pixel PX connected to an i-th gate line Gi
(i=1, 2, . . . , n) and a j-th data line Gj (j=1, 2, . . . , m)
includes a switching element Q and a liquid crystal capacitor Clc,
and a storage capacitor Cst connected thereto. The storage
capacitor Cst may be omitted if necessary
[0061] The switching element Q is a three terminal element such as
a thin film transistor that is provided in the lower display panel
100. A control terminal thereof is connected to the gate line Gi,
an input terminal thereof is connected to a data line Dj, and an
output terminal is connected to the liquid crystal capacitor Clc
and the storage capacitor Cst.
[0062] The liquid crystal capacitor Clc includes a pixel electrode
191 of the lower display panel 100 and a common electrode 270 of
the upper 20 display panel 200 as two terminals, and the liquid
crystal layer 3 between the two electrodes 191 and 270 functions as
a dielectric. The pixel electrode 191 is connected to the switching
element Q, and the common electrode 270 is formed on the entire
surface of the upper display panel 200 and has a common voltage
Vcom applied therewith. Unlike the structure shown in FIG. 2, the
common electrode 270 may be provided on the lower display panel
100, and in this case, at least one of the two electrodes 191 and
270 may be formed in a linear or rod shape.
[0063] The storage capacitor Cst that supplements the liquid
crystal Clc is formed such that an additional signal line (not
shown) provided in the lower display panel 100 and the pixel
electrode 191 overlaps an insulating material interposed
therebetween. The additional signal line is supplied with a
predetermined voltage such as a common voltage Vcom. However, the
storage capacitor Cst may be formed by overlapping the pixel
electrode 191 and a previous gate line formed directly on the pixel
electrode with the insulating material therebetween.
[0064] To provide a color display, each pixel PX displays one of
the primary colors (spatial division), or the pixels PX alternately
display the primary colors with time (temporal division), which
causes the primary colors to be spatially and temporally
synthesized, thereby displaying a desired color. The primary colors
may be composed of, for example, red, green, and blue. As an
example of the spatial division, FIG. 2 shows that each pixel PX
has a color filter 230 for displaying one of the primary colors in
a region of the upper display panel 200 corresponding to the pixel
electrode 191. Unlike the structure shown in FIG. 2, the color
filter 230 may be provided above or below the pixel electrode 191
of the lower display panel 100.
[0065] At least one polarizer (not shown) for polarizing light is
mounted on an outer surface of the liquid crystal panel assembly
300.
[0066] Referring to FIG. 1 again, the gray voltage generator 800
generates all gray voltages related to the transmittance of the
pixel PX, or a limited number of gray voltages (hereinafter,
referred to as "reference gray voltages"). However, the gray
voltage generator 800 may generate only a given number of gray
voltages (referred to as reference gray voltages) instead of
generating all of the gray voltages. The (reference) gray voltages
may have a positive value with respect to the common voltage Vcom
and a 10 negative value with respect to the common voltage
Vcom.
[0067] The gate driver 400 is connected to the gate lines G.sub.1
to G.sub.n of the liquid crystal panel assembly 300, and supplies
gate signals each of which is composed of a combination of a
gate-on voltage Von and a gate-off voltage Voff to the gate lines
G.sub.1 to G.sub.n.
[0068] The data driver 500 is connected to the data lines D.sub.1
to D.sub.m of the liquid crystal panel assembly 300, selects the
gray voltage generated by the gray voltage generator 800, and
supplies the selected gray voltage to the data lines D.sub.1 to
D.sub.m as a data voltage. However, when the gray voltage generator
800 does not supply all of the gray voltages, but supplies only a
predetermined number of reference gray voltages, the data driver
500 divides the reference gray voltage to select a desired data
voltage from the generated gray voltages.
[0069] The signal controller 600 controls, for example, the gate
driver 400 and the data driver 500.
[0070] Each of the drivers 400, 500, 600, and 800 may be directly
mounted on the liquid crystal panel assembly 300 in the form of at
least one IC chip, may be mounted on a flexible printed circuit
film (not shown) and then mounted on the liquid crystal panel
assembly 300 in the form of a TCP (tape carrier package), or may be
mounted on a separate printed circuit board (not shown).
Alternatively, the drivers 400, 500, 600, and 800 may be integrated
into the liquid crystal panel assembly 300 together with, for
example, the signal lines G.sub.1 to G.sub.n and D.sub.1 to D.sub.m
and the thin film transistor switching elements Q. The drivers 400,
500, 600, and 800 may be integrated into a single chip. In this
case, at least one of the drivers or at least one circuit forming
the drivers may be arranged outside the single chip.
[0071] Hereinafter, the operation of the liquid crystal display
will be described in detail.
[0072] The signal controller 600 receives input image signals R, G,
and B and input control signals for displaying the input image
signals from an external graphics controller (not shown). The input
image signals R, G, and B include luminance information of each
pixel PX, and the luminance has a predetermined number of grayscale
levels, for example 1024 (=2.sup.10), 256 (=2.sup.8), or 64
(=2.sup.6) levels. For example, any of the following signals may be
used as the input control signal: a vertical synchronization signal
Vsync, a horizontal synchronization signal Hsync, a main clock
signal MCLK, and a data enable signal DE.
[0073] The signal controller 600 processes the input image signals
R, G, and B so as to be suitable for the operational conditions of
the liquid crystal panel assembly 300 on the basis of the input
image signals R, G, and B and the input control signal, and
generates, for example, a gate control signal CONT1 and a data
control signal CONT2. Then, the signal controller 600 transmits the
gate control signal CONT1 to the gate driver 400 and transmits the
data control signal CONT2 and the processed image signal DAT to the
data driver 500.
[0074] The gate control signal CONT1 includes a scanning start
signal STV for indicating the start of scanning, and at least one
clock signal for controlling the output cycle of the gate-on
voltage Von. The gate control signal CONT1 may further include an
output enable signal OE for defining the duration of the gate-on
voltage Von.
[0075] The data control signal CONT2 includes a horizontal
synchronization start signal STH for indicating that the
transmission of data to a row of pixels PX starts, a load signal
LOAD for allowing data voltages to be transmitted to the data lines
D.sub.1 to D.sub.m, and a data clock signal HCLK. The data control
signal CONT2 may further include an inversion signal RVS for
inverting the polarity of the data voltage with respect to the
common voltage Vcom (hereinafter, "the polarity of data voltage
with respect to the common voltage" is simply referred to as "the
polarity of a data voltage").
[0076] The data driver 500 receives the digital image signal DAT
for a row of pixels PX in response to the data control signal CONT2
transmitted from the signal controller 600, selects a gray voltage
corresponding to each digital image signal DAT, converts the
digital image signal DAT into an analog data signal, and supplies
the analog data signal to the corresponding data lines D.sub.1 to
D.sub.m.
[0077] The gate driver 400 applies the gate-on voltage Von to the
gate lines G.sub.1 to G.sub.n on the basis of the gate control
signal CONT1 from the signal controller 600 to turn on the
switching elements Q connected to the gate lines G.sub.1 to
G.sub.n. Then, the data voltages applied to the data lines D.sub.1
to D.sub.m are supplied to the corresponding pixels PX through the
switching elements Q that are in an on state.
[0078] The difference between the voltage of the data voltage
applied to the pixel PX and the common voltage Vcom is a charging
voltage of the liquid crystal capacitor Clc, that is, a pixel
voltage. The alignment directions of liquid crystal molecules
depend on the level of the pixel voltage, and cause the
polarization of light passing through the liquid crystal layer 3 to
vary. The variation in polarization causes a variation in the
transmittance of light by the polarizer mounted on the liquid
crystal panel assembly 300. Therefore, the pixel PX may display the
luminance indicated by the grayscale level of the image signal
DAT.
[0079] These processes are repeatedly performed for every one
horizontal period (which is referred to as "1H" and is equal to one
period of the horizontal synchronization signal Hsync and the data
enable signal DE). In this way, the gate-on voltage Von is
sequentially applied to all the gate lines G.sub.1 to G.sub.n, and
the data signals are supplied to all the pixels PX, thereby
displaying one frame of images.
[0080] When one frame has ended, the next frame starts. In this
case, the state of the inversion signal RVS applied to the data
driver 500 is controlled such that the polarity of the data voltage
applied to each pixel PX is opposite to the polarity of the data
voltage in the previous frame ("frame inversion"). The polarity of
the data signal applied to one data line may be inverted in the
same frame according to the characteristic of the inversion signal
RVS (for example, row inversion and dot inversion), and the
polarities of the data voltages to be applied to a row of pixels
may be different from each other (for example, column inversion and
dot inversion).
[0081] The alignment of the pixels and the signal lines of the
liquid crystal panel assembly will be described in detail with
reference to FIG. 3.
[0082] FIG. 3 is a view illustrating the spatial alignment of the
pixels and the signal lines of the liquid crystal panel assembly
according to the exemplary embodiment of the present invention.
[0083] For better comprehension and ease of description, only some
of the data lines D.sub.1 to D.sub.7 and some of the gate lines
G.sub.j-1 to G.sub.j+2 are shown.
[0084] Referring to FIG. 3, a row of pixels PX is connected to the
gate lines G.sub.j-1 to G.sub.j+2 and the data lines D.sub.1 to
D.sub.7 through the switching elements Q. In the pixels PX disposed
in the same row, all the pixels disposed in first and third rows
are connected to the data lines D.sub.2, D.sub.4, and D.sub.6 on
the right sides of the pixels PX, and all the pixels disposed on
second and fourth rows are connected to the data lines D.sub.1,
D.sub.3, D.sub.5, and D.sub.7 on the left sides of the pixels
PX.
[0085] The pixels PX disposed in the same column are alternatively
connected to the data lines D.sub.1 to D.sub.7 on the right and
left sides of the pixels PX.
[0086] Further, data voltages having opposite polarities are
applied to every two adjacent data lines D.sub.1 to D.sub.7. That
is, the polarity of the data voltage to be applied to odd-numbered
data lines D.sub.1, D.sub.3, D.sub.5, and D.sub.7 are positive and
the polarity of the data voltage to be applied to even-numbered
data lines D.sub.2, D.sub.4, to D.sub.6 are negative.
[0087] Therefore, positive and negative data voltages are
alternatively applied to the pixels PX (hereinafter, referred to as
"pixel polarity"), which causes dot inversion thereby preventing
the stripe defect from occurring.
[0088] Hereinafter, the liquid crystal panel assembly according to
the exemplary embodiment of the present invention will be described
in detail with reference to FIGS. 4 to 6.
[0089] FIG. 4 is a layout view of the liquid crystal panel assembly
according to the exemplary embodiment of the present invention.
FIGS. 5 and 6 are cross-sectional views of the liquid crystal panel
assembly of FIG. 4 taken along the lines V-V and VI-VI.
[0090] Referring to FIGS. 4 to 6, the liquid crystal panel assembly
according to the exemplary embodiment of the present invention
includes a lower display panel 100, an upper display panel 200, and
a liquid crystal layer 3 interposed therebetween.
[0091] First, the lower display panel 100 will be described in
detail.
[0092] A plurality of gate lines 121 and a plurality of storage
electrode lines 131 are formed on an insulation substrate 110
formed of, for example, transparent glass.
[0093] The gate lines 121 transmit the gate signals and extend in
the horizontal direction. Each of the gate lines 121 includes a
plurality of gate electrodes 124 that protrude upward, and a wide
end portion 129 that is provided for connection to a different
layer or an external driving circuit.
[0094] The storage electrode lines 131 are supplied with a
predetermined voltage, and substantially extend in parallel with
the gate lines 121. Each of the storage electrode lines 131 is
disposed between two adjacent gate lines 121 and maintains the same
interval from the two gate lines 121. The storage electrode lines
131 include the storage electrodes 137 extending in the vertical
direction. However, the shape and alignment of the storage
electrode lines 131 may be modified in various ways.
[0095] The gate lines 121 and the storage electrode lines 131 may
be formed of a conductor having low resistance, for example, an
aluminum-based metal, such as aluminum (Al) or an aluminum alloy, a
silver-based metal, such as silver (Ag) or a silver alloy, a
copper-based metal, such as copper (Cu) or a copper alloy, a
molybdenum-based metal, such as molybdenum (Mo) or a molybdenum
alloy, chromium (Cr), tantalum (Ta), or titanium (Ti). The gate
lines 121 and the storage electrode lines 131 may have a
multi-layered structure including two conductive layers (not shown)
whose physical properties are different from each other. Of these,
one conductive layer is formed of a metallic material having low
resistivity, such as an aluminum-base metal, a silver-base metal,
or a copper-based metal, in order to reduce signal delay or voltage
drop. In contrast, the other conductive layer is formed of a
different material, particularly a material having excellent
physical, chemical, and electrical contact characteristics with ITO
(Indium Tin Oxide) and IZO (Indium Zinc Oxide), such as a
molybdenum-based metal, chromium, titanium, or tantalum. Specific
examples of the combination include a combination of a chromium
lower layer and an aluminum (alloy) upper layer, and a combination
of an aluminum (alloy) lower layer and a molybdenum (alloy) upper
layer. Moreover, the gate lines 121 and the storage electrode lines
131 may be formed of various metals or conductors, other than the
above materials.
[0096] The lateral side's surface of each of the gate lines 121 and
the storage electrode lines 131 is inclined with respect to a
surface of the substrate 110, and the inclination angle is
preferably in a range of about 30.degree. to 80.degree..
[0097] A gate insulating layer 140 made of silicon nitride
(SiN.sub.x) or silicon oxide (SiO.sub.x) is formed on the gate
lines 121 and the storage electrode line 131.
[0098] A plurality of semiconductor islands 154 formed of
hydrogenated amorphous silicon (abbreviated as a-Si) or
polycrystalline silicon are formed on the gate insulating layer
140. The semiconductor islands 154 are respectively disposed on the
gate electrodes 124.
[0099] A plurality of ohmic contacts 163 and 165 are formed on the
semiconductor islands 154. The ohmic contacts 163 and 165 may be
formed of a material such as n+ hydrogenated amorphous silicon, in
which an n-type impurity is doped with high concentration, or of
silicide. A plurality of pairs of ohmic contacts 163 and 165 are
formed on the semiconductor islands 154.
[0100] The lateral sides of each of the semiconductor islands 154
and the ohmic contacts 163 and 165 is inclined with respect to the
surface of the substrate 110, and the inclination angle is in a
range of about 30.degree. to 80.degree..
[0101] A plurality of data lines 171 and a plurality of drain
electrodes 175 are formed on the ohmic contacts 163 and 165 and the
gate insulating layer 140.
[0102] The data lines 171 transmit data signals and substantially
extend in a vertical direction to cross the gate lines 121 and the
storage electrode lines 131. Each of the data lines 171 includes a
plurality of first and second source electrodes 173 extending
toward the gate electrodes 124, and a wide end portion 179 that is
provided for connection to a different layer or an external driving
circuit.
[0103] The drain electrodes 175 are separated from the data lines
171, and face the source electrodes 173 with electrodes 124 as a
center, respectively. Each of the drain electrodes 175 includes one
end portion having a wide extension and the other end portion
having a bar shape which is surrounded by the source electrodes 173
curved in a "U" shape.
[0104] One gate electrode 124, one source electrode 173, and one
drain electrode 175 form one thin film transistor (TFT) together
with the semiconductor island 154. A channel of the thin film
transistor is formed in the semiconductor island 154 between the
source electrode 173 and the drain electrode 175.
[0105] The data line 171 and the drain electrodes 175 are
preferably formed of a refractory metal, such as molybdenum,
chromium, tantalum, or titanium, or an alloy of them. The data line
171 and the drain electrodes 175 may have a multi-layered structure
having a refractory metal layer (not shown) and a low-resistive
conductive layer (not shown). Examples of the multi-layered
structure includes a two-layered structure of a chromium or
molybdenum (alloy) lower layer and an aluminum (alloy) upper layer,
and a three-layered structure of a molybdenum (alloy) lower layer,
an aluminum (alloy) intermediate layer, and a molybdenum (alloy)
upper layer. However, the data line 171 and the drain electrodes
175 may be formed of various materials or conductors, other than
the above materials.
[0106] Preferably, the lateral sides of each of the data line 171
and the drain electrodes 175 is also inclined with respect to the
surface of the substrate 110 at an angle of about 30.degree. to
80.degree..
[0107] The ohmic contacts 163 and 165 are provided only between the
underlying semiconductor islands 154 and the overlying data lines
171 and drain electrodes 175 so as to reduce contact resistance
therebetween. The semiconductor islands 154 have exposed portions
that are not covered with the data line 171 and the drain
electrodes 175, including a portion between the source electrode
173 and the drain electrode 175.
[0108] A passivation layer 180 is formed on the data line 171, the
drain electrodes 175, and the exposed portions of the semiconductor
island 154. The passivation layer 180 is formed of an inorganic
insulator and may have a flat surface. The inorganic insulator may
be exemplified as silicon nitride or silicon oxide. The upper
passivation layer 180 may have photosensitivity, and preferably has
a dielectric constant of 4.0 or less. However, the passivation
layer 180 may have a dual-layered structure having a lower
inorganic layer and an upper organic layer so as to utilize the
excellent insulating characteristic of the organic film and to not
damage the exposed semiconductor island 154.
[0109] A plurality of contact holes (contact holes) 182 and 185 are
formed in the passivation layer 180 to expose one end of the data
lines 171 and the drain electrodes 175. Further, a plurality of
contact holes 181 are formed in the passivation layer 180 and the
gate insulating layer 140 to expose an end portion 129 of the gate
lines 121. Further, an opening 183 is formed in the passivation
layer 180 to expose the gate insulating layer 140. The opening 183
overlaps the storage electrode 137.
[0110] A plurality of pixel electrodes 191 and a plurality of
contact assistants 81 and 82 are formed on the passivation layer
180. These may be formed of a transparent conductive material such
as ITO or IZO, or a reflective metal such as aluminum, silver,
chromium, or an alloy of them.
[0111] The pixel electrode 191 includes first and second sub-pixel
electrodes 191a and 191b that face each other in a diagonal
direction. In particular, the first sub-pixel electrode 191a is
disposed at a lower left portion and the second sub-pixel electrode
191b is disposed at an upper right portion. A second sub-pixel
electrode of another pixel electrode is disposed at the upper
portion of the first sub-pixel electrode 191a, and a first
sub-pixel electrode of another pixel electrode is disposed at the
lower portion of the second sub-pixel electrode 191b. The first and
second sub-pixel electrodes 191a and 191b are connected to each
other through a connection unit 192.
[0112] Each of the sub-pixel electrodes 191a and 191b includes a
pair of horizontal edges that are parallel to the gate line 121 and
a pair of vertical edges that are parallel to the data line 171.
The length of each edge of the first sub-pixel electrode 191a is
substantially equal to that of each edge of the second sub-pixel
electrode 191b. Therefore, the area of the sub-pixel electrode 191a
is substantially equal to that of the sub-pixel electrode 191b.
[0113] The pixel electrode 191 is physically and electrically
connected to the drain electrode 175 through the contact hole 185
so as to be supplied with the data voltage from the drain electrode
175. The pixel electrode 191 to which the data voltage is applied
generates an electric field with the common electrode 270 of
another display panel 200 (not shown) to which the common voltage
is applied, thereby determining a direction of liquid crystal
molecules 31 in the liquid crystal layer 3 interposed between the
two electrodes 191 and 270. The polarization of light passing
through the liquid crystal layer 3 varies on the basis of the
direction of the liquid crystal molecules determined as described
above. The pixel electrode 191 and the common electrode 270 form a
capacitor (hereinafter, referred to as a "liquid crystal
capacitor") so as to maintain the applied voltage after the thin
film transistor is turned off.
[0114] The pixel electrode 191 is opposite to the storage electrode
line 131 such as the storage electrode 137 with the gate insulating
layer 140 interposed therebetween, thereby forming a storage
capacitor. The storage capacitor improves the voltage storage
capacity of the liquid crystal capacitor. At this time, since the
opening 183 is formed in the passivation layer 180, only the gate
insulating layer 140 exists between the pixel electrode 191 and the
storage electrode 137. Therefore, the distance between the pixel
electrode 191 and the storage electrode line 131 becomes short, and
thus the voltage storage capacity is improved.
[0115] At least the storage electrode line 131 disposed between the
first and second sub-pixel electrodes 191a and 191b extends in a
horizontal direction while being overlapped with both the first and
second sub-pixel electrodes 191a and 191b. The gate line 121
extends below the first sub-pixel electrodes 191a, while at least
parts of the gate line 121 overlap the two first sub-pixel
electrodes 191a.
[0116] The data line 171 disposed between the first and second
sub-pixel electrodes 191a and 191b extends in a vertical direction,
while at least parts of the data line 171 overlap both the first
and second sub-pixel electrodes 191a and 191b. Among a plurality of
data lines 171, the data line 171 connected to the pixel electrode
191 through the contact hole 185 is referred to as a first data
line 171s. The data line 171 adjacent to the left of the first data
line 171s is referred to as a second data line 171l, and the data
line 171 adjacent to the right of the first data line 171s is
referred to as the third data line 171r. At this time, each of the
first and second sub-pixel electrodes 191a and 191b overlaps the
first data line 171s, the first sub-pixel electrode 191a overlaps
the second data line 171l, and the second sub-pixel electrode 191b
overlaps the third data line 171r.
[0117] The contact assistant 81 is connected to the end portion 129
of the gate line 121 through the contact hole 181, and the contact
assistant 82 is connected to the end portion 179 of the data line
171 through the contact hole 182. The contact assistants 81 and 82
supplement the adhesive property between the end portion 129 of the
gate line 121 and the external device and between the end portion
179 of the data line 171 and the external device.
[0118] Next, the upper display panel 200 will be explained.
[0119] A light blocking member 220 is formed on an insulation
substrate 210 formed of, for example, transparent glass or plastic.
The light blocking member 220 may include curved portions (not
shown) corresponding to the curved edges of the pixel electrode
191, and quadrangle portions (not shown) corresponding to the thin
film transistor. The light blocking member 220 prevents light
leakage between the pixel electrodes 191 and defines an opening
region which faces the pixel electrode 191.
[0120] A plurality of color filters 230 are formed on the substrate
210 and the light blocking member 220. Most of the plurality of
color filters 230 exist in a region surrounded by the light
blocking member 220 and may extend along a column of pixel
electrodes 191. Each of the color filters 230 may display one of
three primary colors, such as red, green, and blue.
[0121] An overcoat 250 is formed on the color filter 230 and the
light blocking member 220. The overcoat 250 may be formed of an
organic insulator and functions to prevent the color filter 230
from being exposed and supply a flat surface. The overcoat 250 may
be omitted.
[0122] The common electrode 270 is formed on the overcoat 250. The
common electrode 270 is formed of a transparent conductor such as
ITO or IZO.
[0123] Alignment layers 11 and 21 may be formed inside the display
panels 100 and 200. These alignment layers 11 and 21 may be
vertical alignment layers.
[0124] Polarizers (not shown) may be formed outside the display
panels 100 and 200. It is preferable that polarization axes of two
polarizers be perpendicular to each other and have an angle of
45.degree. with the curved edge of the sub-pixel electrodes 191a
and 191b. In a case of a reflective liquid crystal display, one of
the two polarizers may be omitted.
[0125] The liquid crystal display may include the polarizers 12 and
22, retardation films, the display panels 100 and 200, and a
backlight unit (not shown) that supplies light to the liquid
crystal layer 3.
[0126] The liquid crystal layer 3 has positive dielectric
anisotropy. The liquid crystal molecules of the liquid crystal
layer 3 are arranged to be parallel to the upper and lower display
panels when no electric field is applied.
[0127] Overcoming an alignment error occurring in the liquid
crystal panel assembly will be described in detail with reference
to FIG. 7.
[0128] FIG. 7 is a layout view illustrating a case where the
alignment error occurs at the manufacturing process of the liquid
crystal display shown in FIG. 4.
[0129] Referring to FIG. 7, all the data lines 171 are arranged
while being inclined to the left side, as compared with the FIG.
4
[0130] Therefore, the overlapped area between the data line 171 and
the pixel electrode 191 is different from the overlapped area shown
in FIG. 4.
[0131] Parasitic capacitance is present between the data line 171
and the pixel electrode 191 which may affect the pixel electrode
voltage. When data voltages having opposite polarities are applied
to every two adjacent data lines 171, the parasitic capacitances
between each of the adjacent data lines 171 and the pixel electrode
191 are oppositely charged. Therefore, areas where one pixel
electrode 191 overlaps the two data lines 171 to which opposite
polarity data voltages are applied, the charge on the parasitic
capacitance is neutralized. However, if an alignment error occurs
between each of the data lines 171 and the pixel electrode 191, the
areas where the pixel electrode 191 overlaps the two data lines 171
are different from each other. Accordingly, the voltages of some of
the pixel electrodes 191 may be lower or higher and the charge on
the parasitic capacitance is not neutralized and the stripe defect
occurs.
[0132] However, as described in the exemplary embodiment of the
present invention, the stripe defect may be avoided by making the
pixel electrode 191 include a first and a second sub-pixel
electrode 191a and 191b that face each other in the diagonal
direction.
[0133] As shown in FIG. 7, when the alignment error occurs, the
area in which the first sub-pixel electrode 191a overlaps the first
data line 171s increases, but the area in which the second
sub-pixel electrode 191b overlaps the first data line 171s
decreases. That is, even though the alignment error occurs, the
area where the pixel electrode 191 overlaps the first data line
171s to which a positive data voltage is applied is not changed.
Further, even though the area in which the first sub-pixel
electrode 191a overlaps the second data line 171l decreases, the
area in which the second sub-pixel electrode 191a overlaps the
third data line 171r increases. That is, even though the alignment
error occurs, the area where the pixel electrode 191 overlaps the
second or third data lines 171l and 171r to which a negative data
voltage is applied is not changed. Therefore, the charge on the
parasitic capacitance between the pixel electrode 191 and the data
line 171 may be neutralized.
[0134] Hereinafter, a liquid crystal panel assembly according to
another exemplary embodiment of the present invention will be
described with reference to FIG. 8.
[0135] FIG. 8 is a layout view of the liquid crystal panel assembly
according to another exemplary embodiment of the present
invention.
[0136] Referring to FIG. 8, the liquid crystal panel assembly
according to this exemplary embodiment of the present invention
includes a lower display panel (not shown) and an upper display
panel (not shown) that face each other, a liquid crystal layer (not
shown) interposed therebetween, and a pair of polarizers (not
shown) attached outside the display panels.
[0137] The layered structure of the liquid crystal panel assembly
according to this exemplary embodiment of the present invention is
substantially the same as the layered structure of the liquid
crystal panel assembly shown in FIGS. 4 to 6.
[0138] Hereinafter, the lower display panel will be described. A
plurality of gate conductors that include a plurality of gate lines
121 and a plurality of storage electrode lines 131 are formed on an
insulation substrate (not shown). Each of the gate lines 121
includes gate electrodes 124 and end portions 129. A gate
insulating layer (not shown) is formed on the gate conductor 121. A
semiconductor island 154 is formed on the gate insulating layer
(not shown). Further, a plurality of ohmic contacts (not shown) is
formed on the semiconductor island 154. The data lines 171 and the
drain electrodes 175 which include source electrodes 173 and end
portions 179 are formed on the ohmic contacts (not shown) and on
the gate insulating layer 140 (not shown). A passivation layer (not
shown) is formed on the data conductors 171 and 175 and the exposed
semiconductor islands 154. Further, the contact holes 181, 182, and
185 are formed on the passivation layer and the gate insulating
layer. The pixel electrodes 191 and contact assistants 81 and 82
are formed on the passivation layer 180. Further, an alignment film
(not shown) is formed on the pixel electrodes 191, the contact
assistants 81 and 82, and the passivation layer 180.
[0139] Hereinafter, the upper display panel will be described. A
light blocking member (not shown), color filters (not shown), an
overcoat (not shown), a common electrode (not shown), and an
alignment film (not shown) are formed on the insulation substrate
(not shown).
[0140] However, the liquid crystal panel assembly shown in FIG. 8
is different from the liquid crystal panel assembly shown in FIGS.
4 to 6 in that the openings are not formed in the passivation layer
180 at portions where the storage electrodes 137 overlap the pixel
electrodes 191. Further, the drain electrodes 175 each include one
end portion 177 having a wide extension that is opposite to the
other end portion having a bar shape that is surrounded by the
source electrodes 173. The end portions 177 having a wide extension
of the drain electrodes 175 overlap the storage electrodes 137.
[0141] Each end portion 177 having a wide extension of the drain
electrodes 175 and the pixel electrodes 191 overlaps a storage
electrode 137 and a storage electrode line 131 so as to form the
storage capacitor Cst. Further, the end portion 177 having a wide
extension of the drain electrodes 175 improves the capacitance of
the storage capacitor Cst.
[0142] Next, a liquid crystal panel assembly according to another
exemplary embodiment of the present invention will be described in
detail with reference to FIGS. 9 and 10.
[0143] FIG. 9 is a layout view of a liquid crystal panel assembly
according to another exemplary embodiment of the present invention.
FIG. 10 is a cross-sectional view of the liquid crystal panel
assembly shown in FIG. 9 taken along the line IX-IX.
[0144] The liquid crystal panel assembly according to the present
exemplary embodiment includes lower and upper display panels 100
and 200 that face each other, a liquid crystal layer 3 that is
interposed between the lower and upper display panels 100 and 200,
and a pair of polarizers 12 and 22.
[0145] The layered structure of the liquid crystal panel assembly
according to the present exemplary embodiment is substantially the
same as the layered structure of the liquid crystal panel assembly
shown in FIGS. 4 to 6.
[0146] Hereinafter, the lower display panel 100 will be described.
A plurality of gate conductors that include a plurality of gate
lines 121 and a plurality of storage electrode lines 131 are formed
on the insulation substrate 110. The gate lines 121 include gate
electrodes 124 and end portions 129. A gate insulating layer 140 is
formed on the gate conductor 121. A semiconductor stripe 151
including a protruding portion 154 is formed on the gate insulating
layer 140. Further, a plurality of ohmic contacts 163 and 165 are
formed on the semiconductor stripe 151. The source electrodes 173,
the data lines 171 that include end portions 179, and the drain
electrodes 175 are formed on the ohmic contacts 161, 163, and 165
and the gate insulating layer 140.
[0147] A lower passivation layer 180p, a color filter 230, and an
upper passivation layer 180q are formed on the data conductors 171
and 175 and the exposed semiconductor islands 154. Further, the
contact holes 181, 182, 185p, and 185q are formed in the lower and
upper passivation layers 180p and 180q and the gate insulating
layer 140. The openings 183p and 183q are formed in the lower and
upper passivation layers 180p and 180q. The pixel electrodes 191
and contact assistants 81 and 82 are formed on the passivation
layer 180. Further, an alignment film 11 is formed on the pixel
electrodes 191, the contact assistants 81 and 82, and the
passivation layer 180.
[0148] Hereinafter, the upper display panel will be described. A
light blocking member 220, an overcoat 250, a common electrode 270,
and an alignment layer 21 are formed on the insulation substrate
210.
[0149] The liquid crystal panel assembly shown in FIGS. 9 and 10 is
different from the liquid crystal panel assembly shown in FIGS. 4
to 6 in that the pixel electrodes 191 are not separated and a
region defined by the data lines 171 and the gate lines 121 has a
rectangular shape.
[0150] Each data line 171 includes a first portion 171ta and a
second portion 171tb that are not connected in a straight line. The
first portion 171ta is connected to the second portion 171tb
through a connection portion 178. The entire surface of the first
portion 171ta overlaps a part of the pixel electrode 191 that
supplies the data voltage, and the entire surface of the second
portion 171tb overlaps a part of an adjacent pixel electrode 191
that does not supply the data voltage.
[0151] On the basis of one pixel electrode 191, a fourth data line
171t indicates the data line 171 connected through the thin film
transistor Q and a fifth data line 171j indicates the data line 171
adjacent to the left side of the fourth data line 171t. Further, a
sixth data line 171k indicates the data line 171 adjacent to the
right side of the fourth data line 171t. Therefore, one pixel
electrode 191 overlaps the entire second portion 171tb of the
fourth data line 171t and the entire first portion 171ja of the
fifth data line 171j. On the basis of two adjacent pixel electrodes
191, the second portion 171tb of the fourth data line 171t
completely overlaps the first portion 171ka of the sixth data line
171k. That is, one pixel electrode 191 overlaps two adjacent data
lines 171 to which data voltages having opposite polarities are
applied.
[0152] Further, a light blocking member 132 is formed between
adjacent pixel electrodes 191. The light blocking member 132
includes a first light blocking member 134 that is adjacent to the
first portion 171ta of the data line 171t and a second light
blocking member 135 that is adjacent to the second portion 171tb of
the data line 171t. The first light blocking member 134 is
separated from the second light blocking member 135, and the second
light blocking member 135 extends from the storage electrode line
131. The light blocking member 132 is formed of the same material
as the storage electrode line 131.
[0153] As described above, the data line 171 overlaps the pixel
electrodes 191. Therefore, a space is formed between the pixel
electrodes 191. A horizontal direction electric field is formed in
the space between the two pixel electrodes 191 such that the liquid
crystal molecules in the liquid crystal layer 3 are arranged in an
unexpected direction, that is, in the horizontal direction. Then,
light passes through this portion, which causes light leakage. The
light blocking member 132 blocks light to prevent the light
leakage.
[0154] Further, the semiconductor island 154 extends along the data
lines 171 and the drain electrodes 175 to form a semiconductor
stripe 151, and an ohmic contact 163 extends along the data lines
171 to form an ohmic contact stripe 161. The semiconductor stripe
151 has substantially the same shape as those of the data lines
171, the drain electrodes 175, and the ohmic contacts 161 and 165
under the drain electrodes 175 in a plan view.
[0155] According to a method of manufacturing a thin film
transistor display panel according to an exemplary embodiment of
the present invention, the data lines 171, the drain electrodes
175, the semiconductor stripe 151, and the ohmic contacts 161 and
165 are formed by one photolithography process.
[0156] A photosensitive film used for the photolithography process
has different thicknesses depending on position, and includes a
first portion and a second portion in a descending order of
thickness. The first portion is disposed in a wiring region where
the data line 171 and the drain electrode 175 are disposed, and the
second portion is disposed in a channel region of the thin film
transistor.
[0157] The thickness of the photosensitive film may differ
according to a plurality of methods. For example, the thickness of
the photosensitive film may differ by providing a light
transmitting area, a light blocking area, and a translucent area
with an optical mask. A slit pattern, a lattice pattern, or a thin
film having medium transmittance or medium thickness is provided on
the translucent area. When using the slit pattern, it is preferable
that the width of the slit or the interval between the slits is
smaller than the resolution of the light exposer used for the
photolithography process. Alternatively, a reflowable
photosensitive film may be used. That is, the reflowable
photosensitive film is formed by using a general exposure mask
having a light transmitting area and a light blocking area. Then,
the reflowable photosensitive film is reflowed such that the
photosensitive film flows to a region where the photosensitive film
does not remain.
[0158] With the above-described processing, the photolithography
processes may be reduced, thereby making the manufacturing method
simple.
[0159] The liquid crystal panel assembly according to the present
exemplary embodiment is different from the liquid crystal panel
assembly described above. That is, the color filters are not
provided on the upper display panel 200, but a plurality of color
filters 230 are formed below the passivation layer 180 of the lower
display panel 100.
[0160] The color filters 230 extend in a vertical directional while
being periodically curved along the column of the pixel electrode
191. The color filter 230 does not exist in peripheral areas in
which the end portion 129 of the gate line 121 and the end portion
179 of the data line 171 are disposed. The contact hole 185q and
the opening 183q pass through the color filter 230. The penetration
holes 235 and 236 that are larger than the contact hole 185q and
the opening 183q are formed in the color filter 230.
[0161] The adjacent color filters 230 may function as the light
blocking member for blocking light leakage between the adjacent
pixel electrodes 191 that overlap the data line 171. In this case,
the light blocking member on the upper display panel 200 may be
omitted, thereby making the process simple. The passivation layer
180p is formed below the color filter 230. The overcoat 250 of the
common electrode panel 200 may be omitted.
[0162] The liquid crystal layer 3 of the liquid crystal display
according to the present exemplary embodiment includes nematic
liquid crystal with positive dielectric anisotropy. T he liquid
crystal molecules in the liquid crystal layer 3 of the liquid
crystal display according to the present exemplary embodiment are
splay-arranged and then bend-arranged due to a bend voltage as
shown in FIG. 9 so as to drive the display. A liquid crystal
display including the liquid crystal layer 3 having the
above-described liquid crystal molecules 31 is called an OCB
(optically compensated bend) mode display. The liquid crystal
display assembly driven in the OCB mode operates a normally white
mode. That is, the liquid crystal display assembly displays a white
color when no voltage is applied.
[0163] Hereinafter, the OCB mode will be described in detail with
reference to FIGS. 11 and 12.
[0164] FIG. 11 is a view illustrating an alignment state of the
liquid crystal molecules before a predetermined voltage is applied.
FIG. 12 is a view illustrating an alignment state of the liquid
crystal molecules after the predetermined voltage is applied.
[0165] Referring to FIG. 11, when the voltage is not applied, the
liquid crystal molecules 31 in the vicinity of alignment layers 11
and 21 are arranged in a horizontal direction at a pre-tilt angle
.theta., in which one end of the liquid crystal molecule rises
toward a rubbing direction. Therefore, the liquid crystal molecules
31 are arranged in parallel to the surface of the substrates 110
and 210 and are symmetrical with respect to a surface that is
separated from the surfaces of the two alignment layers 11 and 21
at the same distance (hereinafter, referred to as a "center
surface"). This alignment is called a splay alignment.
[0166] In the above-described state, if a predetermined voltage,
that is, a bend voltage, is applied to the liquid crystal molecules
31, an electric field is generated in the liquid crystal layer 3
and the alignment of the liquid crystal molecule 31 is changed from
the splay alignment to another alignment.
[0167] More specifically, when a voltage is applied to the
electrodes (not shown) of the two display panels 100 and 200 and
the electric field that is vertical to the surfaces of the two
display panels 100 and 200 is generated in the liquid crystal layer
3, the liquid crystal molecules 31 in the vicinity of the alignment
films 11 and 21 react to the electric field and rise. However,
since the rising directions of the liquid crystal molecules 31 in
the vicinity of the two alignment films 11 and 21 are the same, the
rising directions of the liquid crystal molecules 31 collide with
each other at the middle portion of the liquid crystal layer 3,
causing a large stress. Therefore, the alignment of the liquid
crystal molecules 31 changes to a twist alignment which is stable
from the viewpoint of energy. This is called a transient splay
alignment.
[0168] In this state, as shown in FIG. 12, when a higher electric
field is applied, the alignment of the liquid crystal molecules 31
of the liquid crystal layer changes to a bend alignment. The
alignment transition of the liquid crystal molecules 31 should
uniformly occur in all the liquid crystal capacitors Clc of the
liquid crystal panel assembly 300.
[0169] The characteristics of the liquid crystal panel assembly
shown in FIGS. 4 to 6 may be applied to the liquid crystal panel
assembly shown in FIGS. 9 and 10.
[0170] Hereinafter, a case where the alignment error occurs in the
liquid crystal panel assembly according to another exemplary
embodiment of the present invention will be described in detail
with reference to FIG. 13.
[0171] FIG. 13 is a layout view illustrating a case where the
alignment error occurs in the liquid crystal panel assembly shown
in FIG. 9.
[0172] Referring to FIG. 13, all the data lines 171 are arranged
while being inclined to the left side based on the pixel electrodes
191 as compared with FIG. 9. Therefore, the overlapped area between
the data line 171 and the pixel electrode 191 is different from the
overlapped area shown in FIG. 9
[0173] Since the pixel electrode 191 sufficiently overlaps the
first portion 171ta of the fourth data line 171t and the second
portion 171jb of the fifth data line 171j, the overlapped area
between the pixel electrode 191 and the fourth data line 171t and
the fifth data line 171j to which the positive data voltage is
applied is not changed even when the alignment error shown in FIG.
10 occurs. Therefore, the positive parasitic capacitance and the
negative parasitic capacitance between the pixel electrode 191 and
the data line 171 are maintained to be the same as each other.
Accordingly, it is possible to remove the parasitic capacitance
generated between the pixel electrode 191 and the data line
171.
[0174] According to the present invention, it is possible to
prevent a coupling defect or a stripe defect while sufficiently
securing the aperture ratio of the liquid crystal display.
[0175] While this invention has been described in connection with
what is presently considered to be practical exemplary embodiments,
it is to be understood that the invention is not limited to the
disclosed embodiments, but, on the contrary, is intended to cover
various modifications and equivalent alignments included within the
spirit and scope of the appended claims.
* * * * *