U.S. patent application number 12/021104 was filed with the patent office on 2008-06-12 for organic light emitting diode display on a flexible substrate.
Invention is credited to Apostolos T. Voutsas.
Application Number | 20080136751 12/021104 |
Document ID | / |
Family ID | 29270119 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080136751 |
Kind Code |
A1 |
Voutsas; Apostolos T. |
June 12, 2008 |
Organic Light Emitting Diode Display on a Flexible Substrate
Abstract
A flexible metal foil substrate organic light emitting diode
(OLED) display and a method for forming the same are provided. The
method comprises: supplying a metal foil substrate such as titanium
(Ti), Inconel alloy, or Kovar, having a thickness in the range of
10 to 500 microns; planarizing the metal foil substrate surface;
depositing an electrical isolation layer having a thickness in the
range of 0.5 to 2 microns overlying the planarized metal foil
substrate surface; depositing amorphous silicon having a thickness
in the range of 25 to 150 nanometers (nm) overlying the electrical
insulation layer; from the amorphous silicon, forming
polycrystalline silicon overlying the electrical insulation layer;
forming thin-film transistors (TFTs) in the polycrystalline
silicon; and, forming an electronic circuit using the TFTs, such as
an OLED display.
Inventors: |
Voutsas; Apostolos T.;
(Vancouver, WA) |
Correspondence
Address: |
SHARP LABORATORIES OF AMERICA, INC.;C/O LAW OFFICE OF GERALD MALISZEWSKI
P.O. BOX 270829
SAN DIEGO
CA
92198-2829
US
|
Family ID: |
29270119 |
Appl. No.: |
12/021104 |
Filed: |
January 28, 2008 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10282744 |
Oct 28, 2002 |
6911666 |
|
|
12021104 |
|
|
|
|
10194895 |
Jul 11, 2002 |
6642092 |
|
|
10282744 |
|
|
|
|
Current U.S.
Class: |
345/76 ;
257/E21.413; 257/E29.151; 257/E29.295 |
Current CPC
Class: |
H01L 29/66757 20130101;
H01L 27/3262 20130101; G11C 13/0007 20130101; H01L 27/1214
20130101; H01L 27/3244 20130101; H01L 51/0097 20130101; H01L
29/4908 20130101; H01L 29/78603 20130101; H01L 2251/5315 20130101;
H01L 2251/5338 20130101; G11C 2213/31 20130101; H01L 27/1262
20130101; H01L 27/1218 20130101; Y02E 10/549 20130101; Y02P 70/50
20151101; Y02P 70/521 20151101 |
Class at
Publication: |
345/76 |
International
Class: |
G09G 3/30 20060101
G09G003/30 |
Claims
1-12. (canceled)
13. A method for forming an organic light emitting diode (OLED)
display on a flexible substrate, the method comprising: supplying a
metal foil substrate with a surface selected from the group
including titanium (Ti), Inconel alloy, and Kovar; forming
polycrystalline silicon overlying the electrical insulation layer;
forming thin-film transistors (TFTs) in the polycrystalline
silicon; and, forming OLEDs overlying the TFTs.
14. The method of claim 13 further comprising: planarizing the
metal foil substrate surface; depositing an electrical isolation
layer overlying the planarized metal foil substrate surface;
depositing amorphous silicon overlying the electrical insulation
layer; and, wherein forming polycrystalline silicon overlying the
electrical insulation layer includes forming polycrystalline
silicon from the amorphous silicon.
15. The method of claim 13 wherein supplying a metal foil substrate
with a surface includes supplying a metal foil having a thickness
in the range of 10 to 500 microns.
16. The method of claim 15 wherein supplying a metal foil substrate
with a surface includes supplying a metal foil having a thickness
in the range of 50 to 250 microns.
17. The method of claim 16 wherein supplying a metal foil substrate
with a surface includes supplying a metal foil having a thickness
in the range of 100 to 200 microns.
18. The method of claim 14 wherein depositing an electrical
isolation layer overlying the planarized metal foil substrate
surface includes depositing a layer having a thickness in the range
of 0.5 to 2 microns.
19. The method of claim 18 wherein depositing an electrical
isolation layer overlying the planarized metal foil substrate
surface includes depositing a layer having a thickness in the range
of 0.5 to 1.5 microns.
20. The method of claim 19 wherein depositing an electrical
isolation layer overlying the planarized metal foil substrate
surface includes depositing a layer having a thickness in the range
of 0.5 to 1 microns.
21. The method of claim 14 wherein depositing amorphous silicon
includes depositing amorphous silicon having a thickness in the
range of 25 to 150 nanometers (nm).
22. The method of claim 21 wherein depositing amorphous silicon
includes depositing amorphous silicon having a thickness in the
range of 25 to 100 nm.
23. The method of claim 22 wherein depositing amorphous silicon
includes depositing amorphous silicon having a thickness in the
range of 35 to 60 nm.
24. The method of claim 13 wherein forming OLEDs overlying the TFTs
includes: forming a metal anode overlying the TFTs; forming a
polymer organic layer overlying the anode; and, forming a
semi-transparent cathode overlying the organic layer.
25. The method of claim 13 further comprising: forming a resin
layer overlying the OLEDs; and, forming a seal plate overlying the
resin layer.
26. The method of claim 13 wherein forming OLEDs overlying the TFTs
includes: forming a metal cathode overlying the TFTs; forming a
polymer organic layer overlying the cathode; and, forming a
semi-transparent anode overlying the organic layer.
27-43. (canceled)
Description
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of a pending
patent application entitled, THIN-FILM TRANSISTORS FORMED ON A
METAL FOIL SUBSTRATE, invented by Voutsas et al., Ser. No. ______,
filed ______, attorney docket no. SLA601.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention generally relates to organic light emitting
diode (OLED) displays and, more particularly, to an OLED display
fabricated on a thin metal foil substrate.
[0004] 2. Description of the Related Art
[0005] As noted in U.S. Pat. No. 6,392,617 (Robert Gleason), arrays
of OLEDs are utilized to create two-dimensional flat panel
displays. As compared to conventional light emitting diodes (LEDs),
which are made of compound semiconductors, the low cost and ease of
patterning OLEDs makes compact, high resolution arrays practical.
OLEDs can be adapted to create either monochrome or color displays
and the OLEDs are conventionally formed on glass or semiconductor
substrates.
[0006] As is known in the art, arrays of OLEDs and LEDs are
typically classified as passive matrix arrays or active matrix
arrays. In a passive matrix array, the current drive circuitry is
external to the array, and in an active matrix array the current
drive circuitry includes one or more transistors that are formed
within each pixel. An advantage of active matrix arrays is that
they do not require peak currents that are as high as passive
matrices. High peak currents are generally undesirable because they
reduce the luminous efficiency of available OLEDs. Because the
transparent conducting layer of an active matrix can be a
continuous sheet, active matrix arrays also mitigate voltage drop
problems that are experienced in the patterned transparent
conductors of passive matrices.
[0007] FIGS. 1 and 2 are depictions of conventional active matrix
pixels (prior art). It should be understood that although
individual active matrix pixels are shown for description purposes,
the individual active matrix pixels shown in these figures are
typically part of an array of pixels that are located closely
together in order to form a display. As shown in FIGS. 1 and 2,
each of the active matrix pixels includes an address (gate) line
102 and 202, a data line 104 and 204, an address transistor 106 and
206, a drive transistor 108 and 208, a storage node 110 and 210,
and an OLED 112 and 212. The address lines allow the pixels to be
individually addressed and the data lines provide the voltage to
activate the drive transistors. The address transistors control the
writing of data from the data lines to the storage nodes. The
storage nodes are represented by capacitors, although they need not
necessarily be separate components, as the gate capacitance of the
drive transistors and the junction capacitance of the address
transistors may provide sufficient capacitance for the storage
nodes. As shown, the OLEDs are connected to a drive voltage
(V.sub.LED) and the current that flows through the OLEDs is
controlled by the drive transistors. When current is allowed to
flow through the drive transistors, the OLEDs give off light
referred to as a luminous flux, as indicated by the arrows 114 and
214.
[0008] Referring to FIG. 1, PMOS transistors are preferred when the
cathode of the OLED 112 is grounded, and referring to FIG. 2, NMOS
transistors are preferred when the anode of the OLED 212 is
connected to the supply voltage (V.sub.LED). Utilizing the PMOS and
NMOS transistors as shown in FIGS. 1 and 2 makes the gate to source
voltages of the drive transistors 108 and 208 insensitive to
voltage drops across the OLEDs, thereby improving the uniformity of
the light 114 and 214 that is given off by the OLEDs.
[0009] The operation of the prior art active matrix pixels is
described with reference to the active matrix pixel configuration
shown in FIG. 2, although the same concepts apply to the active
matrix pixel of FIG. 1. The active matrix pixel shown in FIG. 2
serves as an analog dynamic memory cell. When the address line 202
is high, the data line 204 sets the voltage on the storage node
210, which includes the gate of the drive transistor 208. When the
voltage on the storage node exceeds the threshold voltage of the
drive transistor, the drive transistor conducts causing the OLED
212 to emit light 214 until the voltage on the storage node drops
below the threshold voltage of the drive transistor, or until the
voltage on the storage node is reset through the address transistor
206. The voltage on the storage node will typically drop due to
leakage through the junction of the address transistor and through
the gate dielectric of the drive transistor. However, with
sufficiently low leakage at the address and drive transistors and
high capacitance at the storage node, the current through the OLED
is held relatively constant until the next voltage is set on the
storage node. For example, the voltage is typically reset at a
constant refresh interval as is known in the art. The storage node
is represented as a capacitor in order to indicate that sufficient
charge must be stored on the storage node to account for leakage
between refresh intervals. As stated above, the capacitor does not
necessarily represent a separate component because other sources of
capacitance on the storage node may suffice.
[0010] In the active matrix pixel of FIG. 2, the voltage on the
storage node 210 determines the intensity of the light 214 that is
generated by the OLED 212. If the intensity-current relationship of
the OLED and gate voltage-current relationship of the drive
transistor 208 are known, according to one method, the desired
intensity of light is generated by placing the corresponding
voltage on the storage node. Setting the voltage on the storage
node is typically accomplished by utilizing a digital to analog
converter to establish the voltage on the corresponding data line
204. In an alternative method, the storage node is first discharged
by grounding the data line, and then the data line is set to the
CMOS supply voltage (V.sub.dd). Utilizing the latter method, the
address transistor 202 functions as a current source, charging the
storage node until the storage node is isolated by setting the
address line low. The latter method offers the benefit of not
requiring a digital to analog converter on each data line. However,
one disadvantage of the latter method is that the storage node
capacitance within a single pixel is a non-linear function of the
voltage when supplied by the gates and junctions of the
transistors. Another disadvantage is that the storage node
capacitance of each pixel varies among the pixels in an array.
[0011] As described above, in order to obtain the desired luminous
flux from the OLED 212 of FIG. 2, the voltage on the data line 204
is adjusted to control the current through the drive transistor
208. Unfortunately, current flow through the drive transistor also
depends on characteristics of the drive transistor, such as its
threshold voltage and transconductance. Large arrays of drive
transistors, as required to make a high-resolution display, exhibit
variations in threshold voltage and transconductance that often
cause the drive currents of the OLEDs to differ for identical
control voltages. These variations, in turn, cause a display to
appear non-uniform. In addition, different OLEDs emit different
intensities of light even when driven with identical currents.
Furthermore, the light intensity for a specified drive current
drops as an OLED ages and different OLEDs can degrade at different
rates, again causing a display to appear non-uniform.
[0012] Active matrix pixels are preferably implemented with a
silicon substrate instead of a transparent dielectric substrate
because transparent dielectric substrates require the transistors
to be built as thin film devices. It is difficult to obtain a tight
distribution of threshold voltages in large arrays of thin-film
transistors, especially as more transistors are needed to make the
luminous flux from each pixel insensitive to threshold variations.
For this reason, OLED displays are often fabricated on a glass
substrate. However, if a silicon substrate is used, addressing,
driving, and other circuit functions can be easily integrated,
particularly if the substrate and process are compatible with CMOS
technology. Although known active matrix pixel technology is
compatible with older CMOS technology, OLEDs require higher
voltages than dense CMOS can tolerate, while dense CMOS is
desirable for the small pixels that are required for
high-resolution color displays.
[0013] As mentioned above, glass substrates are predominantly used
in the fabrication of liquid-crystal and OLED displays. One major
disadvantage of glass is that it is fragile. Hence, glass-made
displays are not very robust and they tend to break upon impact. A
glass substrate is also sensitive to heat, which imposes a limit on
the maximum temperature that it can be exposed at during
processing. Furthermore, future applications, which may demand some
degree of comformability/flexibility in the display, that cannot be
readily satisfied with displays fabricated on glass.
[0014] Polysilicon (poly-Si) technology has started penetrating the
market of smaller displays, such as displays used for
personal-digital-assistants (PDAs), cellular phones, car navigation
systems, etc. With current technology, thin poly-Si films are
typically formed by the deposition of amorphous silicon films and
subsequent transformation to polycrystalline silicon upon a
suitable thermal treatment. The maximum temperature and the
duration of such thermal treatment are constrained by the thermal
budget that the substrate can accommodate, before it breaks or it
is otherwise damaged.
[0015] Glass substrates are generally restricted to processing
temperatures below .about.650.degree. C. Higher temperatures, up to
approximately 725.degree. C., can possibly be used without damage,
but only for very short periods. This low temperature constraint
results in poorer quality poly-Si films, which are not compatible
with the fabrication of high performance devices and circuits. An
alternative approach is to induce the phase transformation is by
laser annealing the film, using excimer lasers for example. This
process results in very rapid heating of the film, affecting the
phase transformation without excessively heating the underlying
substrate. Even though the laser annealing process is quite
effective, it tends to be more costly than simply heating the film
by conventional means.
[0016] Another important step in the fabrication of the displays is
deposition of gate insulator (GI) layer. In the semiconductor
industry, such films are typically formed by thermal oxidation at
high temperatures (>1000.degree. C.) to ensure high quality
films. However, these high temperatures cannot used when the
substrates are made of glass. Hence, a compromise in the quality of
the GI layer is typically required for devices made on glass.
[0017] It would be advantageous to identify substrates which are
more robust than glass, and that permit the fabrication of
conformable/flexible displays.
[0018] It would also be advantageous if displays, which are built
on the above-mentioned substrates, could be made compatible with
higher processing temperatures. In that case, higher quality
poly-Si material could be obtained, compatible with the fabrication
of high performance devices and circuits.
SUMMARY OF THE INVENTION
[0019] The present invention describes a method and process for the
fabrication of displays on robust substrates made of metal foils.
The invention describes the use of metal foil substrates for the
fabrication of poly-Si TFT backplanes, and also the processes that
can be used for the fabrication of high quality poly-Si TFT
transistors. The processes involve the combination of conventional
solid-phase-crystallization and thermal oxidation GI formation at
the high temperatures, which is permitted with the use of metal
foil substrates.
[0020] Accordingly, a method is provided for forming an electronics
circuit on a flexible substrate. The method comprises: supplying a
metal foil substrate such as titanium (Ti), Inconel alloy, or
Kovar, having a thickness in the range of 10 to 500 microns;
planarizing the metal foil substrate surface; depositing an
electrical isolation layer having a thickness in the range of 0.5
to 2 microns overlying the planarized metal foil substrate surface;
depositing amorphous silicon having a thickness in the range of 25
to 150 nm overlying the electrical insulation layer; from the
amorphous silicon, forming polycrystalline silicon overlying the
electrical insulation layer; forming thin-film transistors (TFTs)
in the polycrystalline silicon; and, forming an electronic circuit
using the TFTs, such as an OLED display.
[0021] Additional details of the above-described method and a
flexible substrate, active matrix (AM), top emission OLED display
are provided below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIGS. 1 and 2 are depictions of conventional active matrix
pixels (prior art).
[0023] FIG. 3 is a partial cross-sectional view of the present
invention flexible substrate, active matrix (AM), top emission
organic light-emitting diode (OLED) display.
[0024] FIG. 4 is a schematic block diagram of the OLED display of
FIG. 3, using a PNP transistor.
[0025] FIG. 5 is a schematic block diagram of the OLED display of
FIG. 3, using an NPN transistor.
[0026] FIG. 6 is a schematic block diagram of the OLED display of
FIG. 3 using two PNP transistors.
[0027] FIG. 7 is a schematic block diagram of the OLED display of
FIG. 3 using two NPN transistors.
[0028] FIG. 8a is a partial cross-sectional view of the present
invention flexible substrate OLED display of FIG. 8b, with two TFTs
per pixel.
[0029] FIG. 8b is a multilevel plan view of the present invention
flexible substrate OLED display, with two TFT's per pixel.
[0030] FIG. 9 is a plan view of the circuit of either FIG. 6 or
FIG. 7.
[0031] FIG. 10 is a flowchart illustrating the present invention
general fabrication process.
[0032] FIG. 11 is a flowchart illustrating the present invention
method for forming an electronics circuit on a flexible
substrate.
[0033] FIG. 12 is a flowchart illustrating the present invention
method for forming an OLED display on a flexible substrate.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] FIG. 3 is a partial cross-sectional view of the present
invention flexible substrate, active matrix (AM), top emission
organic light emitting diode (OLED) display. The display 300
comprises a metal foil substrate 302 and a plurality of pixels
areas. For simplicity, a single pixel area 304 is shown. Each pixel
area, including pixel area 304, includes at least one thin-film
transistor (TFT) 306 overlying the substrate. The pixel area 304 is
isolated with an isolation material 307.
[0035] FIG. 4 is a schematic block diagram of the OLED display of
FIG. 3, using a PNP transistor. As shown, first TFT 306 has a drain
electrode connected to a power line 400, a gate electrode connected
to a data line 402, and a source connected to the anode of an OLED
404. The cathode of the OLED 404 is connected to ground (or a
voltage potential lower than the power line). As mentioned in the
Background Section, PNP transistors are typically used when the
cathode of the OLED 404 is grounded. The power line 400 supplies a
predetermined, constant voltage. That is, the powerline supplies a
dc voltage.
[0036] FIG. 5 is a schematic block diagram of the OLED display of
FIG. 3, using an NPN transistor. As shown, first NPN TFT 306 has a
drain electrode connected to the cathode of the OLED 404, a gate
electrode connected to a data line 402, and a source connected to
ground.
[0037] Returning to FIG. 3, an OLED 404, shown enclosed with dotted
lines, overlies the first TFT 306 and is connected to the first TFT
306 through a via 308. The metal foil substrate 302 is a material
such as (Ti), Inconel alloy, stainless steel, or Kovar. In one
aspect of the display, the metal foil substrate 302 has a thickness
310 in the range of 10 to 500 microns. Preferably, the metal foil
substrate 302 has a thickness 310 in the range of 50 to 250
microns. Most preferably, the metal foil substrate 302 has a
thickness 310 in the range of 100 to 200 microns. Thinner
substrates make for a more flexible display.
[0038] Typically, the OLED display 300 further comprises an
isolation layer 312 interposed between the metal substrate 302 and
the pixel area 304. In some aspects, the isolation layer 312 is
SiO2 and has a thickness 314 of approximately 1 micron. However,
alternate isolation layer materials are available.
[0039] Connections can be enabled to the conductive substrate 302
using an additional masking step. The metal substrate 302 is
typically covered with a one-micron thick Si02 film to ensure
optimal electrical isolation and maximum barrier properties against
the diffusion of metal contaminants. Making contact to the
substrate, therefore, involves etching through this thick oxide
film. To accomplish this etching, a masking step can be applied
after the definition of poly-Si islands, with the aim of defining
these deep vias. Other possibilities to accomplish the connection
to the substrate are possible, however.
[0040] In some aspects, the OLED 404 includes a metal anode 316
overlying the first TFT 306 and connected to the first TFT 306
source through the via 308, see FIG. 4. An organic polymer layer
318 overlies the metal anode 316, and a semi-transparent cathode
320 overlies the organic polymer layer 318.
[0041] In other aspects, metal layer 316 is the cathode of the OLED
404. see FIG. 5. Then, the organic polymer layer 318 overlies the
metal cathode 316, and a semi-transparent anode 320 overlies the
organic polymer layer 318. In either aspect, a resin layer 322
overlies the pixels, and a seal plate 324 overlying the resin layer
322.
[0042] The fabrication process for the OLED display 300 typically
starts with the fabrication of the TFT backplane. This process is
very similar to that of a liquid crystal display (LCD) device. The
main difference lies in the configuration of the thin-film
transistors in the pixel. In the case of OLEDs, good uniformity in
TFT characteristics is more critical than in the case of LCDs. This
stems primarily by the fact that the light emitted from a pixel is
directly proportional to the current of the pixel-driving TFT as
follows:
Light.varies.Drive Current.varies..mu.(V.sub.G-V.sub.th).sup.2
[0043] where .mu. is a factor related to electron mobility.
[0044] Increasing the TFT mobility makes a pixel brighter, while
increasing the TFT threshold voltage makes a pixel darker.
Significant variations from pixel-to-pixel make a commercial
display product unacceptable. Such brightness variations can be
minimized, either by reducing the intrinsic variability in TFT
characteristics, and/or by employing pixel-driving schemes that
compensate for such variability. In accordance to the latter,
multiple-TFT pixel-driving schemes aim to compensate for variations
in the intrinsic characteristics of individual TFTs.
[0045] Beyond the brightness uniformity issue, single-TFT pixel
architecture suffers from another problem. In the approach of FIG.
3 or FIG. 4, each pixel is pulsed ON for a fraction of the frame
time (=1/number of gate lines). This requires the peak OLED current
to be much higher than the average current, leading to a faster
degradation of the OLED material. To avoid such high current
pulses, designs involving 2-TFT pixels have been developed, as
shown in FIGS. 1 and 2. These designs enable pixel "memory". The
memory permits the pixel to deliver a small current throughout the
entire frame period. In this manner, even though the average
current through the OLED material is the same, the peak current is
greatly reduced, which leads to increased brightness and longer
OLED lifetime. Other more elaborate, 4-TFT pixel designs have also
been proposed to improve brightness uniformity by correcting for
variations in the threshold voltage and mobility of the TFTs.
However, 2-TFT pixel designs appear to be the best comprise between
quality and production costs. The following variations of the
invention are based on such a design. Starting with the limitations
of a 2-TFT pixel design, further improvements in brightness
uniformity are a result of process improvements.
[0046] FIG. 6 is a schematic block diagram of the OLED display of
FIG. 3 using two PNP transistors. The second (PNP) TFT 600 has a
gate electrode connected to a gate line 602 and a source electrode
connected to the data line 402. The first (PNP) TFT 306 has a drain
electrode connected to the power line 400, a source connected to
the anode of an OLED 404, and a gate electrode connected to the
drain of the second TFT 600. The cathode of the OLED 404 is
connected to ground.
[0047] In some aspects, each pixel further includes a storage
capacitor 606 connected between the drain electrode of the second
TFT 600 and the gate electrode of the first TFT 306. In other
aspects, the power line 400 is the metal foil substrate (see FIG.
3, reference designator 302). The drain of each pixel second TFT
600 is connected to the substrate through a connection that can
either be a single via or a plurality of vias.
[0048] FIG. 7 is a schematic block diagram of the OLED display of
FIG. 3 using two NPN transistors. The second (NPN) TFT 700 has a
gate electrode connected to a gate line 602 and a source electrode
connected to the data line 402. The first (NPN) TFT 306 has a drain
electrode connected to the cathode of an OLED 404, a gate electrode
connected to the drain of the second TFT 700, and a source
connected to a ground. The anode of the OLED 404 is connected to
the power line 400.
[0049] In some aspects, each pixel further includes a storage
capacitor 606 connected between the drain electrode of the second
TFT 700 and the gate electrode of the first TFT 306. In other
aspects, the power line 400 is the metal foil substrate (see FIG.
3, reference designator 302). The drain of each pixel second TFT
700 is connected to the substrate through a connection that can
either be a single via or a plurality of vias.
[0050] Conventionally in 2-TFT pixel designs, there are three
connecting lines to the pixel FETs. Two lines are the data line and
gate line buses. The third line (the power line) supplies an
additional constant voltage to the first FET source (FIG. 6) or
OLED anode (FIG. 7). The real estate associated with this third
line contributes additionally to the reduction of the pixel
aperture ratio. Hence, it would be desirable to eliminate this
line. One opportunity to do this is presented in the case of a
conductive substrate, such as a metal foil. Then, the source of the
first FET (FIG. 6) or anode of the OLED (FIG. 7) is directly
connected to the conductive substrate, which is held at the
appropriate, constant voltage (i.e. 2-7V). By doing so, the
aperture ratio is improved without sacrificing pixel functionality.
For clarity, the storage capacitor has been omitted from this
drawing.
[0051] FIG. 8a is a partial cross-sectional view of the present
invention flexible substrate OLED display of FIG. 8b, with two TFTs
per pixel.
[0052] FIG. 8b is a multilevel plan view of the present invention
flexible substrate OLED display, with two TFT's per pixel.
[0053] FIG. 9 is a plan view of the circuit of either FIG. 6 or
FIG. 7. Shown is a single via 800 connected to the drain of the
second TFT 604/702. T1 is first TFT 306 and T2 is either second TFT
600 (FIG. 6) or second TFT 700 (FIG. 7). Note that the placement of
the TFTs, via(s), TFT interconnects, and the OLED is merely
exemplary, as other placements are also possible. It should be
noted that although only one and two-TFT pixel designs have been
explicitly described above, the present invention concepts could be
extrapolated to other designs, such as four-TFT pixels, by those
skilled in the art.
Functional Description
[0054] There are two variations in OLEDs, just as there are types
of LCDs. There are "passive matrix" OLEDs and "active matrix" OLEDs
(so-called AM-OLEDs). TFT technology is especially relevant to
AM-OLEDs. In that case, as with AM-LCDs, the state of each OLED
pixel is individually controlled by TFT devices within the pixel.
As mentioned above, a greater number of TFTs result in greater
pixel brightness uniformity. Uniformity is process-specific, for
example, depending upon the crystallization technology that is used
to make the poly-Si material. The present invention, by adopting
new process technology, achieves adequate pixel uniformity with a
reduced number of FETs per pixel. A lower number of TFTs per pixel
results in a simpler process, better yield (in other words, lower
cost), and improved aperture ratio for the display, as the
transparent area of the pixel increases when the number of
components decreases.
[0055] There is one more classification relevant to OLEDs: "bottom
emission" vs. "top emission" OLEDs, referring to the direction that
light is emitted. In the former case, light is emitted from the
"bottom" of the device, through the substrate. In the latter case,
light is emitted through the top of the device, through the top
substrate. When an opaque substrate such as metal foil is used,
only a top emission OLED is practical. Top emission OLEDs have
several advantages over bottom-emission OLEDs:
[0056] (1) Higher aperture ratio. This is especially true when
considering pixel architectures using more than 2 TFTs. In these
cases the aperture ratio of bottom emission OLEDs is too low for
practical, high-resolution displays;
[0057] (2) Better color purity. Color purity is important in
applications that require very clear color, such as TVs;
[0058] (3) All solid-stage package structure. The thickness of the
module decreases, providing better packaging economics. A bottom
emission OLED requires a moisture control means, as the OLED is
exposed. This moisture control is typically accomplished by adding
desiccant in the array, increasing the array package thickness.
Since the OLED layer in a top emission OLED is already covered,
there is a reduced need for desiccant. Thus, top emission packaging
is freer of void spaces, and the packaging has a reduced overall
thickness.
[0059] One critical element in top emission OLED devices is the
semi-transparent cathode/anode materials. Furthermore, the
deposition process for such materials must to be non-intrusive to
the very sensitive OLED layers, in order to minimize damage to the
OLED layers. Damage to the OLED layers causes substantial reduction
in the brightness and lifetime of the OLED. The OLED layers are
typically polymer-based materials that are formed by spin-on or
inkjet-printing process. Another technique is evaporation, used
exclusively for the so-called small-molecule OLEDs that do not use
polymers. Evaporation technology is difficult to scale up, so
polymer OLEDs (PLEDs) have become increasingly popular for mass
production.
[0060] FIG. 10 is a flowchart illustrating the present invention
general fabrication process. The process is as follows:
[0061] 1. Start with a metal foil substrate. [0062] Metal foil
material can be stainless steel, although other metal materials can
be used such as Ti, Mo, etc. [0063] Thickness of metal foil should
be in the range of 10-500 .mu.m (microns); preferably in the range
of 50-250 .mu.m; even more preferably in the range of 100-200
.mu.m.
[0064] 2. Clean and planarize the surface of the foil substrate. A
number of different approaches can be used to accomplish surface
planarization: [0065] Use Chemical-Mechanical-Polishing (CMP) step
to reduce the surface roughness of the metal foil substrate to
better than 200 nm (average surface roughness). [0066] Use a
spin-coated dielectric material (i.e. Spin-on-glass, SOG) to form a
uniform coating on top of the rough surface of the metal foil. The
thickness of the SOG layer is in the range of 200-500 nm
(nanometers).
[0067] 3. Deposit an electrical isolation layer on the substrate.
If the substrate has been planarized by CMP, this layer is
deposited directly on the metal foil. If the substrate has been
planarized by SOG, this layer is deposited on top of the SOG film.
[0068] The electrical isolation layer also serves as diffusion
barrier against diffusion of impurities from the substrate to the
device active layer(s) built in subsequent steps. [0069] The
isolation/barrier layer could be made of SiO2 or SiNx, SiON, or
combination of these layers. The thickness of the isolation/barrier
layer is in the range of 0.5-2.0 .mu.m (preferably 0.5-1.5 .mu.m,
even more preferably 0.5-1 .mu.m).
[0070] 4. Deposit an amorphous silicon (a-Si) layer on top of the
barrier/isolation layer. [0071] The thickness of the a-Si layer
should be in the range of 25-150 nm preferably 25-100 nm, even more
preferably 35-60 nm). [0072] This layer could be in-situ doped or
doped later with appropriate type and amount of dopant (i.e. Boron
at .about.5e13 at/cm.sup.2) to impose a shift in the threshold
voltage of the fabricated devices towards the desired direction
(i.e. towards the positive direction).
[0073] 5. Crystallize the a-Si layer to form poly-Si material.
[0074] Use standard solid-phase-crystallization method in a furnace
or by Rapid-Thermal-Annealing (RTA). The temperature range for the
phase transformation is 700-1000.degree. C. (preferably
750-950.degree. C.).
[0075] 6. Pattern the poly-Si film to form poly-Si islands.
[0076] 7. Form the gate-insulation (GI) film on top of the poly-Si
islands. This step requires deposition of two types of GI layers.
The first layer is formed by thermal oxidation. This layer forms
the interface between the poly-Si active layer and the GI layer.
High interface quality is desirable for good device
characteristics. This high interface quality is achieved by the
thermally-formed GI layer portion. The remaining GI layer is then
formed by plasma deposition, i.e. using a TEOS-SiO2 process. The
characteristics of this layer also affect the device performance,
hence, the deposition process is geared towards producing a SiO2
film that has low density of fixed charges. [0077] Thickness of
first layer (thermal oxide): 10-50 nm (preferably 20-30 nm). [0078]
Thickness of second layer (plasma-deposited oxide): 40-100 nm
(preferably 50-70 nm).
[0079] The sequence of steps 6 and 7 can be also reversed. Such
reversal may be necessary, if (for example) the high temperature to
which the foil is subjected during thermal oxidation causes
significant shrinkage or expansion to the foil. If this happens
after the film is initially patterned, subsequent patterns (i.e.
lithography steps) may not be able to align to the first pattern
(poly-Si islands) due to mis-registration problems (caused by the
deformation of the substrate). If on the other hand, all
lithography steps occur after the substrate is exposed to the
highest temperature, such issues are avoided.
[0080] 8. Complete the device fabrication using steps and processes
that are conventional in the art.
[0081] 9. Fabricate an OLED device apparatus using poly-Si TFTs
made in the previous steps, as shown in FIG. 3.
[0082] FIG. 11 is a flowchart illustrating the present invention
method for forming an electronics circuit on a flexible substrate.
Although the method (and the method depicted in FIG. 12) is
depicted as a sequence of numbered steps for clarity, no order
should be inferred from the numbering unless explicitly stated. It
should be understood that some of these steps may be skipped,
performed in parallel, or performed without the requirement of
maintaining a strict order of sequence. The method starts at Step
1100.
[0083] Step 1100 supplies a metal foil substrate with a surface
selected from the group including titanium (Ti), Inconel alloy, and
Kovar. Step 1102 planarizes the metal foil substrate surface. Step
1104 deposits an electrical isolation layer overlying the
planarized metal foil substrate surface. Step 1106 deposits
amorphous silicon overlying the electrical insulation layer. Step
1108, from the amorphous silicon, forms polycrystalline silicon
overlying the electrical insulation layer. Step 1110 forms
thin-film transistors (TFTs) in the polycrystalline silicon. Step
1112 forms an electronic circuit using the TFTs. In some aspects,
forming an electronics circuit in Step 1112 includes forming a
organic light emitting diode (OLED) display.
[0084] In some aspects of the method, supplying a metal foil
substrate with a surface in Step 1102 includes supplying a metal
foil having a thickness in the range of 10 to 500 microns.
Preferably, the metal foil has a thickness in the range of 50 to
250 microns. Most preferably, the metal foil has a thickness in the
range of 100 to 200 microns.
[0085] In other aspects, depositing an electrical isolation layer
overlying the planarized metal foil substrate surface in Step 1104
includes depositing a layer having a thickness in the range of 0.5
to 2 microns. Preferably, the electrical isolation layer has a
thickness in the range of 0.5 to 1.5 microns. Most preferably, the
electrical isolation layer has a thickness in the range of 0.5 to 1
microns.
[0086] In some aspects, depositing amorphous silicon in Step 1106
includes depositing amorphous silicon having a thickness in the
range of 25 to 150 nm. Preferably, the amorphous silicon has a
thickness in the range of 25 to 100 nm. Most preferably, the
amorphous silicon has a thickness in the range of 35 to 60 nm.
[0087] FIG. 12 is a flowchart illustrating the present invention
method for forming an OLED display on a flexible substrate. The
method starts at Step 1200. Step 1202 supplies a metal foil
substrate with a surface selected from the group including titanium
(Ti), Inconel alloy, and Kovar. Step 1204 deposits an electrical
isolation layer overlying the planarized metal foil substrate
surface. Step 1206 deposits amorphous silicon overlying the
electrical insulation layer. Step 1208, from the amorphous silicon,
forms polycrystalline silicon overlying the electrical insulation
layer. Step 1210 forms thin-film transistors (TFTs) in the
polycrystalline silicon. Step 1212 forming OLEDs overlying the
TFTs. Step 1214 forms a resin layer overlying the OLEDs. Step 1216
forms a seal plate overlying the resin layer.
[0088] In some aspects of the method, supplying a metal foil
substrate with a surface in Step 1202 includes supplying a metal
foil having a thickness in the range of 10 to 500 microns.
Preferably, the metal foil has a thickness in the range of 50 to
250 microns. Most preferably, the metal foil has a thickness in the
range of 100 to 200 microns.
[0089] In other aspects, depositing an electrical isolation layer
overlying the planarized metal foil substrate surface in Step 1204
includes depositing a layer having a thickness in the range of 0.5
to 2 microns. Preferably, the electrical isolation layer has a
thickness in the range of 0.5 to 1.5 microns. Most preferably, the
electrical isolation layer has a thickness in the range of 0.5 to 1
microns.
[0090] In some aspects, depositing amorphous silicon in Step 1206
includes depositing amorphous silicon having a thickness in the
range of 25 to 150 nm. Preferably, the amorphous silicon has a
thickness in the range of 25 to 100 nm. Most preferably, the
amorphous silicon has a thickness in the range of 35 to 60 nm.
[0091] When the OLED cathode is grounded, forming OLEDs overlying
the TFTs in Step 1212 includes substeps. Step 1212a forms a metal
anode overlying the TFTs. Step 1212b forms a polymer organic layer
overlying the anode. Step 1212c forms a semi-transparent cathode
overlying the organic layer.
[0092] When the OLED anode is connected to a power line, forming
OLEDs overlying the TFTs in Step 1212 includes alternate substeps.
Step 1212d forms a metal cathode overlying the TFTs. Step 1212e
forms a polymer organic layer overlying the cathode. Step 1212c
forms a semi-transparent anode overlying the organic layer.
[0093] A metal foil substrate OLED display and a fabrication method
for same have been provided. Examples have been given as to how the
display elements can be arranged in a pixel area, but the present
invention is not limited to merely the depicted arrangements.
Specific examples of one and two-TFT pixels have been shown, but
the present invention is not limited to any particular number of
TFTs per pixel. Likewise, process specifics have been given to
demonstrate how such a display could be fabricated. However, many
of these process steps could be replaced with other conventional
processes. Although only top emission OLED displays have been
described, the present invention concepts are also applicable to
LCD displays, which also include pixel areas fabricated on a
substrate. Other variations and embodiments of the invention will
occur to those skilled in the art.
* * * * *