U.S. patent application number 11/904305 was filed with the patent office on 2008-06-12 for mim transistor.
This patent application is currently assigned to STMicroelectronics Crolles 2 SAS. Invention is credited to Benoit Froment, Etienne Robilliart.
Application Number | 20080135827 11/904305 |
Document ID | / |
Family ID | 37909614 |
Filed Date | 2008-06-12 |
United States Patent
Application |
20080135827 |
Kind Code |
A1 |
Froment; Benoit ; et
al. |
June 12, 2008 |
MIM transistor
Abstract
The invention concerns a conducting layer having a thickness of
between 1 and 5 atoms, an insulated gate being formed over a part
of the conducting layer.
Inventors: |
Froment; Benoit; (Bruxelles,
BE) ; Robilliart; Etienne; (Lumbin, FR) |
Correspondence
Address: |
SEED INTELLECTUAL PROPERTY LAW GROUP PLLC
701 FIFTH AVENUE, SUITE 5400
SEATTLE
WA
98104-7092
US
|
Assignee: |
STMicroelectronics Crolles 2
SAS
Crolles
FR
|
Family ID: |
37909614 |
Appl. No.: |
11/904305 |
Filed: |
September 25, 2007 |
Current U.S.
Class: |
257/9 ;
257/E29.04 |
Current CPC
Class: |
H01L 49/003
20130101 |
Class at
Publication: |
257/9 ;
257/E29.04 |
International
Class: |
H01L 29/08 20060101
H01L029/08 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 25, 2006 |
FR |
06/53920 |
Claims
1. A transistor comprising: a conducting layer having a thickness
of between 1 and 5 atoms; and an insulated gate being formed on at
least a portion of the conducting layer.
2. The transistor of claim 1, wherein the conducting layer is
formed of metal.
3. The transistor of claim 1, further comprising: a first electrode
and a second electrode, and the insulated gate being positioned
between the first and second electrodes.
4. The transistor of claim 3, wherein the conducting layer extends
between the first electrode and the second electrode.
5. The transistor of claim 1, wherein the conducting layer is on an
insulating layer such that the insulating layer is between the
conducting layer and a semiconductor substrate.
6. The transistor of claim 5, wherein the semiconductor substrate
under the transistor is connected to a determined voltage.
7. The transistor of claim 1, further comprising: a surface in
contact with the conducting layer having a nanoroughness.
8. The transistor of claim 1, wherein the insulated gate includes a
gate and an insulating layer between the gate and the conducting
layer.
9. The transistor of claim 1, wherein the transistor is integrated
into a semiconductor chip.
10. A transistor comprising: a conductive layer having a section
with a thickness equal to or less than 5 atoms; a gate on the
section of the conductive layer having the thickness equal to or
less than 5 atoms; and an insulating layer between the gate and the
conductive layer.
11. The transistor of claim 10, further comprising: a first
electrode and a second electrode on the conductive layer, the gate
and insulating layer positioned between and spaced apart from the
first electrode and the second electrode.
12. The transistor of claim 10, wherein the gate and the conductive
layer are made of metal.
13. The transistor of claim 10, further comprising: a substrate
under the conductive layer, the substrate comprising a
semiconductor substrate and a substrate insulating layer, and the
substrate insulating layer positioned between the conductive layer
and the semiconductor substrate.
14. The transistor of claim 10, wherein the conductive layer is on
a nano-roughened support surface.
15. The transistor of claim 14, further comprising: an insulating
layer having the nano-roughened support surface.
16. The transistor of claim 9, wherein the insulating layer has a
thickness that is sufficiently small such that at least a portion
of the conductive layer is depleted so that the transistor is in a
non-conducting state when an electric field is applied via the
insulated gate.
17. A structure comprising: a first transistor including a first
conducting layer having a thickness of between 1 and 5 atoms and a
first insulated gate being formed on at least a portion of the
first conducting layer; and a second transistor including a second
conducting layer having a thickness of between 1 and 5 atoms and a
second insulated gate being formed on at least a portion of the
second conducting layer, the second transistor adjacent to the
first transistor; wherein first and second semiconductor substrate
portions under the first and second transistors, respectively, have
opposite conductivity types, the first and second semiconductor
substrate portions are adjacent one another and configured to be
biased so that a junction between the semiconductor substrate
portions is non-conducting.
18. The structure of claim 17, where a first material forming the
first semiconductor substrate portion is N-type doped silicon and a
second material forming the second semiconductor substrate portion
is P-type doped silicon.
19. The structure of claim 17, wherein the first material
physically contacts the second material.
20. The structure of claim 17, wherein a continuous conducting
layer on an insulator forms the first and second conducting layers.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the field of miniaturized
electronic components.
[0003] 2. Description of the Related Art
[0004] In the field of voltage controlled integrated electronic
components, currently MOS (Metal-Oxide-Semiconductor) type
transistors are most commonly used, in which an isolated gate is
positioned above a semiconductor portion in which a conducting or
non-conducting channel can be formed depending on the biasing of
the gate. A distinction is generally made between MOS transistors
formed on a semiconductor wafer and MOS transistors formed on a
thin semiconducting layer covered by an insulating layer mounted on
a silicon wafer (SOI structure).
[0005] All of these MOS transistors present diverse problems when
it is attempted to reduce their dimensions in order to achieve
sizes in the order of several tens of nanometers. Among these
problems, there are in particular the following: [0006] particular
effects known as short channel effects are produced, these effects
resulting in only partial control of the channel inversion caused
by the field of the gate; this notably results in dependencies
between the threshold voltage of the transistor, the length of the
gate and the voltage applied between the source and drain of the
transistor; [0007] it is difficult to obtain a gate oxide
sufficiently thin and this leads to the use of gate insulating
materials having very high dielectric constants which today cause
integration problems; [0008] the cost of SOI type structures is
currently very high; [0009] there are difficulties, in particular
when a CMOS structure is used, in other words an N-channel MOS
transistor positioned alongside a P-channel MOS transistor, to
achieve good isolation between the transistors. Currently, the most
common technique consists in using shallow isolation trenches (STI
or Shallow Trench Isolation) or using insulating SOI wells, which
lead to insulating surfaces between the transistors which have
approximately the same surface area as the transistors, thereby
resulting in a large area of lost space on the semiconductor chip;
[0010] in general, there are numerous problems in differentiating
between the ON and OFF states.
BRIEF SUMMARY OF THE INVENTION
[0011] One embodiment provides a new transistor structure allowing
at least some of the problems associated with known MOS structures
to be resolved.
[0012] According to a first embodiment of the present invention,
there is provided a transistor comprising a conducting layer, for
example a metal layer, having a thickness of between 1 and 5 atoms,
an insulated gate being formed over a part of the conducting
layer.
[0013] According to one embodiment of the present invention,
electrodes are formed on both sides of the insulated gate.
[0014] According to a further embodiment of the present invention,
the conducting layer is formed on an insulating layer, the
insulating layer being formed on a semiconductor substrate.
[0015] According to a further embodiment of the present invention,
the semiconductor substrate under the transistor is connected to a
determined voltage.
[0016] According to a further embodiment of the present invention,
the surface in contact with the underside of the transistor is
treated to have a nanoroughness.
[0017] According to a second embodiment of the present invention,
there is provided a complementary structure comprising two
transistors as described above, formed adjacent to each other, in
which the adjacent semiconductor substrate portions under each
transistor are formed of opposite conductivity types, these
portions being arranged to be biased so that the junction between
them is non-conducting.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0018] The foregoing and other features, aspects and advantages
will become apparent from the following detailed description of
embodiments, given by way of illustration and not limitation with
reference to the accompanying drawings, in which:
[0019] FIG. 1 is a schematic view of a Metal-Insulator-Metal (MIM)
transistor according to an embodiment of the present invention;
[0020] FIG. 2 is a schematic view of a further embodiment of a MIM
transistor according to the present invention;
[0021] FIG. 3 shows the usual circuit diagram of a CMOS inverter;
and
[0022] FIGS. 4 and 5 are cross-section schematic views of
complementary MIM transistors according to embodiments of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0023] Embodiments disclosed herein are based on the phenomenon
that, when a charge is positioned (or an electric field is applied)
close to a metal lattice or to a conducting material, the surface
layer of the metal lattice or conducting layer tends to become
depleted. This phenomenon is limited to thicknesses in the order of
one or two crystalline atomic layers of metal (0.1 to 0.3 nm).
[0024] FIG. 1 shows a transistor that utilizes this phenomenon. A
very thin conductive layer (e.g., metal) 2 is deposited on an
insulating substrate 1, the conductive layer having a thickness of
one or a few atoms, for example a thickness in the order of 0.2 nm.
A conducting gate 5 is formed on a part of this layer 2, separated
from the layer 2 by an insulator 6. Contacts are made with the
metal layer 2 on one side and the other side of the gate, in order
to form source and drain contacts. With such a structure, depending
on the biasing of the gate, the resistance between the source and
drain zones will be increased or decreased due to the depletion
imposed on the metal by the gate. Such a structure will be referred
to as a MIM (Metal-Insulator-Metal) transistor.
[0025] Preferably, as illustrated in FIG. 2, a structure is
provided based on experience acquired in the field of standard MOS
transistor fabrication technology. For example, a silicon wafer 10
covered by a thin layer of silicon oxide 11 is used as a substrate,
the silicon oxide layer being covered by the very thin metal layer
2 on which the source and drain contacts S and D are formed on
either side of the insulated gate 5.
[0026] The source voltage will be referred to as V.sub.S, the drain
voltage as V.sub.D, the gate voltage as V.sub.G, and the positive
supply voltage as Vdd. With the structure of FIG. 2, simulations
have shown that, for a gate voltage V.sub.G=0, if the substrate 10
is connected to ground, a conducting state, or ON state, is
obtained for a source voltage V.sub.S=0 and a positive drain
voltage V.sub.D=Vdd. It follows that the resistance in the
conducting state, R.sub.ON, is equal to the resistance per square
unit R.sub.sq of the metallic layer, multiplied by the ratio
between the length and width of the gate L/W. In other words,
R.sub.ON=R.sub.sq(L/W). For a metal layer, for example of nickel,
having a thickness of 0.2 nm and a resistivity .rho.=5 microohms.cm
and for a gate length L of 50 nm and a gate width W of 1 .mu.m,
R.sub.ON in the region of 10 ohms is obtained.
[0027] In the non-conducting state or OFF state, the corresponding
voltages are for example V.sub.S=0, V.sub.D=Vdd, V.sub.G=Vdd, and
R.sub.OFF is then in the region of 1000 ohms or more.
[0028] According to another embodiment, a thin metal layer is
deposited on an insulating layer having a certain roughness. There
are various knowing methods for obtaining a silicon oxide surface
having a roughness in the order of a few angstroms, or
nanoroughness. For example the oxide surface could be bombarded
with argon ions before the metal layer is deposited. It has been
shown by simulations that this roughness of the silicon oxide
surface appreciably increases the ratio I.sub.ON/I.sub.OFF between
the current in the ON state and current in the OFF state.
[0029] Transistors described above can be used to provide
complementary type structures.
[0030] FIG. 3 shows a circuit diagram of a complementary CMOS
inverter comprising two complementary transistors M1 and M2
connected in series between a supply voltage Vdd and ground, their
gates together receiving an input voltage Vin, and the common node
between the transistors being connected to an output node OUT.
[0031] FIG. 4 is a schematic illustration of an example embodiment
of such a structure, comprising MIM transistors as described above.
According to this embodiment of the present invention, the
substrates of two adjacent transistors are biased differently in
order to provide the equivalent to a complementary CMOS transistor
structure.
[0032] Each of the transistors M1 and M2 comprises, as described
above, a very thin conductive layer 2 deposited on an insulating
layer 11. Each of the transistors comprises a gate 5 isolated by an
insulating layer 6. The transistor M1 comprises a source contact 20
and a drain contact 21. The drain contact 21 also forms the source
contact of transistor M2, transistor M2 also comprising a drain
contact 22 on the other side of the gate. In the example embodiment
shown, transistor M1 is formed on an N-type doped silicon layer 31
and the transistor M2 is formed on a P-type doped silicon layer 32.
These layers are formed using known technology relating to
integrated circuit implementation on silicon. A contact 33 is
formed on the N type silicon layer 31, over an intermediate more
highly doped N-type layer 35. In the same way, a contact 34 is
formed on the P-type doped silicon layer 32, over an intermediate
more highly doped P-type region 36. The gates of the two
transistors are together connected to a voltage Vin, the node 21
providing the output OUT of the inverter.
[0033] In the state shown in FIG. 4, the N layer 31 is connected to
Vdd, the P layer 32 is connected to a zero voltage, a zero voltage
is applied to the node 20 and a voltage Vdd is applied to node 22.
Therefore, when the input Vin is connected to Vdd, transistor M2 is
non-conducting (OFF) and transistor M1 is conducting (ON),
resulting in a zero voltage being provided at the output node
OUT.
[0034] FIG. 5 shows the complementary state, in which the same
voltages are applied to the substrate, but the voltage Vin is
inversed and is now equal to 0. Transistor M2 is now therefore
conducting (ON) and transistor M1 is non-conducting (OFF), and the
output voltage at node OUT is equal to Vdd.
[0035] It will be apparent to those skilled in the art that the
embodiment illustrated in FIGS. 4 and 5 is extremely schematic and
can be subjected to numerous variations. This example has been
given to present one of the advantages of the disclosed
embodiments, that two complementary MIM transistors can be
positioned adjacent to each other without it being necessary to
provide an insulating structure between them. Isolation between the
adjacent substrates is ensured, an N-type region being polarized by
a first voltage whilst a P-type region is polarized at a lower
voltage.
[0036] A fundamental advantage of the MIM transistors described
above is that an insulating region is no longer necessary between
adjacent transistors, which allows a considerable reduction in the
integrated surface area.
[0037] A further advantage of the disclosed embodiments is that the
short channel effect no longer exists due to the channel being very
thin and there being practically total control by the gate of the
whole length of the channel.
[0038] A further advantage of the disclosed embodiments is that the
technology is very simple: numerous implantation levels are not
necessary and, if necessary, a structure can be provided on the
same semiconductor chip as a standard MOS or bipolar transistor
structure.
[0039] A further advantage of the disclosed embodiments is that the
switch speed of the transistor is very fast, being limited only by
the relaxation speed of electrons in the metal.
[0040] A further advantage of the disclosed embodiments is that the
resistance in the conducting state is very low, in other words the
current in the conducting state can be high.
[0041] The present invention is susceptible to numerous variations
and modifications which will appear to the man skilled in the art.
In particular, those skilled in the art will select materials that
are appropriate to the particular technologies used. Notably, for
forming the very thin metal layer, a material such as W, Ni, Mo,
Ta, Ti, Pt, having a thickness of 0.2 to 1 nm could for example be
used. Metal alloys could also be used, such as Ni--W, Ni--Fe, for
which depletion may be greater. Non-metal conducting materials
could also be used, which, while having higher resistance, may
provide greater depletion.
[0042] One embodiment has been presented in the form of a planar
transistor. The present invention applies more generally to all
structures and all types of transistors in which a depletion effect
can be used.
[0043] The various embodiments described above can be combined to
provide further embodiments. All of the U.S. patents, U.S. patent
application publications, U.S. patent applications, foreign
patents, foreign patent applications and non-patent publications
referred to in this specification and/or listed in the Application
Data Sheet, are incorporated herein by reference, in their
entirety. Aspects of the embodiments can be modified, if necessary
to employ concepts of the various patents, applications and
publications to provide yet further embodiments.
[0044] These and other changes can be made to the embodiments in
light of the above-detailed description. In general, in the
following claims, the terms used should not be construed to limit
the claims to the specific embodiments disclosed in the
specification and the claims, but should be construed to include
all possible embodiments along with the full scope of equivalents
to which such claims are entitled. Accordingly, the claims are not
limited by the disclosure.
* * * * *