U.S. patent application number 11/593776 was filed with the patent office on 2008-05-29 for dram concurrent writing and sensing scheme.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Shine Chung, Cheng-Hsien Hung.
Application Number | 20080123447 11/593776 |
Document ID | / |
Family ID | 39387641 |
Filed Date | 2008-05-29 |
United States Patent
Application |
20080123447 |
Kind Code |
A1 |
Chung; Shine ; et
al. |
May 29, 2008 |
DRAM CONCURRENT WRITING AND SENSING SCHEME
Abstract
This invention discloses a write-sensing circuit for
semiconductor memories comprising a first and a second local
bit-lines (BLs) forming a complementary BL pair, a first and a
second global bit-lines (GBLs) forming a complementary GBL pair,
and at least one switching circuit controlled by the first and
second GBLs and controllably coupling a predetermined power supply
source to the first and second BLs, separately, wherein when the
first and second GBLs are asserted during a write operation, the
switching circuit couples only one of the first and second BLs to
the predetermined voltage supply source.
Inventors: |
Chung; Shine; (Taipei Hsien,
TW) ; Hung; Cheng-Hsien; (Hsinchu, TW) |
Correspondence
Address: |
L. Howard Chen, Esq.;Kirkpatrick & Lockhart Preston Gates Ellis LLP
Suite 1700, 55 Second Street
San Francisco
CA
94104
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
|
Family ID: |
39387641 |
Appl. No.: |
11/593776 |
Filed: |
November 7, 2006 |
Current U.S.
Class: |
365/202 ;
365/205; 365/226 |
Current CPC
Class: |
G11C 11/4076 20130101;
G11C 11/4096 20130101; G11C 11/4097 20130101 |
Class at
Publication: |
365/202 ;
365/205; 365/226 |
International
Class: |
G11C 7/00 20060101
G11C007/00; G11C 5/14 20060101 G11C005/14 |
Claims
1. A write-sensing circuit for semiconductor memories comprising: a
first and a second local bit-lines (BLs) forming a complementary BL
pair; a first and a second global bit-lines (GBLs) forming a
complementary GBL pair; and at least one switching circuit
controlled by the first and second GBLs and controllably coupling a
predetermined power supply source to the first and second BLs,
separately, wherein when the first and second GBLs are asserted
during a write operation, the switching circuit couples only one of
the first and second BLs to the predetermined voltage supply
source, wherein the predetermined voltage supply source is a lower
voltage power supply source (Vss), wherein the switching circuit
comprises a first and a second N-type metal-oxide-semiconductor
(NMOS) transistors, wherein sources of both the first and second
NMOS transistors are coupled to the Vss, a drain of the first NMOS
transistor is coupled to the second BL, a drain of the second NMOS
transistor is coupled to the first BL, a gate of the first NMOS
transistor is coupled to the first GBL and a gate of the second
NMOS transistor is coupled to the second GBL, wherein the first and
second GBLs remains the same polarity during both read and write
operations.
2. (canceled)
3. (canceled)
4. The write-sensing circuit of claim 1, wherein the switching
circuit comprises a first and a second N-type
metal-oxide-semiconductor (NMOS) transistors, wherein sources of
both the first and second NMOS transistors are coupled to the Vss,
a drain of the first NMOS transistor is coupled to the first BL, a
drain of the second NMOS transistor is coupled to the second BL, a
gate of the first NMOS transistor is coupled to the first GBL and a
gate of the second NMOS transistor is coupled to the second GBL,
wherein the first and second GBLs swap polarities when a operation
changes from a read to a write.
5. The write-sensing circuit of claim 1, wherein the predetermined
power supply source is a positive high voltage power supply source
(Vcc).
6. The write-sensing circuit of claim 5, wherein the switching
circuit comprises a first and a second P-type
metal-oxide-semiconductor (PMOS) transistors, wherein sources of
both the first and second PMOS transistors are coupled to the Vcc,
a drain of the first PMOS transistor is coupled to the second BL, a
drain of the second PMOS transistor is coupled to the first BL, a
gate of the first PMOS transistor is coupled to the first GBL and a
gate of the second PMOS transistor is coupled to the second GBL,
wherein the first and second GBLs remains the same polarity during
both read and write operations.
7. The write-sensing circuit of claim 5, wherein the switching
circuit comprises a first and a second P-type
metal-oxide-semiconductor (PMOS) transistors, wherein sources of
both the first and second PMOS transistors are coupled to the Vcc,
a drain of the first PMOS transistor is coupled to the first BL, a
drain of the second PMOS transistor is coupled to the second BL, a
gate of the first PMOS transistor is coupled to the first GBL and a
gate of the second PMOS transistor is coupled to the second GBL,
wherein the first and second GBLs swap polarities when an operation
changes from a read to a write.
8. The write-sensing circuit of claim 1 further comprising at least
one sense amplifier coupled between the first and second BLs with
the predetermined power supply source supplies power to the sense
amplifier, wherein the assertion of the predetermined power supply
source activates the sense amplifier.
9. The write-sensing circuit of claim 8, wherein the sense
amplifier comprises two cross-coupled inverters.
10. The write-sensing circuit of claim 1 further comprising a first
and a second N-type metal-oxide-semiconductor (NMOS) transistors
with a source and a drain of the first NMOS transistor coupled to
the first BL and the first GBL, respectively, a source and a drain
of the second NMOS transistor coupled to the second BL and the
second GBL, respectively, and the gates of both the first and
second NMOS transistors commonly coupled to a control signal.
11. A write-sensing circuit for dynamic random access memories
(DRAMs) comprising: a first and a second local bit-lines (BLs)
forming a complementary BL pair; a first and a second global
bit-lines (GBLs) forming a complementary GBL pair; and at least one
switching circuit controlled by the first and second GBLs and
controllably coupling a lower voltage power supply source (Vss) to
the first and second BLs, separately, wherein when the
complementary first and second GBLs are asserted during a write
operation, the switching circuit couples only one of the first and
second BLs to the Vss, wherein the switching circuit comprises a
first and a second N-type metal-oxide-semiconductor (NMOS)
transistors, wherein sources of both the first and second NMOS
transistors are coupled to the Vss, a drain of the first NMOS
transistor is coupled to the second BL, a drain of the second NMOS
transistor is coupled to the first BL, a gate of the first NMOS
transistor is coupled to the first GBL and a gate of the second
NMOS transistor is coupled to the second GBL, wherein the first and
second GBLs remains the same polarity during both read and write
operations.
12. (canceled)
13. The write-sensing circuit of claim 11, wherein the switching
circuit comprises a first and a second N-type
metal-oxide-semiconductor (NMOS) transistors, wherein sources of
both the first and second NMOS transistors are coupled to the Vss,
a drain of the first NMOS transistor is coupled to the first BL, a
drain of the second NMOS transistor is coupled to the second BL, a
gate of the first NMOS transistor is coupled to the first GBL and a
gate of the second NMOS transistor is coupled to the second GBL,
wherein the first and second GBLs swap polarities when an operation
changes from a read to a write.
14. The write-sensing circuit of claim 11 further comprising at
least one sense amplifier coupled between the first and second BLs
with the predetermined power supply source supplies power to the
sense amplifier, wherein the assertion of the predetermined power
supply source activates the sense amplifier.
15. The write-sensing circuit of claim 14, wherein the sense
amplifier comprises two cross-coupled inverters.
16. A write-sensing circuit for dynamic random access memories
(DRAMs) comprising: a first and a second local bit-lines (BLs)
forming a complementary BL pair; a first and a second global
bit-lines (GBLs) forming a complementary GBL pair; and at least one
switching circuit controlled by the first and second GBLs and
controllably coupling a positive high voltage power supply source
(Vcc) to the first and second BLs, separately, wherein when the
complementary first and second GBLs are asserted during a write
operation, the switching circuit couples only one of the first and
second BLs to the Vcc.
17. The write-sensing circuit of claim 16, wherein the switching
circuit comprises a first and a second P-type
metal-oxide-semiconductor (PMOS) transistors, wherein sources of
both the first and second PMOS transistors are coupled to the Vcc,
a drain of the first PMOS transistor is coupled to the second BL, a
drain of the second PMOS transistor is coupled to the first BL, a
gate of the first PMOS transistor is coupled to the first GBL and a
gate of the second PMOS transistor is coupled to the second GBL,
wherein the first and second GBLs remains the same polarity during
both read and write operations.
18. The write-sensing circuit of claim 16, wherein the switching
circuit comprises a first and a second P-type
metal-oxide-semiconductor (PMOS) transistors, wherein sources of
both the first and second PMOS transistors are coupled to the Vcc,
a drain of the first PMOS transistor is coupled to the first BL, a
drain of the second PMOS transistor is coupled to the second BL, a
gate of the first PMOS transistor is coupled to the first GBL and a
gate of the second PMOS transistor is coupled to the second GBL,
wherein the first and second GBLs swap polarities when a operation
changes from a read to a write.
19. The write-sensing circuit of claim 16 further comprising at
least one sense amplifier coupled between the first and second BLs
with the predetermined power supply source supplies power to the
sense amplifier, wherein the assertion of the predetermined power
supply source activates the sense amplifier.
20. The write-sensing circuit of claim 19, wherein the sense
amplifier comprises two cross-coupled inverters.
Description
BACKGROUND
[0001] The present invention relates generally to dynamic random
access memory (DRAM) circuits, and, more particularly, to designs
of DRAM write circuit.
[0002] Dynamic random access memory (DRAM) is a type of random
access memory that stores each bit of data in a separate capacitor.
A simplest DRAM cell comprises a single N-type
metal-oxide-semiconductor (NMOS) transistor and a single capacitor.
If charges are stored in the capacitor, the cell is said to store a
logic HIGH, depending on the convention used. Then if no charge is
present, the cell is said to store a logic LOW. Since the charges
in the capacitor dissipate over time, DRAM systems require
additional refreshing circuitries to periodically refresh the
charges stored in the capacitors. Since a capacitor can store only
a very limited amount of charges, to fast distinguish the
difference between a logic `1` and a logic `0`, two bit-lines (BLs)
are typically used for each bit with the first in the bit line pair
known as a bit line true (BLT) and the other being the bit line
complement (BLC). Prior to a sensing, BLT and BLC are equalized to
the same voltage. Upon a sensing, the voltages of the BL pair start
to split oppositely, e.g., if BLT swings to a higher voltage, then
BLC swings to lower voltage. A sense amplifier compares BLT and BLC
voltages and outputs either a high or a low voltage to represent a
logic value stored in the bit.
[0003] The single NMOS transistor's gate is controlled by a
word-line (WL). When the WL is asserted a logic high voltage, the
single NMOS transistor will be turned on and allow the cell
capacitor to be accessed.
[0004] In a large DRAM bank, memory cells are organized in blocks,
and a bank may contain a plurality of blocks. A BL pair is coupled
to all the cells in a column of a block, and then a global bit-line
(GBL) pair is coupled to all the BL pairs belonging to the same
column of the plurality of blocks through select transistors, which
is controlled, conventionally, by a single select signal for the
entire bank. The GBL pairs are coupled to the data input/output
through multiplexers. When writing or reading the DRAM-cells, the
select transistors are turned on, so that data can be written into
the memory cells from the corresponding GBL pairs and through the
corresponding BL pairs, or read from the memory cells through the
corresponding BL pairs onto the corresponding GBL pairs. During
memory cell refreshing, since the cells are not accessed, so that
the select transistors need not be turned on.
[0005] In general, accessing a DRAM cell involves WL activation,
signal development on the BL pairs, BL sensing, WL deactivation and
BL equalization (EQ). BL sensing is a signal write back or
refreshing process. When a DRAM cell is being written, outside
voltage will charge the storage capacitor, there is no data loss
issue. But if the memory cell is not being written and not fully
refreshed before connecting its corresponding BL pair to its
corresponding GBL pair, data stored in the memory cell may be lost
due to large capacitive load of the GBL.
[0006] Assuming a 64-bit DRAM has 256 columns in a bank, then each
time only 1/4 of the BLs need to be accessed. However, because all
the select transistors of an entire bank are controlled by a single
signal in conventional DRAMs, all 256 BL pairs are connected to
their corresponding GBL pairs during a write operation, even though
only 64 GBL pairs are forced with outside voltage source. If the
memory cells on the rest 192 BL pairs are not fully refreshed prior
to the select transistor's turn-on, these memory cells may suffer
data loss. For this reason, the write operation in conventional
DRAM must be sequential, i.e., writing may only start after a
sensing is completed.
[0007] FIG. 1 shows a timing sequence of writing in a conventional
DRAM. Prior to the writing 108, the BLs are equalized in time slot
102. At the beginning of the writing, the WL starts to develop in
time slot 104, and maintains activated throughout the entire write
cycle 100. Sensing occurs in time slot 106. During this time, all
the cells coupled to the activated WL are refreshed to their full
capacity. Writing to the selected cells happens in time slot 108
after the sensing period 106 is completed. Due to these sequential
executions, the writing cycle 100 is particularly long, which
limits the overall speed of the DRAM.
[0008] One way to overcome this limitation is to selectively turn
on only those select transistors for the BL pairs being accessed,
while keep the rest of the select transistors in the memory bank in
off state. But this requires additional select signal lines, which
will increase the memory die size.
[0009] As such, what is desired is a DRAM writing scheme that
allows early writing, i.e., simultaneous writing and sensing,
without increasing memory die size.
SUMMARY
[0010] This invention discloses a write-sensing circuit for
semiconductor memories comprising a first and a second local
bit-lines (BLs) forming a complementary BL pair, a first and a
second global bit-lines (GBLs) forming a complementary GBL pair,
and at least one switching circuit controlled by the first and
second GBLs and controllably coupling a predetermined power supply
source to the first and second BLs, separately, wherein when the
first and second GBLs are asserted during a write operation, the
switching circuit couples only one of the first and second BLs to
the predetermined voltage supply source.
[0011] The construction and method of operation of the invention,
however, together with additional objectives and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The drawings accompanying and forming part of this
specification are included to depict certain aspects of the
invention. A clearer conception of the invention, and of the
components and operation of systems provided with the invention,
will become more readily apparent by referring to the exemplary,
and therefore non-limiting, embodiments illustrated in the
drawings, wherein like reference numbers (if they occur in more
than one view) designate the same elements. The invention may be
better understood by reference to one or more of these drawings in
combination with the description presented herein. It should be
noted that the features illustrated in the drawings are not
necessarily drawn to scale.
[0013] FIG. 1 illustrates a conventional write timing sequence.
[0014] FIG. 2 illustrates a write timing sequence of a concurrent
writing and sensing scheme according to one embodiment of the
present invention.
[0015] FIG. 3 is a schematic diagram illustrating an array
structure of a DRAM according to the embodiment of the present
invention.
[0016] FIGS. 4A.about.4C are schematic diagrams illustrating three
implementations of a write-sensing block according to embodiments
of the present invention.
[0017] FIG. 5 is a schematic diagram illustrating an implementation
of a read/write data path employed in the DRAM of the present
invention.
DESCRIPTION
[0018] The present invention discloses a concurrent writing and
sensing scheme in dynamic random access memories (DRAM) that can
shorten the write cycle of the DRAM.
[0019] FIG. 1 has already been described and discussed as the
relevant background to the present invention. It requires no
further discussion here.
[0020] FIG. 2 illustrates a write timing sequence of a concurrent
writing and sensing scheme according to one embodiment of the
present invention. Here bit-lines (BLs) are also first equalized in
time slot 202. At the beginning of a writing, a selected word-line
(WL) develops in time slot 204. Then sensing starts in time slot
206 as that of the conventional DRAM shown in FIG. 1. But the
present invention starts writing in time slot 208 right after the
WL is developed in time slot 204, concurrent to the sensing in time
slot 206, therefore a write cycle 200 of the present invention is
shortened comparing to the conventional write cycle 100 shown in
FIG. 1.
[0021] A key aspect of the present invention is to keep select
transistors that connect BLs to their corresponding GBLs in off
state during write operation, so that those non-accessed cells in a
memory bank will not face data loss issue if the writing starts
before a sensing ends. Without turning on the select transistors,
the present invention writes data to memory cells through separate
paths which will be described in details in following
paragraphs.
[0022] FIG. 3 is a schematic diagram illustrating a memory core
structure 300 of a DRAM according to the embodiment of the present
invention. For illustrative purpose, the DRAM core structure 300 is
shown to comprise a plurality of blocks 310[0:n], a plurality of
blocks 340[0:n+1], a block 370 and a plurality of global-bit-lines
360[0:m-1] coupled to the block 370, where n and m are
integrals.
[0023] Referring to FIG. 3, the blocks 310[0:n] may be implemented
as DRAM banks. Each bank 310 may comprise a DRAM cell array 320,
and two write-sensing (WS) blocks 330s, one 330[Lx] on the left,
and the other 330[Rx] on the right, where x is an integral between
0 and n. A typical size of the array 320 is 32 rows (WLs) by 1024
columns (BLs). The block 340 may be implemented as a 2-to-1
multiplexer placed between two adjacent banks 310[0] and 310[1] as
shown in FIG. 3. The multiplexer 340[1] selects one of the two WS
blocks 330[R0] and 330[L1]. The output of the multiplexer 340[1] is
coupled to the global-bit-line 360[0]. A left and a right adjacent
WS blocks 330s and a multiplexer 340 form a read-write block 350.
The block 370 may be implemented as a m-to-1 multiplexer to save
line routings in the DRAM. Typically, m=8. FIG. 3 shows only array
structure of one bit, some DRAM may access 64 bits, or columns at a
time. Then for a word-line having 1024 columns, only 64 out of the
1024 columns are written and the rest are sensed and hence
refreshed during a write cycle. Conventionally, the
global-bit-lines 360s are always constructed in pairs to supply a
differential voltage or current to a data sense amplifier.
[0024] FIGS. 4A.about.4C are schematic diagrams illustrating three
implementations of the read-write block 350 according to
embodiments of the present invention. In general, the read-write
block 350 comprises of the multiplexer 340 and two WS blocks 330s.
The multiplexer 340 may be implemented as N-type
metal-semiconductor-oxide (NMOS) transistors, 342, 344, 346 and
348, serving as pass gates between local bit-lines and
global-bit-lines (GBLs). When signal SSL turns to a logic HIGH,
while signal SSR turns to a logic LOW, the NMOS transistors 342 and
344 are turned on while the NMOS transistors 346 and 348 are turned
off, so that the local bit-lines (BL) of the left write-sensing
block 330 are selected to be coupled to the global-bit-lines (362
and 364), i.e., BL[0] is coupled to GBL 362, and BLB[0] is coupled
to GBLB 364. On the other hand, when signal SSL turns to the logic
LOW, while signal SSR turns to a logic HIGH, the NMOS transistors
342 and 344 are turned off while the NMOS transistors 346 and 348
are turned on, so that local bit-lines (BL) of the right
write-sensing block 330 are selected to be coupled to the
global-bit-lines (362 and 364), i.e., BL[1] is coupled to GBL 362,
and BLB[1] is coupled to GBLB 364.
[0025] Referring to FIGS. 4A.about.4C, the WS block 330 comprises a
local BL sense amplifier block 332 and a local BL switching block
334. The sense amplifier block 332 may be implemented as a
conventional cross-coupled inverter pair. To activate the sense
amplifier block 332, signal SP will be pulled up to a positive high
supply voltage (Vcc), and signal SN will be pulled down to a
complimentary low supply voltage (Vss). Differences among
implementations shown in FIG. 4A.about.4C are in the formations and
connections of the BL switching block 432 in FIG. 4A, 434 in FIGS.
4B and 436 in FIG. 4C.
[0026] Referring to FIG. 4A, the BL switching block 432 is formed
by two NMOS transistors 402 and 404. Both sources of the NMOS
transistors 402 and 404 are coupled to the signal SN. A drain and a
gate of the NMOS transistor 402 are coupled to the BLB and
global-bit-line 362, respectively. A drain and a gate of the NMOS
transistor 404 are coupled to the BL and global-bit-line 364,
respectively. During both read and write operations, the
global-bit-lines 362 and 364 are consistently coupled to GBL and
GBLB, respectively. Note that in FIG. 4A, the bit-lines at the
drain of the NMOS transistor 402 and 404 and the bit-lines at the
output of the sense amplifier 332 are twisted.
[0027] Referring to FIG. 4B, the BL switching block 434 is also
formed by two NMOS transistors 402 and 404. Both sources of the
NMOS transistors 402 and 404 are coupled to the signal SN. A drain
and a gate of the NMOS transistor 402 are coupled to the BL and
global-bit-line 362, respectively. A drain and a gate of the NMOS
transistor 404 are coupled to the BLB and global-bit-line 364,
respectively. During read operation, the global-bit-lines 362 and
364 are coupled to GBL and GBLB, respectively. During write
operation, instead, the global-bit-lines 362 and 364 are coupled to
GBLB and GBL, respectively. By swapping the global-bit-lines, the
local bit-lines may avoid the twisting, therefore saving layout
space and complexity.
[0028] Referring to FIG. 4C, the BL switching block 436 is formed
by two P-type metal-semiconductor-oxide (PMOS) transistors 412 and
414. Both sources of the PMOS transistors 412 and 414 are coupled
to the signal SP. A drain and a gate of the PMOS transistor 412 are
coupled to the BL and global-bit-line 362, respectively. A drain
and a gate of the PMOS transistor 414 are coupled to the BLB and
global-bit-line 364, respectively. During read operation, the
global-bit-lines 362 and 364 are coupled to GBL and GBLB,
respectively. During write operation, instead, the global-bit-lines
362 and 364 are coupled to GBLB and GBL, respectively. By swapping
the global-bit-lines, the local bit-lines may avoid the twisting,
therefore save layout space and complexity.
[0029] The DRAM cell and local bit-lines (not shown) are operated
as conventional DRAMs, i.e., the local bit-lines may be pre-charged
to Vcc/2, and during sensing, the state of a selected DRAM cell may
cause the bit-line pair to develop a differential voltage, which
will be amplified by the BL sense amplifier 332 to eventually
rail-to-rail voltage levels.
[0030] During read operation, the global-bit-line 362 and 364 are
pre-charged to Vss for read-write block 350 shown in FIGS. 4A and
4B, and pre-charged to Vcc for read-write block 350 shown in FIG.
4C. The rest of the read operation is identical to all three
implementations shown in FIGS. 4A.about.4C. At the start of a read,
the pull-downs and equalizers (not shown) of local bit-lines are
de-asserted, and a selected word-line (not shown) is asserted. In
order to activate the BL sense amplifier, the signals SN and SP are
pulled to Vss and Vcc, respectively. After the BL is sensed, either
signal SSL or signal SSR will be turned on. In case the
global-bit-lines 362 and 364 are pre-charged to Vss, if BL has
developed to the logic HIGH, then the global-bit-line 362 will be
pulled to the logic HIGH, while the global-bit-line 364 remains
low. Then the differential voltage between the global-bit-lines 362
and 364 can be detected by a sense amplifier (not shown) after the
multiplexer 370 shown in FIG. 3. In case the global-bit-lines 362
and 364 are pre-charged to Vcc, a logic LOW bit-line will develop
the differential voltage between the global-bit-line 362 and
364.
[0031] Referring to FIGS. 4A and 4B, since the global-bit-lines 362
and 364 are pre-charged to Vss, and their voltage swing during
sensing will not be high enough to turn on the NMOS transistor 402
or 404 before the sensing ends, so the NMOS transistor 402 and 404
are always off during read operation. The implementations shown in
FIGS. 4A and 4B work just as that in a conventional DRAM.
[0032] Referring to FIG. 4C, since the global-bit-lines 362 and 364
are pre-charged to Vcc, and their voltage swing during sensing will
not be lower enough to turn on the PMOS transistor 412 or 414
before the sensing ends, so the PMOS transistor 412 and 414 are
always off during read operation. The implementations shown in FIG.
4C also works just as that in a conventional DRAM.
[0033] During the write operation for the implementations shown in
FIGS. 4A.about.4C, both signals SSL and SSR remain de-asserted at
the logic LOW, so that none of the inputs of multiplexer 340 are
selected. At the start of a writing, as in the read case, the
bit-line pull-up and equalizer are turned off, and a selected
word-line is asserted, and then the bit-line sense amplifier 332 is
activated by pulling signal SN to Vss and signal SP to Vcc. For
only those selected columns, their corresponding global-bit-lines
are driven to a complimentary one-HIGH-one-LOW voltages, hence
writing data into the DRAM cells on the asserted word-line and the
selected global-bit-lines. The rest of the global-bit-lines remains
pre-charged, and the bit-line and sense amplifier conditions are
just like that in a read operation, so the DRAM cells on the
asserted word-line but the unselected global-bit-lines are sensed
and hence refreshed. How data are exactly written into the DRAM
cells are described in the following paragraphs.
[0034] Referring to FIG. 4A, when intending to write a logic LOW
into a selected DRAM cell, the corresponding global-bit-lines 362
and 364 or GBL and GBLB are driven to the logic LOW and HIGH,
respectively. Then the NMOS transistors 402 and 404 in the
switching block 432 are turned off and on, respectively. As signal
SN has been pulled to Vss, so that the turned-on NMOS transistor
404 will force BL voltage down to Vss. With the amplification of
the BL sense amplifier 332, the BL and BLB will eventually be
driven to Vss and Vcc, respectively, therefore, a logic LOW will be
written into the DRAM cell on the BL. Oppositely, when intending to
write a logic HIGH into a selected DRAM cell, the corresponding
global-bit-lines 362 and 364 or GBL and GBLB are driven to the
logic HIGH and LOW, respectively. In this case the BL and BLB are
driven to logic HIGH and LOW, respectively, and hence a logic HIGH
will be written into the DRAM cell on the BL.
[0035] Referring to FIG. 4B, when intending to write a logic LOW
into a selected DRAM cell, the corresponding global-bit-lines 362
and 364 or GBLB and GBL are driven to the logic HIGH and LOW,
respectively. Note that the global-bit-lines 362 and 364 are
coupled to GBLB and GBL, respectively, during write operation while
they are coupled to GBL and GBLB, respectively, during read
operation. Then the NMOS transistors 402 and 404 in the switching
block 434 are turned on and off, respectively. As signal SN has
been pulled to Vss, so that the turned-on NMOS transistor 402 will
force BL voltage down to Vss. With the amplification of the BL
sense amplifier 332, the BL and BLB will eventually be driven to
Vss and Vcc, respectively, therefore, a logic LOW will be written
into the DRAM cell on the BL. Oppositely, when intending to write a
logic HIGH into a selected DRAM cell, the corresponding
global-bit-lines 362 and 364 or GBLB and GBL are driven to the
logic LOW and HIGH, respectively. In this case the BL and BLB are
driven to the logic HIGH and LOW, respectively, and hence a logic
HIGH will be written into the DRAM cell on the BL.
[0036] Referring to FIG. 4C, when intending to write a logic LOW
into a selected DRAM cell, the corresponding global-bit-lines 362
and 364 or GBLB and GBL are driven to the logic HIGH and LOW,
respectively. Note that the global-bit-lines 362 and 364 are
coupled to GBLB and GBL, respectively, during write operation while
they are coupled to GBL and GBLB, respectively, during read
operation. Then the PMOS transistors 412 and 414 in the switching
block 436 are turned off and on, respectively. As signal SP has
been pulled to Vcc, so that the turned-on PMOS transistor 402 will
force BLB voltage up to Vcc. With the amplification of the BL sense
amplifier 332, the BL and BLB will eventually be driven to Vss and
Vcc, respectively, therefore, a logic LOW will be written into the
DRAM cell on the BL. Oppositely, when intending to write a logic
HIGH into a selected DRAM cell, the corresponding global-bit-lines
362 and 364 or GBLB and GBL are driven to the logic LOW and HIGH,
respectively. In this case the BL and BLB are driven to the logic
HIGH and LOW, respectively, and hence a logic HIGH will be written
into the DRAM cell on the BL.
[0037] Although only one example employing PMOS transistors in the
switching block 436 is shown in FIG. 4C, one having skill in the
art would recognize that PMOS transistors may also be used to
construct a circuit similar to the one shown in FIG. 4A with
bit-lines twisted, yet, global-word-line polarities need not be
swapped when operations changing from read to write.
[0038] In essence, the present invention utilizes the data
themselves on the GBLs to selectively pull the BLs to their desired
states for writing their corresponding memory cells without turning
on the select transistors. Also note that in all three
implementations of the read-write block 350 shown in FIGS.
4A.about.4C, writing to selected DRAM cells happens concurrently
with the sensing, i.e., refreshing of the none selected DRAM cells
in the same asserted word-line, therefore, the write cycle
according to the embodiments of the present invention takes
approximately the same amount of time, and the overall speed of the
DRAM may be increased. Since there are only two transistors (432,
434 or 436) are added to the BL sense amplifier 332, they can be
inserted in the layout pitch of the existing BL sense amplifier
332, so that the memory die size do not need to be increased.
[0039] FIG. 5 is a schematic diagram illustrating an implementation
of a read/write data path 500 employed in the DRAM of the present
invention. The data path 500, which comprises a write path 510 and
a read path 520, shows data paths before the multiplexer block 370
shown in FIG. 3. The write path 510 may be implemented as a series
of inverter drivers 512, 514 and 516. The read path 520 may be
implemented as a global-bit-line sense amplifier 522 and a driver
524. Whether the write and read paths 510 and 520 inverting data or
not, depends on whether a logic HIGH is represented by Vss or Vcc
stored in a DRAM cell. But the write and read paths 510 and 520
must be designed in the same polarity characteristic, i.e., both
must be either inverting or not inverting at the same time. The
data path 500 shown in FIG. 5 is adopted from conventional
designs.
[0040] The above illustration provides many different embodiments
or embodiments for implementing different features of the
invention. Specific embodiments of components and processes are
described to help clarify the invention. These are, of course,
merely embodiments and are not intended to limit the invention from
that described in the claims.
[0041] Although the invention is illustrated and described herein
as embodied in one or more specific examples, it is nevertheless
not intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims. Accordingly, it is appropriate
that the appended claims be construed broadly and in a manner
consistent with the scope of the invention, as set forth in the
following claims.
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