U.S. patent application number 11/963044 was filed with the patent office on 2008-05-08 for method of forming an integrated circuit including a transistor.
Invention is credited to Ulrike Gruning-Von Schwerin.
Application Number | 20080108199 11/963044 |
Document ID | / |
Family ID | 35504686 |
Filed Date | 2008-05-08 |
United States Patent
Application |
20080108199 |
Kind Code |
A1 |
Schwerin; Ulrike
Gruning-Von |
May 8, 2008 |
METHOD OF FORMING AN INTEGRATED CIRCUIT INCLUDING A TRANSISTOR
Abstract
A method of forming an integrated circuit including a transistor
is disclosed. One embodiment provides an active zone formed in a
semiconductor substrate. Trench insulator structures and cell
insulator structures are adjacent to the active zone. A gate
electrode is formed including a buried portion. The buried portion
is formed in a self-aligned manner with respect to the cell
insulator structures.
Inventors: |
Schwerin; Ulrike Gruning-Von;
(Munchen, DE) |
Correspondence
Address: |
DICKE, BILLIG & CZAJA
FIFTH STREET TOWERS
100 SOUTH FIFTH STREET, SUITE 2250
MINNEAPOLIS
MN
55402
US
|
Family ID: |
35504686 |
Appl. No.: |
11/963044 |
Filed: |
December 21, 2007 |
Current U.S.
Class: |
438/364 ;
257/E21.429; 257/E21.655; 257/E21.66; 257/E27.086; 257/E27.095;
257/E29.267 |
Current CPC
Class: |
H01L 27/10838 20130101;
H01L 29/66621 20130101; H01L 27/10808 20130101; H01L 27/10894
20130101; H01L 29/7834 20130101; H01L 27/10879 20130101; H01L
29/7851 20130101; H01L 27/10876 20130101 |
Class at
Publication: |
438/364 |
International
Class: |
H01L 21/331 20060101
H01L021/331 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 29, 2004 |
DE |
10 2004 031 385.7 |
Claims
1. A method of forming an integrated circuit including a
transistor, comprising: forming an active zone in a semiconductor
substrate, trench insulator structures and cell insulator
structures being adjacent to the active zone; and forming a gate
electrode including a buried portion, wherein the buried portion is
formed in a self-aligned manner with respect to the cell insulator
structures.
2. The method of claim 1, wherein the buried portion of the gate
electrode comprises plate sections adjacent to a body region of the
transistor.
3. The method of claim 2, wherein forming the plate sections
comprises filling a conductive material into pockets formed in the
cell insulator structures.
4. The method of claim 1, comprising forming the buried portion of
the gate electrode in part in a gate trench that is etched into the
active zone and extends between two opposing trench insulator
structures facing each other at the active zone.
5. A method of forming an integrated circuit including a
transistor, the method comprising: forming an active zone in a
semiconductor substrate between two opposing trench insulator
structures and two opposing cell insulator structures; covering the
active zone with a section of a protective layer; etching the
protective layer to expose sections of the active zones adjacent to
the cell insulator structures, wherein a central portion of the
active zone remains covered; applying a hole mask material to cover
the exposed sections of the active zone; removing the section of
the protective layer to expose the central portion; etching the
material of the trench insulator structures to provide pockets
adjacent to the active zone; and filling the pockets with a
conductive material to form a gate electrode.
6. The method of claim 5, wherein the trench insulator structures
and the cell insulator structures are protruding over the active
zone, and further comprising: removing an upper portion of the cell
insulator structures after providing the section of the protective
layer.
7. A method of forming an integrated circuit including a transistor
comprising: forming an active zone in a semiconductor substrate,
between two opposing trench insulator structures and between two
opposing cell insulator structures being adjacent to the active
zone; covering the active zone with a section of a protective
layer; etching the protective layer to expose sections of the
active zones adjacent to the cell insulator structures, wherein a
central portion of the active zone remains covered by the section
of the protective layer; forming a hole mask material to cover the
exposed sections of the active zone; removing the section of the
protective layer to uncover the central portion of the active zone;
etching the uncovered portion of the active zone to form a gate
trench; and filling the gate trench with a conductive material to
form a gate electrode.
8. The method of claim 7, wherein the trench insulator structures
and the cell insulator structures are protruding over the active
zone, and further comprising: removing an upper portion of the cell
insulator structures after providing the section of the protective
layer.
9. The method of claim 7, further comprising: etching the trench
insulator structures after etching the uncovered portion of the
active zone.
10. The method of claim 9, comprising etching the trench insulator
structures isotropically.
11. A method for fabricating an integrated circuit including
transistors, the method comprising: introducing cell insulator
structures and strip-like, parallel trench insulator structures
into a semiconductor substrate to form cell rows spaced apart from
one another by one of the trench insulator structures respectively
and, within each of the cell rows, a plurality of semiconductor
fins from the semiconductor substrate, the semiconductor fins
spaced apart from one another by one of the cell insulator
structures; providing a hole mask that covers the trench insulator
structures and at least outer mask sections of the semiconductor
fins adjoining the cell insulator structures and that comprises
openings exposing trench sections of the semiconductor fins;
uncovering and pulling back sections of the trench insulator
structures that adjoin the trench sections of the semiconductor
fins to form pockets in the trench insulator structures on both
sides in a manner adjoining the trench sections; and filling the
pockets with conductive material to form gate conductor structures,
wherein each gate conductor structure surrounds one of the
semiconductor fins on three sides in the region of the trench
sections.
12. The method of claim 11, comprising uncovering through the
openings in the hole mask the trench sections in each case from one
adjoining trench insulator structure as far as the opposite
adjoining trench insulator structure.
13. The method of claim 11, comprising effecting the uncovering of
sections of the trench insulator structures by introducing gate
trenches into the semiconductor fins using the hole mask.
14. The method of claim 11, comprising: providing the hole mask and
the trench insulator structures from materials which can be jointly
etched selectively with respect to the semiconductor substrate; and
effecting the uncovering of the sections of the trench insulator
structures and the pulling back of the uncovered sections
simultaneously in the course of an etching process with a high
isotropic portion.
15. The method of claim 14, comprising providing the trench
insulator structures and the hole mask from the same material.
16. The method of claim 14, comprising effecting the pulling back
via a wet etching.
17. The method of claim 11, wherein providing the hole mask
comprises: applying a protective layer to the semiconductor
substrate prior to the introduction of the trench insulator
structures and the cell insulator structures, the protective layer
being provided from a different material than the trench insulator
structures; applying an auxiliary layer; photolithographically
patterning the auxiliary layer to form from the auxiliary layer an
auxiliary mask with strip-like trenches running orthogonally with
respect to the cell rows and to uncover the protective layer in the
projection of the trench sections of the semiconductor fins; and
pulling back the protective layer selectively with respect to the
material of the trench insulator structures, to form the hole mask
in sections from residual sections of the protective layer, the
trench insulator structures and the cell insulator structures.
18. The method of claim 17, comprising wherein in each case
precisely one trench section of the respective semiconductor fin
that is formed between the two outer mask sections is uncovered
through one of the openings in the hole mask.
19. The method of claim 17, comprising wherein in each case two
trench sections of the respective semiconductor fin that are formed
in each case between one of the mask sections and a central mask
section are uncovered through two of the openings in the hole
mask.
20. The method of claim 11, comprising providing the semiconductor
fins in each case with precisely one trench section and the two
mask sections, wherein providing the hole mask comprises: applying
a protective layer to the semiconductor substrate prior to
introducing the trench insulator structures and the cell insulator
structures, wherein the protective layer is provided from a
different material than the trench insulator structures and the
cell insulator structures; providing the trench insulator
structures and the cell insulator structures from different
materials; pulling back the cell insulator structures selectively
with respect to the material of the protective layer and the
material of the trench insulator structures; isotropically pulling
back the protective layer, wherein the trench sections of the
semiconductor fins remain covered by sections of the pulled-back
protective layer and wherein the two mask sections of the
semiconductor fins that adjoin the cell insulator structures are
uncovered; applying the material of the hole mask; planarizing and
removing the material of the hole mask at least as far as the upper
edge of the sections of the pulled-back protective layer; and
removing the sections of the pulled-back protective layer
selectively with respect to the material of the hole mask.
21. The method of claim 11, comprising: providing the cell
insulator structures within the cell rows in each case at the
spacing of a cell length; and forming the semiconductor fins of
mutually adjacent cell rows in a manner offset by in each case half
a cell length with respect to one another.
22. The method of claim 11, comprising forming in each case the
cell insulator structures as a filling of an upper section of a
hole trench, in the lower section of which a trench capacitor is
formed.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This Utility patent application claims priority to German
Patent Application No. DE 10 2004 031 385.7, filed on Jun. 29,
2004, and U.S. patent application Ser. No. 11/169,812, filed Jun.
29, 2005, both of which are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The invention relates to a method of forming an integrated
circuit including a transistor.
BACKGROUND
[0003] Memory cells of dynamic random access memories (DRAMs)
include a storage capacitor for storing an electrical charge that
characterizes an information content of the memory cell, and a
selection transistor for addressing the storage capacitor. The
selection transistor is formed as a field effect transistor in a
semiconductor substrate. For the channel length of the selection
transistor, a lower limit arises below which the insulation
properties of the selection transistor in the turned-off state,
corresponding to the nonaddressed state of the memory cell, are
inadequate. The lower limit of the effective channel length Leff
limits the scalability of planar transistor cells (PTC) with a
selection transistor formed horizontally with respect to a
substrate surface of the semiconductor substrate.
[0004] Cell arrangements with vertical transistor cells (VTC) have
been described for memory cell arrangements having trench
capacitors as storage capacitors. In this case, the source/drain
regions of the selection transistor, in the semiconductor
substrate, are oriented essentially vertically with respect to the
substrate surface and are formed one above the other between the
substrate surface and an upper edge of the trench capacitor
embodied in the depth of the semiconductor substrate. In the
addressed state of the memory cell, a channel controlled by a gate
electrode of the selection transistor is formed between the two
source/drain regions perpendicularly to the substrate surface. The
channel width Weff arises in a manner dependent on the smallest
feature size F that can be produced by using a lithographic
patterning method. The channel length Leff is dependent on the
depth in which the lower source/drain region or a lower edge of the
gate electrode is formed.
[0005] Disadvantages of such vertical transistor cells are the
complicated integration thereof in memory cells with stacked
capacitors and also, in the case of integration in memory cells
with trench capacitors, the increase in the aspect ratio of a hole
trench for the formation of trench capacitor and vertical
transistor cell. What are furthermore disadvantageous are the
parasitic action of the gate electrode of one selection transistor
on the selection transistors adjacent to the selection transistor
and also the switch-on/off current Ion that is limited in
magnitude.
[0006] In other vertical memory cells with a vertical transistor
structure, a body region formed between the two source/drain
regions is completely surrounded by the gate electrode (surrounded
gate vertical transistor cell, SGT). The first source/drain region
of the selection transistor is formed in the base region of a
semiconductor fin. A second source/drain region is provided at the
upper edge of the semiconductor fin. The gate electrode extends
along the four side walls of the semiconductor fin. The effective
channel length Leff of such a vertical transistor structure results
from the height of the semiconductor fin. The effective channel
width Weff corresponds to the contour of the fin, at least one side
length of the semiconductor fin arising in a manner dependent on
the minimum feature size F. The total effective channel width
correspondingly amounts to 2 F to 3 F. The integration of
surrounded gate transistor cells in memory cells with stacked
capacitors is complicated. In the case of integration in memory
cells with trench capacitors, the high aspect ratios established in
the course of processing at the hole trench and also the resultant
restrictions with regard to the processing are disadvantageous.
[0007] In the case of recess channel field effect transistors
(recess channel array transistor) the two source/drain regions are
arranged in a horizontal plane with respect to the substrate
surface. The gate electrode is provided in a recess trench
introduced into the semiconductor substrate between the two
source/drain regions of the field effect transistor. The effective
channel length Leff results from the distance between the two
source/drain regions and also the depth to which the recess trench
is introduced into the semiconductor substrate. The effective
channel width Weff corresponds to the minimum feature size F.
[0008] The switch-on/off current Ion/off is disadvantageously
limited by the still restricted effective channel width. The
integration of recess channel FETs in memory cell arrangements with
a high memory cell density is made more difficult by the required
alignment of the gate electrodes with respect to the recess
trenches, for instance if the gate electrodes and the recess
trenches are in each case patterned in the course of a dedicated
photolithographic method process. In contrast to FinFETs or SGT
transistor cells, the active zone is not shielded from adjacent
memory cells by the gate electrode, so that a parasitic
punchthrough of the potential of a gate electrode of one transistor
structure to the transistor structures adjacent to said one
transistor structure disadvantageously occurs.
[0009] An arrangement for memory cells having trench capacitors and
selection transistors with a gate electrode recessed into the
semiconductor substrate is described in U.S. Pat. No.
5,945,707.
[0010] In order to form fin field effect transistors (FinFETs), a
semiconductor fin is formed in each case between two source/drain
regions--formed horizontally with respect to the wafer surface--in
the semiconductor substrate. A gate electrode structure adjoining
the semiconductor fin on three sides is provided transversely with
respect to the semiconductor fin. The effective channel length Leff
of the fin field effect transistor is determined by the length of
that section of the semiconductor fin which is enveloped by the
gate electrode, in accordance with the minimum feature size F. The
effective channel width Weff is determined from the height of the
semiconductor fin, or the depth to which the semiconductor
substrate is pulled back between the two source/drain regions on
both sides of the semiconductor fin.
[0011] German patent application DE10361695.0, incorporated herein
by reference, describes a curved channel field effect transistor
(curved FET, CFET). The CFET is formed in a semiconductor fin
formed from the semiconductor substrate. The two source/drain
regions of the CFET are formed as doped zones at mutually opposite
ends of the semiconductor fin and adjoining a substrate surface of
the semiconductor substrate. Between the two source/drain regions,
the semiconductor fin is recessed by a groove etching, whereby the
channel length of the CFET results in accordance with the channel
length of a recess channel FET. The gate electrode extends, in a
manner insulated from the semiconductor fin by a gate dielectric,
in sections along at least one of the longitudinal sides of the
semiconductor fin. In accordance with the method for fabricating a
memory cell arrangement having CFETs as selection transistors that
is described in the above application, the semiconductor fins are
arranged one after the other in the longitudinal direction to form
cell rows in a manner electrically insulated from one another in
each case. The gate electrodes of CFETs arranged in regard to a
cell row are in each case sections of buried word lines that are
provided in word line trenches running below the substrate surface
along the semiconductor fins. In this case, the word lines are
embedded in dielectric material that fills the word line
trenches.
[0012] In memory cell arrangements having CFETs with gate electrode
sections arranged on both sides of the semiconductor fin, a strand
of two differently driven word lines is in each case situated
opposite each other in the same word line trench. A high memory
cell density leads to a high parasitic coupling capacitance between
the word line strands running within the same word line trench.
SUMMARY
[0013] The invention relates to the fabrication of DRAM memory cell
arrangements having fin field effect transistors and curved channel
field effect transistors. The FinFETs and CFETs are formed in a
manner oriented to semiconductor fins arranged in cell rows. Within
the cell rows, the semiconductor fins are spaced apart from one
another by cell insulator structures. Adjacent cell rows are spaced
apart from one another by striplike trench insulator structures.
The semiconductor fins are in each case recessed in one or in two
inner trench sections by using gate trenches which extend from a
longitudinal side of the respective semiconductor fin to the
opposite longitudinal side. By isotropically etching the oxide of
the trench insulator structures, pockets (fin trenches) are formed,
in a self-aligned manner with respect to the gate trenches in the
trench insulator structures and filled with a gate conductor
material. Vertical gate electrode sections emerge without etching
back from the deposited gate conductor material. In conjunction
with trench capacitors as cell insulator structures, an improved
decoupling and insulation of the trench capacitors from word lines
led above the trench capacitors are achieved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings are included to provide a further
understanding of the present invention and are incorporated in and
constitute a part of this specification. The drawings illustrate
the embodiments of the present invention and together with the
description serve to explain the principles of the invention. Other
embodiments of the present invention and many of the intended
advantages of the present invention will be readily appreciated as
they become better understood by reference to the following
detailed description. The elements of the drawings are not
necessarily to scale relative to each other. Like reference
numerals designate corresponding similar parts.
[0015] FIG. 1 illustrates a plan view of a DRAM cell array with a
section line A-D corresponding to FIGS. 2 to 5.
[0016] FIG. 2 illustrates a first exemplary embodiment of a method
according to the invention with photolithographic formation of the
hole mask and CFETs as fin field effect transistors on the basis of
cross sections.
[0017] FIG. 3 illustrates a second exemplary embodiment of a method
according to the invention with non-photolithographic formation of
the hole mask and FinFETs as fin field effect transistors on the
basis of cross sections.
[0018] FIG. 4 illustrates a third exemplary embodiment of a method
according to the invention for fabricating a DRAM memory cell
arrangement with stacked capacitors.
[0019] FIG. 5 illustrates a fourth exemplary embodiment of a method
according to the invention with non-photolithographic formation of
the hole mask and CFETs as fin field effect transistors on the
basis of cross sections.
[0020] FIG. 6 illustrates a cross section through an exemplary
embodiment of a CFET according to the invention.
[0021] FIG. 7 illustrates a plan view of a DRAM cell array in the
stack layout.
[0022] FIG. 8 illustrates a fifth exemplary embodiment of a method
according to the invention with photolithographic formation of the
hole mask and CFETs as fin field effect transistors in a stack
layout on the basis of cross sections.
DETAILED DESCRIPTION
[0023] In the following Detailed Description, reference is made to
the accompanying drawings, which form a part hereof, and in which
is shown by way of illustration specific embodiments in which the
invention may be practiced. In this regard, directional
terminology, such as "top," "bottom," "front," "back," "leading,"
"trailing," etc., is used with reference to the orientation of the
Figure(s) being described. Because components of embodiments of the
present invention can be positioned in a number of different
orientations, the directional terminology is used for purposes of
illustration and is in no way limiting. It is to be understood that
other embodiments may be utilized and structural or logical changes
may be made without departing from the scope of the present
invention. The following detailed description, therefore, is not to
be taken in a limiting sense, and the scope of the present
invention is defined by the appended claims.
[0024] The invention provides a method for fabricating a DRAM
memory cell arrangement having FinFETs or CFETs by using which
adjacent word lines, for the addressing of the memory cells, are
decoupled well from one another and in the case of which the
alignment of gate electrode structures with respect to a body
region of the respective CFET or FinFET is facilitated. The
invention encompasses a field effect transistor for a DRAM
transistor array having CFETs with gate electrode sections that are
self-aligned with respect to a gate trench etching.
[0025] In one embodiment, in accordance with a method for
fabricating fin field effect transistors and curved channel fin
field effect transistors for DRAM memory cell arrangements, a
semiconductor substrate is provided. Striplike, parallel trench
insulator structures and also cell insulator structures are
introduced into the semiconductor substrate. In this case, cell
rows are formed from the semiconductor substrate between in each
case two trench insulator structures. The cell insulator structures
are in each case provided within the cell rows at the spacing of a
cell length. By using the cell insulator structures, a cell row is
in each case subdivided into a plurality of semiconductor fins
formed from the semiconductor substrate. The trench insulator
structures and the cell insulator structures may be formed in a
different order or simultaneously.
[0026] A hole mask is formed, which covers at least the trench
insulator structures and also in each case at least the two outer
mask sections of the semiconductor fins that adjoin the cell
insulator structures. In each case at least one inner trench
section of the semiconductor fins that is formed between the two
outer mask sections is uncovered through the openings in the hole
mask.
[0027] In this case, the openings in the hole mask extend from one
trench insulator structure adjoining the semiconductor fin as far
as the opposite adjoining trench insulator structure.
[0028] Sections of the trench insulator structures that in each
case adjoin the trench sections of the respective semiconductor
fins are uncovered and pulled back. In this case, pockets are
formed in the trench insulator structures in each case on both
sides adjoining the uncovered sections of the semiconductor
fins.
[0029] In order to form gate conductor structures, conductive
material is deposited, the pockets being filled with the conductive
material. The conductive material is patterned to form gate
conductor structures, word lines running perpendicular to the cell
rows being formed. The word lines form, in sections, gate
electrodes of the fin field effect transistors formed in the
semiconductor fins.
[0030] The uncovering and pulling back of the sections of the
trench insulator structures that in each case adjoin the trench
sections of the semiconductor fins may be effected simultaneously
or progressively in the same process, for instance by simultaneous
isotropic etching back of the hole mask and of the trench insulator
sections.
[0031] The uncovering and pulling back of sections of the trench
insulator structures that in each case adjoin the trench sections
of the semiconductor fins may also be effected successively, for
instance by isotropic etching back of the hole mask and subsequent
anisotropic etching of the trench insulator structures or by the
introduction of gate trenches into the trench sections of the
semiconductor fin, vertical sidewalls of the trench insulator
structures being uncovered, and subsequent isotropic etching of the
trench insulator structures from the gate trenches. In one
embodiment, the fin field effect transistors are always formed as
CFETs.
[0032] The pockets that are in each case situated opposite one
another at a semiconductor fin and have emerged from the pulling
back of the trench insulator structures correspond to fin trenches
in accordance with conventional methods for fabricating fin field
effect transistors.
[0033] According to one embodiment, the pockets are formed in a
self-aligned manner with respect to the trench sections of the
semiconductor fin corresponding to the body regions of the fin
field effect transistors.
[0034] In conventional methods, firstly the trench insulator
structures are pulled back as far as the lower edge of the gate
electrodes to be formed. The material of the gate conductor
structures is deposited areally and subsequently patterned. Between
the gate conductor structures, the material of the gate conductor
structures is to be removed. The gate conductor structure is
overetched in this case in order to avoid the formation of
disturbing conductive structures (poly stringers) on vertical
sidewalls of the semiconductor fin in the region of the
source/drain regions and in order to avoid short circuits between
mutually adjacent gate conductor structures. According to the
invention, the material of the gate conductor structure, below the
substrate surface, is exclusively deposited in the region of the
buried sections of the gate conductor structures. The need to pull
back buried sections of the gate conductor structure below an upper
edge of the semiconductor fin is therefore advantageously
obviated.
[0035] In one embodiment, the depth to which the buried sections of
the gate electrodes extend is predetermined by a well-controllable
etching process with regard to the trench insulator structure and
the process control is thus improved.
[0036] The method can be used both for forming DRAM memory cell
arrangements with stacked capacitors and for forming DRAM memory
cell arrangements with trench capacitors.
[0037] For a memory cell arrangement in the checkerboard layout,
precisely one fin field effect transistor is formed in each
semiconductor fin. In the checkerboard layout, a semiconductor fin
includes the two outer mask sections adjoining the cell insulator
structures, in which sections the hole mask is situated atop, and
also precisely one inner trench section delimited by the outer mask
sections, which is not covered by the hole mask.
[0038] In layouts which provide a common bit contact for in each
case two memory cells, for instance in a memory cell arrangement in
the MINT or stack layout, two fin field effect transistors are
formed in each semiconductor fin. In a stack layout, for instance,
a semiconductor fin includes the two outer mask sections adjoining
the cell insulator structures and also an inner mask section, which
are in each case covered by the hole mask. In each case one of two
trench sections above which the hole mask is opened is fashioned
between in each case one of the two outer mask sections and the
inner mask section.
[0039] According to one embodiment, the pulling back of the trench
insulator structures is preceded by the introduction of gate
trenches into the semiconductor fins, the sections of the trench
insulator structures that adjoin the gate trenches being uncovered
for an isotropic etching. Curved channel field effect transistors
(CFETs) are formed by the introduction of the gate trenches.
[0040] According to another embodiment, the hole mask is pulled
back before or simultaneously with the pulling back of the trench
insulator structures.
[0041] Preferably, for this purpose the hole mask and the trench
insulator structures are provided from materials which can be
jointly etched selectively with respect to the material of the
semiconductor substrate. The hole mask is preferably provided from
the material of the trench insulator structures. When the trench
insulator structures are pulled back in the sections adjoining the
trench sections of the semiconductor fin, the sections of the hole
mask that bear on the trench insulator structures and also the
trench insulator structures are pulled back simultaneously in an
etching process with a high isotropic portion, preferably a wet
etching process.
[0042] In order to provide the hole mask, in a first manner, prior
to the introduction of the trench insulator structures and of the
cell insulator structures, a protective layer is applied to the
semiconductor substrate. In this case, the protective layer is
provided from a different material than the trench insulator
structures. An auxiliary layer is applied to a process surface that
is then formed in sections by the protective layer, the trench
insulator structures and the cell insulator structures. The
auxiliary layer is patterned by using a photolithographic method,
an auxiliary mask with striplike trenches that run orthogonally
with respect to the cell rows being formed from the auxiliary
layer. Through the trenches of the auxiliary mask, the protective
layer is uncovered in each case in the vertical projection of the
inner trench sections of the semiconductor fins. In the vertical
projection of the mask sections of the semiconductor fins, the
protective layer is covered by the auxiliary mask. The protective
layer is pulled back selectively with respect to the material of
the trench insulator structures, so that, after the removal of the
auxiliary mask, the hole mask is formed in sections from residual
sections of the protective layer, the trench insulator structures
and also the cell insulator structures. This way of forming the
hole mask is suitable for memory cell layouts with one and with two
selection transistors per semiconductor fin.
[0043] For memory cell layouts with precisely one selection
transistor per semiconductor fin, according to a second manner, in
order to provide the hole mask, the trench insulator structures are
provided from a different material than the cell insulator
structures. Prior to the introduction of the trench insulator
structures and of the cell insulator structures, a protective layer
is applied to the semiconductor substrate. In this case, the
protective layer is provided from a different material than the
trench insulator structures and the cell insulator structures.
[0044] The cell insulator structures are pulled back selectively
both with respect to the material of the protective layer and with
respect to the material of the trench insulator structures,
vertical sidewalls of the protective layer being uncovered toward
the pulled-back cell insulator structures. The protective layer is
pulled back in an etching process with an isotropic portion. The
layer thickness of the protective layer is reduced in this case. In
addition, the protective layer is pulled back proceeding from the
uncovered sections facing the cell insulator structures. The
pulling back of the protective layer is terminated as soon as the
outer mask sections of the semiconductor fins are uncovered. The
central, inner trench sections of the semiconductor fins remain
covered in each case by a section of the pulled-back protective
layer. A hole mask material is applied and removed and planarized
at least as far as the upper edge of the sections of the
pulled-back protective layer. The sections of the pulled-back
protective layer are removed selectively with respect to the hole
mask material. In this embodiment of the method according to the
invention, the hole mask is formed completely from the hole mask
material.
[0045] In the case of this way of forming the hole mask, the
openings in the hole mask and thus the buried sections of the gate
electrode of a FinFET formed in this way are advantageously formed
in a self-aligned manner with respect to the cell insulator
structures. For CFETs, the gate trench is in each case additionally
aligned with respect to the cell insulator structures.
[0046] This last provides advantages when the cell insulator
structures are provided as filling structures of upper sections of
hole trenches, in the lower sections of which trench capacitors are
formed. A misalignment between the gate trenches and the trench
capacitors, as is typical when using two masks for
photolithographic methods and which could lead at least to
different resistances of a buried connection (buried strap) between
the inner electrode of the trench capacitor and a first
source/drain region of the respectively assigned fin field effect
transistor, is avoided.
[0047] The method further provides advantages when the
semiconductor fins of mutually adjacent cell rows are formed in a
manner offset by in each case half a cell length with respect to
one another. In a checkerboard layout, word lines which are
provided perpendicular to the cell rows and form the gate
electrodes in each case in sections are then led alternately over
gate trenches and trench capacitors. Whereas in conventional
methods the trench insulator structures are completely pulled back
between a respective semiconductor fin and a trench capacitor
adjacent orthogonally with respect to the orientation of the
semiconductor fin and buried sections of the word line or the
buried gate electrode sections thus directly adjoin the trench
capacitors, according to the invention the trench insulator
structures are pulled back only in sections adjoining the
semiconductor fin. The sections adjoining the trench capacitor are
preserved, by contrast. Compared with conventional methods for
fabricating fin field effect transistors, the method according to
the invention therefore enables a good capacitive decoupling and
resistive insulation of the word line from the trench capacitors
traversed or spanned by the word line.
[0048] The method leads to a novel curved channel field effect
transistor (CFET) for DRAM memory cell arrangements. The curved
channel field effect transistor includes an active zone and a gate
electrode. The active zone is formed in a semiconductor fin with
two parallel longitudinal sides, into which a gate trench structure
is introduced in an inner trench section from a fin surface, which
gate trench structure extends from one longitudinal side to the
other longitudinal side.
[0049] The active zone includes two source/drain regions that are
arranged on both sides of the gate trench structure, adjoin the fin
surface and are in each case formed as doped zones, and also a body
region in the section between the two source/drain regions of the
semiconductor fin. The lower edge of the body region is provided
below the lower edge of the gate trench structure, so that the body
region extends from one source/drain region to the other
source/drain region.
[0050] The gate electrode has two plate sections extending in each
case along one of the longitudinal sides of the semiconductor fin.
The plate sections extend to below the lower edge of the gate
trench structure, so that the formation of a conductive channel
between the two source/drain regions can be controlled by a
potential at the gate electrode.
[0051] According to one embodiment, the plate sections extend in
each case proceeding from an intersection edge of the gate trench
structure with the respective longitudinal side of the
semiconductor fin uniformly as far as a maximum depth of half the
fin width along the active zone. The gate trench structure is
formed as a trench section of the respective gate electrode which
connects the two plate sections to one another. The plate sections
of the gate electrode form a fin gate. The plate sections cover the
area of intersection of the gate trench structure with the
respective longitudinal side of the semiconductor fin and overlap
with a uniform width sections of the body region that adjoin the
area of intersection.
[0052] The transistor structure according to the invention can
advantageously be fabricated in a simple manner by using the method
according to the invention described above.
[0053] A DRAM transistor array according to the invention having
curved channel field effect transistors for DRAM memory cell
arrangements has a plurality of such field effect transistors that
are in each case arranged in cell rows.
[0054] In this case, the semiconductor fins of mutually adjacent
cell rows are provided in a manner offset by in each case half a
cell length with respect to one another. Trench insulator
structures are provided between the cell rows.
[0055] In each case either precisely one field effect transistor or
a pair of field effect transistors is or are formed in the
semiconductor fins, the two field effect transistors being arranged
in mirror-inverted fashion with respect to one another and a first
source/drain region of one field effect transistor and a second
source/drain region of the other field effect transistor being
provided as a single contiguous doped zone.
[0056] The gate electrodes of a plurality of field effect
transistors are in each case sections of word lines running
perpendicular to cell rows. In this case, the word lines are led
alternately over the gate trench structures of FinFETs or CFETs and
cell insulator structures or trench capacitors. The word lines are
advantageously insulated and decoupled from the inner electrodes of
the respectively traversed trench capacitors by comparatively thick
sections of the trench insulator structures that have not been
pulled back adjacent to the trench capacitors.
[0057] FIG. 1 illustrates a stack of masks for forming a DRAM
memory cell arrangement in a semiconductor substrate, which gives
rise to a plan view of a DRAM memory cell arrangement. In this
case, the illustration shows the openings from hole masks and, from
strip masks, fin or trench structures resulting from the strip
masks. In the region of a memory cell 100, reference is made to the
structures formed on the basis of the masks in photolithographic
methods.
[0058] Trench capacitors 3' formed in the semiconductor substrate
correspond to openings 93 in a trench mask. The trench capacitors
3' are arranged within cell rows 110 in each case at the spacing of
a cell length. Respectively adjacent cell rows 110 are provided in
a manner offset by half the cell length with respect to one
another.
[0059] Corresponding to fin sections 91 of a cell row mask,
semiconductor fins 11 are formed between in each case two trench
capacitors 3' that are adjacent in the same cell row 110. Trench
insulator structures 2 are formed between the cell rows 110.
Corresponding to trench sections 92 of a gate trench mask, central
sections of the semiconductor fins 11 are pulled back and gate
trenches 13 are formed in the semiconductor fins 11 in the process.
Corresponding to fin sections 98 of a word line mask, word lines 8
are formed above the gate trenches 13. The word lines 8 run
perpendicular to the cell rows 110 and alternately span
semiconductor fins 11 and trench capacitors 3'. Corresponding to
openings 90 in a bit contact mask, bit contacts 84 are provided on
the semiconductor fins 11.
[0060] This illustration shows, from a memory cell 100, a trench
capacitor 3', a semiconductor fin 11 adjoining the trench capacitor
3' toward the left, and the assigned bit contact 84. The
semiconductor fin 11 is recessed by the gate trench 13 between the
trench capacitor 3' and the bit contact 84. The semiconductor fin
11 forms an active zone of a selection transistor of the memory
cell 100, said selection transistor being formed as a CFET. A gate
electrode of the CFET is formed by a section of the word line or
gate conductor structure 8 crossing the semiconductor fin 11 above
the gate trench 13.
[0061] A first source/drain region 121 of the CFET is formed
between the gate trench 13 and the trench capacitor 3' in the
semiconductor fin 11 and is connected to an inner electrode of the
trench capacitor 3'. A second source/drain region 122 of the CFET 4
is formed below the bit contact 84 in the semiconductor fin 11. In
a manner dependent on a potential of the word line 8, in the active
zone of the CFET 4, a conductive channel is formed between the
first 121 and the second 122 source/drain region and through under
the gate trench 13.
[0062] FIG. 2A to FIG. 2F illustrate cross sections along the line
A-B-C-D from FIG. 1 in different phases of an exemplary embodiment
of the method according to the invention for fabricating a DRAM
memory cell arrangement with trench capacitors and CFETs. The cross
sections are in each case accompanied by plan views of the
respective structures with identification of the section lines.
[0063] A semiconductor substrate 1 is provided and a protective
layer 6 is applied on a substrate surface 10 of the semiconductor
substrate 1. The protective layer 6 is provided from silicon
nitride. Further layers, for instance a stress compensating layer,
may be situated under the protective layer 6 (pad nitride). Trench
capacitors 3' are provided in the semiconductor substrate 1. In
this case, the trench capacitors 3' are formed in each case in a
manner oriented to a hole trench that is introduced into the
semiconductor substrate 1 through the protective layer 6. An outer
electrode (not illustrated) of the trench capacitors 3' is formed
as a doped zone in a section of the semiconductor substrate 1 that
surrounds a lower section of the hole trench. The outer electrode
is insulated from a filling of the hole trench in each case by a
capacitor dielectric 35 formed on the wall of the hole trench. The
filling is provided from a conductive material and defines an inner
electrode 31 of the trench capacitor 3'. In a central section of
the hole trench, the inner electrode 31 is insulated from the
surrounding semiconductor substrate 1 by a collar insulator 32
formed along the wall of the hole trench. The collar insulator 32
is pulled back on one side, so that the inner electrode 31 adjoins
the semiconductor substrate 1 in the region of a buried strap
window 33. A cell insulator structure 3 is formed as an oxidic
filling of an upper section of the hole trench approximately above
the substrate surface 10.
[0064] Striplike trenches are etched between the trench capacitors
3' and filled with a dielectric material. Trench insulator
structures 2, 21 emerge from the filling of the trenches.
[0065] In accordance with the cross section B-C along a cell row as
illustrated in FIG. 2A, a semiconductor fin 11 formed from the
semiconductor substrate 1, within the cell row, is delimited by two
mutually adjacent trench capacitors 3'. In the region of the buried
strap window 33, an inner electrode 31 of one trench capacitor 3'
adjoins one of the two semiconductor fins 11 that are adjacent in
the cell row. The inner electrode 31 is insulated from the other
semiconductor fin 11 that is adjacent in the same cell row by using
the collar insulator 32. In accordance with the accompanying plan
view, in this exemplary embodiment, respectively adjacent cell rows
are provided in a manner offset in each case by half a cell length
with respect to one another. The cross section C-D through the
midpoint of a trench capacitor 3' perpendicular to the cell row
reveals that the trench capacitors 3' are in each case insulated by
trench insulator structures 2 from the adjoining semiconductor fin
11 in the adjacent cell row.
[0066] The cross section A-B illustrates a cross section
perpendicular to the cell row in a section in which the
semiconductor fins 11 of adjacent cell rows overlap.
[0067] A cross section through the simultaneously processed support
circuit region 52 of a DRAM is illustrated in addition to the cross
section through a cell array 51. Shallow trench structures 21 are
formed in the support circuit region 52, the semiconductor
substrate 1 being covered by the protective layer 6 outside said
structures.
[0068] The accompanying plan view shows the protective layer 6,
which is subdivided into individual fields by cell insulator
structures 3 within the cell rows and by trench insulator
structures 2 between the cell rows. The fields of the protective
layer 6 in each case bear on the substrate surface 10 in the region
of the semiconductor fins 11.
[0069] An auxiliary layer is applied to the process area formed in
sections from the fields of the protective layer 6, the trench
insulator structures 2, 2' and the cell insulator structures 3 and
is patterned photolithographically. In this case, striplike
trenches 71' orthogonal to the cell rows are formed in the
auxiliary layer, which trenches cross the semiconductor fins 11 in
each case in a central section. With the auxiliary mask 71
developed from the auxiliary layer in this way as an etching mask,
the material of the protective layer 6 is etched back selectively
with respect to the material of the trench insulator structures 2
and the cell insulator structures 3 as far as the substrate surface
10.
[0070] After this etching process, a central section of the
semiconductor fins 11 is in each case uncovered in accordance with
FIG. 2B. The auxiliary mask 71 has trench openings 71', which are
illustrated in cross section in the section B-C and in longitudinal
section in the section C-D. Beneath the trench openings 71', within
the fields of the protective layer 6 the central section of the
semiconductor fins 11 is in each case uncovered through window
openings 71''. Outside the fields of the protective layer 6, a
pulling back of the trench insulator structures 2 or of the cell
insulator structures 3 is indicated, the trench and cell insulator
structures 2, 3 having been pulled back to a lesser extent than the
protective layer 6. During the etching of the window openings 71'',
the support circuit region 52 is completely covered by the
auxiliary mask 71. The trench insulator structures 2 and also the
cell insulator structures 3 are provided from silicon oxide in this
exemplary embodiment. Where reference is made to the silicon oxide
in subsequent method steps, both structures are encompassed
thereby.
[0071] After the removal of the auxiliary mask 71, the
semiconductor substrate 1 is etched selectively with respect to the
silicon nitride of the protective layer 6 and the silicon oxide of
the trench and cell insulator structures 2, 3.
[0072] In accordance with the cross section B-C in FIG. 2C, a gate
trench 13 is in each case introduced in a central section of the
semiconductor fins 11. The gate trench 13 is delimited, within the
cell row, by the sections of the semiconductor fin 11 that have not
been etched back and, perpendicular to the cell row, corresponding
to the cross section C-D, by the silicon oxide of the trench
insulator structures 2. The fields of the protective layer 6 and
also the silicon oxide of the trench and cell insulator structures
2, 3 form a hole mask 7.
[0073] The accompanying plan view reveals the fields of the
protective layer 6 that are embedded between the silicon dioxide of
the trench and cell insulator structures 2, 3, the central sections
of the semiconductor fins 11 being uncovered through window
openings 72'' in the hole mask 7. The lengthenings of the gate
trenches 13 in the silicon oxide 2, 3 are fashioned as groovelike
depressions produced as a side effect during the etching of the
protective layer 6.
[0074] The silicon oxide of the trench and cell insulator
structures 2, 3 is pulled back isotropically in a wet etching
process.
[0075] The result, in a simplified illustration, is the structure
illustrated in FIG. 2D. The trench insulator structures 2 and the
cell insulator structures 3 are pulled back in the vertical
direction by using the isotropic etching. The silicon oxide is
additionally pulled back from uncovered vertical sections of the
silicon oxide in the horizontal direction. Vertical sections of the
trench insulator structure 2 are uncovered on both sides of the
gate trench 13. In accordance with the cross section C-D, the
trench insulator structure 2 is additionally thinned in the
horizontal direction in the region of the gate trench 13. Pockets
22 result on both sides of the gate trench 13, which pockets
continue into the depth of the trench insulator structures 2 at the
bottom of the gate trench 13.
[0076] The pockets 22 are formed in a cross section parallel to the
cross-section line B-C and illustrated in dashed fashion.
[0077] The accompanying plan view illustrates the pockets 22 on
both sides of the window openings 73'' as depressions which in each
case extend along the longitudinal sides of the semiconductor fin
11 beyond the window opening 73''. In the exemplary embodiment
illustrated, the etching depth for pulling back the silicon oxide
of the trench and cell insulator structures 2, 3 amounts to
approximately half the fin width.
[0078] The protective layer 6 is completely removed.
[0079] The result is the structure illustrated in FIG. 2E, in which
the surface of the semiconductor fins 11 is uncovered.
[0080] Implantations for forming source/drain regions 121, 122 of
the selection transistors 4 are subsequently performed. A gate
dielectric 80 is formed on the uncovered sections of the
semiconductor fins 11 for instance by oxidation of the
semiconductor substrate 1 or by deposition of a dielectric
material. Sublayers 81, 82, 83 of a gate conductor layer stack are
deposited one after the other, the pockets 22 being filled with a
conductive material. The gate conductor layer stack is patterned by
using a photolithographic method to form gate conductor structures
or word lines 8 running perpendicular to the cell rows above the
gate trenches 13.
[0081] FIG. 2F illustrates, in the section C-D, a word line 8 in
longitudinal section and, in the section B-C, in each case a
passive word line 8 led over a trench capacitor 3' and an active
word line 8 led over the semiconductor fin 11 of the memory cell in
cross section. The word line 8 includes a base layer 81 made of a
conductive material, for instance doped polysilicon. Buried
sections 811 of the base layer 81 fill the pockets 22 and the gate
trenches 13. A highly conductive layer 82 is applied on the base
layer 81 and an insulator layer 83 is applied on the highly
conductive layer 82. The base layer 81 of the word line 8 is
insulated from the semiconductor fin 11 by the gate dielectric
80.
[0082] A memory cell 100 is illustrated in longitudinal section in
the cross section B-C. The memory cell 100 includes a trench
capacitor 3' and a CFET as selection transistor 4. The selection
transistor 4 includes an active zone 12 formed in a semiconductor
fin 11. The active zone 12 includes a first source/drain region
121, which, in the region of the buried strap window 33, adjoins
the inner electrode 31 of the trench capacitor 3' of the memory
cell 100. The active zone 12 furthermore includes a second
source/drain region 122, which is insulated by a collar insulator
32 from the trench capacitor 3' of the adjacent memory cell that
adjoins the memory cell 100 in the same cell row.
[0083] There is introduced between the two source/drain regions
121, 122 a buried section 811 of a base layer 81 of the gate
conductor structure 8, which, in a cross section parallel to the
cross section B-C, overlaps the body region 125 on both
longitudinal sides with uniform width. When a suitable potential is
applied to the gate conductor structure 8, a conductive channel is
formed in a channel section--covered by the gate conductor
structure 8--of a body region 125 formed between the two
source/drain regions 121, 122. The channel section extends along
the wall of the gate trench 113 and, in sections, on both
longitudinal sides of the semiconductor fin 11.
[0084] The processing of gate conductor structures 8' in the
support circuit region 52 is effected analogously to the gate
conductor structure 8 in the cell array 51. Bit contacts 84 for
making contact with the second source/drain regions 122 are formed.
A plurality of bit contacts 84 are in each case connected to one
another by using bit lines that are formed perpendicular to the
word lines 8. A customary BEOL process for completing a DRAM memory
cell arrangement ensues.
[0085] In the exemplary embodiment of FIG. 3, the cell insulator
structures are produced by the filling of the hole trenches with
doped polysilicon as far as the upper edge of the protective layer
6.
[0086] The structure illustrated in cross section in FIG. 3A
differs from the structure illustrated in FIG. 2 by virtue of the
different choice of material for the cell insulator structures 3
and the trench insulator structures 2. The material of the cell
insulator structures 3 is polysilicon and the material of the
trench insulator structures is silicon oxide.
[0087] The accompanying plan view illustrates two parallel cell
rows that are offset by half a cell length with respect to one
another and are insulated from one another by a trench insulator
structure 2. Within the cell rows, in each case two adjacent
semiconductor fins 11 covered by fields of the protective layer 6
are insulated from one another by cell insulator structures 3 made
of polysilicon that are formed as upper sections of trench
capacitors 3'.
[0088] The polysilicon is etched back in the hole trenches to below
the lower edge of the protective layer 6. The end sides of the
fields of the protective layer 6 that are oriented to the cell
insulator structures 3 are uncovered. In a subsequent etching
process with an isotropic portion, the fields of the protective
layer 6 are thinned and pulled back from the uncovered end sides of
the semiconductor fins 11.
[0089] FIG. 3B reveals that the pulled-back sections 6' of the
protective layer 6 in each case cover central sections of the
semiconductor fins 11 from one trench insulator structure 2 to the
opposite trench insulator structure 2.
[0090] Silicon oxide is deposited and the structure is filled in
the process. The deposited silicon oxide is planarized and removed
at least as far as the upper edge of the pulled-back sections 6' of
the protective layer.
[0091] In accordance with FIG. 3C, an intermediate structure 74
formed in sections from sections of the trench insulator structures
2 and the deposited silicon oxide covers the surface of the
structure. Only in each case the central sections of the
semiconductor fins 11 are covered by the pulled-back sections 6' of
the protective layer.
[0092] The silicon nitride of the pulled-back sections 6' of the
protective layer is removed selectively with respect to the silicon
oxide of the intermediate structure 74.
[0093] The intermediate structure 74 forms a hole mask 7,
illustrated in FIG. 3D. Through openings 74'' in the hole mask 7,
the central sections of the semiconductor fins 11 are uncovered
from one longitudinal side as far as the opposite longitudinal side
of the semiconductor fin 11.
[0094] In the course of a wet etching, the silicon oxide of the
intermediate structure 74 is etched back isotropically. In this
case, proceeding from the window openings 74'', sections of the
trench insulator structures 2 that adjoin the window openings 74''
are uncovered and likewise etched back.
[0095] As illustrated in FIG. 3E, a thinned intermediate structure
75 with enlarged window openings 75'' has emerged from the
intermediate structure 74 from FIG. 3D. Sections of the gate
insulator structures 2 that adjoin the window openings 75'' have
been pulled back and pockets 22 have arisen in their place.
[0096] The pockets 22 extend into the trench insulator structures 2
to a depth of approximately half the fin width in the horizontal
and vertical direction.
[0097] In accordance with FIG. 3F, word lines 8 and source/drain
regions 121, 122 are formed. In contrast to FIG. 2F, which
illustrates a cell array having CFETs, a cell structure having
FinFETs results in accordance with FIG. 3F.
[0098] FIG. 4 relates to the fabrication of a transistor array for
a DRAM memory cell arrangement with stacked capacitors. In contrast
to FIG. 3A and FIG. 2A with a formation of the cell insulator
structures 3 as upper sections of a filling of hole trenches, in
the lower section of which trench capacitors 3' are formed, the
cell insulator structures 3 are simple insulator structures which
can be formed for instance in a method analogously to FIG. 2 partly
at the same time as the trench insulators 2.
[0099] Proceeding from the structure illustrated in FIG. 4, the
processing of a cell array for DRAM memory cell arrangements with
stacked capacitors is effected in accordance with FIGS. 3A to 3F
for memory cell arrangements having FinFETs as selection
transistors or 5A to 5F for memory cell arrangements having CFETs
as selection transistors. Afterward, in each case in addition, the
respective first source/drain regions 121 of the selection
transistors are contact-connected and stacked capacitors are
formed, which are in each case connected to the first source/drain
regions 121.
[0100] The exemplary embodiment illustrated with reference to the
drawings of FIG. 5 differs from the exemplary embodiment
illustrated with reference to FIG. 3 by the fact that gate trenches
13 are etched into the semiconductor fins 11 prior to the silicon
oxide being pulled back isotropically in the course of a wet
etching process using the intermediate structure 74 as a hole mask
7. In this case, the support circuit region 52 is covered by a
resist mask 76. The formation of the pockets 22 and the further
processing are in this case effected largely analogously to FIG.
2E.
[0101] In the exemplary embodiment of a CFET illustrated in FIG. 6,
a first source/drain region 121 and a second source/drain region
122 are formed in a semiconductor fin 11 in a manner adjoining a
substrate surface 10 along a longitudinal axis. The two
source/drain regions 121, 122 are spaced apart from one another by
a gate trench 13. The gate trench 13 is introduced from the
substrate surface 10 such that it reaches to below a lower edge of
the source/drain regions 121, 122. Beneath the source/drain regions
121, 122, a body region 125 of the CFET 4 is formed in the
semiconductor fin 11. The body region 125 adjoins the two
source/drain regions 121, 122 and extends to below the lower edge
of the gate trench 13. Proceeding from the areas of intersection of
the longitudinal sides of the semiconductor fin 11 with the gate
trench 13, plate sections 851 of a gate electrode 85 overlap the
body region 125 on both sides of the semiconductor fin 11 to a
uniform extent. A trench section 852 of the gate electrode 85 is
provided as filling of the gate trench 13. The two plate sections
851 of the gate electrode 85 are connected to one another by the
trench section 852. The gate electrode 85 is spaced apart from the
semiconductor fin 11 by a gate dielectric 80. Insulator structures
2 adjoin the longitudinal sides of the CFET 4.
[0102] During operation of the CFET 4, a conductive channel 14 is
formed between the two source/drain regions 121, 122 by using a
suitable potential at the gate electrode 85 in a section of the
body region 125 that adjoins the gate dielectric 80. A cell current
15 flows through the channel 14. The length of the channel 14 is
essentially determined by the depth of the gate trench 13. The
source/drain regions 121, 122 and also the body region 125 form the
active zone 12 of the CFET 4.
[0103] With this design of the plate section 851, there is no need
for a critical process of etching back the gate electrode material
below the substrate surface. The plate sections can be formed in a
self-aligned manner with respect to the gate trenches 13.
[0104] FIG. 7 illustrates, in a manner corresponding to FIG. 1, a
stack of masks for the formation of a DRAM memory cell arrangement
in a semiconductor substrate, which results in a plan view of a
DRAM memory cell arrangement in a stack layout. In this case, the
illustration shows the openings from hole masks and, from strip and
lattice masks, the fin structures resulting from the respective
masks.
[0105] Corresponding to openings 96 in an AA lattice mask for
forming active zones (active areas, AA) of fin field effect
transistors, semiconductor fins that run along cell rows 110 and
are separated from one another within the same cell row 110 are
formed from a semiconductor substrate. Trench insulator structures
are formed between the cell rows 110 and cell insulator structures
are formed between the semiconductor fins that are adjacent in each
case in the same cell row 110. Corresponding to openings 92 of a
gate trench mask in the region of the semiconductor fins, the
semiconductor fins are in each case pulled back in two trench
sections corresponding to hole mask openings 92' and gate trenches
are introduced into the semiconductor fins in the process. Fin
sections 98 of a word line mask are formed above the gate trenches.
The word lines patterned with the word line mask run perpendicular
to the cell rows 110 and alternately span semiconductor fins and
cell insulator structures. Corresponding to openings 90, 94 of one
or more contact masks, bit contacts are in each case arranged on
outer mask sections of the semiconductor fins and a node contact is
in each case arranged on an inner mask section. The node contacts
will be connected via connecting structures corresponding to
openings 90' of a connecting mask to bit lines corresponding to fin
sections 95 of a bit line mask.
[0106] FIG. 8A to FIG. 8G illustrate, in each case to the left of
the dashed line, a longitudinal section through a semiconductor fin
along the cell row and, to the right of the dashed line, a cross
section through the semiconductor fin transversely with respect to
the cell row in different phases of an exemplary embodiment of the
method according to the invention for fabricating a DRAM memory
cell arrangement having CFETs in a stack layout.
[0107] A semiconductor substrate 1 is provided and a protective
layer 6 is applied to a substrate surface of the semiconductor
substrate 1. The protective layer 6 is provided from silicon
nitride. Further layers, for instance a stress compensating layer,
may be situated under the protective layer 6 (pad nitride).
[0108] In a photolithographic method, a trench lattice is
introduced into the semiconductor substrate 1 through the
protective layer 6. The uncovered semiconductor substrate 1 is
oxidized and the trench lattice is filled with a dielectric
material. The filling includes depositing the dielectric material
and removing the dielectric material deposited outside the trench
lattice by planarization.
[0109] In accordance with the cross section illustrated in FIG. 8A,
semiconductor fins 11 formed from the semiconductor substrate 1
along a cell row are separated by cell insulator structures 3
within the cell row and are separated from adjacent cell rows 110
by trench insulator structures 2, both the cell insulator
structures 3 and the trench insulator structures 2 having been
produced by filling the trench lattice with a dielectric
material.
[0110] An auxiliary layer is applied to the process area formed in
sections from the fields of the protective layer 6, the trench
insulator structures 2 and the cell insulator structures 3 and is
patterned photolithographically. In this case, striplike trenches
71' orthogonal to the cell rows 110 are formed in the auxiliary
layer, which trenches cross the semiconductor fins 11 in each case
over two trench sections. The patterning process is controlled in
such a way that the width of the striplike trenches 71' is smaller
than the respective minimum feature size F governed by the
lithography. With the auxiliary mask 71 developed from the
auxiliary layer in this way as an etching mask, the material of the
protective layer 6 is etched back selectively with respect to the
material of the trench insulator structures 2 and cell insulator
structures 3 at least as far as the substrate surface.
[0111] After this etching process, in each case two trench sections
of the semiconductor fins 11 are uncovered in accordance with FIG.
8B. The auxiliary mask 71 has trench openings 71', which are
illustrated in cross section on the left and in longitudinal
section on the right. Beneath the trench openings 71', within the
fields of the protective layer 6, the inner trench sections of the
semiconductor fins 11 are in each case uncovered through window
openings 71''. A pulling back of the trench insulator structures 2
and cell insulator structures 3 is indicated outside the fields of
the protective layer 6. The trench insulator structures 2 and also
the cell insulator structures 3 are provided from silicon oxide in
this exemplary embodiment.
[0112] After the removal of the auxiliary mask 71, the
semiconductor substrate 1 is etched in two stages in each case
selectively with respect to the silicon nitride of the protective
layer 6 and the silicon oxide of the trench and cell insulator
structures 2, 3. Firstly, gate trenches 13 are aniostropically
etched to a depth of approximately 40 nanometers into the
semiconductor substrate 1. In a second process, silicon is etched
isotropically in order to reliably remove silicon from the vertical
sidewalls of the gate trenches 13 along the trench insulator
structures 2.
[0113] In accordance with the left-hand cross section in FIG. 8C,
gate trenches 13 are in each case introduced into the two inner
trench sections of the semiconductor fins 11. The gate trenches 13
are in each case bounded within the cell row by the mask sections
of the semiconductor fins 11 that have not been etched back, and
perpendicular to the cell row, in accordance with the right-hand
cross section, by the silicon oxide of the trench insulator
structures 2. On account of the isotropic etching process, the gate
trenches 13 undercut the adjoining sections of the protective layer
6 by approximately 0.1 F. The width of the gate trenches 13 is
accordingly approximately 0.7 F to 0.9 F. The fields of the
protective layer 6 and also the silicon oxide of the trench and
cell insulator structures 2, 3 form a hole mask 7.
[0114] The silicon oxide of the trench and cell insulator
structures 2, 3 is pulled back isotropically by approximately 0.2 F
to 0.3 F in a wet etching process.
[0115] The structure illustrated in FIG. 8D is produced, in a
simplified illustration. The trench insulator structures 2 and the
cell insulator structures 3 are pulled back in the vertical
direction by the isotropic etching. The silicon oxide is
additionally pulled back from uncovered vertical sections of the
silicon oxide in the horizontal direction. Vertical sections of the
trench insulator structure 2 are uncovered on both sides of the
gate trenches 13. The trench insulator structures 2 are thinned in
the region of the gate trenches 13 in the horizontal direction.
Pockets 22 in each case result on both sides of the gate trenches
13 and continue into the depth of the trench insulator structures 2
at the bottom of the respective gate trench 13.
[0116] The pockets 22 are formed in a cross section parallel to the
left-hand cross-sectional line and illustrated in dashed
fashion.
[0117] In the plan view, the pockets 22 extend on both sides of the
gate trenches 13 along the longitudinal sides of the semiconductor
fin 11 beyond the gate trenches 13.
[0118] By using an anisotropic etching process, the silicon oxide
is pulled back by a further 25 nanometers and the lower edge of the
pockets 22 is driven further into the silicon in the process.
[0119] FIG. 8E illustrates the extended pockets 22'. The deepening
of the pockets subsequently leads to an increase in the channel
width of the CFETs formed in the semiconductor fin 11.
[0120] A sacrificial oxide is grown on the uncovered sections of
the semiconductor fins 11. The protective layer 6 is completely
removed. Well implantations and implantations of doped zones 126
for the formation or for preparing for the formation of
source/drain regions 121, 122 in the semiconductor fins 11 are
implemented, in part as oblique implantations. A gate dielectric 80
is formed on the uncovered sections of the semiconductor fins 11
for instance by oxidization of the semiconductor substrate 1 or by
deposition of a dielectric material. A base layer 81 of a gate
conductor layer stack is deposited, the pockets 22 being filled
with the material of the base layer, for instance polysilicon.
[0121] FIG. 8F illustrates the base layer 81, the buried sections
of which fill the gate trenches 13 and the extended pockets 22' in
the gate trench insulator structures 2.
[0122] A highly conductive layer 82, for instance having tungsten,
and an insulator layer 83, for instance made of silicon nitride, of
the gate conductor layer stack are deposited and the gate conductor
layer stack is patterned by a photolithographic method to form gate
conductor structures or word lines 8 running perpendicular to the
cell rows above the gate trenches 13. A sidewall oxide is provided
on the sidewalls of the base layer 81 and the sidewalls of the word
lines 8 are covered with sidewall spacer structures 86. Optionally
doped silicon is grown on the uncovered sections of the
semiconductor fins 11. The growing process is controlled such that
the vertical growth is higher than the horizontal growth.
[0123] FIG. 8G illustrates a word line 8 in longitudinal section on
the right and three word lines 8 in cross section on the left. The
word lines 8 include a base layer 81 made of a conductive material,
for instance doped polysilicon. Buried sections 811 of the base
layer 81 fill the pockets 22 and the gate trenches 13. A highly
conductive layer 82 is applied on the base layer 81 and an
insulator layer 83 is applied on the highly conductive layer 82.
The base layer 81 of the word line 8 is insulated from the
semiconductor fin 11 by the gate dielectric 80.
[0124] The semiconductor substrate 1 includes epitaxially grown
sections 111. In the left-hand semiconductor fin 11, the active
zones 125 of two CFETs are formed, which in each case comprise, in
the grown sections 111, a first source/drain region 121 in each
case adjoining the cell insulator structure 3, and a common second
source/drain region 122' in the center of the semiconductor fin 11
and also a body region 12a, 12b.
[0125] Bit contacts and node contacts for connecting the first and
second source/drain regions 121, 122' to bit lines and stacked
capacitors are subsequently provided. A plurality of bit contacts
are in each case connected to one another by using bit lines formed
parallel to the cell rows 110. A customary BEOL process for
completing a DRAM memory cell arrangement with stacked capacitors
follows.
[0126] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that a variety of alternate and/or equivalent
implementations may be substituted for the specific embodiments
shown and described without departing from the scope of the present
invention. This application is intended to cover any adaptations or
variations of the specific embodiments discussed herein. Therefore,
it is intended that this invention be limited only by the claims
and the equivalents thereof.
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