U.S. patent application number 11/982019 was filed with the patent office on 2008-05-08 for delay circuit of semiconductor device.
This patent application is currently assigned to Hynix Semiconductor Inc.. Invention is credited to Chang-Ho Do.
Application Number | 20080106311 11/982019 |
Document ID | / |
Family ID | 39359216 |
Filed Date | 2008-05-08 |
United States Patent
Application |
20080106311 |
Kind Code |
A1 |
Do; Chang-Ho |
May 8, 2008 |
Delay circuit of semiconductor device
Abstract
A delay circuit of a semiconductor device increases its delay
time as an external voltage increases. The delay circuit can also
ensure a desired delay time according to an external voltage,
without additional delay circuits. The delay circuit of the
semiconductor device includes a first delay unit, and a second
delay. The second delay unit has a propagation delay characteristic
different from that of the first delay unit with respect to
variation of a power supply voltage, wherein the first delay unit
is supplied with a first power supply voltage independent of
variation of an external voltage, and the second delay unit is
supplied with a second power supply voltage dependent on the
variation of the external voltage.
Inventors: |
Do; Chang-Ho; (Kyoungki-do,
KR) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 OAKMEAD PARKWAY
SUNNYVALE
CA
94085-4040
US
|
Assignee: |
Hynix Semiconductor Inc.
|
Family ID: |
39359216 |
Appl. No.: |
11/982019 |
Filed: |
November 1, 2007 |
Current U.S.
Class: |
327/161 |
Current CPC
Class: |
H03K 2005/00045
20130101; G11C 7/222 20130101; G11C 7/22 20130101; H03K 5/133
20130101 |
Class at
Publication: |
327/161 |
International
Class: |
H03L 7/00 20060101
H03L007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 2, 2006 |
KR |
2006-0107888 |
Aug 30, 2007 |
KR |
2007-0087594 |
Claims
1. A delay circuit of a semiconductor device, comprising: a first
delay unit; and a second delay unit having a propagation delay
characteristic different from that of the first delay unit with
respect to variation of a power supply voltage, wherein the first
delay unit is supplied with a first power supply voltage
independent of variation of an external voltage, and the second
delay unit is supplied with a second power supply voltage dependent
on the variation of the external voltage.
2. The delay circuit as recited in claim 1, further comprising a
third delay unit connected between the first delay unit and the
second delay unit.
3. The delay circuit as recited in claim 1, wherein the first delay
unit has a fixed delay time.
4. The delay circuit as recited in claim 1, wherein the second
delay unit has a delay time corresponding to the second power
supply voltage.
5. The delay circuit as recited in claim 1, wherein the second
delay unit propagation delay characteristic includes a delay time
which increases as the second power supply voltage increases.
6. The delay circuit as recited in claim 5, wherein the second
delay unit includes a MOS type capacitor.
7. The delay circuit as recited in claim 6, wherein the MOS type
capacitor includes a PMOS transistor having a source and a drain
receiving the second power supply voltage, and a gate connected to
an output node of the first delay unit.
8. The delay circuit as recited in claim 7, wherein the second
power supply voltage is applied to a bulk terminal of the PMOS
transistor.
9. The delay circuit as recited in claim 6, wherein the MOS type
capacitor includes an NMOS transistor having a gate receiving the
second power supply voltage, and a source and a drain connected to
an output node of the first delay unit.
10. The delay circuit as recited in claim 9, wherein a bulk
terminal of the NMOS transistor is connected to the output node of
the first delay unit.
11. The delay circuit as recited in claim 1, wherein the second
power supply voltage has a voltage level substantially equal to the
external voltage.
12. The delay circuit as recited in claim 1, wherein the first
power supply voltage is supplied to the first delay unit
constantly.
13. A delay circuit of a semiconductor device, comprising: a
plurality of inverters configured to receive first and second
voltages independent of variation of an external voltage; and a
plurality of delay units configured to receive a third voltage
dependent on the variation of the external voltage.
14. The delay circuit as recited in claim 13, further comprising a
resistor connected between the inverters and the delay units.
15. The delay circuit as recited in claim 13, wherein the inverters
have a fixed delay time.
16. The delay circuit as recited in claim 13, wherein the delay
units have a delay time corresponding to the third voltage.
17. The delay circuit as recited in claim 13, wherein the delay
units have a propagation delay characteristic in which a delay time
increases as the third voltage increases.
18. The delay circuit as recited in claim 17, wherein the delay
units include a MOS type capacitor.
19. The delay circuit as recited in claim 18, wherein the MOS type
capacitor includes a PMOS transistor having a source and a drain
receiving the third voltage, and a gate connected to an output node
of one of the inverters.
20. The delay circuit as recited in claim 19, wherein the third
voltage is applied to a bulk terminal of the PMOS transistor.
21. The delay circuit as recited in claim 18, wherein the MOS type
capacitor includes an NMOS transistor having a gate receiving the
third voltage, and a source and a drain connected to an output node
of one of the inverters.
22. The delay circuit as recited in claim 21, wherein a bulk
terminal of the NMOS transistor is connected to the output node of
one of the inverters.
23. The delay circuit as recited in claim 13, wherein the third
voltage has a voltage level substantially equal to the external
voltage.
24. The delay circuit as recited in claim 13, wherein the first
voltage makes a power supply voltage of the inverters constant.
25. The delay circuit as recited in claim 13, wherein the second
voltage is a ground voltage.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present invention claims priority to Korean patent
applications numbers 10-2006-0107888 and 10-2007-0087594, filed on
Nov. 2, 2006 and Aug. 30, 2007 respectively, which are incorporated
by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor device, and
more particularly, to a delay circuit of a semiconductor
device.
[0003] Generally, a semiconductor device, e.g., a double data rate
synchronous dynamic random access memory (DDR SDRAM), includes a
plurality of delay circuits for various purposes. The delay circuit
is configured to delay an input signal by a predetermined time. The
delay circuit may be implemented using logic gates, resistors,
capacitors, and so on.
[0004] FIG. 1 illustrates a schematic circuit diagram of a
conventional delay circuit. Referring to FIG. 1, the conventional
delay circuit includes an inverter INV configured to receive an
input signal IN, a resistor R connected between a node A, i.e., an
output node of the inverter INV, and an output node B, and a
capacitor C connected between the output node B and a ground
terminal VSS.
[0005] The inverter INV includes a PMOS transistor PM and an NMOS
transistor NM. The PMOS transistor PM has a source connected to an
external voltage terminal VDD_EXT, a drain connected to the node A,
and a gate receiving the input signal IN. The NMOS transistor NM
has a drain connected to the node A, a source connected to the
ground terminal VSS, and a gate receiving the input signal IN.
[0006] A delay time of the delay circuit is determined by
resistance and capacitance of a path through which the input signal
IN is transferred. The resistance of the path means a sum of an on
resistance of the inverter INV driving the node A, a parasitic
resistance generated due to a line on the path, and a resistance of
the resistor R. The capacitance of the path means a sum of a
capacitance of the line itself, a parasitic capacitance on the
gates of the transistors PM and NM receiving the input signal IN,
and a capacitance of the capacitor C for the intended delay.
[0007] Eq. 1 below shows the relationship between the delay time,
the resistance and the capacitance.
Td.varies.(R.sub.on+R.sub.L).times.C.sub.L Eq. 1
where Td is the delay time, R.sub.on is the on resistance of the
inverter INV, R.sub.L is a sum of the parasitic resistance of the
line and the resistance of the resistor R, and C.sub.L is a sum of
the capacitance of the line itself, the parasitic capacitance on
the gates of the transistors, and the capacitance of the capacitor
C.
[0008] As can be seen from Eq. 1, the delay time of the delay
circuit increases when the resistance or capacitance increases, but
decreases when the resistance or capacitance decreases.
[0009] An external voltage of the external voltage terminal VDD_EXT
is applied to the inverter INV. As the external voltage increases,
the on resistance of the inverter INV decreases and thus the delay
time decreases. That is, the inverter INV has a propagation delay
characteristic that the delay time decreases as the external
voltage increases. If the voltage applied to the inverter INV is
not the external voltage but an internal voltage having a
predetermined voltage level, the inverter INV has a propagation
delay characteristic that it has a constant delay time regardless
of the external voltage. Further, since the ground terminal VSS is
connected to the capacitor C, the delay circuit has a propagation
delay characteristic that it has a constant delay time regardless
of the external voltage.
[0010] In a data read/write operation, the DDR SDRAM must ensure a
sensing margin time, that is, a time until an amplification
operation of a bit line sense amplifier is started after a word
line is activated. To ensure the sensing margin time, the delay
circuit is required to have a propagation delay characteristic that
the delay time increases as the external voltage increases.
Therefore, an additional delay circuit must be designed according
to the external voltage. Further, the sensing margin time cannot be
ensured when the delay time decreases as the external voltage
increases. In this case, polarity of data may be changed.
SUMMARY OF THE INVENTION
[0011] Embodiments of the present invention are directed to
providing a delay circuit of a semiconductor device, in which its
delay time increases as an external voltage increases.
[0012] Embodiments of the present invention are also directed to
providing a delay circuit of a semiconductor device, which can
ensure a desired delay time according to an external voltage,
without additional delay circuits.
[0013] In one embodiment, a delay circuit of a semiconductor device
includes a first delay unit, and a second delay unit having a
propagation delay characteristic different from that of the first
delay unit with respect to variation of a power supply voltage,
wherein the first delay unit is supplied with a first power supply
voltage independent of variation of an external voltage, and the
second delay unit is supplied with a second power supply voltage
dependent on the variation of the external voltage.
[0014] In another embodiment, a delay circuit of a semiconductor
device includes a plurality of inverters configured to receive
first and second voltages independent of variation of an external
voltage, and a plurality of delay units configured to receive a
third voltage dependent on the variation of the external
voltage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 illustrates a schematic circuit diagram of a
conventional delay circuit.
[0016] FIG. 2 illustrates a schematic circuit diagram of a delay
circuit of a semiconductor device in accordance with a first
embodiment of the present invention.
[0017] FIG. 3 illustrates a graph of a capacitance according to
formation/non-formation of a channel in the PMOS type capacitor
described in FIG. 2.
[0018] FIG. 4 illustrates a graph of a capacitance according to an
external voltage applied to the PMOS type capacitor described in
FIG. 2.
[0019] FIG. 5 illustrates a schematic circuit diagram of a delay
circuit of a semiconductor device in accordance with a second
embodiment of the present invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0020] In a delay circuit of the present invention using a
plurality of delay units, different voltages are applied to a first
delay unit and a second delay unit. Thus, the first delay unit has
a characteristic that a delay time is independent of an external
voltage, and the second delay unit has a characteristic that the
delay time increase as the external voltage increases.
Consequently, the delay circuit has a propagation delay
characteristic in which the delay time increases as the external
voltage increases.
[0021] Hereinafter, a delay circuit of a semiconductor device in
accordance with the present invention will be described in detail
with reference to the accompanying drawings.
[0022] FIG. 2 illustrates a schematic circuit diagram of a delay
circuit of a semiconductor device in accordance with a first
embodiment of the present invention.
[0023] Referring to FIG. 2, the delay circuit includes an inverter
INV, a resistor R, and a PMOS type capacitor PMC. The inverter INV
is connected between an internal voltage terminal VDD_INN and a
ground terminal VSS and configured to receive an input signal IN.
The resistor R is connected between a node A, i.e., an output node
of the inverter INV and an output node B. The PMOS type capacitor
PMC is connected between an external voltage terminal VDD_EXT and
the output node B.
[0024] The inverter INV includes a PMOS transistor PM and an NMOS
transistor NM. The PMOS transistor PM has a source connected to the
internal voltage terminal VDD_INN, a drain connected to the node A,
and a gate receiving the input signal IN. The NMOS transistor NM
has a drain connected to the node A, a source connected to the
ground terminal VSS, and a gate receiving the input signal IN.
[0025] The PMOS type capacitor PMC is implemented with a PMOS
transistor having a source and a drain commonly connected to the
external voltage terminal VDD_EXT, and a gate connected to the
output node B. A bulk terminal may also be connected to the
external voltage terminal VDD_EXT, or may be separated according to
circumstances.
[0026] In the PMOS type capacitor PMC, the capacitance when a
channel is formed between the source and the drain is different
from the capacitance when no channel is formed between the source
and the drain. The formation/non-formation of the channel in the
PMOS type capacitor PMC is determined by a relative potential
difference between the two terminals of the PMOS type capacitor
PMC. FIG. 3 illustrates a graph of the capacitance of the PMOS type
capacitor PMC according to the formation/non-formation of the
channel in the PMOS type capacitor PMC. In FIG. 3, a horizontal
axis represents a voltage level of the output node B, and a
vertical axis represents a capacitance of the POMS type capacitor
PMC.
[0027] Referring to FIGS. 2 and 3, the PMOS type capacitor PMC is
connected between the external voltage terminal VDD_EXT and the
output node B. Therefore, the channel may or may not be formed in
the PMOS type capacitor PMC according to the voltage level of the
output node B. As can be seen from FIG. 3, the capacitance when the
channel is formed is greater than the capacitance when no channel
is formed. In other words, the capacitance acting as the load when
the channel is formed is greater than the capacitance when no
channel is formed. The channel is formed in a condition of Eq. 2
below.
V.sub.gs-V.sub.t>0 Eq. 2
where V.sub.gs is a voltage difference between the gate and the
source of the PMOS type capacitor PMC, and V.sub.t is the threshold
voltage of the PMOS type capacitor PMC.
[0028] The capacitance of the PMOS type capacitor PMC according to
the external voltage applied through the external voltage terminal
VDD_EXT will be described below with reference to FIG. 4.
[0029] Referring to FIG. 4, the channel formation section changes
according to the external voltage. As the external voltage
increases, the channel formation section becomes long. This means
that a large capacitance is maintained longer and it acts as a
large-capacitance load for a longer time.
[0030] For example, if the large capacitance (when the channel is
formed) occupies 20% of the delay time and the small capacitance
(when no channel is formed) occupies 80% of the delay time when the
external voltage is low, the large capacitance occupies 80% of the
delay time and the small capacitance occupies 20% of the delay time
when the external voltage is high. Consequently, the delay time
increases linearly as the external voltage increases.
[0031] FIG. 5 illustrates a schematic circuit diagram of a delay
circuit of a semiconductor device in accordance with a second
embodiment of the present invention. For convenience, like
reference numerals are used to refer to like elements throughout
the drawings.
[0032] Referring to FIG. 5, the delay circuit in accordance with
the second embodiment of the present invention includes an
inverter, a resistor R, and an NMOS type capacitor NMC. The NMOS
type capacitor NMC can achieve the same operation as the PMOS type
capacitor PMC described in FIG. 2.
[0033] The NMOS type capacitor NMC is implemented with an NMOS
transistor having a gate receiving an external voltage terminal
VDD_EXT, and a drain and a source commonly connected to an output
node B. Likewise, a bulk terminal may be connected to the output
node B, or may be separated according to circumstances.
[0034] Like the PMOS type capacitor PMC, a capacitance of the NMOS
type capacitor NMC when a channel is formed between the drain and
the source is different from a capacitance of the NMOS type
capacitor NMC when no channel is formed between the drain and the
source. The formation/non-formation of the channel in the NMOS type
capacitor NMC is determined by a relative potential difference
between the two terminals of the NMOS type capacitor NMC. The
capacitance according to the formation/non-formation of a channel
in the NMOS type capacitor NMC is equal to that illustrated in FIG.
3, and the channel formation section according to the external
voltage is equal to that illustrated in FIG. 4.
[0035] As the external voltage increases, the channel formation
section becomes longer. That is, the large capacitance section
becomes longer, thus increasing the delay time.
[0036] Referring to FIGS. 2 and 5, the internal voltage applied
through the internal voltage terminal VDD_INN to the inverter INV
is an independently fixed voltage with respect to the variation of
the external voltage and has a constant voltage level so as to
drive the inverter INV. Therefore, the inverter INV has a
propagation delay characteristic in which the delay time is
constant, regardless of the external voltage. Further, the PMOS
type capacitor PMC and the NMOS type capacitor NMC have a
propagation delay characteristic in which the delay time increases
as the external voltage increases.
[0037] The voltages applied to the PMOS type capacitor PMC and the
NMOS type capacitor NMC are not necessarily equal to the external
voltage. In other words, any voltages can be applied to the PMOS
type capacitor PMC and the NMOS type capacitor NMC only if they are
dependent on the external voltage.
[0038] The semiconductor memory device may include a plurality of
delay circuits illustrated in FIG. 2.
[0039] As described above, the delay circuit of the semiconductor
device can obtain the propagation delay characteristic in which the
delay time increases as the external voltage increases. In the
circuits using a high voltage source, this propagation delay
characteristic is significantly advantageous to increase the delay
time without additional circuits. Particularly, the delay circuits
in accordance with the embodiments of the present invention are
adapted to ensure the sensing margin time.
[0040] In accordance with the embodiments of the present invention,
the delay circuit can obtain the propagation delay characteristic
in which the delay time increases according to the variation of the
external voltage. By applying the delay circuit to circuits
requiring the propagation delay characteristic, the more stable
circuit operation can be obtained. Further, problems caused by
insufficient sensing margin time can be prevented.
[0041] While the present invention has been described with respect
to the specific embodiments, it will be apparent to those skilled
in the art that various changes and modifications may be made
without departing from the spirit and scope of the invention as
defined in the following claims.
* * * * *