U.S. patent application number 11/546679 was filed with the patent office on 2008-04-17 for forming sublithographic heaters for phase change memories.
Invention is credited to Jong-Won S. Lee, Gianpaolo Spadini.
Application Number | 20080090324 11/546679 |
Document ID | / |
Family ID | 39303512 |
Filed Date | 2008-04-17 |
United States Patent
Application |
20080090324 |
Kind Code |
A1 |
Lee; Jong-Won S. ; et
al. |
April 17, 2008 |
Forming sublithographic heaters for phase change memories
Abstract
A phase change memory with a heater with sublithographic
dimensions may be achieved, in some embodiments, with lower thermal
budget. The phase change memory may use a controlled etching
process to reduce the lateral dimension of the heater.
Inventors: |
Lee; Jong-Won S.; (San
Francisco, CA) ; Spadini; Gianpaolo; (Campbell,
CA) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
39303512 |
Appl. No.: |
11/546679 |
Filed: |
October 12, 2006 |
Current U.S.
Class: |
438/95 ;
257/E45.002 |
Current CPC
Class: |
H01L 45/06 20130101;
H01L 45/126 20130101; H01L 45/16 20130101; H01L 45/1233 20130101;
H01L 45/1273 20130101 |
Class at
Publication: |
438/95 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Claims
1. A method comprising: exposing a side of a phase change memory
heater material to an etchant to reduce a lateral dimension of said
heater.
2. The method of claim 1 including forming an upstanding heater and
exposing a portion of its vertical extent.
3. The method of claim 1 including etching said heater including
said exposed vertical extent.
4. The method of claim 1 including using a damascene process to
form said heater.
5. The method of claim 4 including removing a portion of a
dielectric surrounding said heater.
6. The method of claim 3 including covering said etched heater with
an insulator.
7. The method of claim 3 including planarizing said etched
heater.
8. The method of claim 7 including covering said etched heater with
an insulator and then planarizing said etched heater.
9. The method of claim 7 including covering said etched heater with
a sacrificial material to improve planarization
controllability.
10. The method of claim 1 including forming said heater in an
inverted T-shape.
11. A phase change memory comprising: a chalcogenide material; and
a heater for said chalcogenide material, said heater having an
inverted T-shape with a horizontally extending portion and a
vertically extending portion, said vertically extending portion
adjacent said material.
12. The memory of claim 11 wherein said vertically extending
portion has a sublithographic lateral extent.
13. The memory of claim 12 wherein said vertically extending
portion tapers inwardly as it extends towards said horizontally
extending portion.
14. The memory of claim 13 wherein said horizontally extending
portion includes a curved surface that extends into said vertically
extending portion.
15. The memory of claim 11 wherein said heater horizontally
extending portion is wider in a lateral direction than said
vertically extending portion.
16. The memory of claim 11 wherein said heater vertically extending
portion is in contact with said chalcogenide material.
17. The memory of claim 11 without side wall spacers.
18. A system comprising: a processor; a battery to supply power to
said processor; and a phase change memory coupled to said
processor, said phase change memory including a chalcogenide
material and a heater having an inverted T-shape, having a wider
and narrower portion, said narrower portion of the heater being
closer to said chalcogenide material.
19. The system of claim 18 wherein said narrower portion has a
sublithographic lateral extent.
20. The system of claim 19 wherein said wider portion tapers
inwardly as it extends towards said narrower portion.
21. The system of claim 20 wherein said wider portion includes a
curved surface that extends into said narrower portion.
22. The system of claim 18 wherein said wider portion is wider in a
lateral direction than said narrower portion.
23. The system of claim 18 wherein said narrower portion is in
contact with said chalcogenide material.
Description
BACKGROUND
[0001] This invention relates generally to phase change
memories.
[0002] Phase change memory devices use phase change materials,
i.e., materials that may be electrically switched between a
generally amorphous and a generally crystalline state, for
electronic memory application. One type of memory element utilizes
a phase change material that may be, in one application,
electrically switched between a structural state of generally
amorphous and generally crystalline local order or between
different detectable states of local order across the entire
spectrum between completely amorphous and completely crystalline
states. The state of the phase change materials is also
non-volatile in that, when set in either a crystalline,
semi-crystalline, amorphous, or semi-amorphous state representing a
resistance value, that value is retained until changed by another
programming event, as that value represents a phase or physical
state of the material (e.g., crystalline or amorphous). The state
is unaffected by removing electrical power.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is an enlarged, cross-sectional view of one
embodiment of the present invention at an early stage of
manufacture;
[0004] FIG. 2 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present
invention;
[0005] FIG. 3 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present
invention;
[0006] FIG. 4 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present
invention;
[0007] FIG. 5 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present
invention;
[0008] FIG. 6 is an enlarged, cross-sectional view at a subsequent
stage of manufacture in accordance with one embodiment of the
present invention;
[0009] FIG. 7 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present
invention;
[0010] FIG. 8 is an enlarged, cross-sectional view at a subsequent
stage in accordance with one embodiment of the present invention;
and
[0011] FIG. 9 is a system depiction of one embodiment of the
present invention.
DETAILED DESCRIPTION
[0012] In accordance with some embodiments of the present
invention, a phase change memory may be formed with a so-called
sublithographic heater. A sublithographic heater is a heater which
has a lateral dimension which is smaller than the smallest
dimension possible with lithographic techniques or currently about
eighty nanometers.
[0013] Rather than using a lithographic or masking technique, the
ultimate cross-sectional area of the heater, in some embodiments of
the present invention, may be determined by a controlled etching
process.
[0014] In some cases, the lateral dimension of the heater is
smaller which may result in many improved characteristics in some
cases. A reduced heater dimension may aid in reducing the unit cell
area of a phase change memory cell. In addition, the sensitivity of
a phase change memory cell's cycling endurance may be improved. The
unit cell size is typically limited by the size of the device
needed to supply the programming current to the storage cell. The
magnitude of that programming current is generally governed by the
heater dimension. Thus, the phase change memory unit cell area
depends on how small the heater can be defined in a repeatable
fashion. The relationship between the cycling endurance and
programming current magnitude is such that the smaller programming
current preserves the memory cell's initial data fidelity to high
cycling numbers, thus extending the product lifetime or enabling
the product to serve more read/write intensive applications.
[0015] In addition, it may be desirable to enable the fabrication
of sublithographic heaters with less thermal budget. The thermal
budget may be an important consideration, in some embodiments,
since chalcogenide alloys used in phase change memories have
limited thermal endurance during wafer processing.
[0016] Referring to FIG. 1, initially, a phase change memory cell
may be formed over a substrate 10. In some embodiments of the
present invention, the substrate 10 may include a diffusion which
acts as a row line for the phase change memory. Over the row line
in the substrate 10 may be formed a dielectric layer. In some
embodiments, the dielectric layer may be formed of two distinct
layers 12 and 14. A pore 18 is formed through the two layers, down
to the substrate 10, in some embodiments. The pore 18 may be filled
with the heater material 16. A number of different heat materials
may be utilized, including those that include titanium, titanium
nitride, or other alloys or resistive conductors.
[0017] Then, referring to FIG. 2, the structure shown in FIG. 1 may
be planarized to form the bulk heater 16 within the pore 18. As an
alternative, a subtractive etch process with masking may be used to
form the bulk heater 16. Other techniques may be utilized as
well.
[0018] Moving to FIG. 3, the upper layer 14 may be removed, for
example, with a selective etch which selectively removes the layer
14, rather than the layer 12 or the bulk heater 16.
[0019] Thereafter, as shown in FIG. 4, subtractive etching
processing may be utilized to form a sublithographic lateral
dimension of the heater 16. Preferably an etchant is used which is
selective of the bulk heater 16 over the exposed dielectric layer
12. The chemical etching may be accomplished with plasma or wet
etching, for example, using chlorine based etchants. The etching
may be to a controlled depth, at a controlled etch rate for a
controlled etch time. As a result, the exposed vertical dimension
of the heater 16 is etched laterally, reducing the heater
width.
[0020] Next, as shown in FIG. 5, a dielectric layer 20 may be
deposited as a chemical mechanical planarization stop 20.
Thereafter, as shown in FIG. 6, a sacrificial material 22 may be
deposited to improve chemical mechanical planarization
controllability and to reduce surface topography. The sacrificial
layer may be spun on or deposited by plasma enhanced chemical vapor
deposition.
[0021] As shown in FIG. 7, the chemical mechanical planarization
step may planarize the structure down to the layer 20, removing the
upper portion of the bulk heater and forming the heater 16 of a
reduced lateral dimension. In some embodiments, the lateral
dimension of the heater may be a sublithographic dimension which is
less than any dimension possible with existing lithographic
techniques.
[0022] As a result of the way the heater 16 is formed, it may have
an inverted T-shape, with curved sides that taper towards one
another and a thicker base.
[0023] In some embodiments, there is no need to form a conformal
spacer to create the sublithographic heater. Conformal spacer
deposition may be accomplished by high temperature chemical vapor
deposition or atomic layer deposition for control of the geometry
of the resulting spacer. By eliminating the spacer deposition
process, a lower temperature process may be achieved in some
cases.
[0024] Thereafter, ensuing layers may be utilized to either
complete a phase change memory cell or, if desired, to form a
select device thereover. The select device may, for example, be a
diode, a transistor, or an ovonic threshold switch.
[0025] In FIG. 8, a simple structure is illustrated in which a
single ovonic memory cell is created by applying a layer 22 of
chalcogenide, followed by a metallic layer 24 which, in some
embodiments, may form a column line. Thereafter, if desired, an
etching process may be utilized to define the width of the
chalcogenide 22 and the layer 24. Thus, in some embodiments, the
column may run into the page while the row runs across the page
within the substrate 10.
[0026] The inverted or T-shaped heater 16 has a horizontally
extending portion 26 and a vertically extending portion 28 in one
embodiment. The portion 28 may be closest to the chalcogenide 22 in
one embodiment.
[0027] Programming of the chalcogenide material 22 to alter the
state or phase of the material may be accomplished by applying
voltage potentials to the lower electrode and upper electrode 24,
thereby generating a voltage potential across the select device and
memory element. When the voltage potential is greater than the
threshold voltages of select device and memory element, then an
electrical current may flow through the chalcogenide material 30 in
response to the applied voltage potentials, and may result in
heating of the chalcogenide material 22.
[0028] This heating may alter the memory state or phase of the
chalcogenide material 22. Altering the phase or state of the
chalcogenide material 22 may alter the electrical characteristic of
memory material, e.g., the resistance of the material may be
altered by altering the phase of the memory material. Memory
material may also be referred to as a programmable resistive
material.
[0029] In the "reset" state, memory material may be in an amorphous
or semi-amorphous state and in the "set" state, memory material may
be in an a crystalline or semi-crystalline state. The resistance of
memory material in the amorphous or semi-amorphous state may be
greater than the resistance of memory material in the crystalline
or semi-crystalline state. It is to be appreciated that the
association of reset and set with amorphous and crystalline states,
respectively, is a convention and that at least an opposite
convention may be adopted.
[0030] Using electrical current, memory material may be heated to a
relatively higher temperature to amorphosize memory material and
"reset" memory material (e.g., program memory material to a logic
"0" value). Heating the volume of memory material to a relatively
lower crystallization temperature may crystallize memory material
and "set" memory material (e.g., program memory material to a logic
"1" value). Various resistances of memory material may be achieved
to store information by varying the amount of current flow and
duration through the volume of memory material.
[0031] A select device may operate as a switch that is either "off"
or "on" depending on the amount of voltage potential applied across
the memory cell, and more particularly whether the current through
the select device exceeds its threshold current or voltage, which
then triggers the device into the on state. The off state may be a
substantially electrically nonconductive state and the on state may
be a substantially conductive state, with less resistance than the
off state.
[0032] In the on state, the voltage across the select device, in
one embodiment, is equal to its holding voltage V.sub.H plus IxRon,
where Ron is the dynamic resistance from the extrapolated X-axis
intercept, V.sub.H. For example, a select device may have threshold
voltages and, if a voltage potential less than the threshold
voltage of a select device is applied across the select device,
then the select device may remain "off" or in a relatively high
resistive state so that little or no electrical current passes
through the memory cell and most of the voltage drop from selected
row to selected column is across the select device. Alternatively,
if a voltage potential greater than the threshold voltage of a
select device is applied across the select device, then the select
device may "turn on," i.e., operate in a relatively low resistive
state so that electrical current passes through the memory cell. In
other words, one or more series connected select devices may be in
a substantially electrically nonconductive state if less than a
predetermined voltage potential, e.g., the threshold voltage, is
applied across select devices. Select devices may be in a
substantially conductive state if greater than the predetermined
voltage potential is applied across select devices. Select devices
may also be referred to as an access device, an isolation device,
or a switch.
[0033] In one embodiment, each select device may comprise a switch
material 16 such as, for example, a chalcogenide alloy, and may be
referred to as an ovonic threshold switch, or simply an ovonic
switch. The switch material 22 of select devices may be a material
in a substantially amorphous state positioned between two
electrodes that may be repeatedly and reversibly switched between a
higher resistance "off" state (e.g., greater than about ten
megaOhms) and a relatively lower resistance "on" state (e.g., about
one thousand Ohms in series with V.sub.H) by application of a
predetermined electrical current or voltage potential. In this
embodiment, each select device may be a two terminal device that
may have a current-voltage (I-V) characteristic similar to a phase
change memory element that is in the amorphous state. However,
unlike a phase change memory element, the switching material of
select devices may not change phase. That is, the switching
material of select devices may not be a programmable material, and,
as a result, select devices may not be a memory device capable of
storing information. For example, the switching material of select
devices may remain permanently amorphous and the I-V characteristic
may remain the same throughout the operating life.
[0034] In the low voltage or low electric field mode, i.e., where
the voltage applied across select device is less than a threshold
voltage (labeled V.sub.TH), a select device may be "off" or
nonconducting, and exhibit a relatively high resistance, e.g.,
greater than about 10 megaOhms. The select device may remain in the
off state until a sufficient voltage, e.g., V.sub.TH, is applied,
or a sufficient current is applied, e.g., I.sub.TH, that may switch
the select device to a conductive, relatively low resistance on
state. After a voltage potential of greater than about V.sub.TH is
applied across the select device, the voltage potential across the
select device may drop ("snapback") to a holding voltage potential,
V.sub.H. Snapback may refer to the voltage difference between
V.sub.TH and V.sub.H of a select device.
[0035] In the on state, the voltage potential across select device
may remain close to the holding voltage of V.sub.H as current
passing through select device is increased. The select device may
remain on until the current through the select device drops below a
holding current, I.sub.H. Below this value, the select device may
turn off and return to a relatively high resistance, nonconductive
off state until the V.sub.TH and I.sub.TH are exceeded again.
[0036] In some embodiments, only one select device may be used. In
other embodiments, more than two select devices may be used. A
single select device may have a V.sub.H about equal to its
threshold voltage, V.sub.TH, (a voltage difference less than the
threshold voltage of the memory element) to avoid triggering a
reset bit when the select device triggers from a threshold voltage
to a lower holding voltage called the snapback voltage. An another
example, the threshold current of the memory element may be about
equal to the threshold current of the access device even though its
snapback voltage is greater than the memory element's reset bit
threshold voltage.
[0037] One or more MOS or bipolar transistors or one or more diodes
(either MOS or bipolar) may be used as the select device. If a
diode is used, the bit may be selected by lowering the row line
from a higher deselect level. As a further non-limiting example, if
an n-channel MOS transistor is used as a select device with its
source, for example, at ground, the row line may be raised to
select the memory element connected between the drain of the MOS
transistor and the column line. When a single MOS or single bipolar
transistor is used as the select device, a control voltage level
may be used on a "row line" to turn the select device on and off to
access the memory element.
[0038] Turning to FIG. 9, a portion of a system 500 in accordance
with an embodiment of the present invention is described. System
500 may be used in wireless devices such as, for example, a
personal digital assistant (PDA), a laptop or portable computer
with wireless capability, a web tablet, a wireless telephone, a
pager, an instant messaging device, a digital music player, a
digital camera, or other devices that may be adapted to transmit
and/or receive information wirelessly. System 500 may be used in
any of the following systems: a wireless local area network (WLAN)
system, a wireless personal area network (WPAN) system, a cellular
network, although the scope of the present invention is not limited
in this respect.
[0039] System 500 may include a controller 510, an input/output
(I/O) device 520 (e.g. a keypad, display), static random access
memory (SRAM) 560, a memory 530, and a wireless interface 540
coupled to each other via a bus 550. A battery 580 may be used in
some embodiments. It should be noted that the scope of the present
invention is not limited to embodiments having any or all of these
components.
[0040] Controller 510 may comprise, for example, one or more
microprocessors, digital signal processors, microcontrollers, or
the like. Memory 530 may be used to store messages transmitted to
or by system 500. Memory 530 may also optionally be used to store
instructions that are executed by controller 510 during the
operation of system 500, and may be used to store user data. Memory
530 may be provided by one or more different types of memory. For
example, memory 530 may comprise any type of random access memory,
a volatile memory, a non-volatile memory such as a flash memory
and/or a memory such as memory discussed herein.
[0041] I/O device 520 may be used by a user to generate a message.
System 500 may use wireless interface 540 to transmit and receive
messages to and from a wireless communication network with a radio
frequency (RF) signal. Examples of wireless interface 540 may
include an antenna or a wireless transceiver, although the scope of
the present invention is not limited in this respect.
[0042] References throughout this specification to "one embodiment"
or "an embodiment" mean that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one implementation encompassed within the
present invention. Thus, appearances of the phrase "one embodiment"
or "in an embodiment" are not necessarily referring to the same
embodiment. Furthermore, the particular features, structures, or
characteristics may be instituted in other suitable forms other
than the particular embodiment illustrated and all such forms may
be encompassed within the claims of the present application.
[0043] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *