U.S. patent application number 11/874795 was filed with the patent office on 2008-04-17 for stacked modules and method.
This patent application is currently assigned to Staktek Group L.P.. Invention is credited to James Douglas JR. Wehrly.
Application Number | 20080088032 11/874795 |
Document ID | / |
Family ID | 37968096 |
Filed Date | 2008-04-17 |
United States Patent
Application |
20080088032 |
Kind Code |
A1 |
Wehrly; James Douglas JR. |
April 17, 2008 |
Stacked Modules and Method
Abstract
The present invention stacks integrated circuits into modules
that conserve board surface area. In a precursor assembly devised
as a component for a stacked circuit module in accordance with a
preferred embodiment of the present invention, one or more
stiffeners are disposed at least partially between a flex circuit
and an integrated circuit. In a two-high stacked circuit module
devised in accordance with a preferred embodiment of the present
invention, an integrated circuit is stacked above a precursor
assembly. The two integrated circuits are connected with the flex
circuit of the precursor assembly. The present invention may be
employed to advantage in numerous configurations and combinations
of integrated circuits in modules.
Inventors: |
Wehrly; James Douglas JR.;
(Austin, TX) |
Correspondence
Address: |
FISH & RICHARDSON P.C.
P.O BOX 1022
Minneapolis
MN
55440-1022
US
|
Assignee: |
Staktek Group L.P.
|
Family ID: |
37968096 |
Appl. No.: |
11/874795 |
Filed: |
October 18, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11403081 |
Apr 12, 2006 |
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11874795 |
Oct 18, 2007 |
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11317425 |
Dec 22, 2005 |
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11874795 |
Oct 18, 2007 |
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10400309 |
Mar 27, 2003 |
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11317425 |
Dec 22, 2005 |
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10005581 |
Oct 26, 2001 |
6576992 |
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10400309 |
Mar 27, 2003 |
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11258438 |
Oct 25, 2005 |
7310458 |
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11874795 |
Oct 18, 2007 |
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11015521 |
Dec 17, 2004 |
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11258438 |
Oct 25, 2005 |
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10845029 |
May 13, 2004 |
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11015521 |
Dec 17, 2004 |
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PCT/US03/29000 |
Sep 15, 2003 |
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10845029 |
May 13, 2004 |
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11263627 |
Oct 31, 2005 |
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11874795 |
Oct 18, 2007 |
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10958584 |
Oct 5, 2004 |
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11263627 |
Oct 31, 2005 |
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10136890 |
May 2, 2002 |
6940729 |
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10958584 |
Oct 5, 2004 |
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10873847 |
Jun 22, 2004 |
7094632 |
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11263627 |
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10631886 |
Jul 11, 2003 |
7026708 |
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10873847 |
Jun 22, 2004 |
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10453398 |
Jun 3, 2003 |
6914324 |
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10631886 |
Jul 11, 2003 |
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10005581 |
Oct 26, 2001 |
6576992 |
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10453398 |
Jun 3, 2003 |
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10457608 |
Jun 9, 2003 |
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10631886 |
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10005581 |
Oct 26, 2001 |
6576992 |
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10457608 |
Jun 9, 2003 |
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Current U.S.
Class: |
257/777 ;
257/E23.01; 257/E25.023 |
Current CPC
Class: |
H01L 2924/00012
20130101; H01L 2924/00011 20130101; Y10T 29/49169 20150115; H01L
25/105 20130101; H01L 2924/00014 20130101; H01L 2924/3511 20130101;
Y10T 29/53209 20150115; Y10T 29/5327 20150115; H01L 23/3114
20130101; H01L 23/4985 20130101; H01L 2224/73253 20130101; H01L
2224/0401 20130101; H01L 2224/16225 20130101; H01L 2225/06586
20130101; H01L 23/5387 20130101; H01L 2224/73204 20130101; H01L
2225/06579 20130101; H01L 2924/00011 20130101; H01L 2224/16225
20130101; H01L 2224/73203 20130101; H01L 2224/32225 20130101; H01L
2225/06541 20130101; H01L 2924/00014 20130101; H01L 23/5385
20130101; H01L 21/4871 20130101; H01L 2924/14 20130101; H01L 24/16
20130101; H01L 23/49838 20130101; H01L 23/49833 20130101; H01L
2225/06517 20130101; H01L 2225/107 20130101; H01L 2224/0401
20130101; H01L 2224/73204 20130101; H01L 2224/32225 20130101 |
Class at
Publication: |
257/777 ;
257/E23.01 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. An assembly devised as a component for a stacked circuit module
comprising: a first CSP having upper and lower major surfaces,
first and second lateral sides, and first CSP contacts disposed
along the lower major surface; a flex circuit configured for
external electrical connection of the first CSP, the flex circuit
comprising lower flex contacts connected to selected ones of the
first CSP contacts, and first and second upper portions terminated
by first and second edges, respectively, the first upper portion of
the flex circuit being disposed above the upper major surface of
the first CSP along the first lateral side, the second upper
portion of the flex circuit being disposed above the upper major
surface of the first CSP along the second lateral side, and the
first and second edges being disposed a preselected distance apart
above the first CSP; a stiffener attached to the lower major
surface of the first CSP.
2. The assembly of claim 1 in which the first CSP contacts at least
partially project below the lower major surface of the first
CSP.
3. The assembly of claim 1 in which the stiffener disposes the
lower flex contacts apart from the lower major surface of the first
CSP.
4. The assembly of claim 3 in which the flex circuit has plural
conductive layers.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/403,081, filed Apr. 12, 2006. This
application is a continuation-in-part of U.S. patent application
Ser. No. 11/317,425 filed Dec. 22, 2005, which is a continuation of
U.S. patent application Ser. No. 10/400,309 filed Mar. 27, 2003,
which is a continuation of U.S. patent application Ser. No.
10/005,581, filed Oct. 26, 2001, now issued as U.S. Pat. No.
6,576,992 B2.
[0002] This application also is a continuation-in-part of U.S.
patent application Ser. No. 11/258,438 filed Oct. 25, 2005, which
is a continuation-in-part of U.S. patent application Ser. No.
11/015,521, filed Dec. 17, 2004, pending, which is a
continuation-in-part of U.S. patent application Ser. No.
10/845,029, filed May 13, 2004, pending, which is a
continuation-in-part of PCT Application No. PCT/US03/29000, filed
Sep. 15, 2003, pending.
[0003] This application also is a continuation-in-part of U.S.
patent application Ser. No. 11/263,627, filed Oct. 31, 2005,
pending, which is a continuation-in-pail of U.S. patent application
Ser. No. 10/958,584, filed Oct. 5, 2004, pending, which is a
continuation of U.S. patent application Ser. No. 10/136,890, filed
May 2, 2002, now U.S. Pat. No. 6,940,729 B2, issued Sep. 6, 2005.
U.S. patent application Ser. No. 11/263,627 also is a
continuation-in-part of U.S. patent application Ser. No.
10/873,847, filed Jun. 22, 2004, pending, which is a continuation
of U.S. patent application Ser. No. 10/631,886, filed Jul. 11,
2003, pending, which is a continuation-in-part of U.S. patent
application Ser. No. 10/453,398, filed Jun. 3, 2003, now U.S. Pat.
No. 6,914,324 B2, issued Jul. 5, 2005, which is a
continuation-in-part of U.S. patent application Ser. No.
10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 B2,
issued Jun. 10, 2003. U.S. patent application Ser. No. 10/631,886
also is a continuation-in-part of U.S. patent application Ser. No.
10/457,608, filed Jun. 9, 2003, pending, which is a
continuation-in-part of U.S. patent application Ser. No.
10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 B2,
issued Jun. 10, 2003.
[0004] U.S. patent application Ser. Nos. 10/005,581, 10/136,890,
10/400,309, 10/453,398, 10/457,608, 10/631,886, 10/845,029,
10/873,847, 10/958,584, 11/015,521, 11/258,438, 11/263,627,
11/317,425, 11/403,081 and PCT Application No. PCT/US03/29000 are
hereby incorporated by reference for all purposes.
TECHNICAL FIELD
[0005] The present invention relates to aggregating integrated
circuits and, in particular, to stacking integrated circuits in
chip-scale packages and methods for creating stacked modules of
chip-scale packages.
BACKGROUND
[0006] A variety of techniques are used to stack packaged
integrated circuits. Some methods require special packages, while
other techniques stack packages configured to allow stand-alone
deployment in an operating environment.
[0007] "Chip scale packaging" or CSP refers generally to packages
that provide connection to an integrated circuit through a set of
contacts (often embodied as "bumps" or "balls") arrayed across a
major surface of the package. Instead of leads emergent from a
peripheral side of the package as in "leaded" packages, in a CSP,
contacts are placed on a major surface and typically emerge from
the planar bottom surface of the package. The absence of "leads" on
package sides renders most stacking techniques devised for leaded
packages inapplicable for CSP stacking.
[0008] CSP has enabled reductions in size and weight parameters for
many applications. CSP is a broad category including a variety of
packages from near chip scale to die-sized packages such as the die
sized ball grid array (DSBGA). To meet the continuing demands for
cost and form factor reductions concurrent with increasing
capabilities and capacities, technologies that aggregate plural
integrated circuit dies in a package been developed. The techniques
and technology for stacking plural integrated circuit dies within a
single package, however, are not generally applicable for stacking
packages that are configured to allow stand-alone deployment in an
operating environment.
[0009] There are several known techniques for stacking integrated
circuit packages articulated in chip scale technology. A variety of
previous techniques for stacking CSPs typically present complex
structural arrangements and thermal or high frequency performance
issues. For example, thermal performance is a characteristic of
importance in CSP stacks. With increasing operating frequencies of
most systems, high frequency performance issues are also
increasingly important. Further, many stacking techniques result in
modules that exhibit profiles taller than may be preferred for
particular applications.
[0010] Staktek Group L.P., the assignee of the present invention,
has developed a variety of stacked module designs that employ a
form standard or mandrel that can provide thermal and/or
construction advantages while providing a standard form that may
allow use of a flexible circuit design with a variety of CSP types
and body sizes. The mandrel or form standard stack designs come in
a variety of shapes and sizes and materials. Some form standards
extend beyond the perimeter edge or the extent of the CSP body and
thus provide a form about which the flex circuitry transits. Some
other form standards are substantially planar and have a lateral
extent smaller than the lateral extent of an adjacent CSP. Although
form standards provide numerous benefits in stacked module designs,
the use of form standards may add various cost and complexity
issues to the design and manufacturing issues inherent with stacked
modules.
[0011] Stacked module design and assembly techniques and systems
that provide a thermally efficient, reliable structure that perform
well at higher frequencies but do not add excessive height to the
stack that can be manufactured at reasonable cost with readily
understood and managed materials and methods are provided.
SUMMARY
[0012] The present invention allows chip scale-packaged integrated
circuits (CSPs) that are configured to allow stand-alone deployment
in an operating environment to instead be stacked into modules that
conserve PWB or other board surface area. The present invention can
be used to advantage with CSP packages of a variety of sizes and
configurations ranging from typical BGAs with footprints somewhat
larger than the contained die to smaller packages such as, for
example, die-sized packages such as DSBGA. Although the present
invention is applied most frequently to chip scale packages that
contain one die, it may be employed with chip scale packages that
include more than one integrated circuit die.
[0013] In a two-high CSP stack or module devised in accordance with
a preferred embodiment of the present invention, two CSPs are
stacked, with one CSP disposed above the other. The two CSPs are
connected with a pair of flex circuits. Each of the pair of flex
circuits is partially wrapped about a respective opposite lateral
edge of the lower CSP of the module. The flex circuit pair connects
the upper and lower CSPs and provides a thermal and electrical path
connection path between the module and an application environment
such as a printed wiring board (PWB).
[0014] In an alternate preferred embodiment of the present
invention, a precursor assembly for use as a component of a stacked
circuit module is devised having a CSP and a flex circuit with one
or more stiffeners attached to the flex circuit. The stiffeners are
disposed along a major surface of the CSP and may be attached to
the major surface of the CSP by adhesive. Exemplary stacked circuit
modules devised in accordance with a preferred embodiment of the
present invention comprise a second CSP disposed above the CSP of
the precursor assembly, the second CSP being connected to the upper
portions of the flex circuit.
[0015] A tooling apparatus devised in accordance with a preferred
embodiment of the present invention may be use to assemble
precursor assemblies. Preferred embodiments of the tooling
apparatus include a physical form used to impose a preselected
distance between the edges of the flex circuit, which in various
embodiments comprises a flex aligner that limits the lateral
placement of the edges of the flex circuit along upper surface of
the CSP.
[0016] The present invention may be employed to advantage in
numerous configurations and combinations of CSPs in modules
provided for high-density memories, high capacity computing, and
other applications.
[0017] The present invention also provides methods for constructing
stacked circuit modules and precursor assemblies with flexible
circuitry. Using preferred methods of the present invention, a
single set of flexible circuitry, whether articulated as one or two
flex circuits, may be employed with CSP devices of a variety of
configurations.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0018] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present
invention.
[0019] FIG. 2 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present
invention.
[0020] FIG. 3 depicts, in enlarged view, the area marked "A" in
FIG. 2.
[0021] FIG. 4 is an enlarged detail of an exemplar connection in a
preferred embodiment of the present invention.
[0022] FIG. 5 is an enlarged depiction of an exemplar area around a
lower flex contact in a preferred embodiment of the present
invention.
[0023] FIG. 6 depicts a first outer surface layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0024] FIG. 7 depicts a first outer surface layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0025] FIG. 8 depicts a first conductive layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0026] FIG. 9 illustrates a first conductive layer of a flex
circuit employed in a preferred embodiment of the present
invention.
[0027] FIG. 10 depicts an intermediate layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0028] FIG. 11 depicts an intermediate layer of a right side flex
circuit employed in a preferred embodiment of the present
invention.
[0029] FIG. 12 depicts a second conductive layer of a flex circuit
of a preferred embodiment of the present invention.
[0030] FIG. 13 depicts a second conductive layer of a flex circuit
of a preferred embodiment of the present invention.
[0031] FIG. 14 depicts a second outer layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0032] FIG. 15 reflects a second outer layer of a flex circuit
employed in a preferred embodiment of the present invention.
[0033] FIG. 16 depicts an alternative preferred embodiment of the
present invention.
[0034] FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA
packages.
[0035] FIG. 18 illustrates the pinout of a module 10 in an
alternative preferred embodiment of the invention.
[0036] FIG. 19 illustrates the pinout of a module 10 in an
alternative embodiment of the invention.
[0037] FIG. 20 depicts the pinout of an exemplar CSP employed in a
preferred embodiment of the invention.
[0038] FIG. 21 depicts a second conductive layer of a flex circuit
employed in an alternative preferred embodiment of the present
invention.
[0039] FIG. 22 depicts a second conductive layer of a flex circuit
employed in an alternative preferred embodiment of the present
invention.
[0040] FIG. 23 is an elevation view of a precursor assembly devised
in accordance with a preferred embodiment of the present invention
comprising stiffeners.
[0041] FIG. 23A depicts, in enlarged view, the area marked "23A" in
FIG. 23.
[0042] FIG. 24 is a plan view of stiffener stock devised in
accordance with a preferred embodiment of the present
invention.
[0043] FIG. 25 depicts, in enlarged view, the area marked "25" in
FIG. 24.
[0044] FIG. 26 is a perspective view of a panel or strip comprising
flex circuits devised in accordance with a preferred embodiment of
the present invention with stiffener stock attached.
[0045] FIG. 27 is a plan view of a panel or strip comprising flex
circuits devised in accordance with a preferred embodiment of the
present invention with stiffener stock attached.
[0046] FIG. 28 depicts, in enlarged view, the area marked "28" in
FIG. 24.
[0047] FIG. 29 depicts a CSP placed on a flex circuit in accordance
with a preferred embodiment of the present invention.
[0048] FIG. 30 presents another depiction of a CSP placed on a flex
circuit in accordance with a preferred embodiment of the present
invention.
[0049] FIG. 31 depicts two flex circuit edges in an arrangement
according to a preferred embodiment of the present invention.
[0050] FIG. 32 depicts two flex edges in accordance with an
alternative preferred embodiment of the present invention.
[0051] FIG. 33 is a plan view from below of a precursor assembly
devised in accordance with a preferred embodiment of the present
invention.
[0052] FIG. 34 is an elevation view of a stacked circuit module
devised in accordance with a preferred embodiment of the present
invention.
[0053] FIG. 35 is an elevation view of a stacked circuit module
devised in accordance with another preferred embodiment of the
present invention.
[0054] FIG. 36 is a perspective view from below of a stacked
circuit module devised in accordance with a preferred embodiment of
the present invention.
[0055] FIG. 37 is a perspective view from above of a stacked
circuit module devised in accordance with a preferred embodiment of
the present invention.
[0056] FIG. 38 is an elevation view of a stacked circuit module
devised in accordance with another preferred embodiment of the
present invention.
[0057] FIG. 39 depicts a tooling apparatus devised in accordance
with a preferred embodiment of the present invention.
[0058] FIG. 40 depicts an enlarged depiction of the area marked
"40" in FIG. 39.
[0059] FIG. 41 illustrates a tooling apparatus in accordance with a
preferred embodiment of the present invention.
[0060] FIG. 42 illustrates another step in devising an assembly in
accordance with a preferred embodiment of the present
invention.
[0061] FIG. 43 depicts another step in devising an assembly in
accordance with a preferred embodiment of the present
invention.
[0062] FIG. 44 depicts a tooling apparatus devised in accordance
with another preferred embodiment of the present invention, and
illustrates a step in accordance with another preferred embodiment
of the present invention.
[0063] FIG. 45 illustrates another step in devising an assembly in
accordance with another preferred embodiment of the present
invention.
[0064] FIG. 46 depicts another step in devising an assembly in
accordance with another preferred embodiment of the present
invention.
[0065] FIG. 47 illustrates another step in devising an assembly in
accordance with another preferred embodiment of the present
invention.
[0066] FIG. 48 depicts another step in devising an assembly in
accordance with another preferred embodiment of the present
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0067] FIG. 1 is an elevation view of module 10 devised in
accordance with a preferred embodiment of the present invention.
Module 10 is comprised of upper CSP 12 and lower CSP 14. Each of
CSPs 12 and 14 have an upper surface 16 and a lower surface 18 and
opposite lateral sides 20 and 22.
[0068] The invention is used with CSP packages of a variety of
types and configurations such as, for example, those that are
die-sized, as well those that are near chip-scale as well as the
variety of ball grid array packages known in the art. Collectively,
these will be known herein as chip scale packaged integrated
circuits (CSPs) and preferred embodiments will be described in
terms of CSPs, but the particular configurations used in the
explanatory figures are not, however, to be construed as limiting.
For example, the elevation views of FIGS. 1 and 2 are depicted with
CSPs of a particular profile known to those in the art, but it
should be understood that the figures are exemplary only. Later
figures show embodiments of the invention that employ CSPs of other
configurations as an example of one other of the many alternative
CSP configurations with which the invention may be employed. The
invention may be employed to advantage in the wide range of CSP
configurations available in the art where an array of connective
elements is available from at least one major surface. The
invention is advantageously employed with CSPs that contain memory
circuits but may be employed to advantage with logic, computing,
and other types of circuits where added capacity without
commensurate PWB or other board surface area consumption is
desired.
[0069] Typical CSPs, such as, for example, ball-grid-array ("BGA"),
micro-ball-grid array (".mu.BGA"), and fine-pitch ball grid array
("FBGA") packages have an array of connective contacts embodied,
for example, as leads, bumps, solder balls, or balls that extend
from lower surface 18 of a plastic casing in any of several
patterns and pitches. An external portion of the connective
contacts is often finished with a ball of solder. Shown in FIG. 1
are CSP contacts 24 along lower surfaces 18 of CSPs 12 and 14. CSP
contacts 24 provide connection to the integrated circuit within the
respective packages. Collectively, CSP contacts 24 comprise CSP
array 26 shown as to lower CSP 14 in the depicted particular
package configuration as CSP arrays 26.sub.1 and 26.sub.2 which
collectively comprise CSP array 26.
[0070] In FIG. 1, flex circuits ("flex", "flex circuits" or
"flexible circuit structures") 30 and 32 are shown partially
wrapped about lower CSP 14 with flex 30 partially wrapped over
lateral side 20 of lower CSP 14 and flex 32 partially wrapped about
lateral side 22 of lower CSP 14. Lateral sides 20 and 22 may be in
the character of sides or may, if the CSP is especially thin, be in
the character of an edge. Any flexible or conformable substrate
with a multiple internal layer connectivity capability may be used
as a flex circuit in the invention. The entire flex circuit may be
flexible or, as those of skill in the art will recognize, a PCB
structure made flexible in certain areas to allow conformability
around lower CSP 14 and rigid in other areas for planarity along
CSP surfaces may be employed as an alternative flex circuit in the
present invention. For example, structures known as rigid-flex may
be employed.
[0071] Portions of flex circuits 30 and 32 are fixed to upper
surface 16 of lower CSP 14 by adhesive 34 which is shown as a tape
adhesive, but may be a liquid adhesive or may be placed in discrete
locations across the package. Preferably, adhesive 34 is thermally
conductive. Adhesives that include a flux are used to advantage in
assembly of module 10. Layer 34 may also be a thermally conductive
medium to encourage heat flow between the CSPs of module 10.
[0072] Flex circuits 30 and 32 are multi-layer flexible circuit
structures that have at least two conductive layers. Preferably,
the conductive layers are metal such as alloy 110. The use of
plural conductive layers provides advantages as will be seen and
the creation of a distributed capacitance across module 10 intended
to reduce noise or bounce effects that can, particularly at higher
frequencies, degrade signal integrity, as those of skill in the art
will recognize. Module 10 of FIG. 1 has module contacts 36
collectively identified as module array 38.
[0073] FIG. 2 shows a module 10 devised in accordance with a
preferred embodiment of the invention. FIG. 2 illustrates use of a
conformal media 40 provided in a preferred embodiment to assist in
creating conformality of structural areas of module 10. Planarity
of the module is improved by conformal media 40. Preferably,
conformal media 40 is thermally conductive. In alternative
embodiments, thermal spreaders or a thermal medium may be placed as
shown by reference 41. Identified in FIG. 2 are upper flex contacts
42 and lower flex contacts 44 that are at one of the conductive
layers of flex circuits 30 and 32. Upper flex contacts 42 and lower
flex contacts 44 are conductive material and, preferably, are solid
metal. Lower flex contacts 44 are collectively lower flex contact
array 46. Upper flex contacts 42 are collectively upper flex
contact array 48. Only some of upper flex contacts 42 and lower
flex contacts 44 are identified in FIG. 2 to preserve clarity of
the view. It should be understood that each of flex circuits 30 and
32 have both upper flex contacts 42 and lower flex contacts 44.
Lower flex contacts 44 are employed with lower CSP 14 and upper
flex contacts 42 are employed with upper CSP 12. FIG. 2 has an area
marked "A" that is subsequently shown in enlarged depiction in FIG.
3.
[0074] FIG. 3 depicts in enlarged view, the area marked "A" in FIG.
2. FIG. 3 illustrates the connection between example CSP contact 24
and module contact 36 through lower flex contact 44 to illustrate
the solid metal path from lower CSP 14 to module contact 36 and,
therefore, to an application PWB to which module is connectable. As
those of skill in the art will understand, heat transference from
module 10 is thereby encouraged.
[0075] With continuing reference to FIG. 3, CSP contact 24 and
module contact 36 together offset module 10 from an application
platform such as a PWB. The combined heights of CSP contact 24 and
module contact 36 provide a moment arm longer than the height of a
single CSP contact 24 alone. This provides a longer moment arm
through which temperature-gradient-over-time stresses (such as
typified by temp cycle), can be distributed.
[0076] Flex 30 is shown in FIG. 3 to be comprised of multiple
layers. Flex 30 has a first outer surface 50 and a second outer
surface 52. Flex circuit 30 has at least two conductive layers
interior to first and second outer surfaces 50 and 52. There may be
more than two conductive layers in flex 30 and flex 32. In the
depicted preferred embodiment, first conductive layer 54 and second
conductive layer 58 are interior to first and second outer surfaces
50 and 52. Intermediate layer 56 lies between first conductive
layer 54 and second conductive layer 58. There may be more than one
intermediate layer, but one intermediate layer of polyimide is
preferred.
[0077] As depicted in FIG. 3 and seen in more detail in later
figures, lower flex contact 44 is preferably comprised from metal
at the level of second conductive layer 58 interior to second outer
surface 52. Lower flex contact 44 is solid metal in a preferred
embodiment and is comprised of metal alloy such as alloy 110. This
results in a solid metal pathway from lower CSP 14 to an
application board thereby providing a significant thermal pathway
for dissipation of heat generated in module 10.
[0078] FIG. 4 is an enlarged detail of an exemplar connection
between example CSP contact 24 and example module contact 36
through lower flex contact 44 to illustrate the solid metal path
from lower CSP 14 to module contact 36 and, therefore, to an
application PWB to which module 10 is connectable. As shown in FIG.
4, lower flex contact 44 is at second conductive layer 58 that is
interior to first and second outer surface layers 50 and 52
respectively, of flex circuit 30.
[0079] FIG. 5 is an enlarged depiction of an exemplar area around a
lower flex contact 44 in a preferred embodiment. Windows 60 and 62
are opened in first and second outer surface layers 50 and 52
respectively, to provide access to particular lower flex contacts
44 residing at the level of second conductive layer 58 in the flex.
The upper flex contacts 42 are contacted by CSP contacts 24 of
upper CSP 12. Lower flex contacts 44 and upper flex contacts 42 are
particular areas of conductive material (preferably metal such as
alloy 110) at the level of second conductive layer 58 in the flex.
Upper flex contacts 42 and lower flex contacts 44 are demarked in
second conductive layer 58 and, as will be shown in subsequent
Figs., may be connected to or isolated from the conductive plane of
second conductive layer 58. Demarking a lower flex contact 44 from
second conductive layer 58 is represented in FIG. 5 by demarcation
gap 63 shown at second conductive layer 58. Where an upper or lower
flex contact 42 or 44 is not completely isolated from second
conductive layer 58, demarcation gaps do not extend completely
around the flex contact as shown, for example, by lower flex
contacts 44C in later FIG. 12. CSP contacts 24 of lower CSP 14 pass
through a window 60 opened through first outer surface layer 50,
first conductive layer 54, and intermediate layer 56, to contact an
appropriate lower flex contact 44. Window 62 is opened through
second outer surface layer 52 through which module contacts 36 pass
to contact the appropriate lower flex contact 44.
[0080] Respective ones of CSP contacts 24 of upper CSP 12 and lower
CSP 14 are connected at the second conductive layer 58 level in
flex circuits 30 and 32 to interconnect appropriate signal and
voltage contacts of the two CSPs. Respective CSP contacts 24 of
upper CSP 12 and lower CSP 14 that convey ground (VSS) signals are
connected at the first conductive layer 54 level in flex circuits
30 and 32 by vias that pass through intermediate layer 56 to
connect the levels as will subsequently be described in further
detail. Thereby, CSPs 12 and 14 are connected. Consequently, when
flex circuits 30 and 32 are in place about lower CSP 14, respective
CSP contacts 24 of each of upper and lower CSPs 12 and 14 are in
contact with upper and lower flex contacts 42 and 44, respectively.
Selected ones of upper flex contacts 42 and lower flex contacts 44
are connected. Consequently, by being in contact with lower flex
contacts 44, module contacts 36 are in contact with both upper and
lower CSPs 12 and 14.
[0081] In a preferred embodiment, module contacts 36 pass through
windows 62 opened in second outer layer 52 to contact lower flex
contacts 44. In some embodiments, as will be later shown, module 10
will exhibit a module contact array 38 that has a greater number of
contacts than do the constituent CSPs of module 10. In such
embodiments, some of module contacts 36 may contact lower flex
contacts 44 that do not contact one of the CSP contacts 24 of lower
CSP 14 but are connected to CSP contacts 24 of upper CSP 12. This
allows module 10 to express a wider datapath than that expressed by
the constituent CSPs 12 or 14. A module contact 36 may also be in
contact with a lower flex contact 44 to provide a location through
which different levels of CSPs in the module may be enabled when no
unused CSP contacts are available or convenient for that
purpose.
[0082] In a preferred embodiment, first conductive layer 54 is
employed as a ground plane, while second conductive layer 58
provides the functions of being a signal conduction layer and a
voltage conduction layer. Those of skill will note that roles of
the first and second conductive layers may be reversed with
attendant changes in windowing and use of commensurate
interconnections.
[0083] As those of skill will recognize, interconnection of
respective voltage CSP contacts 24 of upper and lower CSPs 12 and
14 will provide a thermal path between upper and lower CSPs to
assist in moderation of thermal gradients through module 10. Such
flattening of the thermal gradient curve across module 10 is
further encouraged by connection of common ground CSP contacts 24
of upper and lower CSPs 12 and 14 through first conductive layer
54. Those of skill will notice that between first and second
conductive layers 54 and 58 there is at least one intermediate
layer 56 that, in a preferred embodiment, is a polyimide. Placement
of such an intermediate layer between ground-conductive first
conductive layer 54 and signal/voltage conductive second conductive
layer 58 provides, in the combination, a distributed capacitance
that assists in mitigation of ground bounce phenomena to improve
high frequency performance of module 10.
[0084] In a preferred embodiment, FIG. 6 depicts first outer
surface layer 50 of flex 30 (i.e., left side of FIG. 1). The view
is from above the flex looking down into flex 30 from the
perspective of first conductive layer 54. Throughout the Figs., the
location reference "B" is to orient views of layers of flex 30 to
those of flex 32 as well as across layers. Windows 60 are opened
through first outer surface layer 50, first conductive layer 54,
and intermediate layer 56. CSP contacts 24 of lower CSP 14 pass
through windows 60 of first outer surface layer 50, first
conductive layer 54, and intermediate layer 56 to reach the level
of second conductive layer 58 of flex 30. At second conductive
layer 58, selected CSP contacts 24 of lower CSP 14 make contact
with selected lower flex contacts 44. Lower flex contacts 44
provide several types of connection in a preferred embodiment as
will be explained with reference to later FIG. 12. When module 10
is assembled, a portion of flex 30 will be wrapped about lateral
side 20 of lower CSP 14 to place edge 62 above upper surface 16 of
lower CSP 14.
[0085] In a preferred embodiment, FIG. 7 depicts first outer
surface layer 50 of flex 32 (i.e., right side of FIG. 1). The view
is from above the flex looking down into flex 32 from the
perspective of first conductive layer 54. The location reference
"B" relatively orients the views of FIGS. 6 and 7. The views of
FIGS. 6 and 7 may be understood together with the reference marks
"B" of each view being placed nearer each other than to any other
corner of the other view of the pair of views of the same layer. As
shown in FIG. 7, windows 60 are opened through first outer surface
layer 50, first conductive layer 54 and intermediate layer 56. CSP
contacts 24 of lower CSP 14 pass through windows 60 of first outer
surface layer 50, first conductive layer 54, and intermediate layer
56 to reach the level of second conductive layer 58 of flex 30. At
second conductive layer 58, selected CSP contacts 24 of lower CSP
14 make contact with lower flex contacts 44. Lower flex contacts 44
provide several types of connection in a preferred embodiment as
will be explained with reference to later FIG. 12. When module 10
is assembled, a portion of flex 32 will be wrapped about lateral
side 22 of lower CSP 14 to place edge 64 above upper surface 16 of
lower CSP 14.
[0086] FIG. 8 depicts first conductive layer 54 of flex 30. Windows
60 continue the opened orifice in flex 30 through which CSP
contacts 24 of lower CSP 14 pass to reach second conductive layer
58 and, therefore, selected lower flex contacts 44 at the level of
second conductive layer 58.
[0087] Those of skill will recognize that as flex 30 is partially
wrapped about lateral side 20 of lower CSP 14, first conductive
layer 54 becomes, on the part of flex 30 disposed above upper
surface 16 of lower CSP 14, the lower-most conductive layer of flex
30 from the perspective of upper CSP 12. In the depicted
embodiment, those CSP contacts 24 of upper CSP 12 that provide
ground (VSS) connections are connected to the first conductive
layer 54. First conductive layer 54 lies beneath, however, second
conductive layer 58 in that part of flex 30 that is wrapped above
lower CSP 14. Consequently, some means must be provided for
connection of the upper flex contact 42 to which ground-conveying
CSP contacts 24 of upper CSP 12 are connected and first conductive
layer 54. Consequently, in the depicted preferred embodiment, those
upper flex contacts 42 that are in contact with ground-conveying
CSP contacts 24 of upper CSP 12 have vias that route through
intermediate layer 56 to reach first conductive layer 54. The sites
where those vias meet first conductive layer 54 are identified in
FIG. 8 as vias 66. These vias may be "on-pad" or coincident with
the flex contact 42 to which they are connected. Those of skill
will note a match between the vias 66 identified in FIG. 8 and vias
66 identified in the later view of second conductive layer 58 of
the depicted preferred embodiment. In a preferred embodiment, vias
66 in coincident locations from Fig. to Fig. are one via. For
clarity of the view, depicted vias in the figures are shown larger
in diameter than in manufactured embodiments. As those of skill
will recognize, the connection between conductive layers provided
by vias (on or off pad) may be provided any of several well-known
techniques such as plated holes or solid lines or wires and need
not literally be vias.
[0088] Also shown in FIG. 8 are off-pad vias 74. Off-pad vias 74
are disposed on first conductive layer 54 at locations near, but
not coincident with selected ones of windows 60. Unlike vias 66
that connect selected ones of upper flex contacts 42 to first
conductive layer 54, off-pad vias 74 connect selected ones of lower
flex contacts 44 to first conductive layer 54. In the vicinity of
upper flex contacts 42, second conductive layer 58 is between the
CSP connected to module 10 by the upper flex contacts 42 (i.e.,
upper CSP 12) and first conductive layer 54. Consequently, vias
between ground-conveying upper flex contacts 42 and first
conductive layer 54 may be directly attached to the selected upper
flex contacts 42 through which ground signals are conveyed. In
contrast, in the vicinity of lower flex contacts 44, first
conductive layer 54 is between the CSP connected to module 10 by
the lower flex contacts 44 (i.e., lower CSP 14) and second
conductive layer 58. Consequently, vias between ground-conveying
lower flex contacts 44 and first conductive layer 54 are offset
from the selected lower flex contacts 44 by off-pad vias 74 shown
in offset locations.
[0089] FIG. 9 illustrates first conductive layer 54 of flex 32. The
location reference marks "B" are employed to relatively orient
FIGS. 8 and 9. Windows 60, vias 66 and off-pad vias 74 are
identified in FIG. 9. Also shown in FIG. 9, are enable vias 68 and
70 and enable trace 72. Enable via 70 is connected off-pad to a
selected lower flex contact 44 that corresponds, in this preferred
embodiment, to an unused CSP contact 24 of lower CSP 14 (i.e., a
N/C). A module contact 36 at that site conveys an enable signal
(C/S) for upper CSP 12 through the selected lower flex contact 44
(which is at the level of second conductive layer 58) to off-pad
enable via 70 that conveys the enable signal to first conductive
layer 54 and thereby to enable trace 72. Enable trace 72 further
conveys the enable signal to enable via 68 which extends through
intermediate layer 56 to selected upper flex contact 42 at the
level of second conductive layer 58 where contact is made with the
C/S pin of upper CSP 12. Thus, upper and lower CSPs 12 and 14 may
be independently enabled.
[0090] FIG. 10 depicts intermediate layer 56 of flex 30. Windows 60
are shown opened in intermediate surface 56. CSP contacts 24 of
lower CSP 14 pass through windows 60 in intermediate layer 58 to
reach lower flex contacts 44 at the level of second conductive
layer 58. Those of skill will notice that, in the depicted
preferred embodiment, windows 60 narrow in diameter from their
manifestation in first outer layer 50. Vias 66, off-pad vias 74,
and enable vias 68 and 70 pass through intermediate layer 56
connecting selected conductive areas at the level of first and
second conductive layers 54 and 58, respectively. FIG. 11 depicts
intermediate layer 56 of flex 32 showing windows 60, vias 66,
off-pad vias 74, and enable vias 68 and 70 passing through
intermediate layer 56.
[0091] FIG. 12 depicts second conductive layer 58 of flex 30 of a
preferred embodiment of the present invention. Depicted are various
types of upper flex contacts 42, various types of lower flex
contacts 44, signal traces 76, and VDD plane 78 as well as
previously described vias 66 and off-pad vias 74. Throughout FIGS.
12 and 13, only exemplars of particular features are identified to
preserve clarity of the view. Flex contacts 44A are connected to
corresponding selected upper flex contacts 42A with signal traces
76. To enhance the clarity of the view, only exemplar individual
flex contacts 44A and 42A are literally identified in FIG. 12. As
shown, in this preferred embodiment, signal traces 76 exhibit path
routes determined to provide substantially equal signal lengths
between corresponding flex contacts 42A and 44A. As shown, traces
76 are separated from the larger surface area of second conductive
layer 58 that is identified as VDD plane 78. VDD plane 78 may be in
one or more delineated sections but, preferably is one section.
Lower flex contacts 44C provide connection to VDD plane 78. In a
preferred embodiment, upper flex contacts 42C and lower flex
contacts 44C connect upper CSP 12 and lower CSP 14, respectively,
to VDD plane 78. Lower flex contacts 44 that are connected to first
conductive layer 54 by off-pad vias 74 are identified as lower flex
contacts 44B. To enhance the clarity of the view, only exemplar
individual lower flex contacts 44B are literally identified in FIG.
12. Upper flex contacts 42 that are connected to first conductive
layer 54 by vias 66 are identified as upper flex contacts 42B.
[0092] FIG. 13 depicts second conductive layer 58 of right side
flex 32 of a preferred embodiment of the present invention.
Depicted are various types of upper flex contacts 42, various types
of lower flex contacts 44, signal traces 76, and VDD plane 78 as
well as previously described vias 66, off-pad vias 74, and enable
vias 70 and 68. FIG. 13 illustrates upper flex contacts 42A
connected by traces 76 to lower flex contacts 44A. VDD plane 78
provides a voltage plane at the level of second conductive layer
58. Lower flex contacts 44C and upper flex contacts 42C connect
lower CSP 14 and upper CSP 12, respectively, to VDD plane 78. Lower
flex contact 44D is shown with enable via 70 described earlier.
Corresponding upper flex contact 42D is connected to lower flex
contact 44D through enable vias 70 and 68 that are connected to
each other through earlier described enable trace 72 at the first
conductive layer 54 level of flex 32.
[0093] FIG. 14 depicts second outer layer 52 of flex 30. Windows 62
are identified. Those of skill will recognize that module contacts
36 pass through windows 62 to contact appropriate lower flex
contacts 44. When flex 30 is partially wrapped about lateral side
20 of lower CSP 14, a portion of second outer layer 52 becomes the
upper-most layer of flex 30 from the perspective of upper CSP 12.
CSP contacts 24 of upper CSP 12 pass through windows 64 to reach
second conductive layer 58 and make contact with appropriate ones
of upper flex contacts 42 located at that level. FIG. 15 reflects
second outer layer 52 of flex 32 and exhibits windows 64 and 62.
Module contacts 36 pass through windows 62 to contact appropriate
lower flex contacts 44. CSP contacts 24 of upper CSP 12 pass
through windows 64 to reach second conductive layer 58 and make
contact with appropriate ones of upper flex contacts 42 located at
that level.
[0094] FIG. 16 depicts an alternative preferred embodiment of the
present invention showing module 10. Those of skill will recognize
that the embodiment depicted in FIG. 16 differs from that in FIG. 2
by the presence of module contacts 36E. Module contacts 36E supply
a part of the datapath of module 10 and may provide a facility for
differential enablement of the constituent CSPs. A module contact
36E not employed in wide datapath provision may provide a contact
point to supply an enable signal to differentially enable upper CSP
12 or lower CSP 14.
[0095] In a wide datapath module 10, the data paths of the
constituent upper CSP 12 and lower CSP 14 are combined to provide a
module 10 that expresses a module datapath that is twice the width
of the datapaths of the constituent CSPs in a two-high module 10.
The preferred method of combination is concatenation, but other
combinations may be employed to combine the datapaths of CSPs 12
and 14 on the array of module contacts 36 and 36E.
[0096] As an example, FIGS. 17, 18, and 19 are provided to
illustrate using added module contacts 36E in alternative
embodiments of the present invention to provide wider datapaths for
module 10 than are present in constituent CSPs 12 and 14. FIG. 17
illustrates a JEDEC pinout for DDR-II FBGA packages. FIG. 18
illustrates the pinout provided by module contacts 36 and 36E of a
module 10 expressing an 8-bit wide datapath. Module 10 is devised
in accordance with the present invention and is, in the exemplar
embodiment, comprised of an upper CSP 12 and lower CSP 14 that are
DDR-II-compliant in timing, but each of which are only 4 bits wide
in datapath. As will be recognized, the module 10 mapped in FIG. 18
expresses an 8-bit wide datapath. For example, FIG. 18 depicts DQ
pins differentiated in source between upper CSP 12 ("top") and
lower CSP 14 ("bot") to aggregate to 8-bits. FIG. 19 illustrates
the pinout provided by module contacts 36 and 36E of module 10
expressing a 16-bit wide datapath. Module 10 is devised in
accordance with the present invention and is, in this exemplar
embodiment, comprised of an upper CSP 12 and lower CSP 14 that are
DDR-II-compliant in timing, but each of which are only 8-bits wide
in datapath. Those of skill in the art will recognize that the wide
datapath embodiment may be employed with any of a variety of CSPs
available in the field and such CSPs need not be DDR compliant.
[0097] FIG. 20 illustrates a typical pinout of a memory circuit
provided as a CSP and useable in the present invention. Individual
array positions are identified by the JEDEC convention of numbered
columns and alphabetic rows. The central area (e.g., A3-A6; B3-B6;
etc.) is unpopulated. CSP contacts 24 are present at the locations
that are identified by alpha-numeric identifiers such as, for
example, A3, shown as an example CSP contact 24. FIG. 21 depicts
second metal layer 58 of flex 30 in an alternative embodiment of
the invention in which module 10 expresses a datapath wider than
that expressed by either of the constituent CSPs 12 and 14. Lower
flex contacts 44E are not contacted by CSP contacts 24 of lower CSP
14, but are contacted by module contacts 36E to provide, with
selected module contacts 36, a datapath for module 10 that is
2n-bits in width where the datapaths of CSPs 12 and 14 have a width
of n-bits. As shown in FIG. 21, lower flex contacts 44E are
connected to upper flex contacts 42E. As shown in earlier FIG. 14,
windows 62 pass through second outer layer 52. In the alternative
preferred embodiment for which second conductive layer 58 is shown
in FIG. 21, module contacts 36 and 36E pass through windows 62 in
second outer layer 52 of flex circuit 30, to contact appropriate
lower flex contacts 44.
[0098] FIG. 22 illustrates second metal layer 58 of flex 32 in an
alternative embodiment of the invention in which module 10
expresses a datapath wider than that expressed by either of the
constituent CSPs 12 and 14. Lower flex contacts 44E are not
contacted by CSP contacts 24 of lower CSP 14, but are contacted by
module contacts 36E to provide, with selected module contacts 36, a
datapath for module 10 that is 2n-bits in width where the datapaths
of CSPs 12 and 14 have a width of n-bits. As shown in FIG. 22,
lower flex contacts 44E are connected to upper flex contacts 42E.
As shown in earlier FIG. 14, windows 62 pass through second outer
layer 52. In the alternative preferred embodiment for which second
conductive layer 58 is shown in FIG. 22, module contacts 36 pass
through windows 62 in second outer layer 52 of flex circuit 32, to
contact appropriate lower flex contacts 44.
[0099] In particular, in the embodiment depicted in FIGS. 21 and
22, module contacts 36E contact flex contacts 44E and 44EE. Those
of skill will recognize that lower flex contacts 44E are, in the
depicted embodiment, eight (8) in number and that there is another
lower flex contacts identified by reference 44EE shown on FIG. 21.
Lower flex contact 44EE is contacted by one of the module contacts
36E to provide differential enablement between upper and lower
CSPs. Those of skill will recognize that lower flex contacts 44F
are connected to corresponding upper flex contacts 42E. CSP
contacts 24 of upper CSP 12 that convey data are in contact with
upper flex contacts 42E. Consequently, the datapaths of both upper
CSP 12 and lower CSP 14 are combined to provide a wide datapath on
module 10. With the depicted connections of FIGS. 21 and 22, lower
flex contacts 44E of flex circuits 30 and 32 convey to module
contacts 36E, the datapath of upper CSP 12, while other lower flex
contacts 44 convey the datapath of lower CSP 14 to module contacts
36 to provide module 10 with a module datapath that is the
combination of the datapath of upper CSP 12 and lower CSP 14. In
the depicted particular embodiment of FIGS. 21 and 22, module 10
expresses a 16-bit datapath and CSP 12 and CSP 14 each express an
8-bit datapath.
[0100] FIGS. 23-33 depict aspects of alternative preferred
embodiments of a precursor assembly for use as a component of a
stacked circuit module. FIGS. 23-33 depict aspects of stiffeners
comprised in exemplary precursor assemblies and additional aspects
of other components used in manufacturing such precursor
assemblies. FIG. 23 is an elevation view of an end of precursor
assembly 105 comprising CSP 114 having an upper surface 116, a
lower surface 118, and opposite lateral sides 120 and 122. Upon
assembly of a stacked circuit module 110 using precursor assembly
105 of this embodiment, CSP 114 will become a lower CSP of a
stacked circuit module 110.
[0101] Among the various CSPs that are useful for CSP 114 are the
types that include at least one integrated circuit or semiconductor
chip surrounded by a package body 127 with a lateral extent L
defined by the opposite lateral edges or sides 120 and 122. The
package body surrounding the integrated circuit(s) or semiconductor
chip(s) need not be plastic, but a large majority of package bodies
in CSP technologies are plastic. The package body need not surround
the integrated circuit(s) or semiconductor chip(s) completely,
leaving one or more sides, edges, surfaces, or other regions of the
integrated circuit(s) or semiconductor chip(s) exposed, but a large
majority of package bodies in CSP technologies completely encase
the integrated circuit(s) or semiconductor chip(s) or leave only
the terminals on integrated circuit or semiconductor chip active
face(s) exposed. The invention may also be used with those CSP-like
packages that exhibit bare die connectives on one major
surface.
[0102] Those of skill will realize that various embodiments of the
present invention may be devised to create modules and precursor
assemblies with different size CSPs and that the constituent CSPs
may be of different types within the same stacked circuit module
110. The disclosed structures and methods allow a single set of
flex circuitry, whether comprised of one or two flex circuits, to
be employed with a variety of package body sizes of CSPs. For
example, one of the constituent CSPs of an example stacked circuit
module 110 may be a typical CSP having lateral edges 120 and 122
that have an appreciable height to present a "side" while other
constituent CSPs of the same stacked circuit module 110 may be
devised in packages that have lateral edges 120 and 122 that are
more in the character of an edge rather than a side having
appreciable height. All devices such as those discussed above and
similar devices are included within the meaning of the term CSP,
which term should be broadly considered in the context of this
application.
[0103] The embodiment of a precursor assembly illustrated in FIG.
23 uses substantially planar stiffeners 139 that are initially
disposed on a flex circuit 130 and affixed thereto with adhesive
134. When precursor assembly 105 is assembled, stiffeners 139 are
disposed along a surface of CSP 114 even if literally separated
from that surface, such as by adhesive 135, for example. In this
embodiment, stiffeners 139 are attached to CSP 114 with adhesive
135. CSP contacts 124, regardless of configuration, generally will
define a mounting height for CSP, such as mounting height H
depicted in FIG. 23A for CSP contacts comprising solder balls.
Preferably, thickness T of stiffeners 139 is less than mounting
height H, for example as depicted in FIG. 23A, with the combined
thickness of stiffener 139 and adhesives 134 and 135 approximately
equal mounting height H so as to dispose the lower portion of the
flex circuit 130 approximately parallel to the lower surface 118 of
CSP 114. In preferred embodiments, stiffeners 139 also are
configured to provide lateral clearance for the CSP arrays 126
comprising various CSP contacts 124. In the exemplar depicted in
FIG. 23, for example, CSP contacts 124 are at least partially
disposed within the volume 140 between stiffeners 139.
[0104] Stiffeners 139 may take several useful configurations, but
in preferred embodiments herein, stiffeners 139 are substantially
planar. A preferred embodiment is shown using stiffeners 139
disposed within the lateral extent L of CSP 114. Other embodiments
may have stiffeners 139 disposed at least partially outside lateral
extent L of CSP 114, one example of which is the embodiments
further discussed below in connection with FIG. 38.
[0105] In preferred embodiments, flex circuit 130 has upper
portions 130U that terminate in edges 170A and 170B which are
separated by gap G above the upper surface 116 of CSP 114. In some
embodiments, gap G is preselected and imposed when precursor
assembly 105 is made. Upper portions 130U of flex circuit 130 are
disposed along the upper surface 116 of CSP 114 even if literally
separated from that surface, such as by adhesive 171, for example.
In such configurations, flex circuit 130 has a folded portion
131.
[0106] FIG. 23 depicts precursor assembly 105 with module contacts
136 through which the precursor assembly 105 may connect to an
application environment or to another precursor assembly 105, for
example, as shown in FIG. 34. In the illustrated embodiment, the
module contacts 136 are deployed in a module contact array 138, but
other configurations of module contacts may be used. Those of skill
will recognize that module contacts 136 in the form of the depicted
solder balls are not required to connect a stacked circuit module
110 to an application environment or to connect a precursor
assembly 105 to another precursor assembly 105, and that other
connective strategies may be employed such as, for example, direct
pad to pad connection schemes or connective structures other than
solder balls.
[0107] A preferred method for practicing the invention produces
precursor assemblies 105 in batches of six. The stiffener(s) and
flex circuit(s) for a particular precursor assembly are provided in
aggregation with other stiffeners and flex circuits, respectively,
for other precursor assemblies. Those of skill will recognize,
however, that the inventive methods described herein can be used
with other batch sizes or with continuous production techniques,
for example those using known reel and tape formats. FIG. 24
depicts an exemplar strip or panel of stiffener stock 237 that may
be employed in some preferred embodiments of the present invention,
and FIG. 25 depicts an enlarged depiction of the area marked "25"
in FIG. 24. The illustrated strip of stiffener stock 237 includes
twelve stiffeners 139 retained by tabs 238 in configuration for
deployment in six precursor assemblies 105. The stiffener material
has cutouts comprising tooling holes 239 and windows 240. Windows
240 are configured to accommodate CSP arrays 126 comprising CSP
contacts 124 of CSP 114. At each longitudinal end of the stiffener
stock 237 depicted, tabs 238A and tooling holes 239A are disposed
generally as half of a tab 238 and a tooling hole 239 as disposed
between adjacent windows 240.
[0108] Stiffener stock 237 as depicted in the embodiment of FIG. 24
comprises a polymer having thermal properties adequate for the
various temperatures at which various solder reflow and other
attachment operations may occur in the production of precursor
assemblies 105 and stacked circuit modules 110 and in the
deployment of stacked circuit modules 110 in an application
environment. In a preferred embodiment, stiffener stock 237
comprises a single layer or multiple laminated layers of polyimide
film selected so that stiffeners 139 have mechanical properties
compatible with the mechanical properties of flex circuit 130, but
other materials that are compatible with the assembly processes may
be used such as resin polymer matrix composites, engineering
ceramics or ceramic fibers, graphite composites, or filled and
non-filled plastics known to those of skill in the art. Preferably,
compatibility of the mechanical properties of stiffeners 139 and
flex circuit 130 are selected to reduce to an acceptable extent any
warping and other deformations of precursor assembly 105 caused by
differential thermal expansion of stiffeners 139 and flex circuit
130. As those of skill will recognize, stiffener stock 237 also may
take other configurations and compositions and may, for example, be
devised in more than one piece and/or be devised of material that
is thermally conductive. In alternative embodiments, stiffener
stock 237 may comprise material of sufficient rigidity such as
stainless steels, aluminum, copper, or other metals or metal alloys
so that stiffeners 139 control the coplanarity of CSP 114 by
inhibiting warping.
[0109] FIGS. 26 and 27 depict perspective and plan views,
respectively, of stiffener stock 237 disposed on a panel or strip
230 comprising flex circuits 130. In the depicted embodiment, six
flex circuits 130 are configured side-by-side, with a portion of
each flex circuit 130 accessible through a respective window 240 of
stiffener stock 237, Strip 230 further comprises lateral edges 231
and strip edge portions 232. In a preferred embodiment, an adhesive
134 (shown earlier) is used to attach stiffener stock 237 and its
component stiffeners 139 and tabs 238 to strip or panel 230 and its
component flex circuits 130. Adhesive 134 in a preferred embodiment
comprises a dry film adhesive. Those of skill will recognize,
however, that adhesive 134 may be selectively applied to selected
portions of stiffener stock 237 or strip 230, or both, and that
other methods for attaching stiffeners 139 to flex circuits 130 may
be employed in accordance with various embodiments of the present
invention including, for example, laminate tape adhesive, liquid
adhesive, and ultrasonic or thermal bonding. Preferably, the
adhesive will be thermally conductive. In a preferred embodiment,
tooling holes 239 facilitate alignment of stiffener stock 237 and
strip 230, although alternative methods such as machine vision
aided pick & place may be employed.
[0110] FIG. 28 depicts an enlarged depiction of the area marked
"28" in FIG. 27. The depiction of FIG. 28 is centered on a site
where a CSP 114 will be disposed. When a CSP 114 is disposed,
selected CSP contacts 124 will be connected to respective ones of
flex contacts disposed in flex contact arrays. For simplicity, the
depiction of FIG. 28 shows through window 240 only selected ones of
flex contacts 144 of a selected flex contact array 146. Components
of stiffener stock 237 relevant to the illustrated site include
stiffeners 139, tabs 238, tooling holes 239, and window 240.
[0111] The portion of strip 230 depicted in FIG. 28 also
illustrates various features of flex circuit 130 of a preferred
embodiment. In the illustrated embodiment, a singulation opening
233 is disposed through strip 230 adjacent to each longitudinal end
of each stiffener 139. Additional singulation openings 234 are
disposed through strip 230 along strip edge portions 232 adjacent
to each lateral edge 231 of strip 230. Edges 170A and 170B of upper
portions 130U of flex circuit 130 are disposed along singulation
openings 234, with each upper portion 130U disposed between a
respective singulation opening 234 and a respective stiffener
139.
[0112] Strip 230 and the flex circuits 130 disposed thereon can be
configured with conductive components in a wide variety of ways.
For example, strip 230 and the flex circuits 130 disposed thereon
can be multi-layer flexible circuit structures, such as the
embodiment discussed above having a first conductive layer and a
second conductive layer that are interior to first and second outer
surfaces, with an intermediate layer disposed between the first
conductive layer and the second conductive layer. As those of skill
in the art will recognize, a single conductive layer or three or
more conductive layers can also be used, and typically the choice
will depend on the complexity of the circuit routing required.
Further, some embodiments may employ only one cover coat, such as
those instances in which a ground plane is exposed. Circuit traces
can be disposed in one or more conductive layers, and selected
conductive layers may contain only ground or voltage planes.
[0113] In one exemplar preferred embodiment useful for stacking
memory CSPs, conductive traces are disposed at one conductive layer
with a ground plane disposed an another conductive layer. In that
embodiment, a single outer surface is used leaving one of the
conductive layers exposed. All contact pads on the exposed
conductive layer are connected to the other conductive surface
through vias, using no conductive traces on the exposed conductive
layer. Connecting the contact pads directly through vias mitigates
solder wicking and reduces costs and thickness of the flex
circuitry.
[0114] The manufacture of strip 230 may employ various
electroplating steps that use current supplied from sprocket rails
engaging sprocket holes 235. Current for electroplating can be
routed along bussing through trim tabs 250, which are severed from
flex circuits 130 during singulation as discussed further below.
Electroplating bus paths also can converge at various connection
points of strip 230, which bussing connections can be severed
following electroplating by making de-bussing punches 251 as
illustrated in FIG. 28. As those of skill in the art will
recognize, however, other methods may be used to dispose conductive
material within and/or on strip 230. At each longitudinal end of
flex circuit 130 in a preferred embodiment, nonbussed portion 150
of flex circuit 130 is disposed alongside tab 238 and between
singulation openings 233 to provide additional clearance for
circuitry of flex circuit 130 during singulation, as discussed
further below.
[0115] FIG. 28 also depicts the various pattern recognition marks,
or "fiducials," used by automated assembly equipment during
manufacture of precursor assemblies 105. Preferably, fiducials are
metal defined, asymmetrically placed, and comprise a cross and a
square where practical. The preferred embodiment depicted has
global fiducials 260 defined by circular metal regions on the
surface of strip 230 and aligned with tooling holes 239. Additional
global fiducials are defined by metal regions in the form of a
square (fiducials 261) and a cross (fiducials 262). The global
fiducials are used as reference points during singulation of
precursor assemblies 105 or stacked circuit modules 110. Also
depicted are local fiducials defined by metal regions in the form
of a square (fiducials 161) and a cross (fiducials 162) defined in
a conductive layer of the flex circuit, which local fiducials are
used by automated equipment as a reference during the placement of
CSP 114 on flex circuit 130.
[0116] Although the description of the embodiment illustrated in
FIG. 28 is directed to features related to a single precursor
assembly 105 to be made using stiffener stock 237 and strip 230,
those of skill will recognize that the described features can be
replicated for other precursor assemblies 105 or that variations in
the described features can be employed for other precursor
assemblies 105.
[0117] Prior to placement of CSP 114 on flex circuit 130, in the
disclosed embodiment adhesive 135 is applied to the exposed upper
surface of stiffener 139. In a preferred embodiment, adhesive 135
comprises a liquid adhesive. Those of skill will recognize,
however, that adhesive 135 may be selectively applied to selected
portions of stiffener 139 and that other methods for attaching
stiffeners 139 to CSP 114 may be employed in various embodiments of
the present invention including, for example, laminate tape
adhesive and dry film adhesive. Preferably, the adhesive will be
thermally conductive.
[0118] Automated pick-and-place equipment know in the art is used
to dispose CSP 114 on flex circuit 130 in a preferred embodiment.
The pick-and-place equipment dips CSP contacts 124 in flux prior to
placement of CSP 114 on flex circuit 130. After placement of CSP
114 on flex circuit 130, heat is supplied during a first solder
reflow operation to produce a solder connection between CSP
contacts 124 and flex contacts 144. The combination of adhesive
134, stiffener 139, and adhesive 135 cooperate to maintain flex
circuit 130 and CSP 114 in proper position during the first solder
reflow operation.
[0119] After CSP 114 is soldered to flex circuit 130, upper
portions 130U of flex circuits 130 are separated from strip 230 by
upper flex cuts 174. FIG. 29 depicts the position of upper flex
cuts 174, and also shows the position of singulation cuts 175 made
later during singulation of precursor assemblies 105 or stacked
circuit modules 110 as discussed below. FIG. 30 depicts the
configuration of flex circuit 130, stiffeners 139, and CSP 114
following the making of upper flex cuts 174 as shown in FIG. 29,
with such depiction bounded to the left and right by the positions
where singulation cuts 175 will be made later in the assembly
process.
[0120] In the depicted embodiments, adhesive 171 is applied to the
upper surface 116 of CSP 114, to upper portions 130U of flex
circuit 130, or to both upper surface 116 and upper portions 130U.
In a preferred embodiment, adhesive 171 comprises a dry film
adhesive. Those of skill will recognize, however, that adhesive 171
may be selectively applied to selected portions of upper surface
116 or upper portions 130U, or both, and that other methods for
attaching the upper surfaces 118 to flex circuits 130 may be
employed in various embodiments of the present invention including,
for example, laminate tape adhesive and liquid adhesive.
Preferably, the adhesive will be thermally conductive.
[0121] As shown in FIGS. 23 and 31, in the disclosed embodiments,
upper portions 130U of flex circuit 130 are disposed along the
upper surface 116 of CSP 114 even if literally separated from that
surface, such as by adhesive 171, for example. Disposition of upper
portions 130U of flex circuit 130 along the upper surface 116 of
CSP 114 can be accomplished using a tooling apparatus 180 devised
in accordance with a preferred embodiment of the present invention,
as depicted in FIGS. 39-43 and discussed below. FIG. 31 depicts
flex circuit edges 170A and 170B in a proximal arrangement
according to a preferred embodiment of the present invention.
[0122] As exemplified by the embodiment illustrated in FIG. 31,
flex circuit 130 is configured for external electrical connection
of lower CSP 114. Referring to FIG. 31, upper sides 133 of upper
portions 130U of flex circuit 130 are depicted having upper flex
contacts or pads 142 disposed in a first upper flex contact array
148A and a second upper flex contract array 148B. As those of skill
will recognize, first upper flex contact array 148A and second
upper flex contract array 148B have been abstracted to illustrate
an exemplar set of upper flex contacts 142 when in practice, first
upper flex contact array 148A and second upper flex contract array
148B may include a greater or lesser number of individual upper
flex contacts or have flex contacts disposed in a different
configuration, or both.
[0123] The depiction of FIG. 31 shows flex edges 170A and 170B
separated by gap G. Flex edges 170A and 170B terminate respective
upper portions 130U of flex circuit 130. Whether one or two
distinct flex circuits are employed, gap G between edges 170A and
170B is controlled by a physical form during assembly of precursor
assembly 105 and first upper flex contact array 148A and second
upper flex contract array 148B will, therefore, be localized or
fixed in relative position. In the exemplary embodiments, first
upper flex contact array 148A and second upper flex contract array
148B together define an array of upper flex contacts 142 configured
for connection to CSP contacts 124 of upper CSP 112.
[0124] Other means may be employed to position or set edges 170A
and 170B and, by extension, first upper flex contact array 148A and
second upper flex contract array 148B. For example, flex edges 170A
and 170B may be devised to be jointly fittable with each other as
shown in FIG. 32 to position first upper flex contact array 148A
and second upper flex contract array 148B. Protrusion 176 fits with
receptive check 177 to both align laterally and transversely edges
170A and 170B. Other similar devices may be employed to laterally
and/or transversely align edges 170A and 170B. Thus, first upper
flex contact array 148A and second upper flex contract array 148B
are disposed in predetermined relation to each other by the jointly
fittable configuration of edges 170A and 170B to mesh with each
other. Consequently, in this depicted alternative embodiment, edges
170A and 170B are disposed in predetermined relation to each other
by their jointly fittable configurations.
[0125] Stacked circuit modules devised in accordance with the
invention can comprise multiple precursor assemblies 105 as shown
in FIG. 34 or a single precursor assembly 105 as shown in FIG. 35.
When assembling precursor assemblies 105 for use in stacked circuit
modules comprising multiple precursor assemblies 105, the precursor
assemblies 105 can be singulated at this stage with singulation
cuts 175, placed for example as depicted in FIG. 29. In such
embodiments, module contacts 136 are disposed along flex contacts
or pads 149 on flex circuit 130 as exemplified in FIG. 33, which
depicts a plan view of an exemplar precursor assembly 105 from
below. As those of skill will recognize, module contact arrays 138
have been abstracted to illustrate an exemplar set of module
contacts 136 when in practice, module contact arrays 138 may
include a greater or lesser number of individual module contacts or
module contacts disposed in a different configuration.
Alternatively, in preferred embodiments singulation with
singulation cuts 175 can be deferred until all precursor assemblies
105 and upper CSPs 112 have been assembled.
[0126] FIG. 34 depicts an exemplar stacked circuit module 110 in
accordance with a preferred embodiment of the present invention
that employs three precursor assemblies 105. In this embodiment,
each flex circuit 130 has folded portions 131 respective disposed
adjacent to first and second lateral sides of the stack. As those
of skill in the art will recognize, however, stacked circuit
modules 110 also can be devised with one, two, three, four, or more
precursor assemblies 105, or with precursor assemblies using CSPs
of different types. In some configurations, one or more lower CSPs
114 may have a lateral extent L having a proportion such that
folded portions 131 of one or more other precursor assemblies 105
may not be disposed outside such lateral extent.
[0127] FIG. 35 depicts an exemplar stacked circuit module 110 in
accordance with a preferred embodiment of the present invention
that employs a single precursor assembly 105. In this embodiment,
flex circuit 130 has folded portions 131 respective disposed
adjacent to first and second lateral sides of the stack. For
stacked circuit modules 110 comprising one lower CSP 114, in a
preferred embodiment upper CSP 112 is attached to flex circuit 130
prior to singulation of stacked circuit modules 110. Automated
pick-and-place equipment know in the art is used to dispose upper
CSP 112 on flex circuit 130 as shown in FIG. 35. The pick-and-place
equipment dips CSP contacts 124 in flux prior to placement of CSP
112 on flex circuit 130. After placement of CSP 112 on flex circuit
130, the stacked circuit modules 110 are clamped while heat is
supplied during a second solder reflow operation to produce a
solder connection between CSP contacts 124 and upper flex contacts
142. The combination of adhesive 134, stiffener 139, adhesive 135,
and adhesive 171 cooperate to maintain flex circuit 130 and CSP 114
in proper position during the second solder reflow operation.
[0128] In a preferred embodiment, module contacts 136 are disposed
along flex contacts or pads 149 on flex circuit 130 in module
contact arrays 138. FIGS. 36 and 37 depict, respectively, lower
perspective and upper perspective views of an exemplar stacked
circuit module 110 in accordance with a preferred embodiment of the
present invention that employs a single precursor assembly 105.
Exemplar stacked circuit modules 110 typically are connected to an
application environment, such as a printed circuit board, in a
third solder reflow operation. The combination of adhesive 134,
stiffener 139, adhesive 135, and adhesive 171 cooperate to maintain
flex circuit 130, CSP 114, and CSP 112 in proper position during
the third solder reflow operation.
[0129] FIG. 38 depicts an exemplar stacked circuit module 110 in
accordance with a preferred embodiment of the present invention
that has stiffeners 139 disposed at least partially outside lateral
extent L of CSP 114. Embodiments as illustrated in FIG. 38 may be
devised when using a strip 230 and stiffener stock 237 devised for
use with a CSPs having larger dimensions than CSP 114 depicted in
FIG. 38. Accordingly, in preferred embodiments, a single size of
strip 230 and stiffener stock 237 can be used for a variety of CSP
package sizes. In various embodiments of precursor assembly 105 in
which stiffeners 139 are disposed at least partially outside
lateral extent L of CSP 114, the portions of stiffeners 139 outside
lateral extent L will substantially control the size of gap G in
many alternative methods of assembly.
[0130] A wide variety of other variations in the configuration and
materials of precursor assemblies 105 and stacked circuit modules
110 will be apparent to those skilled in the art. For example, tabs
238 need not be rectangular or completely trimmed away during
singulation with singulation cuts 175, but can also extend along
some or all of the ends of precursor assembly 105. Singulation
openings 233 and upper flex cuts 174 can take other shapes and be
disposed in different positions, which for example provide a
narrower portion of flex circuit 130 between stiffener 139 and
upper surface 116 of CSP 114 to allow enhanced ventilation. In
alternative embodiments, a stabilizing fill may be employed between
flex circuit 130 and CSP 114, for example as illustrated by
conformal media 40 depicted in FIGS. 2 and 16.
[0131] In preferred embodiments, a low profile for precursor
assembly 105 is provided. In such embodiments, stiffener 139
typically is about 0.13 mm thick, and adhesive 134 is about 0.05 mm
thick. Adhesive 135 typically is about 0.07 mm thick, but can range
across a variety of thicknesses. For example, in various preferred
embodiments Adhesive 135 ranges from about 0.04 mm. to about 0.10
mm thick. Adhesive 171 typically is about 0.08 mm thick. The
various thicknesses used in embodiments devised in accordance with
the invention are subject to wide ranges of alternatives, as those
of skill will recognize.
[0132] FIG. 39 depicts a tooling apparatus 180 devised in
accordance with a preferred embodiment of the present invention
illustrating the use of a physical form to set gap G between edges
170A and 170B of flex circuit 130. Tooling apparatus 180 includes a
flex aligner 182 as shown in FIG. 39 used as a physical form to
impose a preselected distance between the first and second edges.
When forming tool 184 disposes flex circuit 130 adjacent to upper
surface 116 of CSP 114 in forming precursor assembly 105, edges
170A and 170B of flex circuit 130 are limited in lateral placement
along upper surface 116 of CSP 114 by flex aligner 182. Gap "G" is,
therefore, preselected and determined by the dimensions of flex
aligner 182 when disposed between edges 170A and 170B. With gap G
and edges 170A and 170B thus determined, first upper flex contact
array 148A and second upper flex contract array 148B are positioned
during assembly as exemplified in FIG. 31.
[0133] FIG. 40 depicts an enlarged depiction of the area marked
"40" in FIG. 39. As shown in the construction of the example
precursor assembly 105, flex circuit 130 is attached to stiffener
139 with adhesive 134. When precursor assembly 105 comprising CSP
114, stiffeners 139, adhesives 134 and 135, and flex circuit 130 is
disposed in cavity 188 of jig 186, flex circuit 130 is deflected in
an upward direction as shown in FIG. 40.
[0134] FIG. 41 illustrates a step in a method of devising an
precursor assembly 105 in accordance with a preferred embodiment of
the present invention. As indicated, forming tools 184 are moveable
as indicated by the arrow 184M to indicate with the "+" sign
movement of forming tools 184 to dispose upper ends 130U of flex
circuit 130 over CSP 114. The ends 170A and 170B are set apart at
distance "G" apart by flex aligner 182.
[0135] FIG. 42 illustrates another step in a method for devising a
precursor assembly 105 in accordance with a preferred embodiment of
the present invention. Press tool 189 is imposed on precursor
assembly 105 after upper portions 130U of flex circuit 130 have
been disposed over the upper surface 116 of the CSP 114 and forming
tools 184 are withdrawn as indicated by the arrow 184M to indicate
with the "-" sign movement of forming tools 184. Press tool 189
preferably may be heated.
[0136] FIG. 43 depicts another step in a method for devising a
precursor assembly 105 in accordance with a preferred embodiment of
the present invention. Press tool 189 has moved up off of precursor
assembly 105 as indicated by motion arrow 189M. Flex aligner 182
may now be withdrawn and precursor assembly 105 is ready for
combination with either another precursor assembly 105 or a CSP 112
to form a module 110.
[0137] FIG. 44 depicts a tooling apparatus 180 devised in
accordance with another preferred embodiment of the present
invention also using a physical form to set gap G between edges
170A and 170B of flex circuit 130. In a step of a preferred method
for using the tooling apparatus 180 depicted in FIG. 44, jigs 186
are placed in first configuration with jigs 186 set apart by a
first width W1. In this embodiment, precursor assembly 105
comprising CSP 114, stiffeners 139, adhesives 134 and 135, and flex
circuit 130 is disposed in cavity 188 by flex aligner 182, and
upper portions 130U of flex circuit 130 are deflected in an upward
direction in the configuration shown in FIG. 44 by preform tools
187 comprised in press tool 189A.
[0138] In the embodiment depicted in FIG. 45, press tool 189A used
for the step depicted in FIG. 44 is retracted and exchanged for
press tool 189B shown, which does not comprise preform tools 187.
With precursor assembly 105 raised above cavity 188, jigs 186 are
moved in the direction indicated by motion arrows 186M to a second
configuration, in which jigs 186 are set apart by a second width
W2. In the configuration depicted in FIG. 45, the flex preformed by
the step depicted in FIG. 44 relaxes, with upper portions 130U of
flex circuit 130 springing back to some extent from the position
depicted in FIG. 44.
[0139] FIG. 46 depicts another step in a preferred method for using
the illustrated tooling apparatus 180. With jigs 186 set apart by
second width W2, precursor assembly 105 is disposed in cavity 188
by flex aligner 182, which causes upper portions 130U of flex
circuit 130 to be deflected in an inward direction in the
configuration shown in FIG. 46 by interference with jigs 186 set
apart at second width W2.
[0140] FIG. 47 depicts another step in a preferred method for using
the illustrated tooling apparatus 180. With upper portions 130U of
flex circuit 130 disposed above CSP 114, such as depicted in FIG.
46, press tool 189B is imposed on precursor assembly 105. Press
tool 189B preferably may be heated. In this configuration, the ends
170A and 170B of flex circuit 130 are set apart at distance G by
flex aligner 182, and upper portions 130U of flex circuit 130 are
attached to top surface 116 of CSP 114 by adhesive 171, for example
as illustrated in FIG. 23.
[0141] FIG. 48 depicts another step in a method for devising a
precursor assembly 105 in accordance with a preferred embodiment of
the present invention. Press tool 189B has moved up off of
precursor assembly 105 as indicated by motion arrow 189M. Flex
aligner 182 may now be withdrawn and precursor assembly 105 is
ready for combination with either another precursor assembly 105 or
a CSP 112 to form a module 110.
[0142] The tooling apparatus and methods depicted in FIGS. 44-48 do
not have or use forming tools 184 such as those depicted in FIGS.
39-43, but forming tools 184 and other similar structures could be
used in the methods and with the tooling apparatus depicted in
FIGS. 44-48 instead of, or with, press tool 189B.
[0143] Although the present invention has been described in detail,
it will be apparent to those skilled in the art that the invention
may be embodied in a variety of specific forms and that various
changes, substitutions and alterations can be made without
departing from the spirit and scope of the invention. The described
embodiments are only illustrative and not restrictive, and
therefore the scope of the invention is indicated by the following
claims.
* * * * *