U.S. patent application number 11/881816 was filed with the patent office on 2008-03-27 for circuit and method for controlling charge injection in radio frequency switches.
Invention is credited to Christopher N. Brindle, Alexander Dribinsky, Dylan J. Kelly, Tae Youn Kim.
Application Number | 20080076371 11/881816 |
Document ID | / |
Family ID | 39225572 |
Filed Date | 2008-03-27 |
United States Patent
Application |
20080076371 |
Kind Code |
A1 |
Dribinsky; Alexander ; et
al. |
March 27, 2008 |
Circuit and method for controlling charge injection in radio
frequency switches
Abstract
A circuit and method for controlling charge injection in a
circuit are disclosed. In one embodiment, the circuit and method
are employed in a semiconductor-on-insulator (SOI) Radio Frequency
(RF) switch. In one embodiment, an SOI RF switch comprises a
plurality of switching transistors coupled in series, referred to
as "stacked" transistors, and implemented as a monolithic
integrated circuit on an SOI substrate. Charge injection control
elements are coupled to receive injected charge from
resistively-isolated nodes located between the switching
transistors, and to convey the injected charge to at least one node
that is not resistively-isolated. In one embodiment, the charge
injection control elements comprise resistors. In another
embodiment, the charge injection control elements comprise
transistors. A method for controlling charge injection in a switch
circuit is disclosed whereby injected charge is generated at
resistively-isolated nodes between series coupled switching
transistors, and the injected charge is conveyed to at least one
node of the switch circuit that is not resistively-isolated.
Inventors: |
Dribinsky; Alexander;
(Naperville, IL) ; Kim; Tae Youn; (San Diego,
CA) ; Kelly; Dylan J.; (San Diego, CA) ;
Brindle; Christopher N.; (Poway, CA) |
Correspondence
Address: |
Martin J. Jaquez, Esq.;JAQUEZ & ASSOCIATES
Suite 100D
6265 Greenwich Drive
San Diego
CA
92122
US
|
Family ID: |
39225572 |
Appl. No.: |
11/881816 |
Filed: |
July 26, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11520912 |
Sep 14, 2006 |
|
|
|
11881816 |
Jul 26, 2007 |
|
|
|
11484370 |
Jul 10, 2006 |
|
|
|
11881816 |
Jul 26, 2007 |
|
|
|
11484370 |
Jul 10, 2006 |
|
|
|
11881816 |
Jul 26, 2007 |
|
|
|
60718260 |
Sep 15, 2005 |
|
|
|
60698523 |
Jul 11, 2005 |
|
|
|
60698523 |
Jul 11, 2005 |
|
|
|
60833562 |
Jul 26, 2006 |
|
|
|
Current U.S.
Class: |
455/208 |
Current CPC
Class: |
H03K 17/6874 20130101;
H03K 17/08 20130101; H03K 17/102 20130101; H03K 17/284 20130101;
H03K 17/689 20130101; H03K 17/04 20130101; H03K 17/161 20130101;
H03K 17/06 20130101; H03K 2217/0009 20130101 |
Class at
Publication: |
455/208 |
International
Class: |
H04B 1/16 20060101
H04B001/16 |
Claims
1. A switch circuit, comprising: a) a plurality of switching
transistors coupled in series to selectively convey a signal from
an input of the series coupled switching transistors to an output
of the series coupled switching transistors, wherein injected
charge is generated at resistively-isolated nodes between the
switching transistors; and b) a plurality of charge injection
control elements operatively coupled to the switching transistors,
and wherein the charge injection control elements receive the
injected charge from the resistively-isolated nodes and convey the
injected charge to at least one node of the switch circuit that is
not resistively-isolated.
2. The switch circuit of claim 1, wherein each switching transistor
has an associated and corresponding charge injection control
element, and wherein a drain node of each switching transistor is
coupled to a first node of its associated and corresponding charge
injection control element, and wherein a source node of each
switching transistor is coupled to a second node of its associated
and corresponding charge injection control element, and wherein
each charge injection control element conveys the injected charge
between the drain node and the source node of its associated and
corresponding switching transistor.
3. The switch circuit of claim 1, wherein each of the switching
transistors comprises an accumulated charge control (ACC)
transistor.
4. The switch circuit of claim 3, wherein the ACC transistor
includes an accumulated charge sink (ACS) electrically coupled to
convey accumulated charge from the ACS to a gate terminal of the
ACC transistor when the ACC transistor operates in an accumulated
charge regime.
5. The switch circuit of claim 4, wherein a diode selectively
conveys accumulated charge from the ACS to the gate terminal of the
ACC transistor when the ACC transistor operates in an accumulated
charge regime.
6. The switch circuit of claim 2, wherein each charge injection
control element comprises a charge injection control resistor.
7. The switch circuit of claim 6, further comprising a plurality of
gate resistors each having a resistance Rg, wherein a gate of each
switching transistor is connected to an associated and
corresponding one of the plurality of gate resistors, and wherein
the plurality of gate resistors is connected to a control line that
conveys a control signal to the gate of each switching transistor,
and wherein a resistance Rc of each charge injection control
resistor is selected according to a formula
10.times.Rg/N>Rc>Rg/10N, and wherein N comprises a number of
switching transistors in the plurality of switching
transistors.
8. The switch circuit of claim 2, wherein the charge injection
control elements comprise switching circuits having an ON-state and
an OFF-state, and wherein a control signal selectively switches the
charge injection control elements from the ON-state to the
OFF-state at a time subsequent to a time at which each switching
transistor is switched from an ON-state to an OFF-state.
9. The switch circuit of claim 8, wherein the charge injection
control elements comprise charge injection control transistors.
10. The switch circuit of claim 1, wherein the switch circuit
comprises a radio frequency (RF) switch.
11. The switch circuit of claim 3, wherein the ACC transistor uses
a pulse method for controlling accumulated charge.
12. The switch circuit of claim 1, wherein the plurality of
switching transistors comprise semiconductor-on-insulator (SOI)
metal-oxide-semiconductor field effect transistors (MOSFETs).
13. The switch circuit of claim 12, wherein the SOI MOSFETs are
fabricated on a silicon-on-sapphire substrate.
14. A method of controlling charge injection in a switch circuit,
wherein the switch circuit comprises a plurality of switching
transistors coupled in series to selectively convey a signal from
an input of the series coupled transistors to an output of the
series coupled transistors, comprising the steps of: a) generating
injected charge at resistively-isolated nodes between the series
coupled switching transistors; and b) conveying the injected charge
to at least one node of the switch circuit that is not
resistively-isolated.
15. The method of claim 14, wherein each switching transistor has
an associated and corresponding charge injection control element,
and wherein a drain node of each switching transistor is coupled to
a first node of its associated and corresponding charge injection
control element, and wherein a source node of each switching
transistor is coupled to a second node of its associated and
corresponding charge injection control element, and wherein each
charge injection control element conveys the injected charge
between the drain node and the source node of its associated and
corresponding switching transistor.
16. The method of claim 14, wherein each of the switching
transistors comprises an accumulated charge control (ACC)
transistor.
17. The method of claim 16, wherein the ACC transistor includes an
accumulated charge sink (ACS) electrically coupled to convey
accumulated charge from the ACS to a gate terminal of the ACC
transistor when the ACC transistor operates in an accumulated
charge regime.
18. The method of claim 17, wherein a diode selectively conveys
accumulated charge from the ACS to the gate terminal of the ACC
transistor when the ACC transistor operates in an accumulated
charge regime.
19. The method of claim 15, wherein each charge injection control
element comprises a charge injection control resistor.
20. The method of claim 15, wherein the charge injection control
elements comprise switching circuits having an ON-state and an
OFF-state, and wherein the method further comprises a step of
switching the charge control elements from the ON-state to the
OFF-state at a time subsequent to a time at which each switching
transistor is switched from an ON-state to an OFF-state.
21. The method of claim 20, wherein the charge injection control
elements comprise charge injection control transistors.
22. The method of claim 14, wherein the switch circuit comprises a
radio frequency (RF) switch.
23. The method of claim 16, wherein the ACC transistor uses a pulse
method for controlling accumulated charge.
24. A switch circuit, comprising a plurality of switching
transistors connected in a series configuration to selectively
convey a signal from an input of the series coupled transistors to
an output of the series coupled transistors, comprising: a) means
for generating injected charge at resistively-isolated nodes
between the switching transistors; and b) means, operatively
coupled to the generating means, for conveying the injected charge
to at least one node of the switch circuit that is not
resistively-isolated.
25. The switch circuit of claim 24, wherein the conveying means
comprises a plurality of charge injection control elements, and
wherein each switching transistor has an associated and
corresponding charge injection control element, and wherein a drain
node of each switching transistor is coupled to a first node of its
associated and corresponding charge injection control element, and
wherein a source node of each switching transistor is coupled to a
second node of its associated and corresponding charge injection
control element, and wherein each charge injection control element
conveys the injected charge between the drain node and the source
node of its associated and corresponding switching transistor.
26. The switch circuit of claim 24, wherein each of the switching
transistors comprises an accumulated charge control (ACC)
transistor.
27. The switch circuit of claim 25, wherein each charge injection
control element comprises a charge injection control resistor.
28. The switch circuit of claim 27, further comprising a plurality
of gate resistors each having a resistance Rg, wherein a gate of
each switching transistor is connected to an associated and
corresponding one of the plurality of gate resistors, and wherein
the plurality of gate resistors is connected to a control line that
conveys a control signal to the gate of each switching transistor,
and wherein a resistance Rc of each charge injection control
resistor is selected according to a formula
10.times.Rg/N>Rc>Rg/10N, and wherein N comprises a number of
switching transistors in the plurality of switching
transistors.
29. The switch circuit of claim 25, wherein the charge injection
control elements comprise switching circuits having an ON-state and
an OFF-state, and wherein a control signal selectively switches the
charge injection control elements from the ON-state to the
OFF-state, further comprising a means for switching the charge
injection control elements from the ON-state to the OFF-state at a
time subsequent to a time at which each switching transistor is
switched from an ON-state to an OFF-state.
30. The switch circuit of claim 29, wherein the charge injection
control elements comprise charge injection control transistors.
Description
CROSS-REFERENCE TO RELATED UTILITY AND PROVISIONAL APPLICATIONS
Claims of Priority
[0001] This application is a Continuation-in-Part (CIP) of
co-pending and commonly assigned U.S. patent application Ser. No.
11/520,912, filed Sep. 14, 2006, entitled "METHOD AND APPARATUS
IMPROVING GATE OXIDE RELIABILITY BY CONTROLLING ACCUMULATED CHARGE"
[ATTY. DOCKET NO. PER-015-CIP], which claims the benefit under 35
U.S.C. .sctn. 119 (e) of U.S. Provisional Application No.
60/718,260, filed Sep. 15, 2005; the cited application Ser. No.
11/520,912, filed Sep. 14, 2006, is a CIP of U.S. patent
application Ser. No. 11/484,370, filed Jul. 10, 2006, entitled
"METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS
USING AN ACCUMULATED CHARGE SINK" [DOCKET NO. PER-016-PAP],
pending, which claims the benefit under 35 U.S.C. .sctn. 119 (e) of
U.S. Provisional Application No. 60/698,523, filed Jul. 11, 2005;
the present CIP application is also a CIP of the cited U.S. patent
application Ser. No. 11/484,370, filed Jul. 10, 2006, pending; and
the present CIP application claims the benefit under 35 U.S.C.
.sctn. 119 (e) of U.S. Provisional Application No. 60/833,562,
filed Jul. 26, 2006, entitled "CIRCUIT AND METHOD FOR CONTROLLING
CHARGE INJECTION IN RADIO FREQUENCY SWITCHES" [DOCKET NO.
PER-018-PROV]. The present CIP application is related to co-pending
and commonly assigned application Ser. No. 10/922,135, filed Aug.
18, 2004, [DOCKET NO. PER-001-CON], which issued Oct. 17, 2006 as
U.S. Pat. No. 7,123,898, and is a continuation application of
application Ser. No. 10/267,531, filed Oct. 8, 2002, which issued
Oct. 12, 2004 as U.S. Pat. No. 6,804,502, entitled "SWITCH CIRCUIT
AND METHOD OF SWITCHING RADIO FREQUENCY SIGNALS" [DOCKET NO.
PER-001-PAP]. application Ser. No. 10/267,531, filed Oct. 8, 2002,
which issued Oct. 12, 2004 as U.S. Pat. No. 6,804,502, claims the
benefit under 35 U.S.C. .sctn. 119 (e) of U.S. Provisional
Application No. 60/328,353, filed Oct. 10, 2001. The present CIP
application is related to each of the applications set forth above.
All of the applications and issued patents set forth above are
hereby incorporated by reference herein as if set forth in
full.
BACKGROUND
[0002] 1. Field
[0003] The present teachings relate to electronic switches, and
particularly to a circuit and method for controlling charge
injection in semiconductor-on-insulator (SOI) radio frequency (RF)
switches.
[0004] 2. Description of Related Art
[0005] Radio frequency (RF) switches for directing RF signals are
found in many different RF devices such as televisions, video
recorders, cable television equipment, cellular telephones,
wireless pagers, wireless infrastructure equipment, and satellite
communications equipment. As is well known, the performance of RF
switches is controlled by three primary operating performance
parameters: insertion loss, switch isolation, and the "1 dB
compression point." The "1 dB compression point" is related to, and
is indicative of, the linearity performance of an RF switch.
Linearity performance is also indicated by the levels of RF signal
harmonics generated by an RF switch, particularly at high RF power
levels. These three performance parameters are tightly coupled, and
any one parameter can be emphasized in the design of RF switch
components at the expense of others. A fourth performance parameter
that is occasionally considered in the design of RF switches is
commonly referred to as the switching time or switching speed
(defined as the time required to turn one side of a switch on and
turn the other side off). Other characteristics important in RF
switch design include ease and degree (or level) of integration of
the RF switch, complexity, yield, return loss and cost of
manufacture.
[0006] Charge injection is a problem that may occur in switching
circuits such as SOI RF switches. Charge injection occurs when an
applied voltage, such as a gate bias voltage, is connected to a
"resistively-isolated node" through a coupling capacitance. A
resistively-isolated node is defined herein as a node that at some
interval during operation is connected to other circuit elements
only through very high resistance connections. For example, a
resistively-isolated node may occur at a transistor channel node
located between series-connected transistors when the transistors
are in an OFF-state. The coupling capacitance through which charge
injection occurs may be either a parasitic capacitance of a circuit
element (e.g., gate-to-source capacitance in a transistor), or a
capacitance associated with a capacitor. For example, a bias
voltage applied to the gate of a transistor may be connected to a
resistively-isolated source node of the transistor through the
gate-to-source capacitance. In general, charge injection may be a
problem for many types of switching circuits. In particular, charge
injection is significantly deleterious to the performance
properties of SOI RF switches. Further, teachings on prior art SOI
RF switches do not address this problem, for reasons described in
more detail hereinbelow. Consequently, a need exists for a novel
circuit and method for controlling charge injection in SOI RF
switches.
SUMMARY
[0007] A novel circuit and method for controlling charge injection
in an SOI RF switch are disclosed. The SOI RF switch may comprise a
plurality of switching transistors connected in series (referred to
herein as "stacked" switching transistors) implemented as a
monolithic integrated circuit (IC) on an SOI substrate. In one
embodiment the SOI RF switch is fabricated on an Ultra-Thin-Silicon
("UTSi") substrate, also referred to herein as "silicon on
sapphire" (SOS). In another embodiment, the SOI RF switch is
fabricated in silicon-on-bonded wafer technology.
[0008] In an embodiment according to the present disclosure, an SOI
RF switch includes at least one stack comprising a plurality of
switching transistors connected in a series circuit. Charge
injection control elements are connected to receive injected charge
from resistively-isolated nodes located between the switching
transistors, and to convey the injected charge to one or more nodes
that are not resistively-isolated. Optionally, the charge injection
control elements may be connected to receive a control signal for
switching the charge injection control elements between ON-states
and OFF-states. In one embodiment, each switching transistor in a
stack of the SOI RF switch has at least one charge injection
control element operatively connected between a source node and a
drain node of each switching transistor.
[0009] In one embodiment, the charge injection control elements
comprise charge injection control resistors. In another embodiment,
the charge injection control elements comprise charge injection
control transistors connected to receive a control signal for
switching the injection control transistors between and ON-state
and an OFF-state. The charge injection control transistors are
operated so that they are in the ON-state when the switching
transistors are in an ON-state. When the switching transistors are
switched from the ON-state to an OFF-state, the charge injection
control transistors are switched from an ON-state to an OFF-state
after a selected delay time interval, thereby allowing the injected
charge to be conveyed to the least one node that is not
resistively-isolated.
[0010] In one embodiment, a method for controlling charge injection
includes: 1) causing charge injection to occur at
resistively-isolated nodes located between the switching
transistors; 2) conveying the injected charge via charge injection
control elements to at least one node that is not
resistively-isolated; and, 3) optionally switching the charge
injection control elements from an ON-state to an OFF-state.
[0011] According to one embodiment of the method for controlling
charge injection, the charge injection control elements may
comprise charge injection control resistors. In another embodiment,
the charge injection control elements may comprise charge injection
control transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1A schematically illustrates an SOI RF switch circuit
using stacked switching transistors.
[0013] FIG. 1B illustrates the effects of charge injection in an
SOI RF switch circuit using stacked switching transistors.
[0014] FIG. 1C illustrates simulated data for the RF switch of FIG.
1A wherein the RF switch has recently been switched from an
ON-state to an OFF-state.
[0015] FIG. 2 schematically illustrates an embodiment according to
the present disclosure, including a charge injection control
circuit.
[0016] FIG. 3 shows a schematic illustration of an embodiment
according to the present disclosure, using resistors in a charge
injection control circuit.
[0017] FIG. 4 shows a schematic illustration of an embodiment
according to the present disclosure, using transistors in a charge
injection control circuit.
[0018] FIG. 5 is a flow chart diagram illustrating a charge
injection control method.
[0019] FIG. 6A is a simplified schematic of an improved SOI NMOSFET
adapted to control accumulated charge embodied as a four terminal
device.
[0020] FIG. 6B is a simplified schematic of an improved SOI NMOSFET
adapted to control accumulated charge, embodied as a four terminal
device, wherein an accumulated charge sink (ACS) terminal is
coupled to a gate terminal.
[0021] FIG. 6C is a simplified schematic of an improved SOI NMOSFET
adapted to control accumulated charge, embodied as a four terminal
device, wherein an accumulated charge sink (ACS) terminal is
coupled to a gate terminal via a diode.
[0022] FIG. 6D is a simplified schematic of an improved SOI NMOSFET
adapted to control accumulated charge, embodied as a four terminal
device, wherein an accumulated charge sink (ACS) terminal is
coupled to a control circuit.
[0023] Like reference numbers and designations in the various
drawings indicate like elements.
DETAILED DESCRIPTION
[0024] Throughout this description, embodiments and variations are
described for the purpose of illustrating uses and implementations
of the inventive concept. The illustrative description should be
understood as presenting examples of the inventive concept, rather
than as limiting the scope of the concept as disclosed herein.
[0025] The problems caused by charge injection in SOI RF switches
may be described with reference to FIG. 1A. An SOI RF switch 100
comprises stacked switching transistors 111, 113, 115 and 117. As
disclosed in commonly-assigned U.S. application Ser. Nos.
10/922,135 and 10/267,531, incorporated by reference hereinabove,
RF switches using stacked switching transistors have many
performance advantages over prior art RF switches, such as higher
RF power capability and reduced generation of harmonics in the
switched RF signal. Although four stacked switching transistors are
shown in FIG. 1A, it will be apparent to persons skilled in the
arts of electronic circuits that the present teachings apply to RF
switches having an arbitrary plurality of stacked switching
transistors.
[0026] As shown in FIG. 1A, a first channel node of the switching
transistor 111 may receive an input RF signal from a node 101. A
second channel node of the switching transistor 111 is operatively
connected through a node 103 to a first node of the switching
transistor 113. A second channel node of the switching transistor
113 is operatively connected through a node 105 to a first channel
node of the switching transistor 115. A second channel node of the
switching transistor 115 is operatively connected through a node
107 to a first channel node of the switching transistor 117. A
second channel node of the switching transistor 117 is connected to
a node 109, which may output an RF signal. Typically, the nodes 101
and 109 are connected to load impedances (not shown) having
resistance values to ground on the order of 50 or 75 ohms.
[0027] Gate nodes of the switching transistors 111, 113, 115 and
117 are separately connected to gate resistors 121, 123, 125 and
127, respectively. As disclosed in U.S. App. Nos. 10/922,135 and
10/267,531, the gate resistors are included to enable voltage
division of RF signals across the switching transistors, protect
bias circuits, and prevent transmission of parasitic RF signals
between the stacked switching transistors. In some embodiments, the
resistance Rg of each gate resistor should be at least ten times
larger than the RF impedance of the gate-to-drain capacitance Cgd
of the switching transistor to which it is connected. The gate
resistors 121, 123, 125 and 127 are jointly connected to a gate
control line 119 to receive a gate control signal C1.
[0028] The operation and advantages of RF switches such as the SOI
RF switch 100 have been previously disclosed, as for example in
U.S. application Ser. Nos. 10/922,135 and 10/267,531.
[0029] However, the charge injection problem and solution have not
been previously disclosed. In the present example, as illustrated
by FIG. 1A, charge injection may occur at the nodes 103, 105 and
107 in the following manner. For the present example, the switching
transistors 111, 113, 115 and 117 comprise enhancement-mode
n-channel Metal-Oxide-Semiconductor Field Effect Transistors
(MOSFETs) with a threshold voltage of +0.3 V. The gate control
signal C1 is varied between a voltage of +3.0 V wherein the
switching transistors are ON, and a voltage of -3.0 V wherein the
switching transistors are OFF.
[0030] When the gate control signal C11 changes from +3 V to -3 V,
the voltage passes through the switching transistor threshold
voltage +0.3 V. During this process, the switching transistors 111
and 117 will switch from ON to OFF without difficulty because the
nodes 109 and 101 are connected to load resistors (not shown) and
therefore have an average DC potential at approximately ground
potential or 0 V. The first channel node of the switching
transistor 111 and the second channel node of the switching
transistor 117 will be at a DC bias voltage of approximately 0 V,
and their respective gate nodes will be a voltage of -3 V. However,
when the switching transistors 111 and 117 switch from ON to OFF,
the nodes 103, 105 and 107 become resistively isolated, as defined
hereinabove in paragraph 004. For this reason, charge injection
through the gate-to-channel capacitances of the switching
transistors 113 and 115 to the nodes 103, 105 and 107 will occur as
the control signal C1 voltage moves from the threshold voltage of
+0.3 to -3 V. The charge injection will tend to maintain the nodes
103, 105 and 107 at voltages that may be only slightly more
positive than the control signal C1 voltage. This will prevent the
channels of the transistors 103, 105 and 107 from achieving a
highly depleted condition, which is required for proper operation
of the SOI RF switch 100.
[0031] These effects are illustrated in FIG. 1B by simulated data
for the SOI RF switch 100. When a control voltage 142 (C1) is
switched from +3 V to -3 V, voltages 134, 136 and 138, on nodes
107, 105 and 103, respectively, follow the voltage 142 as described
above. Voltages 132 and 140 on nodes 109 and 101, respectively,
remain at 0 V because they are not resistively isolated.
[0032] Prior art teachings are not informed regarding the problem
of charge injection as described above. The principal reason for
this is that RF switches such as SOI RF switch 100 are typically
used to switch RF signals of several volts AC amplitude. If some of
the switching transistors are not in a strong OFF-state, the RF
signals will cause breakdown effects in the switching transistors
that are strongly turned OFF and therefore receive larger RF signal
voltages. These breakdown effects remove the injected charge from
the resistively-isolated nodes, thereby enabling the switches to
operate after a time interval. However, the breakdown effects may
have deleterious effects on the reliability of the switching
transistors. Further, because the breakdown effects occur over a
time interval, the performance of the RF switch is adversely
affected during the time interval. In particular, during the time
interval wherein the injected charge is not completely removed, the
switch response becomes nonlinear, and undesirable RF harmonics may
be generated by the SOI RF switch.
[0033] These deleterious effects are illustrated in FIG. 1C by
simulated data for the SOI RF switch 100 that has been recently
switched from the ON-state to the OFF-state. At a time 99.0000
microseconds, an RF signal 160 is applied at the node 101. RF
signals 158, 156, 154 and 152 appear at nodes 103, 105, 107 and
109, respectively, due to parasitic coupling effects. Persons
skilled in the electronic arts will recognize from the distorted
waveforms seen in the RF signals 158, 156, 154 and 152 that
significant nonlinear distortion is present during the time
interval illustrated, which corresponds to a time when charge
injection effects are present. These deleterious effects due to
charge injection can be reduced or eliminated according to the
teachings herein.
SOI RF Switch with a Charge Injection Control Circuit.
[0034] An embodiment of a charge injection control circuit to
remove injected charge in an SOI RF switch is illustrated by FIG.
2.
[0035] In FIG. 2, an SOI RF switch 200 includes charge injection
control elements 201, 203, 205 and 207 that comprise elements of a
charge injection control circuit. A first and second channel node
of the charge injection control element 201 are operatively
connected to the nodes 101 and 103, respectively. A first and
second channel node of the charge injection control element 203 are
operatively connected to the nodes 103 and 105, respectively. A
first and second channel node of the charge injection control
element 205 are operatively connected to the nodes 105 and 107,
respectively. A first and second channel node of the charge
injection control element 207 are similarly operatively connected
to the nodes 107 and 109, respectively. Optionally (e.g., as
described below in reference to FIG. 4), the charge injection
control elements 201, 203, 205 and 207 may be connected to a
control line 209 to receive a control signal C2.
[0036] The charge injection control elements 201, 203, 205 and 207
receive injected charge from the nodes 103, 105 and 107, and
selectively convey the injected charge to the nodes 101 and 109.
For some embodiments, the control voltage C2 may be used to switch
the charge injection control elements 201, 203, 205 and 207 between
ON and OFF states (e.g., as described below in reference to FIG.
4).
[0037] For improved performance, the charge injection control
elements 201, 203, 205 and 207 should be designed to have an
impedance sufficiently high to prevent degradation of the RF
isolation performance of the SOI RF switch 200. However, the charge
injection control elements 201, 203, 205 and 207 should also have
an impedance sufficiently low to effectively remove the injected
charge and avoid degradation of the switching time for the SOI RF
switch 200. Further, in some embodiments, the charge injection
control elements 201, 203, 205 and 207 are designed so that they do
not cause nonlinear behavior and RF harmonic generation. In
addition, it is desirable that the charge injection control
elements 201, 203, 205 and 207 do not degrade the switching time of
the SOI RF switch 200. These design tradeoffs are described in more
detail below in reference to FIGS. 3 and 4.
[0038] Many configurations of charge injection control elements can
be used to remove injected charge from resistively-isolated nodes
between switching transistors in SOI RF switches.
SOI RF Switch Circuits with Charge Injection Control Circuits Using
Resistors
[0039] An embodiment of a charge injection control circuit using
resistors to remove injected charge in an SOI RF switch is
illustrated in FIG. 3. In FIG. 3, an SOI RF switch 300 includes
charge injection control resistors 301, 303, 305 and 307 that
comprise elements of a charge injection control circuit. A first
node of the charge injection control resistor 301 is operatively
connected to the node 101, and a second node of the charge
injection control resistor 301 is operatively connected to the node
103. Similarly, a first node of the charge injection control
resistor 303 is operatively connected to the node 103, and a second
node of the charge injection control resistor 303 is operatively
connected to the node 105. Similarly, a first node of the charge
injection control resistor 305 is operatively connected to the node
105, and a second node of the charge injection control resistor 305
is operatively connected to the node 107. Similarly, a first node
of the charge injection control resistor 307 is operatively
connected to the node 107, and a second node of the charge
injection control resistor 307 is operatively connected to the node
109. The charge injection control resistors 301, 303, 305 and 307
receive injected charge from the nodes 103, 105 and 107, and convey
the injected charge to the nodes 101 and 109.
[0040] As noted above, for improved performance, the charge
injection control resistors 301, 303, 305 and 307 are designed to
have a sufficiently high resistance valve to prevent degradation of
the RF isolation performance of the SOI RF switch 300. However, the
charge injection control resistors 301, 303, 305 and 307 should
also have a low enough resistance to effectively remove the
injected charge. Using circuit simulation techniques, good
performance has been determined for charge injection resistors
selected according to the following equation: Rc=Rg/N [EQUATION 1]
In Equation 1, Rc is the resistance of each charge injection
control resistor, Rg is the resistance of each gate resistor, and N
is the number of RF switching transistors in the stack, also
referred to as the "stack height". It has been determined that
choosing the charge injection resistors according to EQUATION 1
provides minimal degradation to the isolation and switching time
performance of the SOI RF switch. In one embodiment, SOI RF switch
300 may have gate resistors 121, 123, 125 and 127 that are each 100
K-ohm. In this embodiment, the charge injection control resistors
301, 303, 305 and 307 will each comprise K-ohm resistors, because
the stack height N=4 in this example. The present disclosure also
encompasses use of charge injection control resistors having Rc
values other than as indicated by EQUATION 1. For example, in some
embodiments Rc may be selected in the range
10.times.Rg/N>Rc>Rg/10N.
[0041] U.S. application Ser. No. 11/484,370, filed Jul. 10, 2006,
pending, incorporated by reference hereinabove, discloses using
drain-to-source Rds resistors between the source and drain of a
stacked SOI RF switch having an accumulated charge sink. Although
the Rds resistors 802, 804, and 806 as shown in FIG. 8, of the U.S.
application Ser. No. 11/484,370 have a configuration that is
similar to the charge injection control resistors 301, 303, 305 and
307, their function and operation are distinct. In particular, the
Rds resistors 802, 804, and 806 are included to allow removal of a
DC current generated by using an accumulated charge sink, while the
present disclosure provides a solution to the more general problem
of charge injection in SOI RF switches that may or may not have an
accumulated charge sink.
Charge Injection Control Circuit Using Transistors to Remove
Injected Charge
[0042] An embodiment of a charge injection control circuit using
transistors to remove injected charge in an SOI RF switch is
illustrated by FIG. 4.
[0043] In FIG. 4 an SOI RF switch 400 includes charge injection
control transistors 401, 403, 405 and 407 that comprise elements of
a charge injection control circuit. A first and second channel node
of the charge injection control transistor 401 are operatively
connected to the nodes 101 and 103, respectively. Similarly, a
first and second channel node of the charge injection control
transistor 403 are operatively connected to the nodes 103 and 105,
respectively. Similarly, a first and second channel node of the
charge injection control transistor 405 are operatively connected
to the nodes 105 and 107, respectively. Similarly, a first and
second channel node of the charge injection control transistor 407
are operatively connected to the nodes 107 and 109,
respectively.
[0044] The gates of the charge injection control transistors 401,
403, 405 and 407 are operatively connected to gate resistors 411,
413, 415 and 417, respectively. The gate resistors 411, 413, 415
and 417 are also connected to a control line 209 to receive a
control signal C2 that is conveyed to the gates of the charge
injection control transistors 401, 403, 405 and 407. The resistors
411, 413, 415 and 417 are included to enable voltage division of RF
signals cross the switching transistors, protect bias circuits, and
prevent transmission of parasitic RF signals between the stacked
switching transistors.
[0045] In one embodiment, in operation, the control signal C2
provides a voltage signal to maintain the charge injection control
transistors 401, 403, 405 and 407 in an ON-state during time
intervals in which the gate control signal C1 maintains the
switching transistors 111, 113, 115 and 117 in an ON-state. For
example, the transistors 401, 403, 405, 407, 111, 113, 115 and 117
may all be enhancement-mode n-channel MOSFETs with a threshold
voltage of +0.1 V. The gate control signals C1 and C2 may be
selected to vary between a voltage of +1.0 V to turn the
transistors ON, and a voltage of -3.0 V to turn the transistors
OFF.
[0046] When the gate control signal C1 transitions from +1 V to -3
V, the voltage passes through the switching transistor threshold
voltage +0.1 V. If the gate control signal C2 is maintained at a
voltage of +1 V for a time interval after the gate control signal
C1 transitions from +1 V to -3 V, the nodes 103, 105 and 107
maintain low resistance connections to the nodes 101 and 109 via
the ON-state charge injection control transistors 401, 403, 405 and
407. This low resistance connection conveys the injected charge
from the nodes 103, 105 and 107 to the nodes 101 and 109, thereby
controlling the charge injection process. After the switching
transistors 111, 113, 115 and 117 are in the OFF-state, the charge
injection control transistors 401, 403, 405 and 407 may be switched
to the OFF-state by changing the gate control signal C2 from +1 V
to -3 V.
[0047] In order to reduce charge injection via the charge injection
control transistors 401, 403, 405 and 407 to the nodes 103, 105 and
107 that may occur when the charge injection control transistors
401, 403, 405 and 407 are switched OFF, the capacitances between
the gate nodes and the channel nodes of the charge injection
control transistors should be made smaller than the capacitances
between the gate nodes and the channel nodes of the switching
transistors. This may be accomplished by making the widths of the
charge injection control transistors smaller than the widths of the
switching transistors. For example, if the charge injection control
transistors have a width Wc that is 0.1 times as large as a width
Ws of the switching transistors, the charge injection magnitude
will be smaller by a factor of approximately 0.1. At this level,
the charge injection will be sufficiently small to not degrade
performance for an SOI RF switch such the exemplary SOI RF switch
400.
[0048] Some advantages of using charge injection control
transistors, rather than charge injection control resistors, are
reduced switching time and improved switch isolation.
Charge Injection Control Method
[0049] In FIG. 5 a charge injection control method 500 is
represented by a flow chart diagram. The method begins at a STEP
502, wherein charge injection is caused to occur at resistively
isolated nodes of a circuit. In one embodiment, charge injection is
generated in an SOI RF switch including stacked switching
transistors when the RF switch is switched from an ON-state to an
OFF-state. In this embodiment, the charge injection occurs at
resistively-isolated nodes located between the switching
transistors.
[0050] At a STEP 504, the injected charge is conveyed via charge
injection control elements from the resistively-isolated nodes to
at least one node that is not resistively-isolated. In one
embodiment, the charge injection control elements may comprise
charge injection control resistors. For this embodiment, the method
stops at the STEP 504.
[0051] At an optional STEP 506, the charge injection control
elements are switched from an ON-state to an OFF-state following a
selected time delay interval after the switching transistors are
switched from the ON-state to the OFF-state. For example, the STEP
506 is implemented in an embodiment wherein the charge injection
control elements comprise charge injection control transistors.
Pulse Method for Controlling Accumulated Charge
[0052] As disclosed in U.S. application Ser. No. 11/484,370, filed
Jul. 10, 2006, pending, and in U.S. application Ser. No.
11/520,912, filed Sep. 14, 2006, filed Sep. 15, 2005, both
incorporated by reference hereinabove, accumulated charge can occur
in MOSFET devices that are used in SOI RF switches. A MOSFET device
is defined as operating within an "accumulated charge regime" when
the MOSFET is biased to operate in an off-state, and when carriers
having opposite polarity to the channel carriers are present in the
channel region. Accumulated charge in the channel region can
degrade the performance of MOSFETs used in SOI RF switches. In
particular, the accumulated charge can cause harmonic generation in
RF signals and degrade the gate oxide reliability of a MOSFET
device.
[0053] Accumulated charge in an n-channel MOSFET results from a
slow electron-hole pair generation process that occurs when a gate
voltage Vg is negative with respect to a source bias voltage Vs and
a drain bias voltage Vd. If a positive voltage pulse above a
threshold voltage Vth is applied to the gate terminal of the
MOSFET, a conducting channel comprising electrons is formed in the
body of the MOSFET, and the accumulated charge is dissipated due to
drift and recombination. When the gate voltage Vg returns to the
negative bias level present prior to the application of the
positive voltage pulse, the accumulated charge regenerates in a
time period having a time scale that is typically in the
millisecond range or longer. Consequently, the accumulated charge
in the MOSFET may be controlled by applying a series of positive
voltage pulses to the gate terminal. In one example, the pulse rate
may be selected by observing harmonic generation in an applied RF
signal, and selecting a pulse rate sufficiently high to prevent the
harmonic generation from exceeding a desired level.
[0054] As a practical effect of applying the pulse method of
controlling accumulated charge in an SOI RF switch, charge
injection will occur each time the switching transistors are
switched from an ON-state to an OFF-state. Consequently, the
teachings of the present disclosure for controlling charge
injection are also useful when used in conjunction with SOI RF
switch systems employing the pulse method for controlling
accumulated charge.
Embodiments Using Accumulated Charge Control (ACC) Switching
Transistors
[0055] Embodiments according to the present teachings may, in some
embodiments, use switching transistors (e.g., the switching
transistors 111, 113, 115 and 117 of FIGS. 1A, 2, 3 and 4) having
an accumulated charge sink (ACS) 610, as shown in FIGS. 6A-6D, and
as described in greater detail in U.S. application Ser. No.
11/484,370, filed Jul. 10, 2006, pending, incorporated by reference
hereinabove. For example, the switching transistors 111, 113, 115,
and 117 (see FIGS. 3-4 and associated description above) may, in
some embodiments, comprise accumulated charge control (ACC)
transistors described in the above-incorporated application Ser.
No. 11/484,370, filed Jul. 10, 2006, and shown in FIGS. 6A-6D. In
another embodiment, the switching transistors 111, 113, 115, and
117 may comprise ACC transistors operated according to the pulse
method for controlling accumulated charge, as described above and
as described in greater detail in the above-incorporated
application Ser. No. 11/520,912, filed Sep. 14, 2006.
[0056] As shown in FIGS. 6A-6D, in an improved ACC SOI NMOSFET 600,
a gate terminal 602 is electrically coupled to a gate 601, a source
terminal 604 is electrically coupled to a source 603, and a drain
terminal 606 is electrically coupled to a drain 605. Finally, the
ACC MOSFET 600 includes an ACS terminal 608 that is electrically
coupled to the ACS 610.
[0057] The ACC SOI NMOSFET 600 may be operated using various
techniques and implemented in various circuits in order to control
accumulated charge present in the FET when it is operating in an
accumulated charge regime. For example, in one exemplary embodiment
as shown in FIG. 6B, the gate and ACS terminals, 602 and 608,
respectively, are electrically coupled together. In one embodiment
of the simplified circuit shown in FIG. 6B, the source and drain
bias voltages applied to the terminals 604 and 606, respectively,
may be zero. If the gate bias voltage (Vg) applied to the gate
terminal 602 is sufficiently negative with respect to the source
and drain bias voltages (Vs and Vd, respectively) applied to the
terminals 604 and 606, and with respect to the threshold voltage
V.sub.th, (for example, if V.sub.th is approximately zero, and if
Vg is more negative than approximately -1 V) the ACC NMOSFET 600
operates in the accumulated charge regime. When the MOSFET operates
in this regime, accumulated charge (holes) may accumulate in the
NMOSFET 600.
[0058] Advantageously, the accumulated charge can be removed via
the ACS terminal 608 by connecting the ACS terminal 608 to the gate
terminal 602 as shown in FIG. 6B. This configuration ensures that
when the FET 600 is operated in the OFF-state, it is held in the
correct bias region to effectively remove or otherwise control the
accumulated charge. As shown in FIG. 6B, connecting the ACS
terminal 608 to the gate ensures that the same bias voltages are
applied to both the gate (Vg) and the ACS 610 (V.sub.ACS). The
accumulated charge is thereby removed from the SOI NMOSFET 600 via
the ACS terminal 608.
[0059] In other exemplary embodiments, as described with reference
to FIG. 6C, for example, Vs and Vd may comprise nonzero bias
voltages. According to these examples, Vg must be sufficiently
negative to both Vs and Vd in order for Vg to be sufficiently
negative to V.sub.th to turn the NMOSFET 600 OFF (i.e., operate the
NMOSFET 600 in the OFF-state). When so biased, as described above,
the NMOSFET 600 may enter the accumulated charge regime. For this
example, the voltage V.sub.ACS may also be selected to be equal to
Vg by connecting the ACS terminal 608 to the gate terminal 602,
thereby conveying the accumulated charge from the ACC NMOSFET, as
described above.
[0060] Another exemplary simplified circuit using the improved ACC
SOI NMOSFET 600 is shown in FIG. 6C. As shown in FIG. 6C, in this
embodiment, the ACS terminal 608 may be electrically coupled to a
diode 610, and the diode 610 may, in turn, be coupled to the gate
terminal 602. This embodiment may be used to prevent a positive
current flow into the ACS 610 caused by a positive Vg-to-Vs (or,
equivalently, Vgs, where Vgs=Vg -Vs) bias voltage, as may occur,
for example, when the SOI NMOSFET 300 is biased into an ON-state
condition.
[0061] As with the device shown in FIG. 6B, when biased OFF, the
ACS terminal 608 voltage V.sub.ACS comprises the gate voltage plus
a voltage drop across the diode 610. At very low ACS terminal 610
current levels, the voltage drop across the diode 610 typically
also is very low (e.g., <<500 mV, for example, for a typical
threshold diode).
[0062] When the SOI NMOSFET 600 is biased in an ON-state condition,
the diode 610 is reverse-biased, thereby preventing the flow of
positive current into the source and drain regions. The
reverse-biased configuration reduces power consumption and improves
linearity of the device. The circuit shown in FIG. 6C therefore
works well to remove the accumulated charge when the FET is in the
OFF-state and is operated in the accumulated charge regime. It also
permits almost any positive voltage to be applied to the gate
voltage Vg. This, in turn, allows the ACC MOSFET to effectively
remove accumulated charge when the device operates in the
OFF-state, yet assume the characteristics of a floating body device
when the device operates in the ON-state.
[0063] With the exception of the diode 610 used to prevent the flow
of positive current into the ACS terminal 608, exemplary operation
of the simplified circuit shown in FIG. 6C is the same as the
operation of the circuit described above with reference to FIG.
6B.
[0064] In yet another embodiment, the ACS terminal 608 may be
coupled to a control circuit 612 as illustrated in the simplified
circuit of FIG. 6D. The control circuit 612 may provide a
selectable ACS bias voltage V.sub.ACS that selectively controls the
accumulated charge.
Method of Fabrication
[0065] With varying performance results, RF switches have
heretofore been implemented in different component technologies,
including bulk complementary-metal-oxide-semiconductor (CMOS) and
gallium-arsenide (GaAs) technologies. In fact, most
high-performance high-frequency switches use GaAs technology.
[0066] Although GaAs RF switch implementations offer improved
performance characteristics relative to bulk CMOS, the technology
has several disadvantages. For example, GaAs technology exhibits
relatively low yields of properly functioning integrated circuits.
GaAs RF switches tend to be relatively expensive to design and
manufacture. In addition, although GaAs switches exhibit improved
insertion loss characteristics as described above, they may have
low frequency limitations due to slow states present in the GaAs
substrate. The technology also does not lend itself to high levels
of integration, which requires that digital control circuitry
associated with the RF switch be implemented "off chip" from the
switch. The low power control circuitry associated with the switch
has proven difficult to integrate. This is disadvantageous as it
both increases the overall system cost or manufacture, size and
complexity, as well as reducing system throughput speeds.
[0067] In one embodiment of the present disclosure, the exemplary
circuits described hereinabove are implemented using a fully
insulating substrate silicon-on-insulator (SOI) technology. More
specifically, the MOSFET transistors of the present disclosure are
implemented using "Ultra-Thin-Silicon (UTSi)" (also referred to
herein as "ultrathin silicon-on-sapphire") technology. In
accordance with UTSi manufacturing methods, the transistors used to
implement the inventive RF switch are formed in an extremely thin
layer of silicon in an insulating sapphire wafer. The fully
insulating sapphire substrate enhances the performance
characteristics of the inventive RF switch by reducing the
deleterious substrate coupling effects associated with
non-insulating and partially insulating substrates. For example,
improvements in insertion loss are realized by lowering the
transistor ON-state resistances and by reducing parasitic substrate
conductances and capacitances. In addition, switch isolation is
improved using the fully insulating substrates provided by UTSi
technology. Owing to the fully insulating nature of
silicon-on-sapphire technology, the parasitic capacitance between
the nodes of the RF switches are greatly reduced as compared with
bulk CMOS and other traditional integrated circuit manufacturing
technologies.
Silicon on Insulator RF Integrated Circuits
[0068] As is well known, SOI has been used in the implementation of
high performance microelectronic devices, primarily in applications
requiring radiation hardness and high speed operation. SOI
technologies include, for example, SIMOX, bonded wafers having a
thin silicon layer bonded to an insulating layer, and
silicon-on-sapphire. In order to achieve the desired RF switch
performance characteristics described hereinabove, in one
embodiment, the inventive RF switch is fabricated on a sapphire
substrate.
[0069] Fabrication of devices on an insulating substrate requires
that an effective method for forming silicon CMOS devices on the
insulating substrate be used. The advantages of using a composite
substrate comprising a monocrystalline semiconductor layer, such as
silicon, epitaxially deposited on a supporting insulating
substrate, such as sapphire, are well-recognized, and can be
realized by employing as the substrate an insulating material, such
as sapphire (Al.sub.2O.sub.3), spinel, or other known highly
insulating materials, and providing that the conduction path of any
inter-device leakage current must pass through the substrate.
[0070] An "ideal" SOI wafer can be defined to include a completely
monocrystalline, defect-free silicon layer of sufficient thickness
to accommodate the fabrication of active devices therein. The
silicon layer would be adjacent to an insulating substrate and
would have a minimum of crystal lattice discontinuities at the
silicon-insulator interface. Early attempts to fabricate this
"ideal" silicon-on-insulator wafer were frustrated by a number of
significant problems, which can be summarized as (1) substantial
incursion of contaminants into the epitaxially deposited silicon
layer, especially the p-dopant aluminum, as a consequence of the
high temperatures used in the initial epitaxial silicon deposition
and the subsequent annealing of the silicon layer to reduce defects
therein; and (2) poor crystalline quality of the epitaxial silicon
layers when the problematic high temperatures were avoided or
worked around through various implanting, annealing, and/or
re-growth schemes.
[0071] It has been found that the high quality silicon films
suitable for demanding device applications can be fabricated on
sapphire substrates by a method that involves epitaxial deposition
of a silicon layer on a sapphire substrate, low temperature ion
implant to form a buried amorphous region in the silicon layer, and
annealing the composite at temperatures below about 950 degrees
C.
[0072] Examples of and methods for making such silicon-on-sapphire
devices are described in U.S. Pat. Nos. 5,416,043 ("Minimum charge
FET fabricated on an ultrathin silicon on sapphire wafer");
5,492,857 ("High-frequency wireless communication system on a
single ultrathin silicon on sapphire chip"); 5,572,040
("High-frequency wireless communication system on a single
ultrathin silicon on sapphire chip"); 5,596,205 ("High-frequency
wireless communication system on a single ultrathin silicon on
sapphire chip"); 5,600,169 ("Minimum charge FET fabricated on an
ultrathin silicon on sapphire wafer"); 5,663,570 ("High-frequency
wireless communication system on a single ultrathin silicon on
sapphire chip"); 5,861,336 ("High-frequency wireless communication
system on a single ultrathin silicon on sapphire chip"); 5,863,823
("Self-aligned edge control in silicon on insulator"); 5,883,396
("High-frequency wireless communication system on a single
ultrathin silicon on sapphire chip"); 5,895,957 ("Minimum charge
FET fabricated on an ultrathin silicon on sapphire wafer");
5,920,233 ("Phase locked loop including a sampling circuit for
reducing spurious side bands"); 5,930,638 ("Method of making a low
parasitic resistor on ultrathin silicon on insulator"); 5,973,363
("CMOS circuitry with shortened P-channel length on ultrathin
silicon on insulator"); 5,973,382 ("Capacitor on ultrathin
semiconductor on insulator"); and 6,057,555 ("High-frequency
wireless communication system on a single ultrathin silicon on
sapphire chip"). All of these referenced patents are incorporated
herein in their entirety for their teachings on ultrathin
silicon-on-sapphire integrated circuit design and fabrication.
[0073] Using the methods described in the patents referenced above,
electronic devices can be formed in an extremely thin layer of
silicon on an insulating synthetic sapphire wafer. The thickness of
the silicon layer is typically less than 150 nm. Such an
"ultrathin" silicon layer maximizes the advantages of the
insulating sapphire substrate and allows the integration of
multiple functions on a single integrated circuit. Traditional
transistor isolation wells required for thick silicon are
unnecessary, simplifying transistor processing and increasing
circuit density. To distinguish these above-referenced methods and
devices from earlier thick-silicon embodiments, they are herein
referred to collectively as "ultrathin silicon-on-sapphire."
[0074] In some embodiments of the present disclosure, the MOS
transistors may be formed in ultrathin silicon-on-sapphire wafers
by the methods disclosed in U.S. Pat. Nos. 5,416,043; 5,492,857;
5,572,040; 5,596,205; 5,600,169; 5,663,570; 5,861,336; 5,863,823;
5,883,396; 5,895,957; 5,920,233; 5,930,638; 5,973,363; 5,973,382;
and 6,057,555. However, other known methods of fabricating
silicon-on-sapphire integrated circuits can be used without
departing from the spirit or scope of the present teachings.
[0075] A number of embodiments of the present inventive concept
have been described.
[0076] Nevertheless, it will be understood that various
modifications may be made without departing from the scope of the
inventive teachings. For example, it should be understood that many
types of switch circuits (e.g., single-pole single-throw,
single-pole double-throw, double-throw-pole double-throw, etc.) may
be used according to the present teachings. In another example, it
should be noted that although embodiments having SOI RF switches
have been used herein for exemplary purposes, persons skilled in
the electronic arts will understand that the present teachings may
be applied to many other types of switching circuits having
isolated nodes wherein charge injection may occur.
[0077] Accordingly, it is to be understood that the inventive
concept is not to be limited by the specific illustrated
embodiments, but only by the scope of the appended claims. The
description may provide examples of similar features as are recited
in the claims, but it should not be assumed that such similar
features are identical to those in the claims unless such identity
is essential to comprehend the scope of the claim. In some
instances the intended distinction between claim features and
description features is underscored by using slightly different
terminology.
* * * * *