U.S. patent application number 11/513183 was filed with the patent office on 2008-03-06 for vertical semiconductor light-emitting device and method of manufacturing the same.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Jae-Hee Cho, Hyun-Soo Kim, Kyu-Ho Shin.
Application Number | 20080054291 11/513183 |
Document ID | / |
Family ID | 39150251 |
Filed Date | 2008-03-06 |
United States Patent
Application |
20080054291 |
Kind Code |
A1 |
Kim; Hyun-Soo ; et
al. |
March 6, 2008 |
Vertical semiconductor light-emitting device and method of
manufacturing the same
Abstract
Provided is a vertical semiconductor light-emitting device and a
method of manufacturing the same. The method may include
sequentially forming a lower clad layer, an active layer, and an
upper clad layer on a substrate to form a semiconductor layer and
forming first electrode layers on the upper clad layer. A metal
support layer may be formed on each of the first electrode layers
and a trench may be formed between the first electrode layers. The
substrate may be removed and a second electrode layer may be formed
on the lower clad layer.
Inventors: |
Kim; Hyun-Soo; (Hwaseong-si,
KR) ; Shin; Kyu-Ho; (Seoul, KR) ; Cho;
Jae-Hee; (Yongin-si, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
|
Family ID: |
39150251 |
Appl. No.: |
11/513183 |
Filed: |
August 31, 2006 |
Current U.S.
Class: |
257/103 ;
257/E33.034; 438/46 |
Current CPC
Class: |
H01S 5/183 20130101;
B82Y 20/00 20130101; H01S 5/0217 20130101; H01L 33/0093 20200501;
H01S 5/34333 20130101 |
Class at
Publication: |
257/103 ; 438/46;
257/E33.034 |
International
Class: |
H01L 33/00 20060101
H01L033/00; H01L 21/00 20060101 H01L021/00 |
Claims
1. A method of manufacturing a vertical semiconductor
light-emitting device, the method comprising: sequentially forming
a lower clad layer, an active layer, and an upper clad layer on a
substrate to form a semiconductor layer; forming first electrode
layers on the upper clad layer; forming a metal support layer on
each of the first electrode layers and forming a trench between the
first electrode layers; and removing the substrate and forming a
second electrode layer on the lower clad layer.
2. The method of claim 1, wherein the substrate is a sapphire
substrate.
3. The method of claim 1, wherein the lower clad layer and the
upper clad layer include a nitrification gallium-based
material.
4. The method of claim 1, wherein the active layer is formed of
multi quantum wall (MQW) structure of InGaN/GaN.
5. The method of claim 1, wherein forming the metal support layer
includes: forming a seed layer on the upper clad layer and on a
surface of each of the first electrode layers; forming a
photoresist (PR) layer on the seed layer between the first
electrode layers; forming a metal support layer on the seed layer
corresponding to each of the first electrode layers; and removing
the PR layer and forming a trench in a region from which the PR
layer is removed.
6. The method of claim 5, wherein the trench is formed using a
reactive ion etching (RIE) process.
7. The method of claim 1, wherein removing the substrate and the
forming of the second electrode layer includes: forming a filling
layer including an adhesion material on the trench region and on
the surface of each of the metal support layers; attaching one of
glass, silicon (Si) or sapphire onto the filling layer to form a
bonding layer; and removing the substrate.
8. The method of claim 7, wherein the filling layer is formed of
wax.
9. The method of claim 7, wherein the filling layer is removed
using acetone.
10. The method of claim 1, wherein the substrate is separated from
the lower clad layer by irradiating laser light having a wavelength
less than about 370 nm.
11. The method of claim 7, wherein the substrate is separated from
the lower clad layer by irradiating laser light having a wavelength
less than about 370 nm.
12. The method of claim 1, wherein the second electrode layer is an
n-type conductive material.
13. The method of claim 1, wherein the metal support layer is
formed using plasma vapor deposition (PVD) or chemical vapor
deposition (CVD).
14. A vertical semiconductor light-emitting device, comprising: a
first electrode layer on a semiconductor layer; a seed layer and a
metal support layer on the first electrode layer; a second
electrode layer below the semiconductor layer; and an insulating
support layer that separates the vertical semiconductor
light-emitting device from another vertical semiconductor
light-emitting device.
15. The vertical semiconductor light-emitting device of claim 14,
wherein the semiconductor layer includes a lower clad layer, an
active layer and an upper clad layer.
16. The vertical semiconductor light-emitting device of claim 14,
wherein the second electrode layer is an n-type conductive
material.
17. The vertical semiconductor light-emitting device of claim 14,
wherein the first electrode layer is made of a p-metal.
18. The vertical semiconductor light-emitting device of claim 14,
wherein the metal support layer is made of one of the group
including Cu, Cr, Ni, Ag, Au, Mo, Pd, W and Al.
19. The vertical semiconductor light-emitting device of claim 14,
wherein the seed layer is used to form the metal support layer and
is made of one of the group including Cr, Ti, Au and Ni.
20. The vertical semiconductor light-emitting device of claim 14,
wherein the insulating support layer is an adhesive polymer film.
Description
BACKGROUND
[0001] 1. Field
[0002] Example embodiments relate to a semiconductor light-emitting
device. Other example embodiments relate to a method of
manufacturing a vertical semiconductor light-emitting device by a
simpler process in which yield is improved.
[0003] 2. Description of the Related Art
[0004] In general, light emitting diodes (LED) may be used to
transmit a signal obtained by converting electrical energy into the
shape of infra rays, visible rays and/or light using properties of
a compound semiconductor. LED may be a type of electroluminescent
(EL) devices. LED using a Group III-V compound semiconductor have
been used.
[0005] Group III nitride-based compound semiconductors may be
direct transition type semiconductors. A relatively stable
operation may be performed at higher temperatures than in devices
using semiconductors other than Group III nitride-based compound
semiconductors. The Group III nitride-based compound semiconductors
have been used in light-emitting devices (e.g., an LED and/or a
laser diode (LD)). Group III nitride-based compound semiconductors
may be formed on a substrate formed of sapphire
(Al.sub.2O.sub.3).
[0006] FIG. 1 illustrates a conventional semiconductor
light-emitting device. Referring to FIG. 1, a lower clad layer 12,
an active layer 13 and an upper clad layer 14 may be sequentially
formed on a substrate 11 formed of sapphire. An upper electrode
layer 15 may be formed on the upper clad layer 14 and a lower
electrode layer 16 may be formed on a region of the lower clad
layer 12 in which the active layer 13 is not formed. For a
GaN-based light-emitting device, the lower clad layer 12 may be
formed of n-GaN, the active layer 13 may be formed of a multi
quantum wall (MQW) structure of InGaN/GaN, and the upper clad layer
14 may be formed of p-GaN. The upper electrode layer 15 may include
a contact layer containing a transparent conductive material (e.g.,
indium tin oxide (ITO), Ru/Au and/or Ni/Au) and a pad structure
containing Au formed on a portion of an upper region of the contact
layer. Ti/Al may be used in the lower electrode layer 16.
[0007] The lower electrode layer 16 and the upper electrode layer
15 may be formed on one surface of the substrate 11 and may have
difficulty applying a potential when a light-emitting surface may
be relatively narrow. Because current applied to the active layer
13 through the lower electrode layer 16 may pass through the lower
clad layer 12 disposed below the lower electrode layer 16, the
structure may not be desirable. A vertical semiconductor
light-emitting device may have improved characteristics compared to
the above-described horizontal semiconductor light-emitting device
illustrated in FIG. 1. Because the substrate may be removed, the
lower electrode layer 16 may be formed below the lower clad layer
12. A light-emitting area may be increased and heat dissipation may
be more smoothly performed.
[0008] FIGS. 2A-2H illustrate a conventional method of
manufacturing a vertical semiconductor light-emitting device.
Referring to FIG. 2A, an n-GaN buffer layer 124, an InGaN/GaN
active layer 126 and a p-GaN contact layer 128 may be sequentially
formed on a sapphire substrate 122. Referring to FIG. 2B, trenches
130 may be formed through the p-GaN contact layer 128 exposing the
surface of the sapphire substrate 122. The trenches 130 may serve
to assist a subsequent chip separation process.
[0009] Referring to FIG. 2C, a contact layer 150 may be formed of a
material selected from the group including Pt/Au, Pd/Au, Ru/Au and
Ni/Au. The contact layer 150 may be formed on the p-GaN contact
layer 128. Referring to FIG. 2D, the trenches 130 may be filled
with a photoresist (PR) 154. Referring to FIG. 2E, a metal support
layer 156 may be formed by applying Cu, Cr, Ni, Au and/or Ag onto
the contact layer 150. The metal support layer 156 may be formed by
a dicing process. The metal (e.g., Cu) may be relatively ductile
and thus, the dicing process may not be easily performed. Referring
to FIG. 2F, the sapphire substrate 122 may be removed by
irradiating laser light 158 using an excimer laser. Referring to
FIG. 2G, the PR 154 may be removed. Referring to FIG. 2H, an n-type
ohmic contact layer 160 may be formed on the n-GaN buffer layer 124
using Ti/Al.
SUMMARY
[0010] Example embodiments relate to a semiconductor light-emitting
device. Other example embodiments relate to a method of
manufacturing a vertical semiconductor light-emitting device by a
simpler process in which yield is improved.
[0011] According to example embodiments, a method of manufacturing
a vertical semiconductor light-emitting device may include
sequentially forming a lower clad layer, an active layer, and an
upper clad layer on a substrate to form a semiconductor layer.
First electrode layers may be formed on the upper clad layer, a
metal support layer may be formed on each of the first electrode
layers and a trench may be formed between the first electrode
layers. The substrate may be removed and a second electrode layer
may be formed on the lower clad layer. The substrate may be a
sapphire substrate. The lower clad layer and the upper clad layer
may include a nitrification gallium-based material. The active
layer may be formed of multi quantum wall (MQW) structure of
InGaN/GaN.
[0012] The forming of the metal support layer may include forming a
seed layer on the upper clad layer and on a surface of each of the
first electrode layers. A photoresist (PR) layer may be formed on
the seed layer between the first electrode layers. A metal support
layer may be formed on the seed layer corresponding to each of the
first electrode layers and the PR layer may be removed which may
form a trench in a region from which the PR layer is removed. The
trench may be formed using a reactive ion etching (RIE)
process.
[0013] The removing of the substrate and the forming of the second
electrode layer may include forming a filling layer including an
adhesion material on the trench region and on the surface of each
of the metal support layers, attaching one of glass, silicon (Si)
or sapphire onto the filling layer to form a bonding layer and
removing the substrate. The filling layer may be formed of wax and
may be removed using acetone. The substrate may be separated from
the lower clad layer by irradiating laser light having a wavelength
less than about 370 nm. The second electrode layer may be an n-type
conductive material. The metal support layer may be formed using
plasma vapor deposition (PVD) and/or chemical vapor deposition
(CVD).
[0014] According to example embodiments, a vertical semiconductor
light-emitting device may include a first electrode layer on a
semiconductor layer, a seed layer and a metal support layer on the
first electrode layer, a second electrode layer below the
semiconductor layer and an insulating support layer that separates
the vertical semiconductor light-emitting device from another
vertical semiconductor light-emitting device. The semiconductor
layer may be formed of a lower clad layer, an active layer and an
upper clad layer. The second electrode layer may be made of an
n-type conductive material. The first electrode layer may be made
of a p-metal. The metal support layer may be made of one of the
group including Cu, Cr, Ni, Ag, Au, Mo, Pd, W and/or Al. The seed
layer may be used to form the metal support layer and may be made
of one of the group including Cr, Ti, Au and/or Ni. The insulating
support layer may be an adhesive polymer film (e.g.,
polycarbonate).
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Example embodiments will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings. FIGS. 1-5C represent non-limiting, example
embodiments as described herein.
[0016] FIG. 1 illustrates a conventional semiconductor
light-emitting device;
[0017] FIGS. 2A-2H illustrate a conventional method of
manufacturing a vertical semiconductor light-emitting device;
[0018] FIG. 3 illustrates a structure of a vertical semiconductor
light-emitting device according to example embodiments;
[0019] FIGS. 4A-4I illustrate a method of manufacturing a vertical
semiconductor light-emitting device according to example
embodiments; and
[0020] FIGS. 5A-5C show images formed during the method of
manufacturing a vertical semiconductor light-emitting device
illustrated in FIGS. 4A-4I.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0021] Example embodiments will now be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments are shown. Example embodiments may, however,
be embodied in many different forms and should not be construed as
being limited to the embodiments set forth herein. Rather, these
embodiments are provided so that this disclosure will be thorough
and complete, and will fully convey the scope of example
embodiments to those skilled in the art. In the drawings, the
thicknesses of layers and regions are exaggerated for clarity. Like
reference numerals refer to like elements throughout the
specification.
[0022] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. It
will be understood that the spatially relative terms are intended
to encompass different orientations of the device in use or
operation in addition to the orientation depicted in the figures.
For example, if the device in the figures is turned over, elements
described as "below" or "beneath" other elements or features would
then be oriented "above" the other elements or features. The
example term "below" can encompass both an orientation of above and
below. The device may be otherwise oriented (rotated 90.degree. or
at other orientations) and the spatially relative descriptors used
herein interpreted accordingly.
[0023] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments. As used herein, the singular forms "a", "an"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises", "comprising,", "includes"
and/or "including", when used herein, specify the presence of
stated features, integers, steps, operations, elements and/or
components, but do not preclude the presence or addition of one or
more other features, integers, steps, operations, elements,
components and/or groups thereof.
[0024] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which example
embodiments belong. It will be further understood that terms, such
as those defined in commonly used dictionaries, should be
interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and will not be
interpreted in an idealized or overly formal sense unless expressly
so defined herein.
[0025] FIG. 3 illustrates a structure of a vertical semiconductor
light-emitting device according to example embodiments. Referring
to FIG. 3, a first electrode layer 36 may be formed on a
semiconductor layer 32, and a seed layer 41 and a metal support
layer 37 may be sequentially formed on the first electrode layer
36. A second electrode layer 38 may be formed below the
semiconductor layer 32. An insulating support layer 39 may be
formed to separate vertical semiconductor light-emitting devices
from one another. The insulating support layer 39 may be an
adhesive polymer film (e.g., polycarbonate).
[0026] A method of manufacturing a vertical semiconductor
light-emitting device according to example embodiments will now be
described with reference to FIGS. 4A-4I. Referring to FIG. 4A, a
compound semiconductor layer may be formed on a sapphire substrate
31. In detail, a lower clad layer 33, an active layer 34, and an
upper clad layer 35 may be sequentially formed on the sapphire
substrate 31. For example, the lower clad layer 33 may be formed of
n-GaN, the active layer 34 may be formed of multi quantum wall
(MOW) structure of InGaN/GaN, and the upper clad layer 35 may be
formed of p-GaN. The lower clad layer 33, the active layer 34, and
the upper clad layer 35 may be referred to as a semiconductor layer
32.
[0027] Referring to FIG. 4B, a first electrode layer 36 may be
formed on the semiconductor layer 32. The first electrode layer 36
may be formed of a p-metal. The first electrode layer 36 may be
formed by applying metal (e.g., Ni/Ag and/or Ru) using a process,
for example, sputtering and/or evaporation.
[0028] Referring to FIGS. 4C and 4D, a seed layer 41 may be formed
on the first electrode layer 36 and the semiconductor layer 32. The
seed layer 41 may be used to form a metal support layer 37 of FIG.
4E. The seed layer 41 may be formed of metal (e.g., Cr, Ti, Au
and/or Ni) at a relatively small thickness of several tens of nm. A
photoresist (PR) layer 42 having a thickness of several to several
tens of micrometers may be formed by applying and patterning a
photoresist (PR) onto a region of the seed layer 41 in which the
first electrode layer 36 is not formed. FIG. 5A is plan view in
which the seed layer 41 may be formed of Cr having a thickness of
about 100 nm and the PR layer 42 having a thickness of about 5
micrometers may be formed, in an upward direction of FIG. 4D.
[0029] Referring to FIG. 4E, the metal support layer 37 may be
formed by applying metal (e.g., Cu, Cr, Ni, Ag, Au, Mo, Pd, W
and/or Al) onto the exposed region of the seed layer 41. The metal
support layer 37 may be formed using plasma vapor deposition (PVD)
and/or chemical vapor deposition (CVD), for example, sputtering,
electroplating and/or an electroless plating process. The PR layer
42 may be removed. In FIG. 4E, an end portion of an upper surface
of the metal support layer 37 may be angled. The end portion of the
upper surface of the metal support layer 37 may be formed in the
form of a mushroom which is an actual image illustrated in FIG. 5B.
By removing the PR layer 42, there may be a step difference between
an end portion of a metal support layer 51 and a seed layer 52
formed below the metal support layer 51, as illustrated in FIG.
5C.
[0030] As seen in FIG. 5C, in a conventional method of
manufacturing a vertical semiconductor light-emitting device, a Cu
plate may be formed on a p-type electrode so that a dicing process
may be performed to form a unit device in a subsequent process. In
the method of manufacturing a vertical semiconductor light-emitting
device according to example embodiments, the metal support layers
37 may be separated from one another according to unit devices. A
subsequent additional dicing process of the metal support layer 37
may not be needed
[0031] Referring to FIG. 4F, a trench 43 may be formed between the
metal support layers 37 to expose the substrate 31. The width of
the trench 43 may be greater than several micrometers. The trench
43 may be formed using reactive ion etching, for example,
inductively coupled plasma reactive ion etching (ICP-RIE) process.
An additional mask may not be needed in a process of forming the
trench 43.
[0032] Referring to FIG. 4G, the trench 43 and the surface of the
metal support layer 37 may be filled with a wax having an improved
adhesion property, thereby forming a filling layer 44. Glass,
silicon (Si) and/or sapphire may be attached to the filling layer
44 and may be heated to about 150.degree. C., forming a bonding
layer 45. The bonding layer 45 may be used to fix a device when the
sapphire substrate 31 is removed in a subsequent process.
[0033] Referring to FIG. 4H, the substrate 31 disposed below the
semiconductor layer 32 may be removed. A laser lift-off (LLO)
process, using laser light having a wavelength less than about 370
nanometers, may be used. Heat may be generated between the sapphire
substrate 31 and the semiconductor layer 32 by irradiating a laser
light. A GaN semiconductor material, at a boundary between the
substrate 31 and the semiconductor layer 32, may be decomposed so
that the substrate 31 and the semiconductor layer 32 may be easily
separated from each other. The separated semiconductor layer 32 may
be planarized using a chemical mechanical polishing (CMP) and/or
ICP-RIE polishing process.
[0034] Referring to FIG. 4I, a second electrode layer 38 may be
formed on a bottom surface of the semiconductor layer 32. The
second electrode layer 38 may be formed of an n-type conductive
material and may include Ti/Al, Ti/Cu and/or Ti/Ni. After a support
layer 39 is formed below the second electrode layer 38 and the
semiconductor layer 32, the filling layer 44 may be removed using
acetone. The support layer 39 may be easily separated from the
second electrode layer 38 and the semiconductor layer 32.
Accordingly, a vertical semiconductor laser diode may be more
easily formed in a unit device.
[0035] When a metal support layer is formed of Cu, a dicing process
of the metal support layer may not need to be performed in order to
form a unit device in a subsequent process. Structural stability of
a light-emitting device may be sought and a relatively high yield
may be obtained. Also, an additional mask may not be needed during
a process of forming a trench. There may be no process that induces
stress inside the semiconductor light-emitting device and
relatively high productivity may be obtained with a relatively
simple process.
[0036] While example embodiments have been particularly shown and
described with reference to example embodiments thereof, it will be
understood by those skilled in the art that various changes in form
and details may be made therein without departing from the spirit
and scope of the following claims.
* * * * *