U.S. patent application number 11/876585 was filed with the patent office on 2008-02-21 for semiconductor devices and methods of fabricating the same.
Invention is credited to Atsushi KANDA.
Application Number | 20080042298 11/876585 |
Document ID | / |
Family ID | 26503889 |
Filed Date | 2008-02-21 |
United States Patent
Application |
20080042298 |
Kind Code |
A1 |
KANDA; Atsushi |
February 21, 2008 |
SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Abstract
Embodiments include a semiconductor device comprising: a pad
formed on an insulating layer and having an electric connection
region with external components; and a protective insulating layer
which has an aperture for exposing the electric connection region.
The protective insulating layer may include a first insulating
layer and a second insulating layer, and side surfaces of these
insulating layers are exposed to the aperture. At least part of the
side surfaces surrounding the electric connection region have a
tapered configuration at an acute angle to a top surface of the
pad. This semiconductor device not only enables reduction of the
fabrication steps, but also provides a reliable passivation
structure for a pad with sufficient thickness and stress relaxation
characteristics.
Inventors: |
KANDA; Atsushi; (Sakata-shi,
JP) |
Correspondence
Address: |
KONRAD RAYNES & VICTOR, LLP
315 S. BEVERLY DRIVE
# 210
BEVERLY HILLS
CA
90212
US
|
Family ID: |
26503889 |
Appl. No.: |
11/876585 |
Filed: |
October 22, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10962735 |
Oct 12, 2004 |
7285863 |
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11876585 |
Oct 22, 2007 |
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09607219 |
Jun 30, 2000 |
6818539 |
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10962735 |
Oct 12, 2004 |
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Current U.S.
Class: |
257/774 ;
257/E21.578 |
Current CPC
Class: |
H01L 2924/01078
20130101; H01L 2224/05599 20130101; H01L 2924/1305 20130101; H01L
2924/13091 20130101; H01L 24/05 20130101; H01L 2924/01004 20130101;
H01L 2924/01024 20130101; H01L 2224/13144 20130101; H01L 2924/01013
20130101; H01L 2924/01005 20130101; H01L 2924/00014 20130101; H01L
24/11 20130101; H01L 24/03 20130101; H01L 2224/13099 20130101; H01L
2224/05073 20130101; H01L 2924/01074 20130101; H01L 2924/01046
20130101; H01L 2224/05624 20130101; H01L 24/13 20130101; H01L
2924/01022 20130101; H01L 2924/05042 20130101; H01L 2224/04073
20130101; H01L 2924/01079 20130101; H01L 2924/01018 20130101; H01L
2924/01006 20130101; H01L 2224/0401 20130101; H01L 2924/01014
20130101; H01L 2924/01033 20130101; H01L 2224/05624 20130101; H01L
2924/00014 20130101; H01L 2924/14 20130101; H01L 2924/00 20130101;
H01L 2924/00014 20130101; H01L 2924/1305 20130101; H01L 2224/05599
20130101 |
Class at
Publication: |
257/774 ;
257/E21.578 |
International
Class: |
H01L 23/522 20060101
H01L023/522 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 1999 |
JP |
11-186638 |
May 31, 2000 |
JP |
2000-162322 |
Claims
1. A bonding pad structure comprising: a bonding pad formed over a
portion of a substrate area; and an insulating layer on the bonding
pad; the insulating layer including a first layer and a second
layer, the first layer positioned between the bonding pad and the
second layer, the second layer including a tapered side surface
having an acute angle to a surface of the bonding pad; the bonding
pad including an area that is uncovered by the insulating layer;
and the first layer including an upper surface region uncovered by
the second layer.
2. The semiconductor device of claim 1, wherein the first layer has
a tapered side surface having an acute angle to the surface of the
bonding pad, and the first layer tapered side surface acute angle
is greater than that of the second layer tapered side surface.
3. The semiconductor device of claim 1, wherein the distance
between an upper edge of the first layer and a lower edge of the
second layer tapered side surface is no greater than 3 .mu.m.
4. The semiconductor device of claim 1, wherein the distance
between an upper edge of the first layer and a lower edge of the
second layer tapered side surface is no greater than 1 .mu.m.
5. The semiconductor device of claim 1, wherein the bonding pad
includes a barrier layer positioned on the area that is uncovered
by the insulating layer.
6. The semiconductor device of claim 5, wherein the barrier layer
is also positioned on the second layer tapered side surface, and
wherein the barrier layer is also positioned on the first layer
upper surface region uncovered by the second layer.
7. The bonding pad structure of claim 1, the first layer has a
thickness that is less than that of the second layer.
8. A bonding pad structure comprising: a bonding pad formed over a
portion of a substrate area; and an insulating layer on the bonding
pad; the insulating layer including a first layer and a second
layer, the first layer positioned between the bonding pad and the
second layer, the first layer including a tapered side surface
having an acute angle to a surface of the bonding pad, the second
layer including a tapered side surface having an acute angle to a
surface of the bonding pad, the first layer tapered side surface
acute angle being greater than the second layer tapered side
surface acute angle; the bonding pad including an area that is
uncovered by the insulating layer; and the first layer including an
upper surface region uncovered by the second layer, the upper
surface region uncovered by the second layer extending a distance
between an upper end of the first layer tapered side surface and a
lower end of the second layer tapered side surface, the distance
being no greater than 3 .mu.m.
9. The semiconductor device of claim 8, wherein the distance is no
greater than 1 .mu.m.
10. The semiconductor device of claim 8, wherein the bonding pad
includes a barrier layer positioned on the area that is uncovered
by the insulating layer.
11. The bonding pad structure of claim 8, the first layer having a
thickness in the range of 400 nm to 600 nm, the second layer having
a thickness that is greater than that of the first layer and in the
range of 600 nm to 1400 nm.
12. A semiconductor device comprising: an electrode formed on a
bonding pad over a portion of a substrate area; and an insulating
layer surrounding a portion of the electrode; the insulating layer
including a first layer and a second layer, the first layer
positioned between the bonding pad and the second layer, the second
layer including a tapered side surface having an acute angle to a
surface of the bonding pad, the bonding pad including an area that
is uncovered by the insulating layer, the electrode formed on the
area, and the first layer including an upper surface region
uncovered by the second layer.
13. The semiconductor device of claim 12, wherein the first layer
has a tapered side surface having an acute angle to the surface of
the bonding pad, and wherein the first layer tapered side surface
acute angle is greater than that of the second layer tapered side
surface.
14. The semiconductor device of claim 12, wherein the electrode is
positioned above the upper surface region uncovered by the second
layer.
15. The semiconductor device of claim 13, wherein the electrode is
positioned above the first layer tapered side surface, and wherein
the electrode is positioned above the second layer tapered side
surface.
16. The semiconductor device of claim 13, wherein the first layer
upper surface region uncovered by the second layer extends a
distance between an upper end of the first layer tapered side
surface and a lower end of the second layer tapered side surface,
the distance being no greater than 3 .mu.m.
17. The semiconductor device of claim 12, wherein the distance
between an upper edge of the first layer and a lower edge of the
second layer tapered side surface is no greater than 1 .mu.m.
18. The semiconductor device of claim 13, wherein the bonding pad
includes a barrier layer positioned on the area that is uncovered
by the insulating layer.
19. The semiconductor device of claim 12, wherein the barrier layer
is also positioned directly between the electrode and the first and
second tapered side surfaces, and wherein the barrier layer is also
positioned directly between the electrode and the first layer upper
surface region uncovered by the second layer.
Description
[0001] This is a Continuation of U.S. application Ser. No.
10/962,735, filed Oct. 12, 2004, which is a Divisional of U.S.
application Ser. No. 09/607,219, filed Jun. 30, 2000, which issued
as U.S. Pat. No. 6,818,539. U.S. application Ser. No. 10/962,735
and U.S. Pat. No. 6,818,539 are each hereby incorporated by
reference in their entirety. Japanese patent application no.
11-186638, filed Jun. 30, 1999, is hereby incorporated by reference
in its entirety. Japanese patent application no. 2000-162322, filed
May 31, 2000, is hereby incorporated by reference in its
entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to a pad structure of a
semiconductor device, particularly to semiconductor devices having
a pad on which a connection is formed, and methods of fabricating
the same.
BACKGROUND
[0003] In spite of improvement of high integration of semiconductor
integrated circuits and miniaturization of semiconductor chips, it
has been difficult to reduce the size of a pad having a region
electrically connected with the external components to a
satisfactory level. This is because a pad has to be provided with a
certain dimension to ensure stable electric connection with bonding
wires, bumps, and the like, and to avoid a high resistance in the
connecting point.
[0004] In addition, for a pad on which a bump is formed, it should
be considered to keep adequate coverage for an aperture in a
protective insulating layer. If there is a large and steep step
around an aperture in a protective insulating layer, a barrier
layer may not exhibit adequate coverage, resulting in breakage of
the barrier layer.
[0005] For example, Japanese Patent Application Laid-open No.
10-189606 discloses a technique to attempt to overcome such a
problem. In the technique of this patent application, a protective
insulating layer formed on a metal pad of a semiconductor substrate
has a connection aperture having steps for a bump of a
semiconductor device. In forming such a protective insulating
layer, an insulating layer on a metal pad is subjected to photo
etching several times using a plurality of masks with different
diameters to form an aperture having steps. Since this method
requires a number of photolithography steps, a plurality of
photo-masks are necessary for the photolithographic operation. As a
result, although the coverage of the barrier layer is improved by
this method, a cleaning step or the like is required during and
prior to each photolithographic operation. This results in an
undesirable increase in the number of fabrication steps and
production costs.
SUMMARY
[0006] One embodiment relates to a semiconductor device including a
pad which is formed on an insulating layer. The pad includes an
electric connection region to connect with external components. The
device includes a protective insulating layer which is formed on
the insulating layer and the pad and has an aperture for exposing
the electric connection region. At least part of a side surface of
the protective insulating layer surrounding the electric connection
region is a tapered surface with an acute angle to a top surface of
the pad. The protective insulating layer includes at least first
and second insulating layers, each of which has a side surface
exposed to the aperture.
[0007] Another embodiment relates to a semiconductor device
including a pad which is formed on an insulating layer and includes
an electric connection region to connect with external components.
The device includes a protective insulating layer which is formed
on the insulating layer and the pad and includes an aperture over
at least part of the electric connection region. A side surface of
the protective insulating layer surrounding the electric connection
region is a tapered surface with an acute angle to a top surface of
the pad.
[0008] Another embodiment relates to a method of fabricating a
semiconductor device including: forming a pad with a predetermined
pattern on an insulating layer; forming a protective insulating
layer on the insulating layer and over the pad by sequentially
forming at least first and second insulating layers; forming a mask
layer on the protective insulating layer, the mask layer having an
aperture in a region corresponding to an electric connection region
of the pad; and selectively etching the first and second insulating
layers by using the mask layer as a mask to expose the electric
connection region.
[0009] Still another embodiment relates to a method of fabricating
a semiconductor device comprising: forming a pad with a
predetermined pattern on an insulating layer; forming a protective
insulating layer on the insulating layer over the pad; forming a
mask layer on the protective insulating layer, the mask layer
having an aperture in a region corresponding to an electric
connection region of the pad; and patterning the protective
insulating layer by isotropic etching with the mask layer as a mask
to expose the electric connection region.
[0010] Another embodiment relates to a bonding pad structure
including a bonding pad formed over a portion of a substrate and an
insulating region formed over a portion of the bonding pad, wherein
the bonding pad includes an area surrounded by and uncovered by the
insulating region. The insulating region includes a side surface
surrounding the uncovered area of the bonding pad, wherein at least
part of the side surface is tapered and has an acute angle to a top
surface of the bonding pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Certain embodiments of the invention are described with
reference to the accompanying drawings which, for illustrative
purposes, are schematic and not necessarily drawn to scale.
[0012] FIG. 1 is a cross-sectional view showing a passivation
structure of the pad in a semiconductor device according to a first
embodiment of the present invention.
[0013] FIG. 2 is a plan view showing an arrangement of the pad in a
semiconductor device according to a first embodiment of the present
invention.
[0014] FIG. 3 is a plan view showing an arrangement of the pad in a
comparative semiconductor device.
[0015] FIG. 4 is a cross-sectional view showing a method of
fabricating a pad in a semiconductor device according to an
embodiment of the present invention.
[0016] FIG. 5 is another cross-sectional view showing a method of
fabricating a pad in a semiconductor device according to an
embodiment of the present invention.
[0017] FIG. 6 is still another cross-sectional view showing a
method of fabricating a pad in a semiconductor device according to
an embodiment of the present invention.
[0018] FIG. 7 is a cross-sectional view showing a passivation
structure of a pad in a semiconductor device according to another
embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0019] Certain embodiments provide semiconductor devices which can
be fabricated in a reduced number of steps by using only one mask
for forming a pad that has a reliable passivation structure with a
sufficient thickness and stress relaxation characteristics, as well
as methods of fabricating such semiconductor devices.
[0020] According to a first embodiment of the present invention,
there is provided a semiconductor device comprising a pad which is
formed on an insulating layer and has an electric connection region
with external components, and a protective insulating layer which
is formed on the insulating layer and the pad and has an aperture
for exposing the electric connection region, wherein at least part
of a side surface of the protective insulating layer surrounding
the electric connection region is a tapered surface with an acute
angle to a top surface of the pad, and wherein the protective
insulating layer has first and second insulating layers each of
which has a side surface exposed to the aperture.
[0021] According to this embodiment of a semiconductor device, the
protective insulating layer includes at least two insulating layers
to inhibit formation of cracks and to relax stress in the
protective insulating layer. In addition, since at least part of
the side surface of the protective insulating layer surrounding the
electric connection region is a tapered surface with an acute angle
to the top surface of the pad, a barrier layer or the like can be
provided with excellent coverage.
[0022] Various embodiments may include one or more of the following
features.
[0023] (A) An etching rate of a material forming the first
insulating layer may be different from an etching rate of a
material forming the second insulating layer. As a result, the
configuration of the side surfaces of the first and second
insulating layers can be controlled by selecting etching
conditions.
[0024] (B) The first insulating layer may be formed on the
insulating layer, and the second insulating layer may be formed on
the first insulating layer. The second insulating layer may be
larger than the first insulating layer in thickness. For instance,
the first insulating layer may have a thickness of 400 nm to 600
nm; and the second insulating layer may have a thickness of 600 nm
to 1400 nm. The thickness of the first insulating layer depends on
the coverage for the protective insulating layer, and the thickness
of the second insulating layer depends on the strength of the
protective insulating layer.
[0025] (C) At least a side surface of the second insulating layer
surrounding the electric connection region may be a tapered surface
with an acute angle to the top surface of the pad. A tapered angle
between the side surface of the second insulating layer surrounding
the electric connection region and the top surface of the pad may
be smaller than a tapered angle of the first insulating layer.
Coverage for the barrier layer can be improved by forming the
tapered angle in this manner.
[0026] Specifically, a tapered angle between the side surface of a
portion of the second insulating layer surrounding the electric
connection region and the top surface of the pad may be in the
range of 30.degree. to 60.degree., and an angle between the side
surface of a portion of the first insulating layer surrounding the
electric connection region and the top surface of the pad may be in
the range of 60.degree. to 90.degree..
[0027] (D) The distance between an upper end of the side surface of
the first insulating layer surrounding the electric connection
region and a lower end of the side surface of the second insulating
layer surrounding the electric connection region is preferably in
the range of 0 .mu.m to 3 .mu.m, and more preferably 0 .mu.m to 1
.mu.m. The size of the pad can be decreased by setting the above
distance to this range, which contributes to miniaturization of
semiconductor devices. The above distance may be larger than zero,
that is, the aperture in the second insulating layer may be larger
than the aperture in the first insulating layer. This configuration
reduces the height of steps in the aperture, which results in
better coverage for the barrier layer, for example.
[0028] (E) Furthermore, a bump electrode may be formed on the
electric connection region in the pad through a barrier layer.
Since the protective insulating layer of the present invention can
improve the coverage for the aperture when forming a thin layer
such as the barrier layer, the protective insulating layer is
particularly suitable for use in semiconductor devices having a
bump electrode.
[0029] According to another embodiment of the present invention,
there is provided a semiconductor device comprising a pad which is
formed on an insulating layer and has an electric connection region
with external components, and a protective insulating layer which
is formed on the insulating layer and the pad and has an aperture
for exposing the electric connection region, wherein a side surface
of the protective insulating layer surrounding the electric
connection region is a tapered surface with an acute angle to a top
surface of the pad, and is exposed to the aperture.
[0030] This embodiment differs from the above in that the
protective insulating layer has a single insulating layer with a
tapered configuration. Embodiments of this semiconductor device may
have one or more of following features.
[0031] (A) The protective insulating layer may have a thickness of
1000 nm to 2000 nm.
[0032] (B) A tapered angle between the side surface of the second
insulating layer surrounding the electric connection region and the
top surface of the pad may be in the range of 10.degree. to
80.degree..
[0033] (C) Furthermore, a bump electrode may be provided on the
electric connection region of the pad through a barrier layer.
[0034] According to a another embodiment of the present invention,
there is provided a method of fabricating a semiconductor device
comprising the steps of:
[0035] (a) forming a pad with a predetermined pattern on an
insulating layer;
[0036] (b) forming a protective insulating layer on the insulating
layer over the pad by sequentially forming at least a first and
second insulating layers;
[0037] (c) forming a mask layer on the protective insulating layer,
the mask layer having an aperture in a region corresponding to an
electric connection region of the pad; and
[0038] (d) selectively etching the first and second insulating
layers by using the mask layer as a mask to expose the electric
connection region.
[0039] According to this method, the number of steps as well as
production costs can be reduced by etching the first and second
insulating layers using a single mask. The use of a single mask
does not require any alignment tolerance for a plurality of masks,
thereby enabling reduction of the size of a pad. This contributes
to miniaturization of the semiconductor device.
[0040] Methods of fabricating the semiconductor device of this
embodiment of the present invention may have one or more of
following features.
[0041] (A) The second insulating layer may be patterned by
isotropic etching. The first insulating layer may be patterned by
anisotropic etching. A desired tapered angle can be provided to
each insulating layer by selecting a suitable etching method for
the first and second insulating layers.
[0042] (B) The first and second insulating layers may be
continuously patterned with the same mask layer.
[0043] According to another embodiment of the present invention,
there is provided a method of fabricating a semiconductor device
comprising the steps of:
[0044] (a) forming a pad with a predetermined pattern on an
insulating layer;
[0045] (b) forming a protective insulating layer on the insulating
layer over the pad;
[0046] (c) forming a mask layer on the protective insulating layer,
the mask layer having an aperture in a region corresponding to an
electric connection region of the pad; and
[0047] (d) patterning the protective insulating layer by isotropic
etching with the mask layer as a mask to expose the electric
connection region.
[0048] The method of fabricating a semiconductor device of this
embodiment of the present invention may possess various features of
embodiments discussed above.
[0049] A description of embodiments of the present invention in
conjunction with FIGS. 1-7 follows.
[0050] FIG. 1 is a cross-sectional view showing a pad in which a
bump electrode is formed in a semiconductor device according to an
embodiment of the present invention.
[0051] In this embodiment, a pad 2 containing, for example,
aluminum and a passivation layer (protective insulating layer) 3
having an aperture 3a in an electric connection region 21 which
functions as an electrode pad are formed on an interlayer
insulation layer 1. The semiconductor device has a conventionally
known layer structure (not shown in the drawings) below the
interlayer insulation layer 1. This layer structure comprises, for
example, a semiconductor substrate on which semiconductor elements
such as a MOSFET and a bipolar transistor are formed, with at least
one pair of layers, such as an interlayer insulation layer having
an intercalation contact layer (such as a contact layer or via
contact layer) and an insulating layer having a wiring layer formed
thereon, formed on the semiconductor substrate.
[0052] The passivation layer 3 has a two-layer structure consisting
of a silicon oxide layer (a first insulating layer) 31 and a
silicon nitride layer (a second insulating layer) 32. The
passivation layer 3 has a thickness sufficient to inhibit formation
of cracks in the passivation layer 3 due to impact during a bump
packaging operation and a structure to relax stress.
[0053] In this embodiment, the silicon nitride layer 32 is
preferably thicker than the silicon oxide layer 31. For instance,
the silicon oxide layer 31 has a preferred thickness of 400 nm to
600 nm, and the silicon nitride layer 32 has a preferred thickness
of 600 nm to 1400 nm. Specifically, the silicon oxide layer 31 is
made thin at a slow coating speed to ensure coverage with circuit
elements having a smallest wiring rule. In contrast, the silicon
nitride layer 32 is formed comparatively thickly to provide the
passivation layer 3 with sufficient strength. Taking into account
the strength and stress relaxation effect required for the
passivation layer 3, the total thickness of the passivation layer 3
should preferably be 1200 nm or more.
[0054] In the present embodiment, a side surface 31a of the silicon
oxide layer 31 and a side surface 32a of the silicon nitride layer
32, both surrounding the electric connection region 21, have a
tapered configuration with an acute angle respectively to the top
surface of the pad 2. The (tapered) angle A-1 of the silicon oxide
layer 31 (an angle formed by the top surface of the pad 2 and the
side surface 31a of the silicon oxide layer 31) differs from the
tapered angle A-2 for the silicon nitride layer 32 (an angle formed
by the top surface of the pad 2 and the side surface 32a of the
silicon nitride layer 32).
[0055] The (tapered) angle A-1 for the silicon oxide layer 31 is
preferably from 60.degree. to 90.degree., and more preferably from
60.degree. to 70.degree.. The tapered angle A-2 for the silicon
nitride layer 32 is preferably from 30.degree. to 60.degree., and
more preferably from 30.degree. to 40.degree..
[0056] The tapered configuration of the side surfaces 31a and 32a
of the silicon oxide layer 31 and the silicon nitride layer 32, or
of at least the side surface 32a of the silicon nitride layer 32,
ensures excellent coverage for the barrier layer (not shown in FIG.
1) which will later be formed over the electric connection region
21, silicon oxide layer 31, and silicon nitride layer 32.
[0057] In the present embodiment, the silicon nitride layer 32 has
a side surface 32a at a tapered angle which is smaller than that of
the silicon oxide layer 31, and is self-aligned with respect to the
silicon oxide layer 31. The distance D1 between the upper end of
the side surface 31a of the silicon oxide layer 31 and the lower
end of the side surface 32a of the silicon nitride layer 32 is
preferably 0 .mu.m to 3 .mu.m, and more preferably 0 .mu.m to 1
.mu.m. Such a small distance D1 is enabled because patterning of
the aperture in the silicon oxide layer 31 and silicon nitride
layer 32 is performed by etching with the same mask layer, as
described later.
[0058] Patterning of the silicon oxide layer 31 and silicon nitride
layer 32 using the same mask enables lithographic operation without
any alignment tolerance for a plurality of masks. Therefore, a
maximum area can be secured for the electric connection region 21
and the pad 2 can be made narrower.
[0059] Specifically, as shown in the embodiment of FIG. 2, because
the configuration having a plurality of pads 2 requires a fine
pitch, an area for the electric connection region 21 should be
provided along the longitudinal direction of the pad 2. Such a pad
arrangement will be described by comparing the configuration of the
embodiment shown in FIG. 2 and the configuration considering
alignment tolerance for a plurality of masks as shown in FIG.
3.
[0060] Comparing the configuration of the present invention (FIG.
2) and the comparative configuration (FIG. 3), the area for the pad
2 in the electric connection region 21 in the present invention can
be greater than in the electric connection region 521. Since no
alignment tolerance for a plurality of masks is required when
patterning the silicon oxide layer 31 and silicon nitride layer 32
with the configuration of the present invention, the pad 2 can be
narrower than the comparative configuration.
[0061] More specifically, as the silicon oxide layer (first
insulating layer) 531 and the silicon nitride layer (second
insulating layer) 532 are patterned by using different masks, it is
required to secure the alignment tolerance for a plurality of
masks, as shown in FIG. 3. For this reason, a side surface of the
silicon oxide layer 531 and a side surface of the silicon nitride
layer 532 are separated by a certain distance D2. The area for the
pad 52 must be large corresponding to the distance D2 (usually
about 10 .mu.m). In the configuration of the present invention,
however, the area for the pad 2 can be reduced by the alignment
tolerance for the plurality of masks.
[0062] Consequently, the semiconductor device ensures a fine pad
arrangement which is useful for high integration of semiconductor
integrated circuits and a decrease in size of semiconductor chips
with high reliability.
(Fabrication Method)
[0063] FIGS. 4 to 6 are sectional views showing a method for
fabricating a semiconductor device according to an embodiment of
the present invention.
[0064] (1) As shown in FIG. 4, a pad 2 containing aluminum, for
example, is selectively formed on the uppermost interlayer
insulation layer 1. Next, the silicon oxide layer 31 and silicon
nitride layer 32 are formed on the interlayer insulation layer 1 to
cover the pad 2.
[0065] The silicon oxide layer 31 is formed to ensure the coverage
for circuit elements possessing the smallest wiring rule using a
high-density plasma CVD (Chemical Vapor Deposition) technique, for
example. The silicon oxide layer 31 with a thickness of 400 nm to
600 nm is formed using a silane gas such as mono silane, oxygen,
and an inert gas such as argon at a prescribed flow rate for a
prescribed period of time.
[0066] The silicon nitride layer 32 is formed using a plasma CVD
technique, for example. The silicon nitride layer 32 with a
thickness of 600 nm to 1400 nm is formed using a silane gas such as
mono silane, oxygen, and an inert gas such as argon at a prescribed
flow rate for a prescribed period of time.
[0067] (2) Next, an aperture 4a is formed in a resist layer 4 with
a thickness of 1,000 nm to 2,000 nm formed on the silicon nitride
layer 32 in the area corresponding to the electric connection
region 21 of the pad 2 using a lithographic technology as shown in
FIG. 5.
[0068] Then, the silicon nitride layer 32 is patterned by isotropic
etching using the resist layer 4 as a mask. Specifically, a dry
etching (plasma etching) technology is used. O.sub.2 and CF.sub.4
are used as gases. The operation in this etching step can be
controlled so as to allow the silicon oxide layer 31 to be exposed
beyond the area for the aperture 4a of the resist layer 4. The
silicon oxide layer 31 isotropically etched in this manner has a
slanted surface (a tapered configuration) for the side surface 32a.
Etching conditions are selected to provide the tapered angle of the
side surface 32a for the silicon nitride layer 32 preferably from
30.degree. to 60.degree., and more preferably from 30.degree. to
40.degree., as mentioned above. An example of suitable etching
conditions includes an RF power of 900 W, a chamber pressure of 300
mTorr, and a gas flow of 270 sccm for CF.sub.4 and 35 sccm for
O.sub.2.
[0069] Then, immediately following etching of the silicon nitride
layer 32, anisotropic etching is performed using the same resist
layer 4 as a mask. Specifically, a dry etching (plasma etching)
technology is used. CHF.sub.3 and CF.sub.4 are used together with
an inert gas such as argon. Anisotropic etching conditions are
selected so as to provide a (tapered) angle of the side surface 31a
for the silicon oxide layer 31 in the range of 60.degree. to
90.degree., and more preferably from 60.degree. to 70.degree.. An
example of suitable etching conditions includes an RF power of 1300
W, a chamber pressure of 300 mTorr, and a gas flow of 30 sccm for
CHF.sub.3, 30 sccm for CF.sub.4, and 600 sccm for argon.
[0070] An aperture 3a for exposing the electric connection region
21 for the bottom pad 2 is formed by the etching step.
[0071] Next, after removing the resist layer 2 using a plasma
peeling technique, for example, the product is sintered at
350.degree. C. to 450.degree. C. for about 10 min. to 20 min. to
complete a passivation structure for pad 2 as shown in FIG. 1.
[0072] In the present embodiment, the passivation layer 3
consisting of the silicon oxide layer 31 and silicon nitride layer
32 has sufficient strength and thickness.
[0073] In addition, the passivation layer 3 can be formed by one
lithographic step, specifically by using a single mask (a
photo-mask). As a result, not only the number of steps for the
fabrication can be reduced and the production cost reduced, but
also the product has high reliability even if the size is
reduced.
[0074] Furthermore, although only one lithography step is performed
for exposing the surface of the electric connection region 21 of
the pad 2, different etching methods are used for etching different
layers to avoid formation of large and steep steps in the
passivation layer 3 (see process (2)). As a result, a step
configuration for relaxing the step difference between the silicon
oxide layer 31 and silicon nitride layer 32 can be formed, ensuring
a step-less barrier layer without impairing the coverage.
[0075] (3) FIG. 6 is a cross-sectional view showing an embodiment
of bump electrode formation following the steps described in FIG.
5. A barrier layer 6 is formed on the pad 2 on which the electric
connection region 21 is exposed, the silicon oxide layer 31, and
the silicon nitride layer 32. A bump electrode 7 is formed on
barrier layer 6 according to a conventional method.
[0076] The bump electrode 7 contains gold, for example. The barrier
layer 6 is formed from metals having high barrier capability and
easily connected with gold, such as Ti--W, Ti--Pd, Ti--Pt, Cr, and
the like. The barrier layer 6 is patterned simultaneously with the
formation of the bump electrode 7.
[0077] Because the (tapered) angle A-1 of the side surface 31a for
the silicon oxide layer 31 is in the range from 60.degree. to
90.degree. and the tapered angle A-2 of the side surface 32a for
the silicon nitride layer 32 is in the range from 30.degree. to
60.degree. as mentioned above, a barrier layer 6 with excellent
coverage can be formed without steps at a high precision. The bump
electrode 7 with high reliability is obtained in this manner.
[0078] The silicon oxide layer 31 and silicon nitride layer 32 with
a self-aligned step configuration can be formed by the application
of the present embodiment. Therefore, a maximum area for the
electric connection region 21 can be secured and a decrease in the
size of pitches of the pads 2 can be ensured. This contributes to
an increase in the reliability of small bump electrodes.
[0079] FIG. 7 is a cross-sectional view showing the pad in which a
bump electrode is formed in the semiconductor device according to
another embodiment of the present invention.
[0080] The embodiment differs from the embodiment illustrated in
FIG. 1 in that the insulating layer for the passivation layer
(protective insulating layer) 3 is a single layer. The same symbols
are given to the parts and sections which are substantially the
same as those shown in FIG. 1, and detailed descriptions for these
parts and sections are omitted.
[0081] The passivation layer 3 is formed from one insulating layer.
A silicon oxide layer or silicon nitride layer may be used as the
insulating layer, with the silicon nitride layer being preferred in
view of the strength and stress relaxation effect. The passivation
layer 3 has a thickness sufficient for the passivation layer 3 to
inhibit formation of cracks due to impact during a bump packaging
operation and to relax stress. From this viewpoint, the thickness
of the passivation layer 2 is preferably 1000 nm or more, and more
preferably from 1000 nm to 2000 nm.
[0082] In the present embodiment, a side surface 3b of the
passivation layer 3 surrounding an electric connection region 21
has a tapered configuration at an acute angle to a top surface of
the pad 2. The tapered angle A-3 for the passivation layer 3 (an
angle between the top surface of the pad 2 and the side surface 3b
of the passivation layer 3) is preferably from 10.degree. to
80.degree., and more preferably from 30.degree. to 60.degree.. The
tapered configuration of the side surface 3b of the passivation
layer 3 can improve the coverage for the barrier layer (not shown
in FIG. 7) for the same reasons as described in connection with the
FIG. 1 embodiment.
[0083] In the method of fabricating the semiconductor device
according to this embodiment, the passivation layer 3 is formed by
patterning the insulating layer by means of isotropic etching. The
isotropic etching can be performed in the same manner as the
etching of the silicon nitride layer 32 in the embodiment described
above.
[0084] The present invention is not limited to the above-described
embodiments and many modifications and variations are possible
within the scope of the present invention. For instance, the bump
electrode is not necessarily limited to gold, but other metals can
be used as known in the art. Although a configuration with a pad in
the uppermost layer of the semiconductor device was shown in the
above embodiments, the present invention can be applied to the case
of forming a pad on an insulation substrate or a substrate
comprising a thin insulating layer. Furthermore, the passivation
layer may have a three or more layered configuration. For example,
a layer such as a polyimide resin layer may be provided on the
uppermost layer.
* * * * *