U.S. patent application number 11/902773 was filed with the patent office on 2008-01-31 for current driven d/a converter and its bias circuit.
This patent application is currently assigned to Renesas Technology Corp.. Invention is credited to Osamu Matsumoto, Takahiro Miki, Yasuo Morimoto.
Application Number | 20080024340 11/902773 |
Document ID | / |
Family ID | 35942318 |
Filed Date | 2008-01-31 |
United States Patent
Application |
20080024340 |
Kind Code |
A1 |
Matsumoto; Osamu ; et
al. |
January 31, 2008 |
Current driven D/A converter and its bias circuit
Abstract
A current driven D/A converter sets an OFF control voltage
(BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N,
M32P and M32N at a voltage close to an ON control voltage (BIAS2).
This makes it possible to reduce the swing of the control voltage
(ON control voltage-OFF control voltage) of the NMOS transistors,
and hence to reduce the noise due to charge injections through
parasitic capacitances, and noise of a ground voltage or power
supply voltage due to flowing of discharge currents from the
parasitic capacitances to the ground or power supply at turn off of
the transistors, thereby being able to offer a high performance
current driven D/A converter.
Inventors: |
Matsumoto; Osamu; (Tokyo,
JP) ; Miki; Takahiro; (Tokyo, JP) ; Morimoto;
Yasuo; (Tokyo, JP) |
Correspondence
Address: |
BUCHANAN, INGERSOLL & ROONEY PC
POST OFFICE BOX 1404
ALEXANDRIA
VA
22313-1404
US
|
Assignee: |
Renesas Technology Corp.
Tokyo
JP
|
Family ID: |
35942318 |
Appl. No.: |
11/902773 |
Filed: |
September 25, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11214723 |
Aug 31, 2005 |
7292172 |
|
|
11902773 |
Sep 25, 2007 |
|
|
|
Current U.S.
Class: |
341/135 ;
341/136 |
Current CPC
Class: |
H03M 1/742 20130101;
H03M 1/0604 20130101 |
Class at
Publication: |
341/135 ;
341/136 |
International
Class: |
H03M 1/66 20060101
H03M001/66 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 31, 2004 |
JP |
2004-252939 |
Claims
1. A D/A converter that sets a first control voltage for turning
off a switch connected to a current source at a voltage close to a
second control voltage for turning on the switch, further
comprising a bias circuit for generating bias voltages to be used
as the first control voltage and the second control voltage, said
bias circuit comprising: a first current source having its first
end connected to a first voltage source; a first MOS transistor
having its gate electrode and drain electrode connected to a second
end of said first current source; a second MOS transistor having
its source electrode connected to a source electrode of said first
MOS transistor, and its gate electrode connected to a reference
voltage terminal; and a second current source having its first end
connected to source electrodes of said first and second MOS
transistors, and its second end connected to a second voltage
source.
2. The D/A converter according to claim 1, wherein said switch
includes a MOS transistor whose gate electrode is supplied with
said bias voltages, and the first control voltage is set such that
a gate source voltage of the transistor to be turned off becomes a
threshold voltage of the transistor.
3. The D/A converter according to claim 1, wherein said switch
includes a MOS transistor whose gate electrode is supplied with
said bias voltages from said bias circuit, and the first control
voltage is set such that a gate source voltage of the transistor to
be turned off becomes zero volt.
4. A D/A converter according to claim 1, further comprising a
voltage buffer at an output stage of said bias circuit, wherein
said bias voltages output via the voltage buffer is used as the
first control voltage and the second control voltage.
5. The D/A converter according to claim 1, wherein said first and
second MOS transistors are NMOS transistors.
6. The D/A converter according to claim 1, wherein said first and
second MOS transistors are PMOS transistors.
7. The D/A converter according to claim 1, further comprising a
current mirror circuit connected to the drain electrodes of said
first and second MOS transistors.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a current driven D/A
converter and its bias circuit.
[0003] 2. Description of Related Art
[0004] In a current driven D/A converter composed of MOS
transistors, current switches are implemented by transistors. As
shown in FIG. 7, a conventional current driven D/A converter, which
employs NMOS transistors for current switches, uses a ground
voltage as an OFF control voltage for turning off the current
switches (see non-patent document 1, for example). To switch from
ON to OFF state or vice versa, the gate electrodes of the switching
transistors are supplied with an amplitude greater than a voltage
at which the current switch actually switches off.
[0005] Accordingly, as shown in FIG. 8, charge injections greater
than necessary takes place via parasitic capacitances of the
switching transistors. This causes noise that brings about accuracy
degradation and conversion rate restriction of the D/A
converter.
[0006] Furthermore, as shown in FIG. 9, in the switching transistor
that is turning off from the ON state, charges stored in the
parasitic capacitance in the ON state flow into a ground terminal
at the moment it turns off. Thus, large charge discharge current
flows instantaneously into the ground terminal. Because of the
current and parasitic resistance and parasitic inductance of the
ground terminal, the ground terminal voltage fluctuates, which
brings about performance degradation of the D/A converter.
[0007] Likewise, in the switching transistors composed of PMOS
transistors, large charge injections and noise of the power supply
voltage occur.
[0008] In addition, as shown in FIG. 10, in a current source (M1
and M2) connected in cascode, both the current source transistor M1
and cascode transistor M2 are used in the saturation region. Thus,
the bias voltage of the cascode transistor M2 must be set in such a
manner that the current source transistor M1 is saturated.
Accordingly, the diode connection transistor M3 has been used as a
bias circuit. When the transistors M2 and M3 have the same
threshold voltage, the channel width/channel length ratio (W/L)3 of
the transistor M3 for saturating the transistor M1 is obtained by
the following expression (1). ( W / L ) .times. 3 < ( 1 1 + 1 /
K ) 2 .times. ( W / L ) .times. 1 ( 1 ) ##EQU1## where
K=(W/L)2/(W/L)1. In this case, since (W/L)3 is determined by device
sizes of (W/L)1 and (W/L)2, it can be determined accurately in a
semiconductor integrated circuit.
[0009] In an actual circuit, however, the threshold voltages Vth2
and Vth3 of the transistors M2 and M3 differ because of the
substrate bias effect. Thus, the condition of (W/L)3 for operating
the transistor M1 in the saturation region is given by the
following expression, which means that the condition depends on I0,
Vth2 and Vth3. ( W / L ) .times. 3 < 1 ( ( ( 1 + 1 / K ) .times.
.times. 1 ( W / L ) .times. .times. 1 ) + 1 2 .times. .times. I
.times. .times. 0 .times. ( Vth .times. .times. 2 - Vth .times.
.times. 3 ) ) 2 ( 2 ) ##EQU2## where Iout=Iref is set at I0.
Accordingly, the bias voltage value must be generated with leaving
sufficient margin considering fabrication variations in I0, Vth2
and Vth3. Thus, it is difficult for a low voltage circuit or a
circuit with a small M2 drain voltage to achieve the
conditions.
[0010] Non-patent document 1: "An 80-MHZ 8-bit CMOS D/A Converter",
IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, December
1986.
[0011] With the foregoing configuration, the conventional current
driven D/A converter has noise occurring because of the charge
injections caused by the unnecessarily large amplitude of the
control voltage of the current switches of the current driven D/A
converter, which becomes a factor of the performance
degradation.
[0012] In addition, the large charge discharge current flows from
the gate electrodes of the switching transistors into the ground or
power supply terminal instantaneously when turning off the
transistors. This causes noise in the ground voltage or in the
power supply voltage, which offers a problem of the performance
degradation of the D/A converter.
[0013] Furthermore, because of the variations in the threshold
voltage Vth due to the substrate bias effect, the bias circuit of
the conventional cascode connection current source must generate
the bias voltage with leaving sufficient margin considering the
fabrication variations in the current value and Vth. Thus, in the
low voltage circuit or in the circuit with a small output voltage
of the current source, a problem arises in that it is difficult to
configure the bias circuit that meets the saturation conditions of
the transistors.
SUMMARY OF THE INVENTION
[0014] The present invention is implemented to solve the foregoing
problems. It is therefore an object of the present invention to
provide a high performance current driven D/A converter by reducing
the noise caused by the control voltages of the current switch
transistors, and by reducing the noise in the ground or power
supply voltage occurring at the turn off of the current
switches.
[0015] Another object of the present invention is to provide a bias
circuit of a current driven D/A converter capable of providing a
high performance current driven D/A converter by generating
appropriate bias voltages (control voltages) regardless of the
fabrication variations in the current value and threshold
voltage.
[0016] The current driven D/A converter in accordance with the
present invention sets an OFF control voltage for turning off a
current switch connected to a current source at a voltage close to
an ON control voltage for turning on the current switch.
[0017] According to the present invention, setting the OFF control
voltage of the current switch at the voltage close to the ON
control voltage makes it possible to reduce the swing of the
control voltage (ON control voltage-OFF control voltage) of the
current switch. Thus, it can reduce the noise due to the charge
injections through parasitic capacitances, and noise of ground
voltage or power supply voltage due to flowing of the discharge
current from the parasitic capacitances to the ground or power
supply at the turn off, thereby offering an advantage of being able
to provide a high performance current driven D/A converter.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a circuit diagram showing a configuration of a
current driven D/A converter of an embodiment 1 in accordance with
the present invention;
[0019] FIGS. 2A and 2B are circuit diagrams each showing a
configuration of a current source cell;
[0020] FIG. 3 is a circuit diagram showing another configuration of
the current driven D/A converter of the embodiment 1 in accordance
with the present invention;
[0021] FIG. 4 is a circuit diagram showing a configuration of a
current driven D/A converter of an embodiment 2 in accordance with
the present invention;
[0022] FIG. 5 is a circuit diagram showing another configuration of
the current driven D/A converter of the embodiment 2 in accordance
with the present invention;
[0023] FIG. 6 is a circuit diagram showing a configuration of a
folded cascode operational amplifier to which a current driven D/A
converter of the embodiment 3 in accordance with the present
invention is applied;
[0024] FIG. 7 is a diagram illustrating a conventional current
driven D/A converter;
[0025] FIG. 8 is a diagram illustrating a conventional current
driven D/A converter;
[0026] FIG. 9 is a diagram illustrating a conventional current
driven D/A converter; and
[0027] FIG. 10 is a diagram illustrating a bias circuit of a
conventional cascode connection current source.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0028] The invention will now be described with reference to the
accompanying drawings.
Embodiment 1
[0029] FIG. 1 is a circuit diagram showing a configuration of a
current driven D/A converter of an embodiment 1 in accordance with
the present invention. The current driven D/A converter is an
example of a 3-bit D/A converter.
[0030] In FIG. 1, load resistances RLP and RLN have their first
ends connected to a power supply. An NMOS transistor (current
switch) M12P has its drain electrode connected to a second end of
the load resistance RLP, and its gate electrode connected to a
switch SW12P to which bias voltages (control voltages) BIAS2 and
BIAS3 are supplied. An NMOS transistor (current switch) M12N has
its drain electrode connected to a second end of the load
resistance RLN, and its gate electrode connected to a switch SW12N
to which the bias voltages BIAS2 and BIAS3 are supplied. An NMOS
transistor (current source) M11 has its drain electrode connected
to a common source of the NMOS transistors M12P and M12N, its gate
electrode supplied with a bias voltage BIAS1, and its source
electrode connected to the ground.
[0031] The NMOS transistors M11, M12P and M12N constitute a current
source cell for causing a current Ilsb corresponding to a 1 LSB to
flow. In other words, the current source cell is composed of the
NMOS transistor M11 operating as the current source, and the NMOS
transistors M12P and M12N operating as current switches that turn
on and off complementarily. The NMOS transistors M12P and M12N have
the same size and the same electric characteristics.
[0032] An NMOS transistor (current switch) M22P has its drain
electrode connected to the second end of the load resistance RLP,
and its gate electrode connected to a switch SW22P to which the
bias voltages BIAS2 and BIAS3 are supplied. An NMOS transistor
(current switch) M22N has its drain electrode connected to the
second end of the load resistance RLN, and its gate electrode
connected to a switch SW22N to which the bias voltages BIAS2 and
BIAS3 are supplied. An NMOS transistor (current source) M21 has its
drain electrode connected to a common source of the NMOS
transistors M22P and M22N, its gate electrode supplied with a bias
voltage BIAS1, and its source electrode connected to the
ground.
[0033] The NMOS transistors M21, M22P and M22N constitute a current
source cell for causing a current 2.times.Ilsb to flow.
[0034] FIGS. 2A and 2B are circuit diagrams showing a configuration
of the current source cell. As shown in FIG. 2A, the NMOS
transistors M21, M22P and M22N are each implemented by connecting
two NMOS transistors M11, M12P and M12N in parallel.
[0035] An NMOS transistor (current switch) M32P has its drain
electrode connected to the second end of the load resistance RLP,
and its gate electrode connected to a switch SW32P to which the
bias voltages BIAS2 and BIAS3 are supplied. An NMOS transistor
(current switch) M32N has its drain electrode connected to the
second end of the load resistance RLN, and its gate electrode
connected to a switch SW32N to which the bias voltages BIAS2 and
BIAS3 are supplied. An NMOS transistor (current source) M31 has its
drain electrode connected to a common source of the NMOS
transistors M32P and M32N, its gate electrode supplied with a bias
voltage BIAS1, and its source electrode connected to the
ground.
[0036] The NMOS transistors M31, M32P and M32N constitute a current
source cell for causing a current 4.times.Ilsb to flow. As shown in
FIG. 2B, the NMOS transistors M31, M32P and M32N are each
implemented by connecting four NMOS transistors M11, M12P and M12N
in parallel.
[0037] The circuit configured that an analog output signal 1 is
output from a connecting point of the second end of the load
resistance RLP and the drain electrodes of the NMOS transistors
M12P, M22P and M32P, and that an analog output signal 2 is output
from a connecting point of the second end of the load resistance
RLN and the drain electrodes of the NMOS transistors M12N, M22N and
M32N.
[0038] In response to a 3-bit digital input signal, a control
circuit 10 generates a control signal that turns on one of the
switches SWxP and SWxN of each current source cell, and turns off
the other of them. By connecting the output terminals of the
current source cells, the current amounting to the sum total of the
output currents of the current source cells are produced. The
current is an 8-level analog signal current from a current value 0
to a 7.times.Ilsb. The current is converted to a voltage signal
through the load resistances RLP and RLN, and the analog output
signals 1 and 2 are output as the output signal of the D/A
converter.
[0039] Transistors M91-M98 constitute a bias circuit for generating
the bias voltages (control voltages) for the switching transistors
of the current source cells. The bias circuit will now be
described.
[0040] The PMOS transistor (first current source) M91 has its
source electrode connected to a power supply (first voltage
source). The NMOS transistor (first NMOS transistor) M92 has its
gate electrode and drain electrode connected to the drain electrode
of the PMOS transistor M91 and to the switches SWxP and SWxN so
that it can supply the bias voltage BIAS2. The NMOS transistor
(second NMOS transistor) M93 has its source electrode and back gate
electrode connected to the source electrode of the NMOS transistor
M92, its drain electrode connected to a power supply (second
voltage source), and its gate electrode connected to a reference
voltage terminal. The common source of the NMOS transistors M92 and
M93 is connected to the switches SWxP and SWxN so that it can
supply the bias voltage BIAS3. The NMOS transistors (second current
source) M94A and M94B have their drain electrodes connected to the
common source of the NMOS transistors M92 and M93, and their source
electrodes connected to the ground (third voltage source). The NMOS
transistors M94A and M94B have their gate electrodes supplied with
the bias voltage BIAS1.
[0041] The PMOS transistors M95 and M96 have their source
electrodes connected to a power supply, and their gate electrodes
together with the drain electrode of the PMOS transistor M95
connected to the gate electrode of the PMOS transistor M91. The
NMOS transistor M97 has its drain electrode connected to the drain
electrode of the PMOS transistor M95, its gate electrode supplied
with the bias voltage BIAS1, and its source electrode connected to
the ground. The NMOS transistor M98 has its drain electrode and
gate electrode (reference voltage terminal) connected to the drain
electrode of the PMOS transistor M96 and to the gate electrode of
the NMOS transistor M93, and its source electrode connected to the
ground.
[0042] The NMOS transistors M94A, M94B and M97 have the same size
as the NMOS transistor M11. They share the gate electrodes to which
the bias voltage BIAS1 is applied so that the current Ilsb flows.
The PMOS transistors M95, M96 and M91 constitute a current mirror
circuit, so that the current Ilsb flowing through the PMOS
transistor M95 also flows through the PMOS transistors M96 and M91.
The NMOS transistor M92 has the same size as the NMOS transistors
M12P and M12N. The current value flowing through the NMOS
transistor M94A and NMOS transistor M92 is Ilsb. Accordingly, the
NMOS transistor M94A and NMOS transistor M92 constitute a replica
circuit of the conducting switching transistor side of each current
source cell. The bias voltage BIAS2 is a bias voltage applied to
the gate electrodes of the conducting switching transistor sides,
and the bias voltage BIAS3 is a bias voltage applied to the gate
electrodes of the non-conducting switching transistor sides. The
NMOS transistor M93 has the same size as the NMOS transistor M11,
and has its back gate electrode connected to the source electrode
of the NMOS transistor M93. As for the back gate electrodes of the
transistors other than the NMOS transistor M93, those of the NMOS
transistors are connected to the ground, and those of the PMOS
transistors are connected to the power supply.
[0043] Next, the operation will be described.
[0044] The NMOS transistor M11 of the current source cell must
operate in the saturation region (that is, when Vgs is constant and
Vds is large enough, Id becomes constant regardless of Vds) The
condition for the NMOS transistor M11 to be placed in saturation is
given by the following expression (3). Vds11>Vgs11-Vth11 (3)
where Vgs11 is the gate-source voltage of the NMOS transistor M11,
Vds11 is the drain-source voltage of the NMOS transistor M11, and
Vth11 is the threshold voltage of the NMOS transistor M11. The
voltage value Vds11 is equal to the corresponding bias voltage
BIAS3 of the replica circuit composed of the NMOS transistors M94A
and M92. In addition, since Vgs11=Vgs94A, and Vth11=Vth94A, the
NMOS transistor M11 operates in the saturation region, when the
following condition is satisfied. BIAS3>Vgs94A-Vth94A (4)
[0045] The BIAS3 is given by the following expression (5).
BIAS3=Vgs98-Vgs93 (5) where Vgs98 and Vgs93 are gate-source
voltages of the NMOS transistors M98 and M93. As for the NMOS
transistor M93, it has the same size as the NMOS transistor M94A,
its drain current is Ilsb, and its source electrode and back gate
electrode are connected to the same terminal so that it is free
from the substrate bias effect. Thus, it exhibits the same electric
characteristics as the NMOS transistor M94A, and hence Vgs93=Vgs94A
(6) From the foregoing expressions (4)-(6), the conditions for
placing the NMOS transistor M11 in saturation can be summarized in
the following expression (7). Vgs98>2.times.Vgs94A-Vth94A
Vgs98>2.times.(Vgs94A-Vth94A)+Vth94A (7)
[0046] Since the NMOS transistor M98 is free from the substrate
bias effect, Vth98=Vth94A.
[0047] The current of a MOS transistor is given by the following
expression. Id = 1 2 .times. .mu. .times. .times. n .times. .times.
Cox .times. .times. W L .times. ( Vgs - Vth ) 2 ( 8 ) ##EQU3##
where .mu.n is the mobility of electrons, and Cox is the gate
capacitance per unit area.
[0048] From the foregoing expression (8), the following expression
is obtained. Vgs - Vth = 2 .times. .times. Id .mu. .times. .times.
n .times. .times. Cox .times. L W ( 9 ) ##EQU4## Thus, the
foregoing expression (7) can be achieved by making the W/L ratio of
the NMOS transistor M98 equal to or less than 1/4 of the W/L ratio
of the NMOS transistor M94A.
[0049] In this way, the conditions for operating the NMOS
transistor M11 in the saturation region can be determined only by
the size ratio of the transistors. Since the size ratio of the
transistors can be fabricated at high accuracy in the integrated
circuit, it is easily implemented. In addition, since the NMOS
transistors M93 and M98 are free from the substrate bias effect,
they are free from the changes in the threshold voltage Vth and
current involved in fabrication variations and changes in the
operation environment. Thus, the margins required by the
conventional circuit can be reduced, and hence the operation of a
circuit with a lower power supply voltage becomes possible.
[0050] As for the current source cells composed of the NMOS
transistors M21, M22P and M22N, and of the NMOS transistors M31,
M32P and M32N, they saturate in similar conditions.
[0051] In addition, since Vds11=BIAS3, in the NMOS transistors
M12P, M12N, M22P, M22N, M32P and M32N which are turned off when the
bias voltage BIAS3 is applied, the gate-source voltages become
zero, and the current does not flow if the threshold voltage is
positive.
[0052] Thus, the NMOS transistors M12P, M12N, M22P, M22N, M32P and
M32N have their gates supplied with the voltage that swings from
the bias voltage BIAS2 to BIAS3. Conventionally, the ground voltage
is used as the OFF voltage. Since the voltage range that swings is
reduced in the present embodiment, the charge injection quantities
flowing through the parasitic capacitances of the NMOS transistors
M12P, M12N, M22P, M22N, M32P and M32N are reduced. Consequently,
the noise of the D/A converter is reduced, and the performance such
as the S/N ratio and operation speed is improved.
[0053] Furthermore, in the conventional circuit, large charge
discharge currents flow instantaneously to the ground through the
switching transistors that turn from the ON state to the OFF state.
However, in the present embodiment 1, since the current does not
flow directly to the ground, the noise produced at the ground is
reduced, thereby further improving the S/N ratio and operation
speed.
[0054] Although FIG. 1 shows the current driven D/A converter
composed of the NMOS transistors, the current driven D/A converter
can also be composed of PMOS transistors.
[0055] FIG. 3 is a circuit diagram showing another configuration of
the current driven D/A converter of the embodiment 1 in accordance
with the present invention, in which the 3-bit D/A converter is
composed of the PMOS transistors.
[0056] Comparing the configuration of FIG. 3 with that of FIG. 1,
although the connection is reversed between the power supply and
the ground because the NMOS transistors are replaced by the PMOS
transistors, and the PMOS transistors are replaced by the NMOS
transistors, the remaining configuration is equivalent to that of
FIG. 1.
[0057] Such a circuit configuration can achieve the same effect as
that of FIG. 1.
[0058] As described above, according to the present embodiment 1,
the OFF control voltage of the NMOS transistors or PMOS transistors
M12P, M12N, M22P, M22N, M32P and M32N is set at a voltage closer to
the ON control voltage. As a result, the present embodiment 1 can
reduce the swing of the control voltage of the NMOS transistors or
PMOS transistors, reduce the noise due to the charge injections
through the parasitic capacitances, and reduce the noise of the
ground voltage or power supply voltage because of the flowing of
the discharge current from the parasitic capacitances into the
ground or power supply at the turn off of the transistors, thereby
being able to implement the high performance current driven D/A
converter.
[0059] In addition, the OFF control voltage is set in such a manner
that the gate-source voltages that turn off the NMOS transistors or
PMOS transistors M12P, M12N, M22P, M22N, M32P and M32N become zero
volt. As a result, the present embodiment 1 can further reduce the
swing of the control voltage, and reduce the noise due to the
parasitic capacitance, thereby being able to implement a higher
performance current driven D/A converter.
[0060] Besides, the present embodiment 1 can generate the bias
voltages free from the effect of the threshold voltage due to the
substrate bias effect, and can configure a bias circuit that
satisfies the saturation conditions of the D/A converter that
operates at the low voltage and has the low output voltage of the
current source, thereby being able to implement the high
performance current driven D/A converter.
[0061] Furthermore, it is also possible in FIG. 1 to insert the
current mirror (current mirror circuit) into the drain electrodes
of the NMOS transistors M92 and M93 to cause the current equal to
the drain current of the NMOS transistor M93 to flow through the
NMOS transistor M92. Although it is necessary in this case to set
the current ratio between the PMOS transistor M91 and the NMOS
transistors M94A and M94B at high accuracy, using the current
mirror circuit can achieve it with a small circuit easily.
[0062] In addition, it is also possible in FIG. 3 to insert the
current mirror (current mirror circuit) into the drain electrodes
of the PMOS transistors M92 and M93 to cause the current equal to
the drain current of the PMOS transistor M93 to flow through the
PMOS transistor M92. Although it is necessary in this case to set
the current ratio between the NMOS transistor M91 and the PMOS
transistors M94A and M94B at high accuracy, using the current
mirror circuit can achieve it with a small circuit easily.
[0063] Besides, although the bias circuits of the current driven
D/A converters as shown in FIGS. 1 and 3 are applicable as the
control voltage supply for the current source cells of the current
driven D/A converters as shown in FIGS. 1 and 3, the bias circuits
are also applicable as the control voltage supply of the current
source cells of other current driven D/A converters.
[0064] Furthermore, it is also possible to provide a voltage buffer
20 to the output stage of the bias circuit of the current driven
D/A converter as shown in FIGS. 1 and 3, and to supply the bias
voltages via the voltage buffer to the current source cells of the
current driven D/A converter as the control voltage. The voltage
buffer 20 installed at the output stage of the bias circuit can
reduce the output impedance of the bias circuit, thereby being able
to provide the bias voltage unsusceptible to the effect of
noise.
Embodiment 2
[0065] FIG. 4 is a circuit diagram showing a configuration of the
current driven D/A converter of an embodiment 2 in accordance with
the present invention. In FIG. 4, a PMOS transistor M99 has its
source electrode connected to a power supply, and its gate
electrode connected to the gate electrodes of the PMOS transistors
M95, M96 and M91, thereby configuring a current mirror circuit. An
NMOS transistor M100 has its drain electrode and gate electrode
connected to the drain electrode of the PMOS transistor M99 to
supply the bias voltage BIAS3 to the current source cells, its
source electrode connected to the source electrode of the NMOS
transistor M92 and to the source electrode and back gate electrode
of the NMOS transistor M93. The remaining configuration is the same
as that of FIG. 1.
[0066] Next, the operation will be described.
[0067] In FIG. 4, the bias voltage BIAS3 is generated by the PMOS
transistor M99 and NMOS transistor M100. The gate-source voltage of
the NMOS transistor M100 can be adjusted to the threshold voltage
Vth of the NMOS transistor M100 by flowing a minute current through
the NMOS transistor M100 by adjusting the size of the PMOS
transistor M99. In this case, the swing range of the gate voltages
of the switching transistors become smaller, thereby being able to
further reduce the charge injection quantity.
[0068] Although FIG. 4 shows the current driven D/A converter
composed of the NMOS transistors, the current driven D/A converter
can also be composed of PMOS transistors.
[0069] FIG. 5 is a circuit diagram showing another configuration of
the current driven D/A converter of the embodiment 2 in accordance
with the present invention, in which the 3-bit D/A converter is
composed of the PMOS transistors.
[0070] Comparing the configuration of FIG. 5 with that of FIG. 4,
although the connection is reversed between the power supply and
the ground because the NMOS transistors are replaced by the PMOS
transistors, and the PMOS transistors are replaced by the NMOS
transistors, the remaining configuration is equivalent to that of
FIG. 4.
[0071] Such a circuit configuration can achieve the same effect as
that of FIG. 4.
[0072] As described above, according to the present embodiment 2,
the OFF control voltage is set in such a manner that the
gate-source voltages of the NMOS transistors or PMOS transistors
M12P, M12N, M22P, M22N, M32P and M32N become equal to the threshold
voltage of the NMOS transistors or PMOS transistors. As a result,
the present embodiment 2 can further reduce the swing of the
control voltage, and reduce the noise due to the parasitic
capacitance, thereby being able to implement the higher performance
current driven D/A converter.
Embodiment 3
[0073] FIG. 6 is a circuit diagram showing a configuration of a
folded cascode operational amplifier to which the current driven
D/A converter of an embodiment 3 in accordance with the present
invention is applied. In FIG. 6, the folded cascode operational
amplifier includes a differential pair composed of NMOS transistors
M11P and M11N and a differential pair composed of NMOS transistors
M13A and M13B, and an output stage composed of PMOS transistors
M14P, M14N, M15P and M15N and NMOS transistors M16P, M16N, M17P and
M17N. Input voltages VIP and VIN are applied to the gate electrodes
of the NMOS transistors M11P and M11N. An output voltage VOUTP is
output from between the PMOS transistor M15N and NMOS transistor
M16N, and an output voltage VOUTN is output from between the PMOS
transistor M15P and NMOS transistor M16P. In the folded cascode
operational amplifier, all the transistors must operate in the
saturation region.
[0074] A bias circuit (conventional circuit) composed of PMOS
transistors M21P, M21N, M22P and M22N, and NMOS transistors M23P,
M23N, M24P and M24N, and a resistor R1 generates a bias voltage
BIAS1 and a bias voltage BIAS4.
[0075] A bias circuit (employing the embodiment 1) composed of PMOS
transistors M101A, M101B, M102, M105 and M106, and NMOS transistors
M103, M104, M107 and M108 is provided for generating the bias
voltage BIAS2. The circuit, which operates in the same manner as
the bias circuit of the current driven D/A converter of the
embodiment 1, is free from the substrate bias effect. Accordingly,
it can easily generate the bias voltage that saturates the PMOS
transistors M14P and M14N independently of the fabrication
variations and operation environment.
[0076] A bias circuit (employing the embodiment 1) composed of PMOS
transistors M203, M204, M207 and M208, and NMOS transistors M201A,
M201B, M202, M205 and M206 is provided for generating the bias
voltage BIAS3. The circuit, which is also free from the substrate
bias effect, can easily generate the bias voltage that saturates
the PMOS transistors M17P and M17N independently of the fabrication
variations and operation environment.
[0077] As described above, the present embodiment 3 employs the
bias circuit of the embodiment 1 as the bias circuits for
generating the bias voltages BIAS2 and BIAS3. As a result, since it
is free from the substrate bias effect, the present embodiment 3
can easily generate the bias voltages that saturate the transistors
easily independently of the fabrication variations or the operation
environment in the folded cascode operational amplifier.
* * * * *