U.S. patent application number 11/893049 was filed with the patent office on 2008-01-24 for ferroelectric memory and its manufacturing method.
Invention is credited to Shinich Fukada, Kazuhiro Masuda, Mamoru Ueda.
Application Number | 20080020492 11/893049 |
Document ID | / |
Family ID | 35943784 |
Filed Date | 2008-01-24 |
United States Patent
Application |
20080020492 |
Kind Code |
A1 |
Ueda; Mamoru ; et
al. |
January 24, 2008 |
Ferroelectric memory and its manufacturing method
Abstract
A ferroelectric memory includes a base member, a first
dielectric layer formed above the base member, a second dielectric
layer formed above the first dielectric layer, a contact hole that
penetrates the first and second dielectric layers, a plug formed in
the contact hole, and a barrier layer formed above the plug, and a
ferroelectric capacitor formed from a lower electrode, a
ferroelectric layer and an upper electrode successively laminated
in a region including above the plug. The second dielectric layer
has a property that is more difficult to be polished than the plug
and the first dielectric layer.
Inventors: |
Ueda; Mamoru; (Suwa, JP)
; Masuda; Kazuhiro; (Fujimi, JP) ; Fukada;
Shinich; (Hamura, JP) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 828
BLOOMFIELD HILLS
MI
48303
US
|
Family ID: |
35943784 |
Appl. No.: |
11/893049 |
Filed: |
August 14, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11210010 |
Aug 23, 2005 |
7279342 |
|
|
11893049 |
Aug 14, 2007 |
|
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Current U.S.
Class: |
438/3 ;
257/E21.09; 257/E21.664; 257/E27.104 |
Current CPC
Class: |
H01L 27/11502 20130101;
H01L 27/11507 20130101 |
Class at
Publication: |
438/003 ;
257/E21.09 |
International
Class: |
H01L 21/20 20060101
H01L021/20 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 25, 2004 |
JP |
2004-245361 |
Claims
1. A method for manufacturing a ferroelectric memory, comprising:
(a) forming a contact hole that penetrates a first dielectric layer
formed above a base member, and a second dielectric layer formed
above the first dielectric layer; (b) forming a conductive layer
inside the contact hole and above the second dielectric layer; (c)
forming a plug inside the contact hole, having an upper surface at
a position lower than an upper surface of the second dielectric
layer, by polishing the conductive layer until the second
dielectric layer is exposed; (d) forming a barrier layer inside the
contact hole and above the plug; and (e) forming a ferroelectric
capacitor by successively laminating a lower electrode, a
ferroelectric layer and an upper electrode in a region including
above the plug, wherein the second dielectric layer has a property
that is more difficult to be polished than the conductive layer and
the first dielectric layer.
2. A method for manufacturing a ferroelectric memory according to
claim 1, further comprising forming another barrier layer along an
inner surface of the contact hole before the step (b), wherein the
plug is formed inside the another barrier layer in the step
(c).
3. A method for manufacturing a ferroelectric memory according to
claim 1, wherein the step (c) includes a step conducted by a
chemical mechanical polishing method.
4. A method for manufacturing a ferroelectric memory according to
claim 1, wherein, in the step (c), an upper portion of the
conductive layer inside the contact hole is further removed by
etching.
5. A method for manufacturing a ferroelectric memory according to
claim 1, further comprising forming an adhesion layer in a region
including above the barrier layer, after the step (d), wherein the
ferroelectric capacitor is formed above the adhesion layer in the
step (e).
6. A method for manufacturing a ferroelectric memory according to
claim 5, wherein, in the step (e), the lower electrode, the
ferroelectric layer and the upper electrode are successively
laminated to form a laminated body, and the laminated body and the
adhesion layer are patterned by a common process.
Description
RELATED APPLICATIONS
[0001] This application is a divisional patent application of U.S.
Ser. No. 11/210,010, filed Aug. 23, 2005 and claims priority to
Japanese Patent Application No. 2004-245361 filed Aug. 25, 2004
which is hereby expressly incorporated by reference herein in its
entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The present invention relates to ferroelectric memories and
methods for manufacturing the same.
[0004] 2. Related Art
[0005] For ferroelectric memories, the structure in which a
ferroelectric capacitor is stacked on a selection transistor is
known. A dielectric layer is provided between the ferroelectric
capacitor and the selection transistor, and an electrical
connection between them is made by a plug embedded in a contact
hole in the dielectric layer. The plug is formed by forming a film
of conductive layer that is a plug material inside the contact hole
and on the dielectric layer, and the entire conductive layer is
polished by using a chemical mechanical polishing (CMP) method or
the like. However, in this case, a recess (concave section), which
is caused by a difference in the polishing rate between the
conductive layer and the surrounding dielectric layer, is generated
in the conductive layer at the contact hole. If the recess is left
remained, the ferroelectric capacitor cannot be formed on a flat
surface, so that the stability in the manufacturing process may be
damaged, and the reliability may possibly be lowered. It is noted
that, in the process of manufacturing the ferroelectric capacitor,
a process of oxidizing the ferroelectric layer is necessary, and
therefore prevention of oxidation of the plug is required.
[0006] It is an object of the present invention to provide
ferroelectric memories that can improve the reliability and methods
for manufacturing the same.
SUMMARY
[0007] A ferroelectric memory in accordance with the present
invention includes:
[0008] a base member;
[0009] a first dielectric layer formed above the base member;
[0010] a second dielectric layer formed above the first dielectric
layer;
[0011] a contact hole that penetrates the first dielectric layer
and the second dielectric layer;
[0012] a plug formed in the contact hole, and a barrier layer
formed above the plug; and
[0013] a ferroelectric capacitor formed from a lower electrode, a
ferroelectric layer and an upper electrode successively laminated
in a region including above the plug,
[0014] wherein the second dielectric layer has a property that is
more difficult to be polished than the plug and the first
dielectric layer.
[0015] According to the present invention, when the plug is formed
by conducting a polishing treatment by a planarization process,
because the second dielectric layer that is more difficult to be
polished than the first dielectric layer serves as a stopper, the
amount of recess in the plug can be made greater. For this reason,
the barrier layer can be readily thickly formed, and oxidation of
the plug can be effectively prevented. Also, the second dielectric
layer serves as a hydrogen barrier for the ferroelectric capacitor,
such that deterioration of the ferroelectric layer by hydrogen that
is generated from the first dielectric layer can be prevented.
[0016] It is noted that, in the present invention, a case in which
a layer B provided above a specific layer A includes a case where a
layer B is provided directly on a layer A, and a case where a layer
B is provided above a layer A through another layer. This similarly
applies to the following inventions.
[0017] The ferroelectric memory may further include an adhesion
layer that is formed between the lower electrode and the barrier
layer, and formed in a region including the lower electrode.
[0018] By this, the adhesion to the lower electrode can be
improved.
[0019] In the ferroelectric memory, the barrier layer may include
one of a titanium aluminum nitride layer and a titanium nitride
layer.
[0020] In the ferroelectric memory, the second dielectric layer may
include one of a silicon nitride layer, a silicon oxinitride layer
and an aluminum oxide layer.
[0021] The ferroelectric memory may further include another barrier
layer that is formed along an inner surface of the contact hole,
wherein the plug may be formed inside the other barrier layer.
[0022] A method for manufacturing a ferroelectric memory in
accordance with the present invention includes:
[0023] (a) forming a contact hole that penetrates a first
dielectric layer formed above a base member, and a second
dielectric layer formed above the first dielectric layer;
[0024] (b) forming a conductive layer inside the contact hole and
above the second dielectric layer;
[0025] (c) forming a plug inside the contact hole, having an upper
surface at a position lower than an upper surface of the second
dielectric layer, by polishing the conductive layer until the
second dielectric layer is exposed;
[0026] (d) forming a barrier layer inside the contact hole and
above the plug; and
[0027] (e) forming a ferroelectric capacitor by successively
laminating a lower electrode, a ferroelectric layer and an upper
electrode in a region including above the plug,
[0028] wherein the second dielectric layer has a property that is
more difficult to be polished than the conductive layer and the
first dielectric layer.
[0029] According to the present invention, when the conductive
layer is formed by conducting a polishing treatment by a
planarization process, the second dielectric layer that is more
difficult to be polished than the first dielectric layer serves as
a stopper, such that the amount of recess in the plug can be made
greater. For this reason, the barrier layer can be readily thickly
formed, and oxidation of the plug can be effectively prevented.
Also, the second dielectric layer serves as a hydrogen barrier for
the ferroelectric capacitor, such that deterioration of the
ferroelectric layer by hydrogen that is generated from the first
dielectric layer can be prevented.
[0030] In the method for manufacturing a ferroelectric memory may
further include forming another barrier layer along an inner
surface of the contact hole, before the step (b), wherein the plug
may be formed inside the other barrier layer in the step (c).
[0031] In the method for manufacturing a ferroelectric memory, the
step (c) may include a step conducted by a chemical mechanical
polishing method.
[0032] In the method for manufacturing a ferroelectric memory, in
the step (c), an upper portion of the conductive layer inside the
contact hole may be further removed by etching.
[0033] By this, the upper portion of the conductive layer is
further removed, and therefore the barrier layer can be formed much
thicker.
[0034] The method for manufacturing a ferroelectric memory may
further include forming an adhesion layer in a region including
above the barrier layer, after the step (d), wherein the
ferroelectric capacitor may be formed above the adhesion layer in
the step (e).
[0035] By this, the adhesion to the lower electrode can be
improved.
[0036] In the method for manufacturing a ferroelectric memory, in
the step (e), the lower electrode, the ferroelectric layer and the
upper electrode may be successively laminated to form a laminated
body, and the laminated body and the adhesion layer may be
patterned in the same process.
[0037] By this, the laminated body that becomes the ferroelectric
capacitor and the adhesion layer can be patterned in the same
process, such that the manufacturing process can be simplified.
BRIEF DESCRIPTION OF THE DRAWINGS
[0038] FIG. 1 is a view showing a ferroelectric memory in
accordance with a first embodiment of the present invention.
[0039] FIG. 2 is a view showing a method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0040] FIG. 3 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0041] FIG. 4 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0042] FIG. 5 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0043] FIG. 6 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0044] FIG. 7 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0045] FIG. 8 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0046] FIG. 9 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the first embodiment of the
present invention.
[0047] FIG. 10 is a view showing a ferroelectric memory in
accordance with a second embodiment of the present invention.
[0048] FIG. 11 is a view showing a method for manufacturing the
ferroelectric memory in accordance with the second embodiment of
the present invention.
[0049] FIG. 12 is a view showing the method for manufacturing the
ferroelectric memory in accordance with the second embodiment of
the present invention.
DETAILED DESCRIPTION
[0050] Embodiments of the present invention are described below
with reference to the accompanying drawings.
First Embodiment
[0051] FIG. 1 is a view schematically showing a ferroelectric
memory in accordance with a first embodiment of the present
invention.
[0052] The ferroelectric memory in accordance with the present
embodiment includes a base member 10, first and second dielectric
layers 12 and 14, a contact hole 20, a contact section 30, and a
ferroelectric capacitor 40.
[0053] The base member 10 is a semiconductor substrate (for
example, a silicon substrate). A plurality of transistors (not
shown) is formed in the base member 10. Each transistor includes an
impurity region that becomes to be a source region or a drain
region, a gate dielectric layer, and a gate electrode. An element
isolation region (not shown) is formed between adjacent
transistors, to provide electrical insulation between the
transistors. The ferroelectric memory in accordance with the
present embodiment is, for example, a 1T1C type with a stacked
structure.
[0054] The first dielectric layer 12 is formed on the base member
10. When the base member 10 is formed from a silicon substrate, the
first dielectric layer 12 may be formed from, for example, a
silicon oxide layer (SiO.sub.2 layer).
[0055] The second dielectric layer 14 is formed on the first
dielectric layer 12. In other words, the first and second
dielectric layers 12 and 14 are successively laminated over the
base member 10. The second dielectric layer 14 has a property that
is more difficult to be (chemically and mechanically) polished
(property of a smaller polishing rate) than the first dielectric
layer 12 or a plug 34 to be described below. The second dielectric
layer 14 may be formed from at least one of, for example, a silicon
nitride layer (SiN layer), a silicon oxinitride layer (SiON layer)
and an aluminum oxide layer (Al.sub.2O.sub.3 layer). It is noted
that the second dielectric layer 14 may cover the entire upper
surface of the first dielectric layer 12.
[0056] The contact hole 20 penetrates the first and second
dielectric layers 12 and 14. More specifically, the contact hole 20
includes a bore 22 that penetrates the first dielectric layer 12
and a second bore 24 that penetrates the second dielectric layer 14
(see FIG. 3), and is formed with the two connected to each other.
The contact section 30 having electrical conductivity is formed in
the contact hole 20.
[0057] The contact hole 30 is formed extending in a direction
orthogonal to the surface of the base member 10, and penetrates the
first and second dielectric layers 12 and 14. One of end sections
of the contact section 30 is electrically connected to a transistor
(either a source region or a drain region) in the base substrate
10, and the other end section is electrically connected to the
ferroelectric capacitor 40. In other words, the contact section 30
electrically connects the transistor and the ferroelectric
capacitor 40.
[0058] The contact section 30 includes a plug 34 and a barrier
layer 36 over the plug 34. In the example shown in FIG. 1, the
contact section 30 further includes another barrier layer 32 formed
along an inner surface (bottom surface and side surface) of the
contact hole 20. In this case, the plug 34 is formed on the inside
surrounded by the barrier layer 32. The plug 34 is formed inside
the contact hole 20, and includes, for example, a tungsten (W)
layer. The barrier layer 36 may be formed from at least one of, for
example, a titanium aluminum nitride layer (TiAlN layer) and a
titanium nitride layer (TiN layer). The barrier layer 32 formed
along the inner surface of the contact hole 20 may be formed from
the same material as that of the barrier layer 36 provided on the
plug 34. The barrier layers 32 and 36 make diffusion prevention and
oxidation prevention for the plug 34 possible, and the resistance
of the contact section 30 can be lowered. Also, the barrier layer
36 may be used to improve the adhesion between the plug 34 and a
lower electrode 42 to be described below.
[0059] It is noted that the plug 34 has a property that is easier
to be polished than the second dielectric layer 14. By this, when
the plug 34 is formed by conducting a polishing treatment (for
example, a chemical mechanical polishing treatment) by a
planarization process, the second dielectric layer 14 can be used
as a stopper. In other words, the material of the plug 34 can be
preferentially polished while the second dielectric layer 14 is
hardly polished.
[0060] The ferroelectric capacitor 40 is formed in a region
including above the plug 34 (the contact section 30). In other
words, in a plan view viewed in a direction orthogonal to the
surface of the base member 10, a plane area of the ferroelectric
capacitor 40 includes the plug 34 and its surrounding area (the
second dielectric layer 14).
[0061] The ferroelectric capacitor 40 is formed from a lower
electrode 42, a ferroelectric layer 44 and an upper electrode 46
successively laminated. The lower electrode 42 is electrically
connected to the plug 34 through the barrier layer 36. More
specifically, the lower electrode 42 of the ferroelectric capacitor
40 is electrically connected to either the source region or the
drain region of the transistor. In the ferroelectric memory of the
present embodiment, the lower electrode 42 of the ferroelectric
capacitor 40 is electrically connected to a bit line, and the upper
electrode 46 of the ferroelectric capacitor 40 is electrically
connected to a plate line, and a gate electrode of the transistor
is electrically connected to a word line.
[0062] The lower electrode 42 and the upper electrode 46 may be
formed from, for example, Pt, Ir, Ir oxide (IrO.sub.x), Ru, Ru
oxide (RuO.sub.x), SrRu compound oxide (SrRuO.sub.x), or the like.
Each of the lower electrode 42 and the upper electrode 46 may be
formed from a single layer, or a plurality of layers.
[0063] The ferroelectric layer 44 may be formed with a PZT type
ferroelectric composed of oxides including Pb, Zr and Ti as
constituting elements. Alternatively, Pb (Zr, Ti, Nb) O.sub.3 (PZTN
type) in which Nb is doped at the Ti site may be used.
Alternatively, the ferroelectric layer 44 may not be limited to
these materials, and for example, any of SBT type, BST type, BIT
type and BLT type material can be used.
[0064] In the ferroelectric memory in accordance with the present
embodiment, for example, when the plug 34 is formed through
conducting a polishing treatment by a planarization process (see a
manufacturing method to be described below), the amount of recess
at the plug 34 can be made greater because the second dielectric
layer 14 that is more difficult to be polished than the first
dielectric layer 12 serves as a stopper. For this reason, the
barrier layer 36 can be readily thickly formed, and oxidation of
the plug 34 can be effectively prevented. As a result, an increase
in the resistance and a volume expansion of the plug 34 can be
prevented. Also, the second dielectric layer 14 serves as a
hydrogen barrier for the ferroelectric capacitor 40, such that the
ferroelectric layer 44 can be prevented from becoming deteriorated
(reduced) by hydrogen that is generated from the first dielectric
layer 12.
[0065] Next, a method for manufacturing a ferroelectric memory in
accordance with an embodiment is described. FIG. 2-FIG. 9 are views
schematically showing a method for manufacturing a ferroelectric
memory in accordance with the present embodiment.
[0066] As shown in FIG. 2, a first dielectric layer 12 is formed on
a base member 10. The first dielectric layer 12 is formed on a
surface of the base member 10 where plural transistors are formed.
Next, a second dielectric layer 14 is formed on the first
dielectric layer 12. The second dielectric layer 14 may be formed
in a manner to cover the entire upper surface of the first
dielectric layer 12. The first and second dielectric layers 12 and
14 may be formed by using a known technique such as a CVD (Chemical
Vapor Deposition) method. It is noted that the materials and
properties of the first and second dielectric layers 12 and 14 are
the same as those described above.
[0067] As shown in FIG. 3, a contact hole 20 that penetrates the
first and second dielectric layers 12 and 14 is formed. In this
case, a photolithography technique may be used. More specifically,
a resist layer (not shown) that opens over a portion of the second
dielectric layer 14 is formed. The portion that opens through the
resist layer is etched, thereby forming a bore 24 that penetrates
the second dielectric layer 14 and a bore 22 that penetrates the
first dielectric layer 12. The contact hole 20 includes the bore 22
and the bore 24, and the bores 22 and 24 are connected with each
other. The base member 10 is exposed through the contact hole
20.
[0068] As shown in FIG. 4 through FIG. 8, a contact section 30 is
formed in the contact hole 20. In the present embodiment, the
contact section 30 includes a plug 34, and barrier layers 32 and
36.
[0069] First, as shown in FIG. 4, a barrier layer (another barrier
layer) 31 is formed along an inner surface of the contact hole 20.
The barrier layer 31 may be formed by sputtering or the like. The
barrier layer 31 is formed on a side surface (end faces of the
first and second dielectric layers 12 and 14) of the contact hole
20 and a bottom surface (an upper surface of the base member 10) of
the contact hole 20, and on an upper surface of the second
dielectric layer 14 in a manner to be continuous with the portion
formed inside the contact hole 20. However, the barrier layer 31 is
formed in a manner not to embed the contact hole 20.
[0070] Next, as shown in FIG. 5, a conductive layer 33 is formed
inside the contact hole 20 and on the second dielectric layer 14.
The contact layer 33 is formed in a manner that the interior (more
specifically, the inside surrounded by the barrier layer 31) of the
contact hole 20 is embedded. When the barrier layer 31 is formed,
the conductive layer 33 is formed on the barrier layer 31. The
conductive layer 33 may be formed by sputtering or the like.
[0071] Then, as shown in FIG. 6, the conductive layer 33 is
polished. In the present embodiment, a portion of the conductive
layer 33 and a portion of the barrier layer 31 are polished and
removed. In other words, the conductive layer 33 (and the barrier
layer 31) is polished until the second dielectric layer 14 that
serves as a stopper is exposed. In the polishing process, a process
by a chemical mechanical polishing (CMP) method may be used.
Because the second dielectric layer 14 has a property that is more
difficult to be polished than the conductive layer 33, the
conductive layer 33 is more preferentially polished than the second
dielectric layer 14. As a result, a recess (a concave portion 26)
defined by the conductive layer 33 is generated inside the contact
hole 20. In the present embodiment, the second dielectric layer 14
that is more difficult to be polished than the first dielectric
layer 12 serves as a stopper, such that the amount of recess in the
conductive layer 33 (the plug 34) can be made greater. In other
words, the concave portion 26 can be formed deep, and therefore a
space can be secured for thickly forming the barrier layer 35 to be
described below. Also, because of the presence of the second
dielectric layer 14, the first dielectric layer 12 is not polished,
and therefore the surface around the contact hole 20 can be better
planarized than prior art. It is noted that, when the barrier layer
31 is more readily polished than the second dielectric layer 14,
the barrier layer 31 is also preferentially polished than the
second dielectric layer 14, and an upper portion of the barrier
layer 31 inside the contact hole 20 is also polished and removed,
as shown in FIG. 6.
[0072] After the aforementioned polishing process is completed, an
upper portion of the conductive layer 33 (the plug 34) inside the
contact hole 20 may be further removed, in order to form the recess
(the concave portion 26) much deeper. For example, the upper
portion of the conductive layer 33 may be etched (for example, by
dry etching). By so doing, the barrier layer 36 to be described
below can be formed much thicker. However, in the present
embodiment, because the concave portion 26 can be made deep by the
polishing process applied to the conductive layer 33 described
above, the etching process may be omitted.
[0073] In this manner, the plug 34 can be formed from the
conductive layer 33. An upper surface of the plug 34 is at a
position lower than the upper surface of the second dielectric
layer 14. In other words, the concave portion 26 is formed above
the plug 34. Also, the plug 34 is formed inside the barrier layer
32.
[0074] Next, as shown in FIG. 7, a barrier layer 35 is formed on
the plug 34 inside the contact hole 20 (in other words, in the
concave portion 26) and on the second dielectric layer 14. The
barrier layer 35 is formed in a manner to embed the concave portion
26. The barrier layer 35 may be formed by sputtering or the
like.
[0075] Then, as shown in FIG. 8, the barrier layer 35 is polished,
thereby forming a barrier layer 36 inside the contact hole 20 over
the plug 34. The details of the process for polishing the barrier
layer correspond to the details of the process for polishing the
conductive layer described above.
[0076] In this manner, the contact section 30 can be formed.
According to the present embodiment, the recess (concave portion
26) created in the process of forming the plug 34 is eliminated by
the formation of the barrier layer 36, such that the upper surface
of the contact section 30 and the upper surface of the second
dielectric layer 14 are generally flush with each other.
Accordingly, a ferroelectric capacitor 40 to be described below can
be formed on a flat surface. It is noted that the materials and
properties of the barrier layer 32, the plug 34 and the barrier
layer 36 are the same as those described above in conjunction with
the structure.
[0077] As shown in FIG. 9, a ferroelectric capacitor 40 is formed
in a region including above the plug 34. Concretely, a lower
electrode 42, a ferroelectric layer 44 and an upper electrode 46
are successively laminated to form a laminated body 41, and the
laminated body 41 is patterned in a specified configuration.
[0078] As a method for forming the lower electrode 42, a sputtering
method, a vacuum vapor deposition method, a CVD method, or the like
may be used. As a method for forming the ferroelectric layer 44, a
solution coating method (including a sol-gel method, a MOD (Metal
Organic Decomposition) method, or the like), a MOCVD (Metal Organic
Chemical Vapor Deposition) method, or the like can be used. It is
noted that the upper electrode 46 can be formed by using a like
method applied to the lower electrode 42.
[0079] Then, the laminated body 41 is patterned. By using a
photolithography technique, a resist layer R1 may be formed on the
laminated body 41, and portions of the laminated body 41 exposed
through the resist layer R1 may be removed by etching, as shown in
FIG. 9.
[0080] When the ferroelectric capacitor 40 is formed by patterning
the laminated body 41, an anneal treatment in an oxygen atmosphere
is conducted for stabilization of the ferroelectric layer 44 (for
example, for etching damage recovery). In the present embodiment,
because the barrier layer 36 having a predetermined thickness is
formed on the plug 34, oxidation of the plug 34 can be effectively
prevented.
[0081] According to the method for manufacturing a ferroelectric
memory in accordance with the present embodiment, when the
conductive layer 33 is formed by conducting a polishing treatment
by a planarization process, the second dielectric layer 14 that is
more difficult to be polished than the first dielectric layer 12
serves as a stopper, such that the amount of recess of the plug 34
can be made greater. For this reason, the barrier layer 36 can be
readily made thick, and oxidation of the plug 34 can be effectively
prevented. Also, the second dielectric layer 14 serves as a
hydrogen barrier for the ferroelectric capacitor, the ferroelectric
layer 44 can be prevented from becoming deteriorated (reduced) by
hydrogen generated from the first dielectric layer 12.
Second Embodiment
[0082] FIG. 10 is a view schematically showing a ferroelectric
memory in accordance with a second embodiment of the present
invention.
[0083] The ferroelectric memory in accordance with the present
embodiment includes the composition of the ferroelectric memory
described above, and further includes an adhesion layer 50.
[0084] The adhesion layer 50 is formed between a lower electrode 42
and a barrier layer 36 (a contact section 30). As shown in FIG. 10,
the lower electrode. 42 may be formed on one of surfaces of the
adhesion layer 50, and the barrier layer 36 may be formed on the
other surface. Also, the adhesion layer 50 is formed in a region
including the lower electrode 42. In other words, in a plan view
viewed in a direction orthogonal to the surface of the base member
10, a plane area of the adhesion layer 50 includes at least a plane
area of the lower electrode 42. For example, the plane area of the
adhesion layer 50 may generally match with the plane area of the
lower electrode 42. The adhesion layer 50 can improve adhesion of
the contact section 30 and the second dielectric layer 14 to the
ferroelectric capacitor 40.
[0085] The adhesion layer 50 may be formed from the same material
as that of the barrier layer 36 (for example, a TiAlN layer or a
TiN layer), or may be formed from a different material. The
adhesion layer 50 has a greater adhesion to the lower electrode 42
than to the plug 34. When the adhesion layer 50 is formed from a
material different from that of the barrier layer 36, the adhesion
layer 50 may have even a greater adhesion to the lower electrode 42
than to the barrier layer 36.
[0086] Next, a method for manufacturing a ferroelectric memory in
accordance with the present embodiment is described. FIG. 11 and
FIG. 12 are views schematically showing the method for
manufacturing a ferroelectric memory in accordance with the present
embodiment.
[0087] As shown in FIG. 11, after the contact section 30 is formed
in the contact hole 20, an adhesion layer 52 is formed in a region
including above the barrier layer 36. The adhesion layer 52 is
formed on the barrier layer 36 and on the surrounding second
dielectric layer 14. For example, the adhesion layer 52 may be
formed by sputtering or the like.
[0088] Then, as shown in FIG. 12, a laminated body 41 that becomes
a ferroelectric capacitor 40 is formed on the adhesion layer 52,
and the laminated body 41 and the adhesion layer 52 are patterned
in the same process. When the patterning is conducted by using a
photolithography technique, a resist layer R2 is formed on the
laminated body 41, and portions of the laminated body 41 exposed
through the resist layer R2 are removed by etching. By the same
etching process, both of the laminated body 41 and the adhesion
layer 52 may be patterned at the same time. Accordingly, the
ferroelectric capacitor 40 and the adhesion layer 50 can be
patterned and formed by the same process, such that the
manufacturing process can be simplified.
[0089] It is noted that other compositions and effects of the
present embodiment include the compositions and effects that can be
derived from the description of the first embodiment.
[0090] The present invention is not limited to the embodiments
described above, and many modifications can be made. For example,
the present invention may include compositions that are
substantially the same as the compositions described in the
embodiments (for example, a composition with the same function,
method and result, or a composition with the same objects and
results). Also, the present invention includes compositions in
which portions not essential in the compositions described in the
embodiments are replaced with others. Also, the present invention
includes compositions that achieve the same functions and effects
or achieve the same objects of those of the compositions described
in the embodiments. Furthermore, the present invention includes
compositions that include publicly known technology added to the
compositions described in the embodiments.
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