U.S. patent application number 11/758108 was filed with the patent office on 2008-01-24 for non-volatile semiconductor storage device.
Invention is credited to Yoshiki Kawajiri, Masaaki Mihara, Taku OGURA.
Application Number | 20080019162 11/758108 |
Document ID | / |
Family ID | 38971282 |
Filed Date | 2008-01-24 |
United States Patent
Application |
20080019162 |
Kind Code |
A1 |
OGURA; Taku ; et
al. |
January 24, 2008 |
NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
Abstract
This non-volatile semiconductor storage device includes a
flip-flop in which two inverters, each consisting of a load
transistor and a storage transistor connected in series, are
cross-connected; and two gate transistors, each respectively
connected to a node of the flip-flop on a side thereof. The storage
transistors of the inverters are constituted by storage transistors
which can be threshold voltage controlled by injection of electrons
into the neighborhood of their gates. This non-volatile
semiconductor storage device further includes two bit lines, each
of which is connected to a respective one of the two gate
transistors; a word line which is connected to both of the gate
electrodes of the two gate transistors; a first voltage supply line
which is connected to the sources of the storage transistors of the
inverters; and a second voltage supply line which is connected to
the sources of the load transistors of the inverters.
Inventors: |
OGURA; Taku; (Amagasaki-shi,
JP) ; Mihara; Masaaki; (Amagasaki-shi, JP) ;
Kawajiri; Yoshiki; (Amagasaki-shi, JP) |
Correspondence
Address: |
MARK D. SARALINO (GENERAL);RENNER, OTTO, BOISSELLE & SKLAR, LLP
1621 EUCLID AVENUE, NINETEENTH FLOOR
CLEVELAND
OH
44115-2191
US
|
Family ID: |
38971282 |
Appl. No.: |
11/758108 |
Filed: |
June 5, 2007 |
Current U.S.
Class: |
365/72 ;
365/203 |
Current CPC
Class: |
G11C 14/00 20130101;
G11C 14/0063 20130101; G11C 11/412 20130101 |
Class at
Publication: |
365/72 ;
365/203 |
International
Class: |
G11C 5/06 20060101
G11C005/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 21, 2006 |
JP |
2006-199673 |
Claims
1. A non-volatile semiconductor storage device, comprising: a
flip-flop in which two inverters, each consisting of a load
transistor and a storage transistor connected in series, are
cross-connected; two gate transistors, each respectively connected
to a node of said flip-flop on a side thereof; two bit lines, each
of which is connected to a respective one of said two gate
transistors, and which are controlled to a voltage between
operating power supply voltage and ground voltage; a word line
which is connected to both of the gate electrodes of said two gate
transistors, and which is controlled to a voltage between operating
power supply voltage and ground voltage; a first voltage supply
line which is connected to the sources of said storage transistors
of said inverters, and to which a predetermined first voltage is
supplied during writing and during erasure; and a second voltage
supply line which is connected to the sources of said load
transistors of said inverters, and to which a predetermined second
voltage is supplied during writing; wherein said storage
transistors of said inverters are constituted by storage
transistors which can be threshold voltage controlled by injection
of electrons into the neighborhood of their gates.
2. A non-volatile semiconductor storage device according to claim
1, wherein each of said storage transistor comprises: an insulation
layer side spacer which is formed at a side portion of its gate
electrode; and a low impurity density region which is formed at a
border portion of its drain; and wherein: during writing, said
first voltage supply line applies said first voltage to the sources
of said storage transistors, and said second voltage supply line
applies said second voltage to the gates of said storage
transistors via the sources of said load transistors; and thereby
information is written into said storage transistors by channel hot
electrons being injected into said insulation layer side spacers;
and during erasure, said first voltage supply line applies said
first voltage to the sources of said storage transistors; and
thereby information which is stored in said storage transistors is
erased by an avalanche of hot holes being injected into said
insulation layer side spacers.
3. A non-volatile semiconductor storage device according to claim
1, wherein each said inverter comprises a transistor for pre-charge
which is connected in parallel with said load transistor thereof;
and further comprising pre-charge control voltage supply lines
which supply pre-charge control voltages to the gates of said
transistors for pre-charge; and wherein said transistors for
pre-charge are ON/OFF controlled independently from said load
transistors by said pre-charge control voltages supplied by said
pre-charge control voltage supply lines.
4. A non-volatile semiconductor storage device according to claim
3, wherein said second voltage supply line is provided separately
for each of said inverters.
5. A non-volatile semiconductor storage device according to claim
3, wherein said first voltage supply line is provided separately
for each of said inverters.
6. A non-volatile semiconductor storage device according to claim
1, wherein the continuity resistances of the load transistors of
said two inverters are unbalanced.
7. A non-volatile semiconductor storage device according to claim
1, wherein the electrostatic capacitances with respect to the power
supply voltage lines, or with respect to ground, of said two
inverters are unbalanced.
8. A non-volatile semiconductor storage device according to claim
1, wherein the continuity resistances of the storage transistors of
said two inverters are unbalanced.
9. A method for determining the state of a non-volatile
semiconductor storage device according to claim 3, comprising a
step of supplying a pre-charge control voltage selectively to one
only of said pre-charge control voltage supply lines, and thereby
turning only one but not the other of said transistors for
pre-charge of said two inverters ON, thus forcibly determining the
state of said flip-flop.
10. A method for determining the state of a non-volatile
semiconductor storage device according to claim 4, comprising: a
step of supplying a voltage lower than said first voltage to said
first voltage supply line, and thereby raising the source
potentials of said storage transistors of said two inverters and
turning said storage transistors OFF; a step of supplying different
voltages to said second voltage supply lines, thereby applying
pre-charge voltages of different potentials to said nodes via said
transistors for pre-charge of said two inverters; and a step of
gradually decreasing said low voltage supplied to said first
voltage supply line, thereby gradually lowering the source
potentials of said storage transistors of said two inverters.
11. A method for determining the state of a non-volatile
semiconductor storage device according to claim 4, comprising: a
step of supplying voltages lower than said first voltage to said
first voltage supply lines, and thereby raising the source
potentials of said storage transistors of said two inverters and
turning said storage transistors OFF; a step of supplying the same
voltage to said second voltage supply lines, thereby applying
pre-charge voltages of the same potential to said nodes via said
transistors for pre-charge of said two inverters; and a step of
gradually decreasing said low voltages supplied to said first
voltage supply lines while maintaining a predetermined potential
difference therebetween, thereby gradually lowering the source
potentials of said storage transistors of said two inverters while
maintaining a predetermined potential difference therebetween.
12. A semiconductor integrated circuit device comprising a
non-volatile semiconductor storage device as described in claim 1,
a circuit which may require repair comprising a portion which may
require repair, and a redundancy circuit which serves as an
alternative to said circuit which may require repair; and wherein
said non-volatile semiconductor storage device is a storage circuit
which stores repair information specifying which circuit may
require repair by said redundancy circuit serving as an alternative
thereto.
13. A semiconductor integrated circuit device comprising a
non-volatile semiconductor storage device as described in claim 1,
an analog circuit, and a constant trimming circuit which adjusts a
circuit constant of said analog circuit; and wherein said
non-volatile semiconductor storage device is a storage circuit
which stores information in said constant trimming circuit for
specifying said circuit constant.
14. A semiconductor integrated circuit device comprising a
non-volatile semiconductor storage device as described in claim 1,
an oscillation circuit, and a frequency trimming circuit which
adjusts the oscillation frequency of said oscillation circuit; and
wherein said non-volatile semiconductor storage device is a storage
circuit which stores information in said frequency trimming circuit
for specifying said oscillation frequency.
15. A semiconductor integrated circuit device comprising a
non-volatile semiconductor storage device as described in claim 1,
a reference voltage generation circuit, and a voltage trimming
circuit which adjusts the reference voltage generated by said
reference voltage generation circuit; and wherein said non-volatile
semiconductor storage device is a storage circuit which stores
information in said voltage trimming circuit for specifying said
reference voltage.
16. A semiconductor integrated circuit device comprising a
non-volatile semiconductor storage device as described in claim 1,
and a security circuit which identifies a chip in which said
semiconductor integrated circuit device is mounted; and wherein
said non-volatile semiconductor storage device is a storage circuit
which stores information in said security circuit for specifying
said chip.
Description
CROSS REFERENCE
[0001] This Nonprovisional application claims priority under 35
U.S.C. .sctn. 119(a) on Patent Application No. 2006-199673 filed in
Japan on Jul. 21, 2006, the entire contents of which are hereby
incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a non-volatile
semiconductor storage device which can be electrically erased and
written, to a state determination method for such a semiconductor
storage device, and to a semiconductor integrated circuit device
incorporating such a semiconductor storage device.
[0003] Along with increase of internal SRAM capacity, the necessity
has increased for providing redundancy, for performing individual
tuning after making boards such as LCD drivers and the like, and
for low cost fuses which are being demanded along with the great
increase in various types of application which involve personal
identification information (ID codes, encryption and decryption
keys, numbers of IC cards, and the like).
[0004] In the prior art, as fuse elements which can be made with a
standard CMOS process, there is a known one in which a polysilicon
or metal wiring layer is blown out by a laser or an electrical
current, a known one in which an insulating gate layer or the like
is destroyed by voltage, and the like. However, such a fuse which
employs such a blowing out or insulation destruction method or the
like is not suitable for the application described above, since it
can only be programmed once.
[0005] On the other hand, in the case of using a non-volatile
element of the floating gate type which can be manufactured by a
CMOS process, although it is possible to implement a fuse which can
be electrically erased and written, introduction of a special
process for making the transistors non-volatile, such with a prior
art type flash memory, is not appropriate from the point of view of
cost. Furthermore, with a floating gate type element made with a
standard CMOS process, there has been the problem that the data
storage characteristics deteriorate as the insulating layer becomes
thinner along with increase of the integration scale.
[0006] Thus in, for example, U.S. Pat. No. 6,518,614, Japanese
Laid-Open Patent Publication 2004-56095, and Japanese Laid-Open
Patent Publication 2005-353106, there are disclosed a non-volatile
storage device which can be manufactured by a standard CMOS
process, and a non-volatile storage device which does not have any
special floating gates.
[0007] FIG. 1 is a figure showing the memory cell structure of a
non-volatile storage device which has been manufactured by a
standard CMOS process, as disclosed in Japanese Laid-Open Patent
Publication 2005-353106. Fundamentally, this consists of N-type MOS
transistors MCN1 and MCN2 which constitute a non-volatile data
storage unit, and a flip-flop unit (MN3, MN4, MP1, and MP2) of a
static latch type which takes the output nodes T and B of the
non-volatile data storage unit as differential inputs. In this
flip-flop unit, normal reading out and writing SRAM operation is
performed. Furthermore, it is possible to reload the information of
the non-volatile data storage unit and to store data in the
flip-flop unit.
[0008] FIG. 2 show the data setting method. This data setting
method is a method in which the data is determined by the voltage
difference between the threshold values of the two N-type MOS
transistors MCN1 and MCN2. In the initial state (FIG. 2A) before
writing data, the N-type MOS transistors MCN1 and MCN2 both have
the threshold voltage Vth, and, in this state, the output data of
the flip-flop is indeterminate. In order to determine the data,
first, writing of the data to "0" is performed (FIG. 2B). This
writing is implemented by raising the threshold voltage on the side
of MCN1 to Vth1 (where Vth1>Vth0). With this structure, it is
not possible to perform erasure (reduction of Vth). Because of
this, subsequent writing of the data "1" from the data "0" state is
implemented by raising the threshold voltage on the side of MCN2 to
Vth2 (where Vth2>Vth1) (FIG. 2C).
[0009] FIG. 3 shows the method for changing the threshold voltages
of the N-type MOS transistors of the above described non-volatile
data storage unit. In FIG. 3, the data "0" case is shown, i.e. the
case in which the threshold voltage on the side of MCN1 is raised.
Fundamentally, positive advantage is taken of the deterioration
characteristic of an N-type MOS transistor due to hot carriers. In
other words, it is arranged to set to 0 V the source potential of
that transistor MCN1 whose threshold voltage it is desired to
raise, to set its gate potential (MLW) to 2.5 V, and to set its
drain potential (the node T) to 5V, thereby raising its threshold
voltage in the vicinity of its drain terminal by the hot carrier
injection phenomenon. At this time, in order for the potential of
the bit line BLT to be sufficiently supplied to the node T, it is
necessary to raise the potential of BLT to 5 V, and to raise the
potential of the word line WL of the flip-flop unit to 7V. As for
that transistor MCN2 whose threshold voltage it is not desired to
raise, by setting the potential of BLB to 0 V, it is arranged for
hot carrier injection not to take place in the vicinity of the
drain terminal of that transistor MCN2. And, when writing the data
"1", since the threshold voltage on the side of MCN2 is be raised,
BLT is set to 0 V and BLB is set to 5 V. The other conditions are
the same as when writing the data "0".
[0010] FIG. 4 shows the method for transferring data transfer from
the non-volatile data storage unit to the flip-flop unit. This
figure shows the data transfer method in the data "0" case, in
other words when the threshold voltage Vth1 of MCN1 is higher than
the threshold voltage Vth0 of MCN2. In the state of the flip-flop
unit in which the word line WL=0 V and a restore control signal
RESTORE=0 V, by lowering an equalization control signal ZEQ from
Vcc to 0 V at the time instant T0, the node T and the node B are
equalized at the same potential. This equalization operation ends
at the time instant T1. And MLW, which is the gate potential of the
transistors MCN1 and MCN2, is gradually raised from the time
instant T2. When this is done, MCN2 is turned ON first, being that
transistor whose threshold voltage is the lower, and the potential
at the node B is pulled down. Although MCN1 also goes ON after some
time, finally the latch is established in the state in which the
node B on the side of the transistor MCN2 whose threshold voltage
is the lower has reached 0 V, while the node T on the side of the
transistor MCN1 has reached Vcc. And the rising of MLW is completed
at the time instant T3. By raising RESTORE from 0 V to Vcc at the
time instant T4, the latching of the flip-flop unit is activated,
and the data is held in a stable manner. Finally, at the time
instant T5, MLW reaches 0 V and this process terminates.
[0011] While the operation of such a memory cell is as described
above, there are the following problems with this structure.
[0012] (1) The margin of threshold voltage difference is small.
[0013] Vth1-Vth0 corresponds to this threshold voltage difference
margin in the case of the data "0", and Vth2-Vth1 in the case of
the data "1". To some extent, there is an upper limit value Vth_max
for the amount of change of the threshold voltage due to the hot
carrier injection phenomenon. If the margin is allocated equally
between reading out the data "0" and the data "1", then, if it is
supposed that rewriting is performed once, the margin for each
becomes (Vth_max-Vth0)/2. And, if it is supposed that rewriting is
performed N times, then taking the maximum value of Vth_control as
Vth_max, it must be divided into 2N portions, and the margin of
each of the data "0" and the data "1" becomes (Vth_max-Vth0)/2N, so
that the margin becomes yet smaller.
[0014] (2) As operating voltages when writing data into this
non-volatile data storage unit, it is necessary to apply high
voltages (7 V and 5 V) to the word line WL and to the bit lines BLT
and BLB for each memory cell which it is necessary to control. This
means that it is necessary to use high withstand voltage
transistors for the drivers which drive the word lines and the bit
lines, and for the column selection transistors for selecting the
bit lines. Since the performance with high withstand voltage
transistors, which are optimized for high voltage, is deteriorated
when operating at Vcc=1.8 V as during normal reading out operation,
accordingly the problem occurs that this entails access delay. And
increasing the size of the transistors in order to increase the
current drive capability causes the accompanying problem that the
chip area becomes large.
[0015] One object of the present invention is to provide a
rewritable non-volatile semiconductor storage device, with which it
is possible to make the reading out margin large.
[0016] A further object of the present invention is to provide a
rewritable non-volatile semiconductor storage device, with which it
is possible to perform control of the word lines and the bit lines
at the Vcc level.
[0017] Other objects of the present invention are to provide a
state determination method for such a semiconductor storage device,
and to provide a semiconductor integrated circuit device
incorporating such a semiconductor storage device.
SUMMARY OF THE INVENTION
[0018] The non-volatile semiconductor storage device of the present
invention includes a flip-flop in which two inverters, each
consisting of a load transistor and a storage transistor connected
in series, are cross-connected; and two gate transistors, each
respectively connected to a node of said flip-flop on a side
thereof.
[0019] Furthermore, the non-volatile semiconductor storage device
of the present invention includes two bit lines, each of which is
connected to a respective one of said two gate transistors, and a
word line which is connected to both of the gate electrodes of said
two gate transistors. These two bit lines and this word line are
controlled to a voltage between operating power supply voltage and
ground voltage.
[0020] Moreover, the non-volatile semiconductor storage device of
the present invention includes a first voltage supply line which is
connected to the sources of said storage transistors of said
inverters, and a second voltage supply line which is connected to
the sources of said load transistors of said inverters. A
predetermined first voltage is supplied to the first voltage supply
line during writing and during erasure. And a predetermined second
voltage is supplied to the second voltage supply line during
writing. This predetermined first voltage and this predetermined
second voltage may be, for example, high voltages greater than or
equal to the operating power supply voltage.
[0021] These storage transistors are constituted by storage
transistors which can be threshold voltage controlled by injection
of electrons into the neighborhood of their gates. In the
non-volatile semiconductor storage device described above, the
writing and erasure of data are implemented by controlling the
threshold voltages of the storage transistors. These threshold
voltages are provided via the first voltage supply line and the
second voltage supply line which are connected to the two ends of
the two inverters (the sources of the load transistors and the
sources of the storage transistors).
[0022] Accordingly, when performing writing by elevating the
threshold voltage of a first one of the storage transistors, and
when performing erasure by lowering the threshold voltage of this
first one of the storage transistors, this may be performed by the
word lines and the bit lines operating at the level of the
operating power supply voltage (Vcc). For this, in the above
described non-volatile semiconductor storage device which makes it
possible for peripheral circuitry to be more compact and be read
out at higher speed, each of the storage transistors further
includes an insulation layer side spacer which is formed at a side
portion of its gate electrode; and a low impurity density region
which is formed at a border portion of its drain.
[0023] During writing, said first voltage supply line applies said
first voltage to the sources of said storage transistors, and said
second voltage supply line applies said second voltage to the gates
of said storage transistors via the sources of said load
transistors; and thereby information is written into said storage
transistors by channel hot electrons being injected into said
insulation layer side spacer.
[0024] And, during erasure, said first voltage supply line applies
said first voltage to the sources of said storage transistors; and
thereby erasure of information which is stored in said storage
transistors is performed by an avalanche of hot holes being
injected into said insulation layer side spacer.
[0025] The above described first voltage and second voltage are
high voltages which are greater than Vcc.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] FIG. 1 is a figure showing the structure of a prior art
memory cell;
[0027] FIGS. 2A to 2C are figures for explanation of the data
setting method and the reading out margin for this prior art memory
cell;
[0028] FIG. 3 is a figure showing the write voltage application
condition for writing to a non-volatile data storage unit of this
prior art memory cell;
[0029] FIG. 4 is a figure for explanation of a method of data
transfer from a non-volatile data storage unit to a flip-flop unit
of the above described prior art memory cell;
[0030] FIG. 5 is a figure showing the structure of a six transistor
memory cell according to a first embodiment of the present
invention;
[0031] FIG. 6 is a figure showing the structure of a storage device
in which a number of these memory cells are arranged in an
array;
[0032] FIG. 7 is a figure showing the structure of a storage
transistor of this memory cell, and also showing its operation and
the condition of voltage application thereto during writing;
[0033] FIG. 8 is a figure showing the condition of voltage
application to this memory cell when writing data to its storage
transistors;
[0034] FIG. 9 is a figure showing the data erase voltage
application condition for this storage transistor;
[0035] FIG. 10 is a figure showing the condition of voltage
application to this memory cell when erasing data from its storage
transistors;
[0036] FIGS. 11A to 11C are figures for explanation of the data
setting method and the reading out margin for this memory cell;
[0037] FIG. 12 is a figure showing the condition of voltage
application to a storage transistor of this memory cell when
reading out data therefrom;
[0038] FIG. 13 is a figure showing the condition of voltage
application to this memory cell when reading out data from its
storage transistors;
[0039] FIG. 14 is a structural diagram of a memory cell in which
the channel width of one of its load transistors is made wider, so
that the continuity resistances of the two inverters are
unbalanced;
[0040] FIG. 15 is a structural diagram of a memory cell in which
extra condensers are connected, so that the electrostatic
capacities possessed by the two inverters are unbalanced;
[0041] FIG. 16 is a figure showing the structure of a VPS divided
type eight transistor memory cell, according to a second embodiment
of the present invention;
[0042] FIG. 17 is a figure showing the structure of a storage
device in which a number of these memory cells are arranged in an
array;
[0043] FIG. 18 is a figure showing the condition of voltage
application when writing data to a storage transistor of this
memory cell;
[0044] FIG. 19 is a figure showing the condition of voltage
application to this memory cell when writing data to its storage
transistors;
[0045] FIG. 20 is a figure showing the data erase voltage
application condition for this storage transistor;
[0046] FIG. 21 is a figure showing the condition of voltage
application to this memory cell when writing data to its storage
transistors;
[0047] FIGS. 22A to 22C are figures for explanation of the data
setting method and the reading out margin for this memory cell;
[0048] FIG. 23 is a figure for explanation of a data determination
procedure for this memory cell (which determines the data to "1"
even if writing has not yet been performed);
[0049] FIGS. 24A to 24C are figures for explanation of the reading
out margin for data in the data determination procedure described
above;
[0050] FIG. 25 is a figure for explanation of a procedure for
determining the data of this memory cell, which is in its initial
state, to "1";
[0051] FIG. 26 is a figure showing the condition of voltage
application when reading out data from a storage transistor of this
memory cell;
[0052] FIG. 27 is a figure showing the condition of voltage
application when reading out data from the storage transistors of
this memory cell;
[0053] FIG. 28 is a figure for explanation of a data determination
procedure for this memory cell;
[0054] FIG. 29 is a figure for explanation of another data
determination procedure for this memory cell;
[0055] FIG. 30 is a figure for explanation of yet another data
determination procedure for this memory cell;
[0056] FIG. 31 is a structural diagram of a memory cell in which
the channel width of one of its load transistors is made wider, so
that the continuity resistances of the two inverters are
unbalanced;
[0057] FIG. 32 is a structural diagram of a memory cell in which
extra condensers are connected, so that the electrostatic
capacities possessed by the two inverters are unbalanced;
[0058] FIG. 33 is a figure for explanation of a method of measuring
the threshold voltages of the storage transistors;
[0059] FIG. 34 is a figure showing the structure of a source line
segmented type eight transistor memory cell, according to a third
embodiment of the present invention;
[0060] FIG. 35 is a figure showing the structure of a storage
device in which a number of these memory cells are arranged in an
array;
[0061] FIG. 36 is a figure showing the condition of voltage
application when writing data to a storage transistor of this
memory cell;
[0062] FIG. 37 is a figure showing the condition of voltage
application to this memory cell when writing data to its storage
transistors;
[0063] FIG. 38 is a figure showing the data erase voltage
application condition for this storage transistor;
[0064] FIG. 39 is a figure showing the condition of voltage
application to this memory cell when writing data to its storage
transistors;
[0065] FIGS. 40A to 40C are figures for explanation of the data
setting method and the reading out margin for this memory cell;
[0066] FIG. 41 is a figure for explanation of a data determination
procedure for this memory cell (which determines the data to "1"
even if writing has not yet been performed);
[0067] FIGS. 42A to 42C are figures for explanation of the reading
out margin for data in the data determination procedure described
above;
[0068] FIG. 43 is a figure for explanation of a procedure for
determining the data of this memory cell, which is in its initial
state, to "1";
[0069] FIG. 44 is a figure showing the condition of voltage
application when reading out data from a storage transistor of this
memory cell;
[0070] FIG. 45 is a figure showing the condition of voltage
application when reading out data from the storage transistors of
this memory cell;
[0071] FIG. 46 is a figure for explanation of a data determination
procedure for this memory cell;
[0072] FIG. 47 is a figure for explanation of another data
determination procedure for this memory cell;
[0073] FIG. 48 is a figure for explanation of yet another data
determination procedure for this memory cell;
[0074] FIG. 49 is a structural diagram of a memory cell in which
the channel width of one of its load transistors is made wider, so
that the continuity resistances of the two inverters are
unbalanced;
[0075] FIG. 50 is a structural diagram of a memory cell in which
extra condensers are connected, so that the electrostatic
capacities possessed by the two inverters are unbalanced;
[0076] FIG. 51 is a figure for explanation of a method of measuring
the threshold voltages of the storage transistors;
[0077] FIG. 52 is a figure showing the layout upon the
semiconductor substrate of the memory cells according to the second
and the third embodiments;
[0078] FIG. 53 is a structural diagram of an RFID chip which
employs the memory cell described above; and
[0079] FIG. 54 is a schematic plan view of a system LSI chip which
employs the memory cell described above.
DETAILED DESCRIPTION OF THE INVENTION
Embodiment One
[0080] A non-volatile storage device according to a first
embodiment of the present invention, and a semiconductor integrated
circuit device which incorporates it, will now be explained with
reference to FIGS. 5 through 15.
[0081] FIG. 5 is a circuit diagram of a single non-volatile memory
cell of a non-volatile storage device. This memory cell comprises
six MOS transistors. It includes a flip-flop in which an inverter
(a true side inverter) in which a P-type MOS transistor MP1 and an
N-type MOS transistor MCN1 are connected in series, and an inverter
(a bar side inverter) in which a P-type MOS transistor MP2 and an
N-type MOS transistor MCN2 are connected in series, are static
latch connected. Among these, the P-type MOS transistors MP1 and
MP2 are termed load transistors, while the N-type MOS transistors
MCN1 and MCN2 are termed storage transistors. As explained in FIG.
7 below, the storage transistors MCN1 and MCN2 function as
non-volatile elements which can change their threshold values in a
non-volatile manner by accumulating and neutralizing electric
charges on their side spacer portions.
[0082] In this flip-flop, the inverter in which the load transistor
MP1 and the storage transistor MCN1 are connected in series
functions as a storage unit on the true side, while the inverter in
which the load transistor MP2 and the storage transistor MCN2 are
connected in series functions as a storage unit on the bar side.
The connection portion between the load transistor MP1 and the
storage transistor MCN1 is a node T, while the connection portion
between the load transistor MP2 and the storage transistor MCN2 is
a node B. When the node T is at high potential and the node B is at
low potential, the stored contents is "0"; while, when the node T
is at low potential and the node B is at high potential, the stored
contents is "1".
[0083] The storage transistor side end portions of these inverters,
in other words the sources of the storage transistors MCN1 and
MCN2, are connected to a source line SL (a supply line for a first
voltage). And the load transistor side end portions of these
inverters, in other words the sources of the load transistors MP1
and MP2, are connected to a VPS line (a supply line for a second
voltage). Furthermore, the wells of the load transistors MP1 and
MP2 are connected to a VPM line.
[0084] The node T is connected to a bit line BLT (Bit Line-True)
via a transfer gate MN1, while the node B is connected to a bit
line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates
MN1 and MN2 are N-type MOS transistors, and a common word line WL
is connected to both of these gates.
[0085] FIG. 6 is a figure showing a structure in which a number of
the non-volatile cells shown in FIG. 5 are arranged in an array. In
this memory cell array, the non-volatile memory cells of FIG. 5 are
arranged in an X,Y matrix array. And one word line WL is provided
for each row (the rows are arranged along the Y axis direction),
while one bit line BLT and one bit line BLB are provided for each
column (the columns are arranged along the X axis direction). Each
of these word lines WL and bit lines BLT and BLB is controlled
independently. On the other hand, the other signal lines (VPS, VPM,
and SL) are provided in common for all of the memory cells, and are
controlled all together for the entire memory cell array.
[0086] FIG. 7 shows the structure of one of these storage
transistors MCN1 (or MCN2), and its operation during writing.
Furthermore, FIG. 8 is a figure showing the state of voltage
application when writing to this storage transistor MCN1.
[0087] In FIG. 7, a P-type well 104 of depth 0.8 .mu.m and average
boron density 210.sup.17 cm.sup.-3 is formed upon a surface region
of a P-type silicon substrate 101 of resistivity 10 .OMEGA.cm. The
two separate storage transistors MCN1 and MCN2 are defined by a
plurality of trenches (element separators) 102 of depth 250 nm on
this P-type well 104. In this figure, only one of the storage
transistors (MCN1) is shown.
[0088] This storage transistor is an N-channel type transistor, and
comprises, on the surface region of the P-type well 104, a drain
109 and a source 115 which are formed adjacent to the trenches 102
on the two sides, and a drain extension 107 which is formed in a
region adjacent to the drain 109. The drain 109 and the source 115
are formed with an average arsenic density of 110.sup.20 cm.sup.-3,
and the drain extension 107 is formed with an average arsenic
density of 510.sup.18 cm.sup.-3.
[0089] Furthermore, upon the substrate in the channel region, which
is the region of the surface of the P-type well 104 between the
drain 109 and the source 115, there are formed a gate oxide layer
105 of thickness 5 nm, and a gate electrode 106 which is made from
a polysilicon layer of thickness 200 nm and having a phosphorus
density of 210.sup.20 cm.sup.-3. Furthermore, on both sides of this
gate oxide layer 105 and gate electrode 106, there are formed side
spacers 108 which are made as insulating layers of thickness 50 nm.
It should be understood that the side spacer 108S on the source
side is exposed to the channel region of the substrate, since no
extension region is formed around the periphery of the source
115.
[0090] Furthermore, within the region of the P-type well 104, a
P-type diffusion layer 111 having an average boron density of
110.sup.20 cm.sup.-3, which is an electrode for grounding this
P-type well, is formed in a region which is separated from the
storage transistor described above by one of the trenches 102.
[0091] With this storage transistor, the threshold voltage can be
elevated by injecting carriers into the side spacer 108S on the
source side. Furthermore, as will be explained with reference to
FIG. 9, it is also possible to return the threshold voltage to its
initial state by extracting the carriers which have been injected
into the side spacer 108S. In this way, this storage transistor
stores data in a non-volatile manner.
[0092] It should be understood that, although the initial threshold
voltage of this storage transistor is 1.2 V, the variation is great
since it is a transistor of a distinctive structure, and
accordingly, from the point of view of reliability, it is not
possible to utilize such a storage transistor singly as a storage
element. Because of this, in this embodiment, the memory cell is
built with the flip-flop structure shown in FIG. 5.
[0093] In FIG. 7, the write operation is an operation of injecting
channel hot electrons HE into the aforementioned side spacer 108S
by applying 0 V to a drain line VD and by applying to a source line
VS a positive voltage (for example 6V) which is less than the
junction withstand voltage. Due to this injection of channel hot
electrons, the threshold voltage is elevated by trapped electrons,
and the system transmits to the written state.
[0094] In order to bring the storage transistor MCN1 to this
potential configuration, voltages are applied to the memory cell in
the condition shown in FIG. 8. This figure shows the state when the
threshold voltage of the storage transistor MCN1 is elevated and
the data "0" is being written. In the condition with VPS, VPM, and
SL set to 6 V, the word line WL is set to Vcc (1.8 V), and the bit
line BLT is set to 0 V while BLB is set to Vcc. By putting ON the
transfer gate MN1, which is a N-type MOS transistor, along with the
node T (the drain of the storage transistor MCN1) being brought to
almost the same potential as the bit line BLT (0 V), since, due to
this, the load transistor MP2 is turned ON, accordingly the node B
(the gate of the storage transistor MCN1) is brought to almost the
same potential as VPS (6 V). Due to this, the voltage application
condition of the storage transistor MCN1 becomes the same as in
FIG. 7. At this time, electrical currents of around 300 .mu.A flow
in the transfer gate MN1 and the storage transistor MCN1, and the
threshold voltage of the storage transistor MCN1 is elevated to
Vth2.
[0095] Furthermore, when writing the data "1", while the threshold
voltage on the side of the storage transistor MCN2 becomes
elevated, the other conditions are the same as when writing the
data "0", with only the voltage settings for BLT=Vcc and BLB=0 V
being reversed.
[0096] It should be understood that although, in the embodiment
described above, 6V was applied to the gate of the transistor MCN1
(the node B), and 6V was also applied to the source of the
transistor MCN1 (the source line SL), it would also be acceptable
for these voltages to be different voltages.
[0097] FIGS. 9 and 10 are figures showing the conditions in which
erase voltages are applied to the storage transistors MCN1 (MCN2).
Referring to FIG. 9, the erase operation is an operation in which a
positive voltage less than the junction withstand voltage (for
example 9 V) is applied to the source line VS, and 0 V is applied
to the gate line VG and to the drain line VD, and thereby an
avalanche of hot holes HH is created from the source electrode 115,
and these are injected into the side spacer 108S. Due to this, the
electrons in the side spacer 108S which were trapped by the above
described write operation are neutralized, and the data which was
written is erased by decreasing the threshold voltage.
[0098] In the actual memory cell, these voltages are applied under
the conditions shown in FIG. 10. Fundamentally, the erase operation
is performed all at once for all the memory cells in the memory
array shown in FIG. 6. Under the conditions that VPM is set to Vcc,
VPS is set to 0 V, and SL is set to 9 V, the word lines WL are
brought to Vcc and the bit lines BLT and BLB are brought to 0 V. By
turning ON the transfer gates MN1 and MN2, which are N-type MOS
transistors, the node T and the node B are brought to 0 V, and the
voltage application conditions of the storage transistors MCN1 and
MCN2 are brought to be the same as those shown in FIG. 9.
[0099] Since, in this manner, with the voltage application
conditions during writing as shown in FIGS. 7 and 8, and with the
voltage application conditions during erasure as shown in FIGS. 9
and 10, the design is arranged so that these operations are
performed with the word lines and the bit lines, for which
independent control is required for each memory cell, being brought
to 0 V or to Vcc, in other words so that the application of high
voltage is unnecessary, accordingly it becomes unnecessary to use
transistors of high withstand voltage in the control circuitry for
the word lines and the bit lines, and thereby it is possible to
anticipate the use of transistors of higher performance than in the
case of the prior art, whereby the speed of the reading out
operation may be increased.
[0100] FIGS. 11A to 11C are figures for explanation of the method
of threshold value control for the storage transistors MCN1 and
MCN2 by the above described write operation, in other words of the
method of setting data into this non-volatile memory cell. Here,
the data is "1" when the threshold voltage of the storage
transistor MCN1 is in the low state (ON) and moreover the threshold
voltage of the storage transistor MCN2 is in the high state (OFF);
while the data is "0" when the threshold voltage of the storage
transistor MCN1 is in the high state (OFF) and moreover the
threshold voltage of the storage transistor MCN2 is in the low
state (ON).
[0101] FIG. 11A shows the case before data setting, in other words
when the threshold voltages of both of the storage transistors MCN2
and MCN2 are in their initial state Vth0. In this case, the state
of the memory cell is indeterminate.
[0102] FIG. 11B shows the threshold voltages when this non-volatile
memory cell is set to the data "0". The writing of the data "0" is
implemented by raising the threshold voltage of the storage
transistor MCN1 from its initial state of FIG. 11A to Vth2 (where
Vth2>Vth0).
[0103] And FIG. 11c shows the threshold voltages when this
non-volatile memory cell is set to the data "1". The writing of the
data "1" is implemented by raising the threshold voltage of the
storage transistor MCN2 from its initial state of FIG. 11A to Vth2
(where Vth2>Vth0).
[0104] When the erase operation explained with reference to FIGS. 9
and 10 is performed, the system returns to the state shown in FIG.
11A of this figure, even though the threshold voltages are
controlled as shown in FIGS. 11B and 11C.
[0105] Since, in this manner, the structure is arranged so that,
even though the threshold voltages of the storage transistors MCN1
and MCN2 have once been raised, it is still possible again to lower
them to the initial state Vth0, accordingly, even though requests
for rewriting of the data have been issued a number of times, it is
still possible to obtain a sufficient margin for reading out, which
is the difference between the threshold voltages on the true side
(the storage transistor MCN1) and on the bar side (the storage
transistor MCN2).
[0106] FIGS. 12 and 13 are figures showing the voltage application
conditions when reading out this non-volatile memory cell.
Referring to FIG. 12, the operation of reading out is performed by
reading out the voltage on the drain line VD, when the source line
VS is set to 0 V and Vcc has been applied to the gate line VG. In
the actual memory cell, the voltages are applied in the conditions
shown in FIG. 13. This read out operation is the same as the
operation of reading out a SRAM, and employs a differential type
sense amp. VPS and VPM are set to Vcc and SL is set to 0 V, and the
change in the bit lines BLT and BLB, which corresponds to the data
in this flip-flop, is read out by the differential type sense amp,
under the condition that the word line WL is set to Vcc. When BLT
is at a low voltage (0 V) and moreover BLB is at a high voltage
(Vcc), then the data is "1"; while, when BLT is at a high voltage
(Vcc) and moreover BLB is at a low voltage (0 V), then the data is
"0".
Variants of Embodiment One
[0107] With this six transistor non-volatile memory cell of the
first embodiment, in the state in which writing has not been
performed, in other words in the state in which the threshold
voltages of the storage transistors MCN1 and MCN2 are both low, the
data is indeterminate. Thus, as shown in FIGS. 14 and 15, by
unbalancing the circuit structure on the true side (the storage
transistor MCN1) and on the bar side (the storage transistor MCN2),
it is possible to determine the data as being "0" or "1" when the
power is raised.
[0108] The non-volatile memory cell shown in FIG. 14 is one in
which the channel widths of the two load transistors MP1 and MP2
are unbalanced. In this example, the channel width of the load
transistor MP1 (shown by the thick lines) is made to be twice the
channel width of the load transistor MP2, so that the resistance
value of the load transistor MP1 when it is ON becomes about 1/2 of
the resistance value of the load transistor MP2 when it is ON.
[0109] When the power supply to the memory cell having this
structure is turned ON in the state in which neither one of the
storage transistors MCN1 and MCN2 has been written, the potential
at the node T rises faster than that at the node B, and the load
transistor MP1 and the storage transistor MCN2 go into the ON
state, while the load transistor MP2 and the storage transistor
MCN1 go into the OFF state; in other words, the data stabilizes at
"0".
[0110] It should be understood that, instead of unbalancing the
channel widths as described above, it would also be acceptable to
unbalance the channel lengths. Furthermore, it would also be
acceptable for the load transistor whose channel width or channel
length is changed to be either MP1 or MP2. Moreover, it would also
be acceptable to perform this unbalancing by changing the channel
width or the channel length of one of the storage transistors MCN1
or MCN2.
[0111] On the other hand, the non-volatile memory cell shown in
FIG. 15 is one in which a capacitor is connected to each of the two
nodes T and B of the flip-flop. A capacitor C1 is connected between
the node T and the power supply line Vcc, while a capacitor C2 is
connected between the node B and ground. The capacitances of these
capacitors may be, for example, around 50 fF.
[0112] Due to this, when the power supply is turned ON in the state
in which neither writing nor erasure of either of the two storage
transistors MCN1 and MCN2 has been performed, since the potential
of the node T rises quickly directly after the power supply has
been turned ON while the potential of the node B rises more slowly,
accordingly the system stabilizes with the load transistor MP1 and
the storage transistor MCN2 in the ON state and the load transistor
MP2 and the storage transistor MCN1 in the OFF state, in other
words at the data "0".
[0113] Although, in the example shown in FIG. 15, capacitors were
connected to both the node T and to the node B, it would also be
possible to provide a non-volatile memory cell of an asymmetric
circuit structure, with a capacitor being connected to only one of
the nodes.
Embodiment Two
[0114] A non-volatile storage device according to a second
embodiment of the present invention, and a semiconductor integrated
circuit device which incorporates it, will now be explained with
reference to FIGS. 16 through 33.
[0115] FIG. 16 is a circuit diagram of a single non-volatile memory
cell of this non-volatile storage device. This memory cell is a
non-volatile memory cell of a VPS divided eight transistor type.
This memory cell comprises a flip-flop in which an inverter (a true
side inverter) in which a P-type MOS transistor MP1 and an N-type
MOS transistor MCN1 are connected in series, and an inverter (a bar
side inverter) in which a P-type MOS transistor MP2 and an N-type
MOS transistor MCN2 are connected in series, are static latch
connected. Among these, the P-type MOS transistors MP1 and MP2 are
termed load transistors, while the N-type MOS transistors MCN1 and
MCN2 are termed storage transistors. As explained in FIG. 18 below,
the storage transistors MCN1 and MCN2 function as non-volatile
elements which can change their threshold values in a non-volatile
manner by accumulating and neutralizing electric charges on their
side spacer portions.
[0116] The storage transistor side end portions of these inverters,
in other words the sources of the storage transistors MCN1 and
MCN2, are connected to a source line SL. And the load transistor
side end portion of the true side inverter, in other words the
source of the load transistor MP1, is connected to a line VPST,
while the load transistor side end portion of the bar side
inverter, in other words the source of the load transistor MP2, is
connected to a line VPSB.
[0117] In this flip-flop, the inverter in which the load transistor
MP1 and the storage transistor MCN1 are connected in series
functions as a storage unit on the true side, while the inverter in
which the load transistor MP2 and the storage transistor MCN2 are
connected in series functions as a storage unit on the bar side.
The connection portion between the load transistor MP1 and the
storage transistor MCN1 is a node T, while the connection portion
between the load transistor MP2 and the storage transistor MCN2 is
a node B. When the node T is at high potential and the node B is at
low potential, the stored contents is "0"; while, when the node T
is at low potential and the node B is at high potential, the stored
contents is "1".
[0118] The node T is connected to a bit line BLT (Bit Line-True)
via a transfer gate MN1, while the node B is connected to a bit
line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates
MN1 and MN2 are N-type MOS transistors, and a common word line WL
is connected to both of these gates.
[0119] Furthermore a P-type MOS transistor MP3, which is a
transistor for pre-charge, is connected in parallel with the load
transistor MP1, in other words between the node T and VPST.
Moreover a P-type MOS transistor MP4, which also is a transistor
for pre-charge, is connected in parallel with the load transistor
MP2, in other words between the node B and VPSB. A T-side
pre-charge line PRET is connected to the gate of the P-type MOS
transistor MP3, while a B-side pre-charge line PREB is connected to
the gate of the P-type MOS transistor MP4. Furthermore, all of the
P-type MOS transistors MP1 through MP4 are formed within the same N
well, and the potential of this N well is controlled by a signal
VPM.
[0120] FIG. 17 is a figure showing a structure in which a number of
the non-volatile cells shown in FIG. 16 are arranged in an array.
In this memory cell array, the non-volatile memory cells of FIG. 16
are arranged in an X,Y matrix array. And one word line WL is
provided for each row (the rows are arranged along the Y axis
direction), while one bit line BLT and one bit line BLB are
provided for each column (the columns are arranged along the X axis
direction). Each of these word lines WL and bit lines BLT and BLB
is controlled independently. On the other hand, the other signal
lines (PREB, PRET, VPST, VPSB, VPM, and SL) are provided in common
for all of the memory cells, and are controlled all together for
the entire memory cell array.
[0121] FIG. 18 shows the structure of one of these storage
transistors MCN1 (or MCN2), and its operation during writing.
Furthermore, FIG. 19 is a figure showing the state of voltage
application when writing to this storage transistor MCN1. In FIG.
18, a P-type well 104 of depth 0.8 .mu.m and average boron density
210.sup.17 cm.sup.-3 is formed upon a surface region of a P-type
silicon substrate 101 of resistivity 10 .OMEGA.cm. The two separate
storage transistors MCN1 and MCN2 are defined by a plurality of
trenches (element separators) 102 of depth 250 nm on this P-type
well 104. In this figure, only one of the storage transistors
(MCN1) is shown.
[0122] This storage transistor is an N-channel type transistor, and
comprises, on the surface region of the P-type well 104, a drain
109 and a source 115 which are formed adjacent to the trenches 102
on the two sides, and a drain extension 107 which is formed in a
region adjacent to the drain 109. The drain 109 and the source 115
are formed with an average arsenic density of 110.sup.20 cm.sup.3,
and the drain extension 107 is formed with an average arsenic
density of 510.sup.18 cm.sup.-3.
[0123] Furthermore, upon the substrate in the channel region, which
is the region of the surface of the P-type well 104 between the
drain 109 and the source 115, there are formed a gate oxide layer
105 of thickness 5 nm, and a gate electrode 106 which is made from
a polysilicon layer of thickness 200 nm and having a phosphorus
density of 210.sup.20 cm.sup.-3. Furthermore, on both sides of this
gate oxide layer 105 and gate electrode 106, there are formed side
spacers 108 which are made as insulating layers of thickness 50 nm.
It should be understood that the side spacer 108S on the source
side is exposed to the channel region of the substrate, since no
extension region is formed around the periphery of the source
115.
[0124] Furthermore, within the region of the P-type well 104, a
P-type diffusion layer 111 having an average boron density of
110.sup.20 cm.sup.-3, which is an electrode for grounding this
P-type well, is formed in a region which is separated from the
storage transistor described above by one of the trenches 102.
[0125] With this storage transistor, the threshold voltage can be
elevated by injecting carriers into the side spacer 108S on the
source side. Furthermore, as will be explained with reference to
FIG. 20, it is also possible to return the threshold voltage to its
initial state by extracting the carriers which have been injected
into the side spacer 108S. In this way, this storage transistor
stores data in a non-volatile manner.
[0126] It should be understood that, although the initial threshold
voltage of this storage transistor is 1.2 V, the variation is great
since it is a transistor of a distinctive structure, and
accordingly, from the point of view of reliability, it is not
possible to utilize such a storage transistor singly as a storage
element. Because of this, in this embodiment, the memory cell is
built with the flip-flop structure shown in FIG. 16.
[0127] In FIG. 18, the write operation is an operation of injecting
channel hot electrons HE into the aforementioned side spacer 108S
by applying 0 V to the drain line VD and by applying a positive
voltage (for example 6 V) which is less than the junction withstand
voltage to the source line VS. Due to this injection of channel hot
electrons, the threshold voltage is elevated by trapped electrons,
and the system transmits to the write state.
[0128] In order to bring the storage transistor MCN1 to this
potential configuration, voltages are applied to the memory cell in
the condition shown in FIG. 19. This figure shows the state when
the threshold voltage of the storage transistor MCN1 is elevated
and the data "0" is being written. In the condition with PREB,
PRET, VPST, VPSB, VPM, and SL set to 6 V, the word line WL is set
to Vcc, and the bit line BLT is set to 0 V while BLB is set to Vcc.
By putting ON the transfer gate MN1, which is a N-type MOS
transistor, along with the node T (the drain of the storage
transistor MCN1) being brought to almost the same potential as the
bit line BLT (0 V), since, due to this, the load transistor MP2 is
turned ON, accordingly the node B (the gate of the storage
transistor MCN1) is brought to almost the same potential as VPSB (6
V). Due to this, the voltage application condition of the storage
transistor MCN1 becomes the same as in FIG. 18. At this time,
electrical currents of around 300 .mu.A flow in the transfer gate
MN1 and in the storage transistor MCN1, and the threshold voltage
of the storage transistor MCN1 is elevated to Vth2.
[0129] Furthermore, when writing the data "1", while the threshold
voltage on the side of the storage transistor MCN2 becomes
elevated, the other conditions are the same as when writing the
data "0", with only the voltage settings for BLT=Vcc and BLB=0 V
being reversed.
[0130] It should be understood that although, in the embodiment
described above, 6V was applied to the gate of the transistor MCN1
(the node B), and 6V was also applied to the source of the
transistor MCN1 (the source line SL), it would also be acceptable
for these voltages to be different voltages.
[0131] FIGS. 20 and 21 are figures showing the conditions in which
erase voltages are applied to the storage transistors MCN1 (MCN2).
Referring to FIG. 20, the erase operation is an operation in which
a positive voltage less than the junction withstand voltage (for
example 9 V) is applied to the source line VS, and 0 V is applied
to the gate line VG and to the drain line VD, and thereby an
avalanche of hot holes HH from the source electrode 115 is created,
and these are injected into the side spacer 108S. Due to this, the
electrons in the side spacer 108S trapped by the above described
write operation are neutralized, and the data which was written is
erased by decreasing the threshold voltage.
[0132] In the actual memory cell, these voltages are applied under
the conditions shown in FIG. 21. Fundamentally, the erase operation
is performed all at once for all the memory cells in the memory
array shown in FIG. 17. Under the conditions that PREB, PRET, and
VPM are set to Vcc, VPST and VPSB are set to 0 V, and SL is set to
9 V, the word lines WL are brought to Vcc and the bit lines BLT and
BLB are brought to 0 V. By turning ON the transfer gates MN1 and
MN2, which are N-type MOS transistors, the node T and the node B
are brought to 0 V, and the voltage application conditions of the
storage transistors MCN1 and MCN2 are brought to be the same as
those shown in FIG. 20.
[0133] Since, in this manner, with the voltage application
conditions during writing as shown in FIGS. 18 and 19, and with the
voltage application conditions during erasure as shown in FIGS. 20
and 21, the design is arranged so that these operations are
performed with the word lines and the bit lines, for which
independent control is required for each memory cell, being brought
to 0 V or to Vcc, in other words so that the application of high
voltage is unnecessary, accordingly it becomes unnecessary to use
transistors of high withstand voltage in the control circuitry for
the word lines and the bit lines, and thereby it is possible to
anticipate the use of transistors of higher performance than in the
prior art, whereby the speed of the reading out operation may be
increased.
[0134] FIGS. 22A to 22C are figures for explanation of the method
of threshold value control for the storage transistors MCN1 and
MCN2 by the above described write operation, in other words of the
method of setting data into this non-volatile memory cell. Here,
the data is "1" when the threshold voltage of the storage
transistor MCN1 is in the low state (ON) and moreover the threshold
voltage of the storage transistor MCN2 is in the high state (OFF);
while the data is "0" when the threshold voltage of the storage
transistor MCN1 is in the high state (OFF) and moreover the
threshold voltage of the storage transistor MCN2 is in the low
state (ON).
[0135] FIG. 22A shows the case before data setting, in other words
when the threshold voltages of both of the storage transistors MCN1
and MCN2 are in their initial state Vth0. Even in this case, due to
the procedure shown in FIG. 23 or FIG. 25, the state of this
non-volatile memory cell is determined as being data "1".
[0136] FIG. 22B shows the threshold voltages when this non-volatile
memory cell is set to the data "0". The writing of the data "0" is
implemented by raising the threshold voltage of the storage
transistor MCN1 from its initial state of (A) of this figure to
Vth2 (where Vth2>Vth0).
[0137] And FIG. 22C shows the threshold voltages when this
non-volatile memory cell is set to the data "1". The writing of the
data "1" is implemented by raising the threshold voltage of the
storage transistor MCN2 from its initial state of (A) of this
figure to Vth2 (where Vth2>Vth0).
[0138] When the erase operation explained with reference to FIGS.
20 and 21 is performed, the system returns to the state shown in
FIG. 22A of this figure, even though the threshold voltages are
controlled as shown in FIGS. 22B and 22C.
[0139] Since, in this manner, the structure is arranged so that,
even though the threshold voltages of the storage transistors MCN1
and MCN2 have once been raised, it is still possible again to lower
them to the initial state Vth0, and furthermore since it is
possible forcibly to determine the storage transistors MCN1 and
MCN2 to the data "1", even if they are both in the initial state
Vth0, accordingly, even though requests for rewriting of the data
have been issued a number of times, it is still possible to obtain
a sufficient margin for reading out, which is the difference
between the threshold voltages on the true side (the storage
transistor MCN1) and on the bar side (the storage transistor
MCN2).
[0140] By the writing operation shown in FIGS. 18 and 19, it is
possible to perform writing to either one of the storage
transistors MCN1 and MCN2, and it is possible to write the data "1"
or "0" into the memory cell. On the other hand, if the memory cell
is in its initial state, in other words if writing has not been
performed to either one of the storage transistors MCN1 and MCN2 so
that the threshold voltages of both of the storage transistors MCN1
and MCN2 are in their initial state Vth0, then generally the
contents stored in the memory cell is indeterminate. However, by
applying voltages to the memory cell in its initial state according
to the following procedure, it is possible to determine the storage
contents of this memory cell to either "1" or "0".
[0141] FIG. 23 is a figure for explanation of the voltage
application procedure for determining the data of the non-volatile
memory cell of the present invention. This procedure is an
operation which, if the storage contents of this non-volatile
memory cell is "1" or "0", can set the state of the memory cell
(the flip-flop) according to this storage contents, and which can
fix the data forcibly at "1" if the memory cell is in its initial
state. If, in a memory array in which a plurality of memory cells
are arranged, memory cells whose storage contents is "1" and "0"
and memory cells in the initial state are mixed together, then, by
performing this procedure all at once for all of the memory cells
in the memory array, for those memory cells whose storage contents
is "1" and "0", the states of their flip-flops are set according to
their storage contents, while, for those memory cells which are in
the initial state, the states of their flip-flops are forcibly set
to "1". This procedure is executed during starting up of the
memory.
[0142] The procedure shown in FIG. 23 proceeds as follows. In the
condition with the word line WL and the bit lines BLT and BLB set
to 0 V, first, the source potential SL is raised from 0 V to Vcc at
the time instant T0, so that the storage transistors MCN1 and MCN2
are both turned OFF; and then, at the time instant T1, the
pre-charge transistors MP3 and MP4 are turned ON by dropping the
pre-charge control signals PRET and PREB from Vcc to 0 V. At the
same time, among the pre-charge voltages which are set to Vcc, the
pre-charge voltage VPST on the true side is decreased by .DELTA.V
(which is a voltage sufficiently smaller than Vth2-Vth0, for
example 0.2 V). Due to this, the pre-charge voltages at the node T
and the node B also become Vcc-.DELTA.V and Vcc respectively, and
the voltage between the source and the drain of the storage
transistor MCN2 becomes just .DELTA.V higher than the voltage
between the source and the drain of the storage transistor MCN1.
Because of this, it is possible to increase the apparent threshold
voltage on the side of the storage transistor MCN2 by just
.DELTA.V.
[0143] At the time instant T2, PRET and PREB return to Vcc, and,
from the time instant T3, the source potential SL slowly drops
towards 0 V. At this time, if the storage contents of the memory
cell is "1", then, since the transistor MCN1 whose threshold
voltage is the lower goes to ON before the transistor MCN2,
accordingly the node T is pulled down to 0 V first while the node B
goes to Vcc, so that the data of the flip-flop is determined at
"1". On the other hand, if the storage contents of the memory cell
is "0", then, since likewise the threshold voltage of the
transistor MCN2 is lower than the threshold voltage of the
transistor MCN1 (even though its threshold voltage is elevated by
just .DELTA.V) so that the storage transistor MCN2 goes to ON
first, accordingly the node B is pulled down to 0 V first while the
node T goes to Vcc, so that the data of the flip-flop is determined
at "0".
[0144] Furthermore, if the storage contents of the memory cell is
"indeterminate", in other words if the threshold voltages of both
the transistors MCN1 and MCN2 are Vth0, then, since the apparent
threshold voltage of the storage transistor MCN1 is just .DELTA.V
lower than the threshold voltage of the storage transistor MCN2,
accordingly the transistor MCN1 goes ON before the transistor MCN2,
and the node T is pulled down to 0 V first while the node B goes to
Vcc, so that the data of the flip-flop is determined at "1".
[0145] VPST is returned to Vcc at a time instant T4 after the state
of the flip-flop is determined.
[0146] Since often a memory cell in which the threshold voltages of
MCN1 and MCN2 are both Vth0 is a cell to which, up till now,
neither writing nor rewriting has been performed, and since, with
this type of memory cell, the transistors do not deteriorate along
with rewriting, accordingly, with regard to the setting of
.DELTA.V, it is sufficient only to pay consideration to variation
of the initial threshold voltages of the transistors. Thus it is
considered that, for example, around 0.2 V is sufficient.
[0147] The voltage application procedure shown in FIG. 23 is the
procedure when determining the memory cell in its initial state to
the data "1", but it is also possible to determine the memory cell
in its initial state to the data "0" by, in the source potential
control of the P-type MOS transistors, decreasing the voltage of
VPSB by just .DELTA.V, instead of decreasing the voltage of VPST as
above.
[0148] FIGS. 24A to 24C are figures for explanation of the margin
for data determination when performing the voltage application
procedure shown in FIG. 23. In the initial state in which the
threshold voltages of the transistors MCN1 and MCN2 are both Vth0,
as previously described, by making the pre-charge voltage of the
node T be just .DELTA.V lower than that of the node B, the apparent
threshold voltage on the MCN2 side is increased by just .DELTA.V,
so that the data is forcibly recognized as "1" (FIG. 24A).
Although, for a memory cell in which the data "0" has already been
written, the margin comes to be decreased by just .DELTA.V, suppose
that Vth2-Vth0=1 V and .DELTA.V=0.2 V: then the margin becomes 0.8
V (FIG. 24B). And conversely, for a memory cell in which the data
"1" has already been written, by increasing the margin by just
.DELTA.V, suppose that Vth2-Vth0=1 V and .DELTA.V=0.2 V: then the
margin becomes 1.2 V (FIG. 24C).
[0149] FIG. 25 is a figure for explanation of the procedure for
voltage application for determining the data for a memory cell
which is in its initial state. In other words, while the procedure
shown in FIG. 23 is a procedure which, for a memory array in which
memory cells whose storage contents are "1" and "0" and memory
cells which are in their initial state are mixed together,
determines the data of these memory cells all at once, by contrast,
the procedure shown in FIG. 25 is a procedure which is only
effective for a memory cell which is in its initial state, and
which reliably determines the data of such a memory cell in its
initial state as being either "1" or "0".
[0150] By executing this procedure, if memory cells to which data
has already been written and memory cells which are in their
initial state are mixed together, individually for those memory
cells which are in their initial states, or by executing this
procedure all at once for a memory array of which all of the memory
cells are in their initial state, it is possible to determine the
data of those memory cells as "1" or "0". In the following
explanation, the procedure will be shown for forcibly determining
the storage contents of a memory cell in its initial state to
"1".
[0151] Under the condition that the word line WL and the bit lines
BLT and BLB are set to 0 V, first at the time instant T0 the source
potential SL is raised from 0 V to Vcc and MCN1 and MCN2 are turned
OFF, and then at the time instant T1, by dropping the pre-charge
control signals PREB and PRET and the source potential VPST of the
pre-charge transistor MP3 from Vcc to 0 V, the node B is charged up
to Vcc by the pre-charge transistor MP4, and the node T is
electrically discharged via the pre-charge transistor MP3. And, at
the time instant T2, PREB and PRET return to Vcc, and then, at the
time instant T3, by setting SL from Vcc to 0 V, due to the
transistor MCN1 whose gate potential is the higher going to ON
before the transistor MCN2, the node T is pulled down to 0 V in the
state in which the node B is held at Vcc, so that the data in this
flip-flop is determined as being "1". And then, at the time instant
T4, VPST is returned to Vcc.
[0152] The procedure shown in FIG. 25 is a procedure for forcibly
determining the storage contents of the memory cell to "1", but it
would also be possible forcibly to determine the storage contents
to "0". In other words, by dropping the source potential VPSB of
the pre-charge transistor MP4 from Vcc to 0 V at the time instant
T1, instead of the source potential VPST of the pre-charge
transistor MP3, the node B is set to 0 V, so that the data is
determined at "0".
[0153] By executing the procedure of FIG. 23 or the procedure of
FIG. 25, even if memory cells are present in their initial state in
which both of the two storage transistors MCN1 and MCN2 are in
their initial state of Vth0, it is possible to determine their
storage contents uniquely at "1" or at "0".
[0154] If this non-volatile memory cell is used instead of a fuse,
and if its storage contents are uniquely determined to "1", then,
still in the initial state, it is possible to implement the state
before cutting the fuse (corresponding to the data "1").
[0155] FIGS. 26 and 27 are figures showing the voltage application
conditions when reading out from this non-volatile memory cell.
Referring to FIG. 26, the operation of reading out is performed by
reading out the voltage on the drain line VD, when the source line
VS is set to 0 V and Vcc has been applied to the gate line VG. In
the actual memory cell, the voltages are applied in the conditions
shown in FIG. 27. This read out operation is the same as the
operation of reading out an SRAM, and employs a differential type
sense amp. PREB, PRET, VPST, VPSB, and VPM are set to Vcc and SL is
set to 0 V, and the change in the bit lines BLT and BLB, which
corresponds to the data in this flip-flop, is read out by the
differential type sense amp, under the condition that the word line
WL is set to Vcc. When BLT is at a low voltage (0 V) and moreover
BLB is at a high voltage (Vcc), then the data is "1"; while, when
BLT is at a high voltage (Vcc) and moreover BLB is at a low voltage
(0 V), then the data is "0".
[0156] While the data determination procedure shown in FIG. 25
shows a method which, even if memory cells in their initial state
(i.e. memory cells for which both of the storage transistors MCN1
and MCN2 are in their initial state (with threshold voltage=Vth0))
are present, can forcibly determine them to "1", if no such memory
cells in their initial state are present, or if it will be no
problem even if the data values of the memory cells in their
initial state are indeterminate, then it is possible to employ the
determination procedure shown in FIGS. 28 through 30. With this
procedure, no decrease (refer to FIG. 24) of the determination
margin by .DELTA.V takes place, as in the procedure shown in FIG.
23.
[0157] The procedure shown in FIG. 28 is conducted as follows.
Under the condition that the word line WL and the bit lines BLT and
BLB are set to 0 V and VPST, VPSB, and VPM are set to Vcc, first at
the time instant T0 the source potential SL is raised from 0 V to
Vcc, and the storage transistors MCN1 and MCN2 are turned OFF. In
this state, by lowering the pre-charge control signals PRET and
PREB from Vcc to 0 V at the time instant T1, the pre-charge
transistors MP3 and MP4 are turned ON, and the node T and the node
B are pre-charged to Vcc. After PRET and PREB return to Vcc at the
time instant T2 and the pre-charging has been completed, from the
time instant T3, the source potential SL slowly sinks towards 0 V.
At this time, if the data is "1", then, since the transistor MCN1
whose threshold voltage is the lower goes to ON first before the
transistor MCN2, accordingly the node T is pulled down to 0 V first
while the node B goes to Vcc, so that the data of the flip-flop is
determined at "1". On the other hand, if the data is "0", then,
since the transistor MCN2 whose threshold voltage is the lower goes
to ON first before the transistor MCN1, accordingly the node B is
pulled down to 0 V first while the node T goes to Vcc, so that the
data of the flip-flop is determined at "0".
[0158] And the procedure shown in FIG. 29 is conducted as follows.
The word line WL and the bit lines BLT and BLB are set to 0 V, and
VPST, VPBSB, and VPM are set to Vcc, and moreover the source
potential SL is fixed at 0 V. Under these conditions, by dropping
the pre-charge control signals PRET and PREB from Vcc to 0 V at the
time instant T0, the pre-charge transistors MP3 and MP4 are turned
ON, and the node T and the node B are pre-charged. With regard to
the pre-charge level of the node T and the node B, the current flow
amount which flows as DC in each of the transistors MP1, MP3, and
MCN1, or in each of the transistors MP2, MP4, and MCN2, now becomes
constant and stabilizes. At this time, if the data is "1", then,
since the current drive force of the transistor MCN1 whose
threshold voltage is the lower is greater than that of MCN2,
accordingly the node T goes to a lower potential than the node B,
and, after completion of the pre-charge at the time instant T1, the
data of the flip-flop is determined at "1". On the other hand, if
the data is "0", then, since the current drive force of the
transistor MCN2 whose threshold voltage is the lower is greater
than that of MCN1, accordingly the node B goes to a lower potential
than the node T, and, after completion of the pre-charge at the
time instant T1, the data of the flip-flop is determined at
"0".
[0159] To compare this determination procedure with the
determination procedure shown in FIG. 28, although it has a demerit
from the point of view of consumption of electrical power since a
DC feedthrough current flows in the flip-flop during the pre-charge
process, nevertheless it has the merit from the point of view of
simplicity and ease of control that it is possible to control the
source line potentials SL by fixing them at 0 V.
[0160] Moreover, the procedure shown in FIG. 30 is conducted as
follows. The distinguishing feature of this data determination
procedure is that the pre-charge voltages of the node T and the
node B are supplied from the bit line side. Along with fixing PRET
and PREB at Vcc, the word line WL and the bit lines BLT and BLB are
set to Vcc, and, by setting the potentials VPST and VPSB to 0 V,
thus cutting off the transistors MP1 through MP4, the node T and
the node B are each pre-charged to Vcc-Vthn via the transfer gates
MN1 and MN2 from the bit lines BLT and BLB which have been charged
up to Vcc. Here Vthn is the threshold voltage of the transistors
MN1 and MN2. At the time instant T0 the word line WL is dropped
from Vcc to 0 V, and, with the node T and the node B made floating,
the data of the flip-flop is determined by the difference between
the amounts of electrical charge discharged from the transistors
MCN1 and MCN2. If the data is "1", then, since the current drive
force of the transistor MCN1 whose threshold voltage is the lower
is greater than that of MCN2, accordingly the node T goes to a
lower potential than the node B, and, after the potentials VPST and
VPSB have risen from 0 V to Vcc at the time instant T1, the data of
this non-volatile memory cell is determined at "1". On the other
hand, if the data is "0", then, since the current drive amount of
the transistor MCN2 whose threshold voltage is the lower is greater
than that of MCN1, accordingly the node B goes to a lower potential
than the node T, and, after the potentials VPST and VPSB have risen
from 0 V to Vcc at the time instant T1, the data of this
non-volatile memory cell is determined at "0". After this, VPS is
raised to Vcc at the time instant T1.
Variants of Embodiment Two
[0161] With this eight transistor VPS divided type non-volatile
memory cell of the second embodiment, in the state in which writing
has not been performed, in other words in the state in which the
threshold voltages of the storage transistors MCN1 and MCN2 are
both low, the data cannot be determined by performing the raising
processing (i.e. the data determination processing) shown in FIGS.
28 through 30. Thus, as shown in FIGS. 31 and 32, by unbalancing
the circuit structure on the true side (the storage transistor
MCN1) and on the bar side (the storage transistor MCN2), it is
possible to determine the data as being one of "0" or "1" upon
raising.
[0162] The non-volatile memory cell shown in FIG. 31 is one in
which the channel widths of the two load transistors MP1 and MP2
are unbalanced. In this example, the channel width of the load
transistor MP1 (shown by the thick lines) is made to be twice the
channel width of the load transistor MP2, so that the resistance
value of the load transistor MP1 when it is ON becomes about 1/2 of
the resistance value of the load transistor MP2 when it is ON.
[0163] When the power supply to the memory cell having this
structure is turned ON in the state in which neither one of the
storage transistors MCN1 and MCN2 has been written, the potential
at the node T rises faster than that at the node B, and the load
transistor MP1 and the storage transistor MCN2 go into the ON
state, while the load transistor MP2 and the storage transistor
MCN1 go into the OFF state; in other words, the data stabilizes at
"0".
[0164] It should be understood that, instead of unbalancing the
channel widths as described above, it would also be acceptable to
unbalance the channel lengths. Furthermore, it would also be
acceptable for the load transistor whose channel width or channel
length is changed to be either MP1 or MP2. Moreover, it would also
be acceptable to perform this unbalancing by changing the channel
width or the channel length of one of the storage transistors MCN1
or MCN2.
[0165] On the other hand, the non-volatile memory cell shown in
FIG. 32 is one in which a capacitor is connected to each of the two
nodes T and B of the flip-flop. A capacitor C1 is connected between
the node T and the power supply line Vcc, while a capacitor C2 is
connected between the node B and ground. The capacitances of these
capacitors may be, for example, around 50 fF.
[0166] Due to this, when the power supply is turned ON in the state
in which neither writing nor erasure of either of the two storage
transistors MCN1 and MCN2 has been performed, since the potential
of the node T rises quickly directly after the power supply has
been turned ON while the potential of the node B rises more slowly,
accordingly the system stabilizes with the load transistor MP1 and
the storage transistor MCN2 in the ON state and the load transistor
MP2 and the storage transistor MCN1 in the OFF state, in other
words at the data "0".
[0167] Although, in the example shown in FIG. 32, capacitors were
connected to both the node T and to the node B, it would also be
possible to provide a non-volatile memory cell of an asymmetric
circuit structure, with a capacitor being connected to only one of
the nodes.
[0168] --The Threshold Voltage Measurement Method in the Second
Embodiment--
[0169] It should be understood that, with this non-volatile memory
cell of an eight transistor structure, it is possible to measure
the threshold voltages of the storage transistors by establishing a
potential arrangement as, for example, shown in FIG. 33. By
measurement of the threshold voltages by this method, it becomes
possible to perform evaluation of the variation of the threshold
voltages in the initial state, and evaluation of the amount of
change of the threshold voltages during a write operation or an
erase operation and of the high temperature storage characteristics
of the threshold voltages after rewriting and so on.
[0170] In FIG. 33, the case is shown of deciding upon the threshold
voltage of the storage transistor MCN1. In the state in which the
source potential SL of the storage transistor MCN1=0 V, 0.5 V is
supplied from the bit line BLT via the transfer gate MN1 to the
drain of this storage transistor MCN1 (i.e. to the node T). The
potential on VPSB (the voltage MAP) is supplied from the load
transistors MP2 and MP4 to the gate of the storage transistor MCN1
(i.e. to the node B).
[0171] Since the gate potential of the load transistor MP2 (i.e.
the node T) is set to 0.5 V, accordingly this transistor is turned
ON if the potential of VPSB is greater than or equal to 0.5 V+Vthp,
and potential comes to be supplied to the node B. On the other
hand, since the gate potential PREB of the load transistor MP4 is
set to 0 V, accordingly this transistor is turned ON if the
potential of VPSB is greater than or equal to Vthp, so that it
becomes possible for potential to be supplied to the node B. Vthp
is the threshold voltage of the P-type MOS transistors shown by MP1
through MP4, and is around 0.7 V with a standard CMOS process, and
it becomes possible to decide upon the threshold voltage of the
transistor MCN1 (the gate voltage which is necessary for some fixed
electrical current to flow) in a voltage range greater than or
equal to this. When measuring the threshold voltage on the side of
the transistor MCN1, the gate potential of the transistor MCN2 (the
node T) is set to 0.5 V, in order for the gate potential of the
transistor MCN1 (the node B) not to be pulled down by leakage
electrical current on the side of the transistor MCN2.
[0172] While FIG. 33 shows the voltage application condition for
the case of measuring the threshold voltage of the storage
transistor MCN1, it is also possible to measure the threshold
voltage of the other storage transistor MCN2, simply by controlling
the bit lines BLT and BLB, and the pre-charge signals PRET and
PREB, in the converse manner.
[0173] It should be understood that although, in order to perform
this threshold value measurement, the pre-charge line is divided
into PRET and PREB, if this measurement is not to be performed, it
would be acceptable to provide a single common pre-charge line both
to the true side and to the bar side.
Embodiment Three
[0174] A non-volatile storage device according to a third
embodiment of the present invention, and a semiconductor integrated
circuit device which incorporates it, will now be explained with
reference to FIGS. 34 through 51.
[0175] FIG. 34 is a circuit diagram of a single non-volatile memory
cell of this non-volatile storage device. This memory cell is a
non-volatile memory cell of an SL divided type eight transistor
structure. This memory cell comprises a flip-flop in which an
inverter (a true side inverter) in which a P-type MOS transistor
MP1 and an N-type MOS transistor MCN1 are connected in series, and
an inverter (a bar side inverter) in which a P-type MOS transistor
MP2 and an N-type MOS transistor MCN2 are connected in series, are
static latch connected. Among these, the P-type MOS transistors MP1
and MP2 are termed load transistors, while the N-type MOS
transistors MCN1 and MCN2 are termed storage transistors. As
explained in FIG. 36 below, the storage transistors MCN1 and MCN2
function as non-volatile elements which can change their threshold
values in a non-volatile manner by accumulating and neutralizing
electric charges on their side wall portions.
[0176] The storage transistor side end portion of the true side
inverter, in other words the source of the storage transistor MCN1,
is connected to a true side source line SLT. Furthermore, the
storage transistor side end portion of the bar side inverter, in
other words the source of the storage transistor MCN2, is connected
to a bar side source line SLB. And the load transistor side end
portions of both of these inverters, in other words the sources of
the load transistors MP1 and MP2, are connected to a line VPS.
[0177] In this flip-flop, the inverter in which the load transistor
MP1 and the storage transistor MCN1 are connected in series
functions as a storage unit on the true side, while the inverter in
which the load transistor MP2 and the storage transistor MCN2 are
connected in series functions as a storage unit on the bar side.
The connection portion between the load transistor MP1 and the
storage transistor MCN1 is a node T, while the connection portion
between the load transistor MP2 and the storage transistor MCN2 is
a node B. When the node T is at high potential and the node B is at
low potential, the stored contents is "0"; while, when the node T
is at low potential and the node B is at high potential, the stored
contents is "1".
[0178] The node T is connected to a bit line BLT (Bit Line-True)
via a transfer gate MN1, while the node B is connected to a bit
line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates
MN1 and MN2 are N-type MOS transistors, and a common word line WL
is connected to both of these gates.
[0179] Furthermore a P-type MOS transistor MP3, which is a
transistor for pre-charge, is connected in parallel with the load
transistor MP1, in other words between the node T and VPS. Moreover
a P-type MOS transistor MP4, which also is a transistor for
pre-charge, is connected in parallel with the load transistor MP2,
in other words between the node B and VPS. A T-side pre-charge line
PRET is connected to the gate of the P-type MOS transistor MP3,
while a B-side pre-charge line PREB is connected to the gate of the
P-type MOS transistor MP4. Furthermore, all of the P-type MOS
transistors MP1 through MP4 are formed within the same N well, and
the potential of this N well is controlled by a signal VPM.
[0180] FIG. 35 is a figure showing a structure in which a number of
the non-volatile cells shown in FIG. 34 are arranged in an array.
In this memory cell array, the non-volatile memory cells of FIG. 34
are arranged in an X,Y matrix array. And one word line WL is
provided for each row (the rows are arranged along the Y axis
direction), while one bit line BLT and one bit line BLB are
provided for each column (the columns are arranged along the X axis
direction). Each of these word lines WL and bit lines BLT and BLB
is controlled independently. On the other hand, the other signal
lines (PREB, PRET, VPS, VPM, SLT, and SLB) are provided in common
for all of the memory cells, and are controlled all together for
the entire memory cell array.
[0181] FIG. 36 shows the structure of one of these storage
transistors MCN1 (or MCN2), and its operation during writing.
Furthermore, FIG. 37 is a figure showing the state of voltage
application when writing to this storage transistor MCN1.
[0182] In FIG. 36, a P-type well 104 of depth 0.8 .mu.m and average
boron density 210.sup.17 cm.sup.-3 is formed upon a surface region
of a P-type silicon substrate 101 of resistivity 10 .OMEGA.cm. The
two separate storage transistors MCN1 and MCN2 are defined by a
plurality of trenches (element separators) 102 of depth 250 nm on
this P-type well 104. In this figure, only one of the storage
transistors (MCN1) is shown.
[0183] This storage transistor is an N-channel type transistor, and
comprises, on the surface region of the P-type well 104, a drain
109 and a source 115 which are formed adjacent to the trenches 102
on the two sides, and a drain extension 107 which is formed in a
region adjacent to the drain 109. The drain 109 and the source 115
are formed with an average arsenic density of 110.sup.20 cm.sup.-3,
and the drain extension 107 is formed with an average arsenic
density of 510.sup.18 cm.sup.-3.
[0184] Furthermore, upon the substrate in the channel region, which
is the region of the surface of the P-type well 104 between the
drain 109 and the source 115, there are formed a gate oxide layer
105 of thickness 5 nm, and a gate electrode 106 which is made from
a polysilicon layer of thickness 200 nm and having a phosphorus
density of 210.sup.20 cm.sup.-3. Furthermore, on both sides of this
gate oxide layer 105 and gate electrode 106, there are formed side
spacers 108 which are made as insulating layers of thickness 50 nm.
It should be understood that the side spacer 108S on the source
side is exposed to the channel region of the substrate, since no
extension region is formed around the periphery of the source
115.
[0185] Furthermore, within the region of the P-type well 104, a
P-type diffusion layer 111 having an average boron density of
110.sup.20 cm.sup.-3, which is an electrode for grounding this
P-type well, is formed in a region which is separated from the
storage transistor described above by one of the trenches 102.
[0186] With this storage transistor, the threshold voltage can be
elevated by injecting carriers into the side spacer 108S on the
source side. Furthermore, as will be explained with reference to
FIG. 38, it is also possible to return the threshold voltage to its
initial state by extracting the carriers which have been injected
into the side spacer 108S. In this way, this storage transistor
stores data in a non-volatile manner.
[0187] It should be understood that, although the initial threshold
voltage of this storage transistor is 1.2 V, the variation is great
since it is a transistor of a distinctive structure, and
accordingly, from the point of view of reliability, it is not
possible to utilize such a storage transistor singly as a storage
element. Because of this, in this embodiment, the memory cell is
built with the flip-flop structure shown in FIG. 34.
[0188] In FIG. 36, the write operation is an operation of injecting
channel hot electrons HE into the aforementioned side spacer 108S
by applying 0 V to the drain line VD and by applying a positive
voltage (for example 6 V) which is less than the junction withstand
voltage to the source line VS. Due to this injection of channel hot
electrons, the threshold voltage is elevated by trapped electrons,
and the system transmits to the write state.
[0189] In order to bring the storage transistor MCN1 to this
potential configuration, voltages are applied to the memory cell in
the condition shown in FIG. 37. This figure shows the state when
the threshold voltage of the storage transistor MCN1 is elevated
and the data "0" is being written. In the condition with PREB,
PRET, VPS, VPM, SLT, and SLB set to 6 V, the word line WL is set to
Vcc, and the bit line BLT is set to 0 V while BLB is set to Vcc. By
putting ON the transfer gate MN1, which is a N-type MOS transistor,
along with the node T (the drain of the storage transistor MCN1)
being brought to almost the same potential as the bit line BLT (0
V), since, due to this, the load transistor MP2 is turned ON,
accordingly the node B (the gate of the storage transistor MCN1) is
brought to almost the same potential as VPSB (6 V). Due to this,
the voltage application condition of the storage transistor MCN1
becomes the same as in FIG. 36. At this time, electrical currents
of around 300 .mu.A flow in the transfer gate MN1 and in the
storage transistor MCN1, and the threshold voltage of the storage
transistor MCN1 is elevated to Vth2.
[0190] Furthermore, when writing the data "1", while the threshold
voltage on the side of the storage transistor MCN2 becomes
elevated, the other conditions are the same as when writing the
data "0", with only the voltage settings for BLT=Vcc and BLB=0 V
being reversed.
[0191] It should be understood that although, in the embodiment
described above, 6V was applied to the gate of the transistor MCN1
(the node B), and 6V was also applied to the source of the
transistor MCN1 (the source line SL), it would also be acceptable
for these voltages to be different voltages.
[0192] FIGS. 38 and 39 are figures showing the conditions in which
erase voltages are applied to the storage transistors MCN1 (MCN2).
Referring to FIG. 38, the erase operation is an operation in which
a positive voltage less than the junction withstand voltage (for
example 9 V) is applied to the source line VS, and 0 V is applied
to the gate line VG and to the drain line VD, and thereby an
avalanche of hot holes HH from the source electrode 115 is created,
and these are injected into the side spacer 108S. Due to this, the
electrons in the side spacer 108S trapped by the above described
write operation are neutralized, and the data which was written is
erased by decreasing the threshold voltage.
[0193] In the actual memory cell, these voltages are applied under
the conditions shown in FIG. 39. Fundamentally, the erase operation
is performed all at once for all the memory cells in the memory
array shown in FIG. 35. Under the conditions that PREB, PRET, and
VPM are set to Vcc, VPS is set to 0 V, and SLT and SLB are set to 9
V, the word lines WL are brought to Vcc and the bit lines BLT and
BLB are brought to 0 V. By turning ON the transfer gates MN1 and
MN2, which are N-type MOS transistors, the node T and the node B
are brought to 0 V, and the voltage application conditions of the
storage transistors MCN1 and MCN2 are brought to be the same as
those shown in FIG. 38.
[0194] Since, in this manner, with the voltage application
conditions during writing as shown in FIGS. 36 and 37, and with the
voltage application conditions during erasure as shown in FIGS. 38
and 39, the design is arranged so that these operations are
performed with the word lines and the bit lines, for which
independent control is required for each memory cell, being brought
to 0 V or to Vcc, in other words so that the application of high
voltage is unnecessary, accordingly it becomes unnecessary to use
transistors of high withstand voltage in the control circuitry for
the word lines and the bit lines, and thereby it is possible to
anticipate the use of transistors of higher performance than in the
prior art, whereby the speed of the reading out operation may be
increased.
[0195] FIGS. 40A to 40C are figures for explanation of the method
of threshold value control for the storage transistors MCN1 and
MCN2 by the above described write operation, in other words of the
method of setting data into this non-volatile memory cell. Here,
the data is "1" when the threshold voltage of the storage
transistor MCN1 is in the low state (ON) and moreover the threshold
voltage of the storage transistor MCN2 is in the high state (OFF);
while the data is "0" when the threshold voltage of the storage
transistor MCN1 is in the high state (OFF) and moreover the
threshold voltage of the storage transistor MCN2 is in the low
state (ON).
[0196] FIG. 40A shows the case before data setting, in other words
when the threshold voltages of both of the storage transistors MCN1
and MCN2 are in their initial state Vth0. Even in this case, due to
the procedure shown in FIG. 41 or FIG. 43, the state of this
non-volatile memory cell is determined as being data "1".
[0197] FIG. 40B shows the threshold voltages when this non-volatile
memory cell is set to the data "0". The writing of the data "0" is
implemented by raising the threshold voltage of the storage
transistor MCN1 from its initial state of FIG. 40A to Vth2 (where
Vth2>Vth0).
[0198] And FIG. 40C shows the threshold voltages when this
non-volatile memory cell is set to the data "1". The writing of the
data "1" is implemented by raising the threshold voltage of the
storage transistor MCN2 from its initial state of FIG. 40A to Vth2
(where Vth2>Vth0).
[0199] When the erase operation explained with reference to FIGS.
38 and 39 is performed, the system returns to the state shown in
FIG. 40A, even though the threshold voltages are controlled as
shown in FIGS. 40B and 40C.
[0200] Since, in this manner, the structure is arranged so that,
even though the threshold voltages of the storage transistors MCN1
and MCN2 have once been raised, it is still possible again to lower
them to the initial state Vth0, and furthermore since it is
possible forcibly to determine the storage transistors MCN1 and
MCN2 to the data "1", even if they are both in the initial state
Vth0, accordingly, even though requests for rewriting of the data
have been issued a number of times, it is still possible to obtain
a sufficient margin for reading out, which is the difference
between the threshold voltages on the true side (the storage
transistor MCN1) and on the bar side (the storage transistor
MCN2).
[0201] By the writing operation shown in FIGS. 36 and 37, it is
possible to perform writing to either one of the storage
transistors MCN1 and MCN2, and it is possible to write the data "1"
or "0" into the memory cell. On the other hand, if the memory cell
is in its initial state, in other words if writing has not been
performed to either one of the storage transistors MCN1 and MCN2 so
that the threshold voltages of both of the storage transistors MCN1
and MCN2 are in their initial state Vth0, then generally the
contents stored in the memory cell is indeterminate. However, by
applying voltages to the memory cell in its initial state according
to the following procedure, it is possible to determine the storage
contents of this memory cell to either "1" or "0".
[0202] FIG. 41 is a figure for explanation of the voltage
application procedure for determining the data of the non-volatile
memory cell of the present invention. This procedure is an
operation which, if the storage contents of this non-volatile
memory cell is "1" or "0", can set the state of the memory cell
(the flip-flop) according to this storage contents, and which can
fix the data forcibly at "1" if the memory cell is in its initial
state. If, in a memory array in which a plurality of memory cells
are arranged, memory cells whose storage contents is "1" and "0"
and memory cells in the initial state are mixed together, then, by
performing this procedure all at once for all of the memory cells
in the memory array, for those memory cells whose storage contents
is "1" and "0", the states of their flip-flops are set according to
their storage contents, while, for those memory cells which are in
the initial state, the states of their flip-flops are forcibly set
to "1". This procedure is executed during starting up of the
memory.
[0203] The procedure shown in FIG. 41 proceeds as follows. In the
condition with the word line WL and the bit lines BLT and BLB set
to 0 V, and with VPS and VPM set to Vcc, first, the source
potentials SLT and SLB are raised from 0 V to Vcc at the time
instant T0, so that the storage transistors MCN1 and MCN2 are both
turned OFF. Then, at the time instant T1, the pre-charge
transistors MP3 and MP4 are turned ON by dropping the pre-charge
control signals PRET and PREB from Vcc to 0 V, and the node T and
the node B are charged to Vcc.
[0204] At the time instant T2, PRET and PREB return to Vcc, and,
from the time instant T3, the true side source potential SLT slowly
drops towards 0 V. Moreover, at a time instant T4 which is more
delayed than the time instant T3, the bar side source potential SLB
slowly drops towards 0 V. At this time, control is performed so
that SLB-SLT=.DELTA.Vs (for example .DELTA.Vs=0.2 V). Due to this,
the voltage between the source and the drain of the storage
transistor MCN2 comes to be controlled to be just .DELTA.Vs higher
than the voltage between the source and the drain of the storage
transistor MCN1, and thereby it is possible to make the apparent
threshold voltage on the side of the storage transistor MCN2 higher
by just the amount .DELTA.Vs.
[0205] At this time, if the storage contents of the memory cell is
"1", then, since the transistor MCN1 whose threshold voltage is the
lower goes to ON before the transistor MCN2, accordingly the node T
is pulled down to 0 V first while the node B goes to Vcc, so that
the data of the flip-flop is determined at "1". On the other hand,
if the storage contents of the memory cell is "0", then, since
likewise the threshold voltage of the transistor MCN2 is lower than
the threshold voltage of the transistor MCN1 (even though its
threshold voltage is elevated by just the amount .DELTA.Vs) so that
the storage transistor MCN2 goes to ON first, accordingly the node
B is pulled down to 0 V first while the node T goes to Vcc, so that
the data of the flip-flop is determined at "0".
[0206] Furthermore, if the storage contents of the memory cell is
"indeterminate", in other words if the threshold voltages of both
the transistors MCN1 and MCN2 are Vth0, then, since the apparent
threshold voltage of the storage transistor MCN1 is just .DELTA.Vs
lower than the threshold voltage of the storage transistor MCN2,
accordingly the transistor MCN1 goes ON before the transistor MCN2,
and the node T is pulled down to 0 V first while the node B goes to
Vcc, so that the data of the flip-flop is determined at "1".
[0207] Since often a memory cell in which the threshold voltages of
MCN1 and MCN2 are both Vth0 is a cell to which, up till now,
neither writing nor rewriting has been performed, and since, with
this type of memory cell, the transistors do not deteriorate along
with rewriting, accordingly, with regard to the setting of
.DELTA.V, it is sufficient only to pay consideration to variation
of the initial threshold voltages of the transistors. Thus it is
considered that, for example, around 0.2 V is sufficient.
[0208] The voltage application procedure shown in FIG. 41 is the
procedure when determining the memory cell in its initial state to
the data "1", but it is also possible to determine the memory cell
in its initial state to the data "0" by, in the source potential
control of the storage transistors, reversing the potential
relationship of SLT and SLB.
[0209] FIGS. 42A to 42C are figures for explanation of the margin
for data determination when performing the voltage application
procedure shown in FIG. 41. In the initial state in which the
threshold voltages of the transistors MCN1 and MCN2 are both Vth0,
as previously described, by making the source potential SLB on the
bar side be just .DELTA.Vs higher than the source potential SLT on
the true side, the apparent threshold voltage on the MCN2 side is
increased by just .DELTA.Vs, so that the data is forcibly
recognized as "1" (FIG. 42A). Although, for a memory cell in which
the data "0" has already been written, the margin comes to be
decreased by just .DELTA.Vs, suppose that Vth2-Vth0=1 V and
.DELTA.Vs=0.2 V: then the margin becomes 0.8 V (FIG. 42B). And
conversely, for a memory cell in which the data "1" has already
been written, by increasing the margin by just .DELTA.Vs, suppose
that Vth2-Vth0=1 V and .DELTA.Vs=0.2 V: then the margin becomes 1.2
V (FIG. 42C).
[0210] FIG. 43 is a figure for explanation of the procedure for
voltage application for determining the data for a memory cell
which is in its initial state. In other words, while the procedure
shown in FIG. 43 is a procedure which, for a memory array in which
memory cells whose storage contents are "1" and "0" and memory
cells which are in their initial state are mixed together,
determines the data of these memory cells all at once, by contrast,
the procedure shown in FIG. 43 is a procedure which is only
effective for a memory cell which is in its initial state, and
which reliably determines the data of such a memory cell in its
initial state as being either "1" or "0".
[0211] By executing this procedure, if memory cells to which data
has already been written and memory cells which are in their
initial state are mixed together, individually for those memory
cells which are in their initial states, or by executing this
procedure all at once for a memory array of which all of the memory
cells are in their initial state, it is possible to determine the
data of those memory cells as "1" or "0". In the following
explanation, the procedure will be shown for forcibly determining
the storage contents of a memory cell in its initial state to
"1".
[0212] Under the condition that the word line WL and the bit lines
BLT and BLB are set to 0 V, and that VPS and VPM are set to Vcc,
first at the time instant T0 the source potential SLB on the bar
side is raised from 0 V to Vcc and the storage transistor MCN2 is
turned OFF. Then, at the time instant T1, by dropping the
pre-charge control signal PREB from Vcc to 0 V, the node B is
charged up to Vcc by the pre-charge transistor MP4. At the time
instant T2 PREB returns to Vcc, and then, at the time instant T3,
SLB is returned from Vcc to 0 V. Due to this, by the transistor
MCN1 whose gate potential is the higher going to ON before the
transistor MCN2, in the state in which the node B is held at Vcc,
the node T is pulled down to 0 V, so that the data in this
flip-flop is determined as being "1".
[0213] The procedure shown in FIG. 43 is a procedure for forcibly
determining the storage contents of the memory cell to "1", but it
would also be possible forcibly to determine the storage contents
to "0". In other words, by raising the true side source potential
SLT from 0 V to Vcc at the time instant T1, instead of the bar side
source potential SLB, and by dropping the gate potential PRET of
the pre-charge transistor MP3 from Vcc to 0 V at the time instant
T1, instead of the gate potential PREB of the pre-charge transistor
MP4, the node B is set to 0 V, so that the data is determined at
"0".
[0214] By executing the procedure of FIG. 41 or the procedure of
FIG. 43, even if memory cells are present in their initial state in
which both of the two storage transistors MCN1 and MCN2 are in
their initial state of Vth0, it is possible to determine their
storage contents uniquely at "1" or at "0".
[0215] If this non-volatile memory cell is used instead of a fuse,
and if its storage contents are uniquely determined to "1", then,
still in the initial state, it is possible to implement the state
before cutting the fuse (corresponding to the data "1").
[0216] FIGS. 44 and 45 are figures showing the voltage application
conditions when reading out from this non-volatile memory cell.
Referring to FIG. 44, the operation of reading out is performed by
reading out the voltage on the drain line VD, when the source line
VS is set to 0 V and Vcc has been applied to the gate line VG. In
the actual memory cell, the voltages are applied in the conditions
shown in FIG. 45. This read out operation is the same as the
operation of reading out an SRAM, and employs a differential type
sense amp. PREB, PRET, VPS, and VPM are set to Vcc and SLT and SLB
are set to 0 V, and the change in the bit lines BLT and BLB, which
corresponds to the data in this flip-flop, is read out by the
differential type sense amp, under the condition that the word line
WL is set to Vcc. When BLT is at a low voltage (0 V) and moreover
BLB is at a high voltage (Vcc), then the data is "1"; while, when
BLT is at a high voltage (Vcc) and moreover BLB is at a low voltage
(0 V), then the data is "0".
[0217] While the data determination procedure shown in FIG. 43
shows a method which, even if memory cells in their initial state
(i.e. memory cells for which both of the storage transistors MCN1
and MCN2 are in their initial state (with threshold voltage=Vth0))
are present, can forcibly determine them to "1", if no such memory
cells in their initial state are present, or if it will be no
problem even if the data values of the memory cells in their
initial state are indeterminate, then it is possible to employ the
determination procedure shown in FIGS. 46 through 48. With this
procedure, no decrease (refer to FIG. 43) of the determination
margin by .DELTA.Vs takes place, as in the procedure shown in FIG.
41.
[0218] The procedure shown in FIG. 46 is conducted as follows.
Under the condition that the word line WL and the bit lines BLT and
BLB are set to 0 V and VPS and VPM are set to Vcc, first at the
time instant T0 the source potentials SLT and SLB are raised from 0
V to Vcc, and the storage transistors MCN1 and MCN2 are turned OFF.
In this state, by lowering the pre-charge control signals PRET and
PREB from Vcc to 0 V at the time instant T1, the pre-charge
transistors MP3 and MP4 are turned ON, and the node T and the node
B are pre-charged to Vcc. After PRET and PREB return to Vcc at the
time instant T2 and the pre-charging has been completed, from the
time instant T3, the source potentials SLT and SLB slowly sink
towards 0 V. At this time, if the data is "1", then, since the
transistor MCN1 whose threshold voltage is the lower goes to ON
first before the transistor MCN2, accordingly the node T is pulled
down to 0 V first while the node B goes to Vcc, so that the data of
the flip-flop is determined at "1". On the other hand, if the data
is "0", then, since the transistor MCN2 whose threshold voltage is
the lower goes to ON first before the transistor MCN1, accordingly
the node B is pulled down to 0 V first while the node T goes to
Vcc, so that the data of the flip-flop is determined at "0".
[0219] And the procedure shown in FIG. 47 is conducted as follows.
The word line WL and the bit lines BLT and BLB are set to 0 V, and
VPS and VPM are set to Vcc, and moreover the source potentials SLT
and SLB are fixed at 0 V. Under these conditions, by dropping the
pre-charge control signals PRET and PREB from Vcc to 0 V at the
time instant T0, the pre-charge transistors MP3 and MP4 are turned
ON, and the node T and the node B are pre-charged. With regard to
the pre-charge level of the node T and the node B, the current flow
amount which flows as DC in each of the transistors MP1, MP3, and
MCN1, or in each of the transistors MP2, MP4, and MCN2, now becomes
constant and stabilizes. At this time, if the data is "1", then,
since the current drive force of the transistor MCN1 whose
threshold voltage is the lower is greater than that of MCN2,
accordingly the node T goes to a lower potential than the node B,
and, after completion of the pre-charge at the time instant T1, the
data of the flip-flop is determined at "1". On the other hand, if
the data is "0", then, since the current drive force of the
transistor MCN2 whose threshold voltage is the lower is greater
than that of MCN1, accordingly the node B goes to a lower potential
than the node T, and, after completion of the pre-charge at the
time instant T1, the data of the flip-flop is determined at
"0".
[0220] To compare this determination procedure with the
determination procedure shown in FIG. 46, although it has a demerit
from the point of view of consumption of electrical power since a
feedthrough DC current flows in the flip-flop during the pre-charge
process, nevertheless it has the merit from the point of view of
simplicity and ease of control that it is possible to control the
source line potentials SLT and SLB by fixing them at 0 V.
[0221] Moreover, the procedure shown in FIG. 48 is conducted as
follows. In this data determination procedure, an important point
is that the pre-charge voltages of the node T and the node B are
supplied from the bit line side. Along with fixing PRET and PREB at
Vcc, the word line WL and the bit lines BLT and BLB are set to Vcc,
and, by setting the potential VPS to 0 V, thus cutting off the
transistors MP1 through MP4, the node T and the node B are each
pre-charged to Vcc-Vthn via the transfer gates MN1 and MN2 from the
bit lines BLT and BLB which have been charged up to Vcc. Here Vthn
is the threshold voltage of the transistors MN1 and MN2. At the
time instant T0 the word line WL is dropped from Vcc to 0 V, and,
with the node T and the node B made floating, the data of the
flip-flop is determined by the difference between the amounts of
electrical charge discharged from the transistors MCN1 and MCN2. If
the data is "1", then, since the current drive force of the
transistor MCN1 whose threshold voltage is the lower is greater
than that of MCN2, accordingly the node T goes to a lower potential
than the node B, and, after the potential VPS has risen from 0 V to
Vcc at the time instant T1, the data of this non-volatile memory
cell is determined at "1". On the other hand, if the data is "0",
then, since the current drive amount of the transistor MCN2 whose
threshold voltage is the lower is greater than that of MCN1,
accordingly the node B goes to a lower potential than the node T,
and, after the potential VPS has risen from 0 V to Vcc at the time
instant T1, the data of this non-volatile memory cell is determined
at "0".
Variants of Embodiment Three
[0222] With this eight transistor SL divided type non-volatile
memory cell of the third embodiment, in the state in which writing
has not been performed, in other words in the state in is which the
threshold voltages of the storage transistors MCN1 and MCN2 are
both low, the data cannot be determined by performing the raising
processing (i.e. the data determination processing) shown in FIGS.
46 through 48. Thus, as shown in FIGS. 49 and 50, by unbalancing
the circuit structure on the true side (the storage transistor
MCN1) and on the bar side (the storage transistor MCN2), it is
possible to determine the data as being one of "0" or "1" upon
raising.
[0223] The non-volatile memory cell shown in FIG. 49 is one in
which the channel widths of the two load transistors MP1 and MP2
are unbalanced. In this example, the channel width of the load
transistor MP1 (shown by the thick lines) is made to be twice the
channel width of the load transistor MP2, so that the resistance
value of the load transistor MP1 when it is ON becomes about 1/2 of
the resistance value of the load transistor MP2 when it is ON.
[0224] When the power supply to the memory cell having this
structure is turned ON in the state in which neither one of the
storage transistors MCN1 and MCN2 has been written, the potential
at the node T rises faster than that at the node B, and the load
transistor MP1 and the storage transistor MCN2 go into the ON
state, while the load transistor MP2 and the storage transistor
MCN1 go into the OFF state; in other words, the data stabilizes at
"0".
[0225] It should be understood that, instead of unbalancing the
channel widths as described above, it would also be acceptable to
unbalance the channel lengths. Furthermore, it would also be
acceptable for the load transistor whose channel width or channel
length is changed to be either MP1 or MP2. Moreover, it would also
be acceptable to perform this unbalancing by changing the channel
width or the channel length of one of the storage transistors MCN1
or MCN2.
[0226] On the other hand, the non-volatile memory cell shown in
FIG. 50 is one in which a capacitor is connected to each of the two
nodes T and B of the flip-flop. A capacitor C1 is connected between
the node T and the power supply line Vcc, while a capacitor C2 is
connected between the node B and ground. The capacitances of these
capacitors may be, for example, around 50 fF.
[0227] Due to this, when the power supply is turned ON in the state
in which neither writing nor erasure of either of the two storage
transistors MCN1 and MCN2 has been performed, since the potential
of the node T rises quickly directly after the power supply has
been turned ON while the potential of the node B rises more slowly,
accordingly the system stabilizes with the load transistor MP1 and
the storage transistor MCN2 in the ON state and the load transistor
MP2 and the storage transistor MCN1 in the OFF state, in other
words at the data "0".
[0228] Although, in the example shown in FIG. 50, capacitors were
connected to both the node T and to the node B, it would also be
possible to provide a non-volatile memory cell of an asymmetric
circuit structure, with a capacitor being connected to only one of
the nodes.
[0229] --The Threshold Voltage Measurement Method in the Third
Embodiment--
[0230] It should be understood that, with this non-volatile memory
cell of an eight transistor structure, it is possible to measure
the threshold voltages of the storage transistors by establishing a
potential arrangement as, for example, shown in FIG. 51. By
measurement of the threshold voltages by this method, it becomes
possible to perform evaluation of the variation of the threshold
voltages in the initial state, and evaluation of the amount of
change of the threshold voltages during a write operation or an
erase operation and of the high temperature storage characteristics
of the threshold voltages after rewriting and so on.
[0231] In FIG. 51, the case is shown of deciding upon the threshold
voltage of the storage transistor MCN1. In the state in which the
source potential SLT of the storage transistor MCN1 which is to be
tested is set to =0 V, 1 V is supplied from the bit line BLT via
the transfer gate MN1 to the drain of the storage transistor MCN1
(the node T). And the potential on VPS (the voltage MAP) is
supplied from the load transistors MP2 and MP4 to the gate of the
storage transistor MCN1 (i.e. to the node B).
[0232] Since the gate potential of the load transistor MP2 (i.e.
the node T) is set to 1 V, accordingly this transistor is turned ON
if the potential of VPSB is greater than or equal to 1 V+Vthp, and
potential comes to be supplied to the node B. On the other hand,
since the gate potential PREB of the load transistor MP4 is set to
0 V, accordingly this transistor is turned ON if the potential of
VPSB is greater than or equal to Vthp, so that it becomes possible
for potential to be supplied to the node B. Vthp is the threshold
voltage of the P-type MOS transistors shown by MP1 through MP4, and
is around 0.7 V with a standard CMOS process. Accordingly, it
becomes possible to decide upon the threshold voltage of the
transistor MCN1 (the gate voltage which is necessary for some fixed
electrical current to flow) in a voltage range greater than or
equal to this. When measuring the threshold voltage on the side of
the transistor MCN1, the source potential of the transistor MCN2
and the MAP voltage and the bit lines are set to floating, in order
to eliminate unnecessary leak-pass on the side of the transistor
MCN2.
[0233] While FIG. 51 shows the voltage application condition for
the case of measuring the threshold voltage of the storage
transistor MCN1, it is also possible to measure the threshold
voltage of the other storage transistor MCN2, simply by controlling
the bit lines BLT and BLB, by controlling the source potentials SLT
and SLB, and by controlling the pre-charge signals PRET and PREB,
in the converse manner.
[0234] It should be understood that although, in order to perform
this threshold value measurement, the pre-charge line is divided
into PRET and PREB, if this measurement is not to be performed, it
would be acceptable to provide a single common pre-charge line both
to the true side and to the bar side.
[0235] --The Layout of the Second and Third Embodiments Upon the
Semiconductor Substrate--
[0236] FIG. 52 shows the layout upon the semiconductor substrate of
these memory cells according to the second and the third
embodiments.
[0237] (A) of this figure shows the layout of the active regions
and the gate electrodes upon the surface of the substrate. And (B)
of this figure shows the second and third layers of metal wiring.
As shown in (A) of this figure, the storage transistors on the true
side and on the bar side are laid out in the same direction, so
that it is arranged for the characteristics still to be mutually
the same, even if an error occurs due to an impurity intruding
diagonally.
[0238] Furthermore, as shown in (C) of this figure, the VPS lines
and the source lines (SL) are divided, in this layout, into lines
on the true side and lines on the bar side, so that, by shorting
together either pair of these (making them common), it is possible
to build a structure of the VPS divided type as in the second
embodiment, or a structure of the SL divided type as in the third
embodiment. In this manner, by employing the layout of this figure,
while keeping the processing as far as the second layer of metal
wiring the same, it is possible to manufacture either a
non-volatile semiconductor memory cell of the VPS divided type of
the second embodiment, or a non-volatile semiconductor memory cell
of the SL divided type of the third embodiment, simply by changing
only the third layer of metal wiring.
Embodiments Four and Five
[0239] FIG. 53 is a circuit block diagram of an RFID chip to which
a non-volatile memory cell as described above is provided. An
antenna L configured externally to this chip is connected to pads
P1 and P2, in order to receive an RF signal which is generated by
an external reader. A power supply capacitor CT of capacitance 120
pF, a voltage clamp circuit VOLTAGE CLAMP, a power supply modulator
MODULATOR, and a bridge rectifier BRIDGE RECTIFIER are connected
between these pads P1 and P2. A power supply stabilization
capacitor CF is connected to the output of the bridge rectifier,
and, by feeding back to the voltage clamp circuit a control signal
from a voltage regulator REGULATOR for detecting the output
voltage, stabilization of the power supply voltage may be
anticipated. Furthermore, a Vcc detection circuit VCC DETECTOR
which generates an internal power supply voltage (Vcc) and a
voltage generation circuit VPP GENERATOR which generates various
voltages other than Vcc are connected to the output of the bridge
rectifier. Moreover, a circuit MODE SELECTOR which detects the
operational mode included in the RF signal received by the bridge
rectifier, a clock signal detection circuit CLOCK EXTRACTOR, and a
circuit DATA MODULATOR which extracts write data to a module EEPROM
of a non-volatile storage device, are provided to the output of the
bridge rectifier. And a controller CONTROLLER controls the
operation of the module EEPROM of the non-volatile storage device
which receives the operation mode data.
[0240] In the module EEPROM of the non-volatile storage device
which is mounted to this RFID chip, there are written an ID number
for authenticating the chip, an address for delivery service, goods
information which is an alternative to a bar code (price, day of
production, place of production, producer, component information,
and so on), information required for an air cargo tag (name of
carrier, name of owner, place of loading, destination, and so on),
or the like.
[0241] FIG. 54 is a schematic plan view of a system LSI chip which
is an example of a semiconductor integrated circuit device to which
a non-volatile memory cell according to the present invention is
mounted. Although the system LSI shown in this figure is not
particularly limited, it includes a semiconductor substrate around
the border of which are arranged a large number of external
connection electrodes 120 such as bonding pads or the like, with an
external input and output circuit 121 and an analog input and
output circuit 122 being provided on the inside thereof. This
external input and output circuit 121 and analog input and output
circuit 122 take an external power supply, whose level such as 3.3
V is relatively high, as a supply of operating power. And a level
shift circuit 123 drops this external power supply to an internal
power supply voltage such as 1.8 V.
[0242] In the interior of the level shift circuit 123, there are
provided a static random access memory (SRAM) 124, a central
processing device (CPU) 125, a cache memory (CACH) 126, a logic
circuit (LOGIC) 127, a phase locked loop circuit (PLL) 128, an
analog-digital conversion circuit (ADC) 129, a digital-analog
conversion circuit (DAC) 130, and a system controller (SYSC) 131.
Each of the units designated as 132, 133, and 134 is an
electrically erasable and writable non-volatile memory (EEPROM),
and is a non-volatile storage device according to the present
invention having an appropriate predetermined capacity.
[0243] The non-volatile memory 132 is used for storing repair
information for the SRAM 124 (i.e. control information for
replacing defective memory cells with redundant memory cells). In
other words, this semiconductor integrated circuit device includes
circuits which may require repair (memory cells within the SRAM
124, if they become defective) and redundancy circuits (redundant
memory cells within the SRAM 124) which can serve as alternatives
to those circuits which may require repair; and, moreover, includes
the non-volatile memory 132 which stores repair information. This
repair information is information which specifies which circuits
requiring repair may be replaced by which redundancy circuits.
[0244] Moreover, this semiconductor integrated circuit device
includes an analog circuit and a constant trimming circuit which
adjusts one or more circuit constants of this analog circuit. In
this structure, the non-volatile memory 133 is used for storing
information in this constant trimming circuit for specifying these
circuit constants. Furthermore, this semiconductor integrated
circuit device includes an oscillation circuit and a frequency
trimming circuit which adjusts the oscillation frequency of the
oscillation circuit. In this structure, the non-volatile memory 133
is used for storing information within this frequency trimming
circuit for specifying this oscillation frequency. Yet further,
this semiconductor integrated circuit device includes a reference
voltage generation circuit and a voltage trimming circuit which
adjusts the reference voltage generated by the reference voltage
generation circuit. In this structure, the non-volatile memory 133
is used for storing information within this voltage trimming
circuit for specifying this reference voltage. Even further, this
semiconductor integrated circuit device includes a security circuit
for identifying the chip. In this structure, the non-volatile
memory 133 is used for storing information within this security
circuit for identifying the chip.
[0245] Finally, the non-volatile memory 134 is endowed with 256
bits of memory capacity, and is used for storing ID information for
this chip, operational mode information for this chip, and other
appropriate data.
* * * * *