U.S. patent application number 11/789003 was filed with the patent office on 2008-01-10 for non-volatile memory device.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Sung-Gon Choi, Jeong-Uk Han, Chang-Min Jeon, Hee-Seog Jeon, Ji-Do Ryu, Bo-Young Seo, Hyun-Khe Yoo.
Application Number | 20080008003 11/789003 |
Document ID | / |
Family ID | 38601936 |
Filed Date | 2008-01-10 |
United States Patent
Application |
20080008003 |
Kind Code |
A1 |
Yoo; Hyun-Khe ; et
al. |
January 10, 2008 |
Non-Volatile memory device
Abstract
A non-volatile memory device includes a memory cell block, a
first switching block, and a second switching block. A plurality of
memory cells are arranged in the memory cell block and each of the
memory cells includes a memory transistor having a floating gate
and a control gate and is connected to a local bit line and
includes a selection transistor connected to the memory transistor
in series that is connected to a source line. The first switching
block selectively connects a global bit line to the local bit line
and the second switching block controls the memory cells in the
memory cell block in units of a predetermined number of bits. The
first switching block includes at least two switching devices
connected in parallel between the global bit line and the local bit
line.
Inventors: |
Yoo; Hyun-Khe; (Suwon-si,
KR) ; Ryu; Ji-Do; (Suwon-si, KR) ; Seo;
Bo-Young; (Anyang-si, KR) ; Jeon; Chang-Min;
(Seoul, KR) ; Jeon; Hee-Seog; (Hwaseong-si,
KR) ; Choi; Sung-Gon; (Osan-si, KR) ; Han;
Jeong-Uk; (Suwon-si, KR) |
Correspondence
Address: |
MILLS & ONELLO LLP
ELEVEN BEACON STREET, SUITE 605
BOSTON
MA
02108
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
Suwon-si
KR
|
Family ID: |
38601936 |
Appl. No.: |
11/789003 |
Filed: |
April 23, 2007 |
Current U.S.
Class: |
365/185.13 |
Current CPC
Class: |
G11C 7/18 20130101; G11C
16/0433 20130101; G11C 16/24 20130101; G11C 2207/002 20130101 |
Class at
Publication: |
365/185.13 |
International
Class: |
G11C 11/34 20060101
G11C011/34 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 4, 2006 |
KR |
10-2006-0062626 |
Claims
1. A non-volatile memory device comprising: a memory cell block in
which a plurality of memory cells are arranged, each of the memory
cells including: a memory transistor having a floating gate and a
control gate and is connected to a local bit line, and a selection
transistor connected to the memory transistor in series and is
further connected to a source line; a first switching block
configured to selectively connect a global bit line to the local
bit line; and a second switching block configured to control the
memory cells in the memory cell block in units of a predetermined
number of bits, wherein the first switching block includes at least
two switching devices connected in parallel between the global bit
line and the local bit line.
2. The non-volatile memory device of claim 1, wherein each of the
switching devices is an NMOS, PMOS, or CMOS device.
3. The non-volatile memory device of claim 1, wherein each of the
switching devices is substantially the same as the selection
transistor.
4. The non-volatile memory device of claim 1, wherein the
predetermined number of bits is eight bits.
5. The non-volatile memory device of claim 1, wherein the control
gate of the memory transistor is connected to a local sense line
and the second switching block selectively connects a global sense
line to the local sense line.
6. The non-volatile memory device of claim 1, wherein the memory
cell block comprises EEPROM memory cells.
7. A non-volatile memory device comprising: a plurality of memory
sectors including a plurality of memory cells, each of the memory
cells having a memory transistor and a selection transistor; a
global bit line; a global sense line; a local bit line configured
to apply a bit line voltage to one of the memory sectors
corresponding to the local bit line; a local sense line configured
to connect control gates of the memory transistors in units of a
predetermined number of bits; a first switching device configured
to selectively connect the global bit line to the local bit line;
and a second switching device configured to selectively connect the
global sense line to the local sense line, wherein the first
switching device includes at least two switching transistors
connected in parallel between the global bit line and the local bit
line.
8. The non-volatile memory device of claim 7, wherein each of the
switching transistors is an NMOS, PMOS, or CMOS device.
9. The non-volatile memory device of claim 7, wherein each of the
switching transistors is substantially the same as the selection
transistor.
10. The non-volatile memory device of claim 7, wherein the
predetermined number of bits is eight bits.
11. The non-volatile memory device of claim 7, wherein the
plurality of memory cells comprises EEPROM memory cells.
Description
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS
[0001] This application claims the benefit of priority to Korean
Patent Application No. 10-2006-0062626, filed on Jul. 4, 2006, in
the Korean Intellectual Property Office, the disclosure of which is
incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor memory
device, and more particularly, to a non-volatile memory device
having a 2-T (transistor) FN (fowler-Nordheim) type EEPROM
(electrically erasable programmable read-only memory) memory
cell.
[0004] 2. Description of the Related Art
[0005] Unlike DRAM or SRAM devices that are erasable when power is
not supplied, non-volatile memory devices are not erasable even
when the power supply is discontinued. A typical non-volatile
memory device is an EEPROM that is electrically programmable and
erasable. The EEPROM is used to store permanent codes and is
typically programmed in units of bytes and erased in units of
blocks or sectors. Recently, flash memories that are erasable in
units of bytes have been suggested, where a 2T FN type EEPROM is
mainly used for such flash memories.
[0006] The 2T FN type EEPROM refers to an EEPROM in which two
transistors constitute one memory cell and programming and erasing
is performed using an FN tunneling method. The two transistors
constituting the memory cell are connected in series, in which one
is a FLOTOX (floating gate tunnel oxide) type memory transistor and
the other is a selection transistor.
[0007] As the memory capacity of the EEPROM device has increased,
the size of a unit memory cell has gradually decreased, so that the
active width and capacitance of the memory cell has been reduced.
As a result, the efficiency in the programming and erasing of the
memory cell has been deteriorated. Consequently, as a threshold
voltage of an on-cell memory transistor has increased, the affect
with respect to the on-cell current has become disadvantageous. The
"on-cell," or an "erased cell," means a memory cell in which the
threshold voltage is lowered, for example, not greater than +1V, as
electrons escape from a floating gate of the memory transistor. In
contrast, an "off-cell", or a "programmed cell", is a memory cell
in which the threshold voltage is high, for example, not less than
+5V, as electrons are accumulated at the floating gate of the
memory transistor.
[0008] Once the threshold voltage of the on-cell becomes high, the
amount of the on-cell current is decreased. In particular, the
threshold voltage Vth of the on-cell increases due to the repeated
work of storing and deleting data. Accordingly, as the amount of
current of the on-cell decreases, it is difficult to determine
whether it is the on-cell or the off-cell. When the determination
of the on-cell or off-cell becomes difficult, a read error can
occur.
[0009] To solve the problem, a process improvement has been
implemented to improve the quality of a tunnel oxide in which
electrons are tunneled. However, this improvement alone has not
completely resolved the problem, since various restrictions in view
of the process exist.
SUMMARY OF THE INVENTION
[0010] In accordance with aspects of the present invention,
provided is a non-volatile memory device which improves a current
characteristic of an EEPROM memory cell, in particular, an on-cell
current characteristic, to make a read speed relatively fast, while
also reducing the possibility of a read error.
[0011] According to an aspect of the present invention, a
non-volatile memory device comprises a memory cell block, a first
switching block, and a second switching block. A plurality of
memory cells are arranged in the memory cell block and each of the
memory cells includes a memory transistor having a floating gate
and a control gate and is connected to a local bit line, and a
selection transistor connected to the memory transistor in series
and is further connected to a source line. The first switching
block is configured to selectively connect a global bit line to the
local bit line and the second switching block is configured to
control the memory cells in the memory cell block in units of a
predetermined number of bits. The first switching block includes at
least two switching devices connected in parallel between the
global bit line and the local bit line.
[0012] Each of the switching devices can be an NMOS, PMOS, or CMOS
device.
[0013] Each of the switching devices can be substantially the same
as the selection transistor.
[0014] The predetermined number of bits can be eight bits.
[0015] The control gate of the memory transistor can be connected
to a local sense line and the second switching block can be
configured to selectively connect the global sense line to the
local sense line.
[0016] The memory cell block can comprise EEPROM memory cells.
[0017] According to another aspect of the present invention, a
non-volatile memory device comprises a plurality of memory sectors
including a plurality of memory cells, each of the memory cells
having a memory transistor and a selection transistor, a global bit
line, a global sense line, a local bit line configured to apply a
bit line voltage to one of the memory sectors corresponding to the
local bit line, a local sense line configured to connect control
gates of the memory transistors in units of a predetermined number
of bits, a first switching device configured to selectively connect
the global bit line to the local bit line, and a second switching
device configured to selectively connect the global sense line to
the local sense line. The first switching device includes at least
two switching transistors connected in parallel between the global
bit line and the local bit line.
[0018] Each of the switching transistors can be an NMOS, PMOS, or
CMOS device.
[0019] Each of the switching transistors can be substantially the
same as the selection transistor.
[0020] The predetermined number of bits can be eight bits.
[0021] The plurality of memory cells can comprise EEPROM memory
cells.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Various aspects of the present invention will become more
apparent by describing in detail illustrative embodiments with
reference to the attached drawings, in which:
[0023] FIG. 1 is a circuit diagram showing an embodiment of a part
of a memory array of a non-volatile memory device according to an
aspect of the present invention;
[0024] FIG. 2 is a cross-sectional view schematically showing an
embodiment of a memory cell of the memory array of the non-volatile
memory device of FIG. 1;
[0025] FIGS. 3A and 3B are circuit diagrams for explaining the
operation of an embodiment of a sector selection switching device
of the memory array of the non-volatile memory device of FIG. 1;
and
[0026] FIGS. 4A and 4B are circuit diagrams for explaining the
operation of another embodiment of a sector selection switching
device of a non-volatile memory device according to another aspect
of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0027] Hereinafter, aspects of the present invention will be
described or explained with reference to the attached figures. The
invention is not limited to or by the illustrative preferred
embodiments disclosed herein. Like reference numerals in the
figures denote like elements.
[0028] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are used
to distinguish one element from another, but not to imply a
required sequence of elements. For example, a first element can be
termed a second element, and, similarly, a second element can be
termed a first element, without departing from the scope of the
present invention. As used herein, the term "and/or" includes any
and all combinations of one or more of the associated listed
items.
[0029] It will be understood that when an element is referred to as
being "on" or "connected" or "coupled" to another element, it can
be directly on or connected or coupled to the other element or
intervening elements may be present. In contrast, when an element
is referred to as being "directly on" or "directly connected" or
"directly coupled" to another element, there are no intervening
elements present. Other words used to describe the relationship
between elements should be interpreted in a like fashion (e.g.,
"between" versus "directly between," "adjacent" versus "directly
adjacent," etc.).
[0030] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a," "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises," "comprising," "includes" and/or
"including," when used herein, specify the presence of stated
features, steps, operations, elements, and/or components, but do
not preclude the presence or addition of one or more other
features, steps, operations, elements, components, and/or groups
thereof.
[0031] FIG. 1 is a circuit diagram showing an embodiment of a part
of a memory array of a non-volatile memory device according to an
aspect of the present invention. Referring to FIG. 1, a
non-volatile memory device according to this embodiment includes a
plurality of memory cell blocks MCBi, for example, MCB1, MCB2,
which are referred to as sectors, a plurality of sector selection
switching blocks SSBi, for example, SSB1, SSB2, and a byte
selection switching block.
[0032] Each of the memory cell blocks MCBi includes a plurality of
memory cells MC arranged in rows and columns. Each of the memory
cells MC can be formed of two transistors, that is, a memory
transistor T.sub.1 and a selection transistor T.sub.2. The memory
transistor T.sub.1 stores data at a level of "0" or "1" while the
selection transistor T.sub.2 selects a memory bit. In this
embodiment, the memory transistor T.sub.1 is a FLOTOX (floating
gate tunnel oxide) type transistor having a floating gate FG and a
control gate CG. And the selection transistor T.sub.2 includes a
selection gate SG. A plurality of the memory cells MC constitutes a
memory cell block MCBi, such as MCB1 and MCB2.
[0033] The control gates CG of the memory transistors T.sub.1
located in the memory cell block MCB1 are connected to a plurality
of local sense lines SL.sub.in, for example, SL.sub.11, SL.sub.12,
. . . SL.sub.1m, one sense line in each row. The selection gates of
the selection transistors T.sub.2 are connected to a plurality of
word lines WLi, for example, WL1, WL2, WLm, also one word line in
each row. Also, the selection transistors T.sub.2 are connected to
a plurality of common source lines SO.sub.i, for example, SO.sub.1,
SO.sub.2. The common source lines SO.sub.i can be configured for
each row, each column, each sector, or the entire memory device. In
FIG. 1, not all the connections of the common source lines SO.sub.i
are illustrated.
[0034] The sector selection switching blocks SSBi and the byte
selection switching block are located proximate to the memory cell
blocks MCBi. The sector selection switching blocks SSBi include a
plurality of sector selection switching devices T.sub.41, T.sub.42,
T.sub.43, and T.sub.44. The sector selection switching devices
T.sub.41, T.sub.42, T.sub.43, and T.sub.44 can be embodied in form
of a switching transistor at each of a predetermined number, for
example, 64, of the memory cells in the column direction.
[0035] Each of the sector selection switching devices T.sub.41,
T.sub.42, T.sub.43, and T.sub.44 selectively connects a global bit
line BLi, for example, BL0, . . . BL7, BL8, to a local bit line
BLn, for example, BL.sub.10, BL.sub.17, BL.sub.50, which extends
over a single sector, and is controlled by a sector selection gate
line SSGi, for example, SSG1, SSG2, SSG3, SSG4, which extend
parallel to the word lines WLi. In the present embodiment, at least
two sector selection switching transistors are connected in
parallel between each global bit line and the local bit line
corresponding thereto.
[0036] The sector selection switching devices T.sub.41, T.sub.42,
T.sub.43, and T.sub.44 are located in the same conductive region as
the memory cell MC. For example, when the memory cell MC is located
in a first conductive region 140, the sector selection switching
devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44 are also located
in the first conductive region 140. The "first conductive type" and
the "second conductive type" refer to conductive types that are
opposite to each other, like P-type and N type. The conductive
region can be a well or semiconductor substrate. Also, the sector
selection switching devices T.sub.41, T.sub.42, T.sub.43, and
T.sub.44 can be, for example, PMOS, NMOS, or CMOS. In the present
embodiment, each of the sector selection switching devices
T.sub.41, T.sub.42, T.sub.43, and T.sub.44 is embodied in an N-type
transistor. But in other embodiments they could, for example be
embodied in P-type transistors.
[0037] The byte selection switching block includes a byte selection
switching device T.sub.3 that selects the memory cell in units of
bytes from a selected sector. The byte selection switching device
T.sub.3 can be embodied in form of a switching transistor for every
1 byte memory cell, as an example.
[0038] The byte selection switching device T.sub.3 selectively
connects a plurality of global sense lines SLi, for example, SL1,
SL2, to the local sense lines SL.sub.in, for example, SL.sub.11,
SL.sub.12, SL.sub.1m, and is controlled by the byte selection gate
lines BSG.sub.i, for example, BSG.sub.0, BSG.sub.1, BSG.sub.2,
BSG.sub.4, which extend parallel to the bit lines.
[0039] The byte selection switching device T.sub.3 is located in a
different conductive region from the memory cell MC, in this
embodiment. For example, when the memory cell MC is located in the
first conductive region 140, the byte selection switching device
T.sub.3 is located in a second conductive region 150. The
conductive region can be a well or semiconductor substrate. Also,
the byte selection switching device T.sub.3 can be, for example,
PMOS, NMOS, or CMOS. In the present embodiment, the byte selection
switching device T.sub.3 is embodied in a P-type transistor.
[0040] In the present embodiment, a sector MCBi is comprised of 2
byte memory cells in the row direction and n-number, for example,
64, of the memory cells in the column direction. The sector
selection switching blocks SSBi are located at the upper or lower
end of each sector MCBi while the byte selection switching device
T.sub.3 is located at the left or right side of each sector
MCBi.
[0041] FIG. 2 is a cross-sectional view schematically showing an
embodiment of a memory cell of the memory array of the non-volatile
memory device of FIG. 1. As shown in FIG. 2, the memory cell MC of
the non-volatile memory device includes the memory transistor
T.sub.1 and the selection transistor T.sub.2 formed in a pocket
P-type well PPwell 140 that is formed in a deep N-type well DNwell
150 in a P-type semiconductor substrate (not shown).
[0042] The memory transistor T.sub.1 includes a floating gate 21 in
the pocket P-type well PPwell, an intergate insulation film 22 on
the upper surface of the floating gate 21, and a control gate 23 on
the upper surface of the intergate insulation film 22. Also, a gate
insulation film 11 is interposed between the pocket P-type well
PPwell and the floating gate 21. The gate insulation film 11
includes a tunneling region having a relatively thin thickness. The
tunneling region can be formed to have a thickness at which FN
tunneling is possible during the programming and erasing of the
memory cell MC, methods for determining such a thickness being
known in the art. Electric charges move to the floating gate 21
through the tunneling region.
[0043] A port of the memory transistor T.sub.1, for example, a
drain region N, is connected to the corresponding local bit line
(e.g., BL.sub.10). The selection transistor T.sub.2 includes a
selection gate 30 and can include an insulation film pattern 31 and
a pseudo gate 32 similar to the memory transistor T.sub.1, in view
of the simplification of a process. A port of the selection
transistor T.sub.2, for example, a source region, is connected to a
common source line SO. Also, a gate insulation film 12 is
interposed between the pocket P-type well PPwell and the selection
gate 30.
[0044] As shown in FIG. 2, as the bit line and the memory
transistor T.sub.1 are located close to each other, the memory
transistor T.sub.1 can be disturbed by continuous stress from an
applied bit line voltage. Accordingly, the on-cell current of the
memory transistor T.sub.1 can be deteriorated.
[0045] As the bit line voltage is applied to only a sector selected
using the sector selection switching device, although the
disturbance due to the bit line voltage can be reduced, a unit
memory cell area is further limited due to the increase of
integration and the structure of a sector. Accordingly, the memory
transistor T.sub.1 must be formed to be appropriate for a cell unit
pitch. Thus, the active width of the memory transistor T.sub.1 is
limited so that the on-cell current is further limited.
[0046] To improve the on-cell current, in the present embodiment,
the sector selection switching devices T.sub.41, T.sub.42,
T.sub.43, and T.sub.44 are implemented in a parallel structure. The
amount of current of the sector selection switching devices
T.sub.41, T.sub.42, T.sub.43, and T.sub.44 can be increased by
increasing the active widths of the sector selection switching
devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44. However, since
the cell unit pitch in the row direction (that is, word line
direction, referred to as "cell X pitch") is smaller than it is in
the column direction (that is, the pitch in a bit line direction,
referred to as "cell Y pitch"), there is a limit to the amount of
increase in the active widths of the sector selection switching
devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44. Also, since the
sector selection switching devices T.sub.41, T.sub.42, T.sub.43,
and T.sub.44 can be substantially the same as the selection
transistor T.sub.2, it is difficult to increase the active width of
the sector selection switching devices T.sub.41, T.sub.42,
T.sub.43, and T.sub.44. In spite of the above limitations, the
sector selection switching devices T.sub.41, T.sub.42, T.sub.43,
and T.sub.44 can be equipped with a current driving capability over
a unit memory cell current, while not working as a bottleneck of
the bit line current.
[0047] Thus, in accordance with the present embodiment, to improve
the current driving capability of the sector selection switching
devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44, as shown in
FIG. 1, two switching devices T.sub.41 and T.sub.42, and T.sub.43
and T.sub.44, are connected in parallel between each global bit
line and the local bit line corresponding thereto.
[0048] FIGS. 3A and 3B are circuit diagrams for explaining the
operation of an embodiment of a sector selection switching device
of the memory array of the non-volatile memory device of FIG. 1.
Referring to FIG. 3A, the operation of the sector selection
switching devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44 during
program (read) will be described.
[0049] The two sector selection switching devices T.sub.41 and
T.sub.42 are connected in parallel between the local bit lines
BL.sub.in, for example, BL.sub.50, extending over a sector, and the
global bit lines BL, for example, BL0, to selectively connect the
local bit lines BL.sub.in and the global bit lines BLi.
[0050] The other two sector selection switching devices T.sub.43
and T.sub.44 are connected in parallel between the local bit lines
BL.sub.in, for example, BL.sub.50, extending over another sector,
and the global bit lines BL, for example, BL0, to selectively
connect the local bit lines BL.sub.in and the global bit lines
BLi.
[0051] It is assumed that BL.sub.10 is a selected local bit line
and BL.sub.50 is an unselected local bit line. That is, it is
assumed that the first memory block MCB1 is selected and the other
memory block, for example, MCB2, is not selected.
[0052] In this case, Vni, for example, -7V, is applied to the
pocket P-type well PPwell, 0V is applied to the control gates of
the sector selection switching device T.sub.4, and T.sub.42, and
Vni, for example, -7V, is applied to the control gates of the
sector selection switching devices T.sub.43 and T.sub.44.
Accordingly, the sector selection switching devices T.sub.43 and
T.sub.44 are turned off and the sector selection switching devices
T.sub.41 and T.sub.42 are turned on so that the global bit line,
for example, BL0, and the selected local bit line BL.sub.10 are
electrically connected. That is, the local bit line corresponding
to the sector that is selected by the sector selection switching
devices T.sub.41 and T.sub.42, here the local bit line of the first
memory block MCB1, are connected to the corresponding global bit
line. In contrast, the local bit line corresponding to the
unselected sector, for example, the second memory block MCB2, is
not connected to its corresponding global bit line.
[0053] Thus, during the programming of the memory cell, a bit line
program voltage V.sub.BL,prog is applied from the global bit line
to the local bit line selected through the sector selection
switching devices T.sub.41 and T.sub.42. Thus, during the
programming, the current can be provided from the global bit line
to the local bit line selected through the two sector selection
switching devices T.sub.41 and T.sub.42, as indicated by a dashed
line in FIG. 3A. Thus, a program speed can be faster, as will be
appreciated by those skilled in the art.
[0054] The bit line program voltage V.sub.BL,prog is V.sub.ni and
0V respectively for the program and program inhibit, as shown in
Table 1. The voltage condition for the program of a non-volatile
memory device according to the present embodiment is shown in Table
1.
TABLE-US-00001 TABLE 1 BL SL WL S0 SSG BSG PPwell DNWELL Selection
Vni/0 Vpp Vni/0 Fl 0 0 Vni Vpp Non- Fl 0 Vnn/ Fl Vni Vpp 0 Vpp
selection 0 (where, Vpp: positive high voltage, Vpi: positive
intermediate voltage, Vnn: negative high voltage, Vni: negative
intermediate voltage, Fl: floating, 0: ground) Vpp, Vpi, Vnn, and
Vni can be, for example, 10 V, 7 V, -10 V, and -7 V,
respectively.
[0055] Referring to FIG. 3B, an operation of the sector selection
switching devices T.sub.41, T.sub.42, T.sub.43, and T.sub.44 will
be described during a reading operation.
[0056] The connection relationship among the global bit line BL,
for example, BLO, the local bit lines BL.sub.10, BL.sub.50, and the
sector selection switching devices T.sub.41, T.sub.42, T.sub.43,
and T.sub.44 is the same as that shown in FIG. 3A. However, the
voltage condition for the reading of the memory cell is different
from the voltage condition for the programming shown in FIG. 3A.
The voltage condition for the reading of a non-volatile memory
device according to the present embodiment is shown in Table 2.
TABLE-US-00002 TABLE 2 BL SL WL S0 SSG BSG PPwell DNWELL Selection
Vcc/0 Vr Vr 0 Vcc 0 0 Vcc Non- 0 Vr 0 0 0 Vcc 0 Vcc selection
(where Vpp: positive high voltage, Vpi: positive intermediate
voltage, Vnn: negative high voltage, Vni: negative intermediate
voltage, Vr: read voltage, 0: ground)
[0057] For illustrative purposes, it is again assumed that
BL.sub.10 is a selected local bit line and BL.sub.50 is an
unselected local bit line. That is, it is assumed that the first
memory block MCB1 is selected and the other memory block, for
example, MCB2 is not selected.
[0058] In this case, 0V is applied to the pocket P-type well
PPwell, Vcc is applied to the control gates of the sector selection
switching device T.sub.41 and T.sub.42, and a bit line read voltage
V.sub.BL, read is applied to the global bit line. Accordingly, the
sector selection switching devices T.sub.43 and T.sub.44 are turned
off and the sector selection switching devices T.sub.41 and
T.sub.42 are turned on so that the global bit line and the selected
local bit line BL.sub.10 are connected. The bit line read voltage
V.sub.BL,read can be set to Vcc, 0, or an appropriate voltage level
between 0 and Vcc, for example, 0.5V.
[0059] When the selected memory cell is the on-cell, as indicated
by a dashed line in FIG. 3B, the on-cell current flows from the
selected local bit line BL.sub.10 to the global bit line BL0
through the two sector selection switching devices T.sub.41 and
T.sub.42. An effect of increasing the transistor width can be
obtained by connecting the two sector selection switching devices
T.sub.41 and T.sub.42 in parallel between the global bit line and
the corresponding local bit line. Thus, the on-cell current flowing
through the local bit line is provided to the global bit line
without being limited by the sector selection switching devices
T.sub.41 and T.sub.42 and a sense amplifier (not shown) connected
to the global bit line can detect the on-cell current without
error. Also, a read speed can be faster, as will be appreciated by
those skilled in the art.
[0060] Thus, according to the present embodiment, the current
driving capability of the sector selection switching devices
T.sub.41, T.sub.42, T.sub.43, and T.sub.44 is improved so that the
characteristic of the bit line current, in particular, the on-cell
current, can be enhanced.
[0061] FIGS. 4A and 4B are circuit diagrams for explaining the
operation of another embodiment of a sector selection switching
device of a non-volatile memory device of according to another
aspect of the present invention. Referring to FIG. 4A, the
operation of the sector selection switching device during program
of a memory device according to the present comparative example
will be described below.
[0062] In the example shown in FIG. 4A, the global bit line BL can
be connected to a corresponding local bit line through a sector
selection transistor T.sub.51, or T.sub.52. Thus, when the sector
selection transistor T.sub.51, or T.sub.52 connecting the global
bit line and the selected local bit line is turned on, the bit line
program voltage V.sub.BL,Prog is applied from the global bit line
to the selected local bit line through the sector selection
transistor. In FIG. 4A the local bit line corresponding to sector
selection transistor T.sub.51 has been selected, so T.sub.51 is
turned on and its local bit line is shown as "Selection Bit Line."
Accordingly, the local bit line associated with sector selection
transistor T.sub.52 has not been selected, so T.sub.52 is turned
off and its local bit line is shown as "UnSelection Bit Line."
[0063] Referring to FIG. 4B, Vcc is applied to the control gate of
the sector selection switching device T.sub.51 connected to the
selected local bit line and 0V is applied to the control gate of
the sector selection switching device T.sub.52 connected to the
unselected local bit line. As the sector selection switching device
T.sub.51 having the control gate to which Vcc is applied is turned
on, the global bit line BL and the selected local bit line are
connected to each other.
[0064] When the selected memory cell is the on-cell, the on-cell
current flows from the selected local bit line to the global bit
line BL through the sector selection switching device T.sub.51. In
the prior art approach, the sector selection switching device
worked as a bottleneck, limiting the cell current, since the sector
selection switching device took the form of a transistor having
active width that was limited to fit to the cell unit pitch.
[0065] In contrast, in accordance with aspects of the present
invention, despite such limitations of the active width of a
transistor used as a sector selection switching device, two or more
sector selection switching devices are provided in parallel between
the two local lines to be selectively connected to the global bit
line, thus the current driving capability of the sector selection
switching device is improved, avoiding the bottleneck of the prior
art approach. Accordingly, the on-cell current characteristic is
improved.
[0066] As described above, according to the present invention, the
current characteristic, in particular, the on-cell current
characteristic, of the EEPROM memory cell is improved. Accordingly,
the read speed is made faster and the determination of the
on-cell/off-cell is made easy so that a possibility of error in
reading is reduced.
[0067] While this invention has been particularly shown and
described with reference to preferred embodiments, it will be
understood by those skilled in the art that various changes in form
and details can be made therein without departing from the spirit
and scope of the invention as defined by the appended claims. It is
intended by the following claims to claim that which is literally
described and all equivalents thereto, including all modifications
and variations that fall within the scope of each claim.
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