U.S. patent application number 11/643904 was filed with the patent office on 2008-01-03 for nonvolatile semiconductor memory device and manufacturing method thereof.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Takamitsu Ishihara.
Application Number | 20080001203 11/643904 |
Document ID | / |
Family ID | 38875699 |
Filed Date | 2008-01-03 |
United States Patent
Application |
20080001203 |
Kind Code |
A1 |
Ishihara; Takamitsu |
January 3, 2008 |
Nonvolatile semiconductor memory device and manufacturing method
thereof
Abstract
A nonvolatile semiconductor memory device includes a
semiconductor substrate of a first conductivity type, a pair of
source and drain diffusion regions of a second conductivity type
oppositely formed on a surface of the semiconductor substrate, and
a stacked structure having a gate insulating film, a charge
accumulation film, an interlayer insulating film and a control gate
which are formed in order on a channel region of the surface of the
semiconductor substrate interposed between the source and drain
diffusion regions. An edge of the stacked structure in the vicinity
of the source region is formed away from a junction position
between the source diffusion region and the channel region.
Inventors: |
Ishihara; Takamitsu;
(Yokohama-shi, JP) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER;LLP
901 NEW YORK AVENUE, NW
WASHINGTON
DC
20001-4413
US
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
|
Family ID: |
38875699 |
Appl. No.: |
11/643904 |
Filed: |
December 22, 2006 |
Current U.S.
Class: |
257/314 ;
257/E21.682; 257/E27.103; 257/E29.129; 257/E29.306 |
Current CPC
Class: |
H01L 29/42324 20130101;
H01L 29/7885 20130101; H01L 27/11521 20130101; H01L 27/115
20130101 |
Class at
Publication: |
257/314 |
International
Class: |
H01L 29/76 20060101
H01L029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 3, 2006 |
JP |
2006-183658 |
Claims
1. A nonvolatile semiconductor memory device comprising: a
semiconductor substrate of a first conductivity type; a pair of a
source diffusion region and a drain diffusion region of a second
conductivity type oppositely formed on a surface of the
semiconductor substrate; and a stacked structure having a gate
insulating film, a charge accumulation film, an interlayer
insulating film and a control gate which are formed in order on a
channel region of the surface of the semiconductor substrate
interposed between the source diffusion region and the drain
diffusion region, an edge of the stacked structure in the vicinity
of the source region being formed away from a junction position
between the source diffusion region and the channel region.
2. The device according to claim 1, wherein a diffusion depth of
the source diffusion region is shallower than that of the drain
region.
3. The device according to claim 1, wherein a width of the source
diffusion region is formed to be less than a width of the drain
diffusion region in a gate length direction of the control
gate.
4. The device according to claim 3, wherein a lightly-doped
impurity region of the second conductivity type, whose impurity
concentration is lower than those of the source diffusion region
and the drain diffusion region, is formed between the drain
diffusion region and the channel region.
5. The device according to claim 1, wherein a highly-doped impurity
region of the first conductivity type, whose impurity concentration
is higher than that of the substrate, is formed in the channel
region adjacent to the source region around an edge of the stacked
structure.
6. The device according to claim 5, wherein a width of the source
diffusion region is formed to be less than a width of the drain
diffusion region in a gate length direction of the control
gate.
7. The device according to claim 1, wherein a lightly-doped
impurity region of the second conductivity type, whose impurity
concentration is lower than those of the source diffusion region
and the drain diffusion region, is formed between the drain
diffusion region and the channel region.
8. The device according to claim 1, wherein the charge accumulation
film includes polysilicon.
9. The device according to claim 1, wherein the charge accumulation
film includes silicon nitride.
10. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked film by stacking
in order a gate insulating layer, a charge accumulation layer, a
first interlayer insulating layer and a control gate layer on a
semiconductor substrate of a first conductivity type; by
selectively etching the stacked film, forming, at regular intervals
in one predetermined direction, a plurality of stacked structures
having gate insulating films, charge accumulation films, first
interlayer insulating films and control gates, while alternately
forming a source planned region and a drain planned region with one
of the stacked structures interposed therebetween on the
semiconductor substrate; forming a second interlayer insulating
film to cover the plurality of stacked structures; narrowing an
exposed surface of the source planned region by processing the
second interlayer insulating film such that sidewall insulating
films are formed only on side surfaces of the stacked structures
along the source planned region; and forming a source diffusion
region in the source planned region and a drain diffusion region in
the drain planned region, by ion-implanting impurities of a second
conductivity type perpendicularly to an upper surface of the
semiconductor substrate with the stacked structures and the
sidewall insulating films used as masks.
11. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer by stacking
in order a gate insulating layer, a charge accumulation layer, a
first interlayer insulating layer and a control gate layer on a
semiconductor substrate of a first conductivity type; by
selectively etching the stacked layer, arranging in a predetermined
direction a plurality of stacked structures having gate insulating
films, charge accumulation films, first interlayer insulating films
and control gates, while alternately forming a source planned
region and a drain planned region with one of the stacked
structures interposed therebetween on the semiconductor substrate;
and forming a source diffusion region and a drain diffusion region,
which are of a second conductivity type, along the predetermined
direction on the surface of the semiconductor substrate by ion
implantation of impurities of the second conductivity type using
the stacked structures as masks, such that a depth of the source
diffusion region is shallower than that of the drain diffusion
region.
12. The method according to claim 11, wherein said forming a source
diffusion region and a drain diffusion region includes: forming a
second interlayer insulating film to bury the plurality of stacked
structures; removing the second interlayer insulating film on the
drain planned region; leaving the second insulating film on the
source planned region at a desired height; and forming the depth of
the source diffusion region shallower than that of the drain
diffusion region, by ion-implanting impurities of the second
conductivity type perpendicularly to an upper surface of the
semiconductor substrate, while interposing the second interlayer
insulating film left only on the source planned region.
13. The method according to claim 11, wherein said arranging a
plurality of stacked structures in a predetermined direction
includes: arranging the stacked structures such that the source
planned region having a small space and the drain planned region
having a large space are alternately arranged in the predetermined
direction, and said forming the source diffusion region and the
drain diffusion region includes: forming the second interlayer
insulating film so as to cover the plurality of stacked structures,
to bury the source planned region and to line the drain planned
region and inner surfaces of the stacked structures adjacent
thereto; providing an opening in the second interlayer insulating
film on the drain planned region; and forming the depth of the
source diffusion region shallower than that of the drain diffusion
region, by ion-implanting impurities of the second conductivity
type perpendicularly to an upper surface of the semiconductor
substrate, while interposing the second interlayer insulating film
deposited on the source planned region.
14. The method according to claim 11, wherein said arranging a
plurality of stacked structures in a predetermined direction
includes: arranging the stacked structures such that the source
planned region having a small space and the drain planned region
having a large space are alternately arranged in the predetermined
direction, and said forming the source diffusion region and the
drain diffusion region includes: forming the second interlayer
insulating film so as to cover the plurality of stacked structures,
to bury the source planned region and to line the drain planned
region and inner surfaces of the stacked structures adjacent
thereto; providing an opening in the second interlayer insulating
film in the drain planned region; ion-implanting impurities of the
second conductivity type in a low concentration and obliquely with
respect to an upper surface of the semiconductor substrate from two
directions including a direction running from the drain planned
region to the source planned region and a direction opposite
thereto, such that a lightly-doped impurity region is formed only
in the vicinity of the boundary between the stacked structures and
the drain planned region; and forming the source diffusion region
in the source planned region, while forming the drain diffusion
region in the drain planned region so as to adjoin the
lightly-doped impurity region, by ion-implanting the impurities of
the second conductivity type perpendicularly to the upper surface
of the semiconductor substrate.
15. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer by stacking
in order a gate insulating layer, a charge accumulation layer, a
first interlayer insulating layer and a control gate layer on a
semiconductor substrate of a first conductivity type; by
selectively etching the stacked layer, arranging in one
predetermined direction a plurality of stacked structures having
gate insulating films, charge accumulation films, first interlayer
insulating films and control gates, while alternately forming a
source planned region and a drain planned region with one of the
stacked structures interposed therebetween on the semiconductor
substrate; forming a highly-doped impurity region of the first
conductivity type having a concentration higher than that of the
semiconductor substrate only in the vicinity of a boundary between
the stacked structures and the source planned region, by implanting
impurity ions of the first conductivity type in a high
concentration and obliquely with respect to an upper surface of the
semiconductor substrate in a direction running from the source
planned region to the drain planned region; and forming the source
diffusion region in the source planned region so as to adjoin the
highly-doped impurity region, while forming the drain diffusion
region in the drain planned region, by ion-implanting impurities of
the second conductivity type perpendicularly to the upper surface
of the semiconductor substrate.
16. The method according to claim 15, wherein said forming
highly-doped impurity region of the first conductivity type
includes: forming an ion implantation blocking mask on the drain
planned region; and implanting impurity ions of the second
conductivity type obliquely with respect to the upper surface of
the semiconductor substrate from two directions including a
direction running from the source planned region to the drain
planned region and a direction opposite thereto.
17. The method according to claim 15, wherein said forming the
highly-doped impurity region of the first conductivity type
includes: forming a second interlayer insulating film to cover the
plurality of stacked structures, so as to bury the drain planned
region having a small space and to line the source planned region
having a large space and sidewalls of the stacked structures
adjacent thereto; providing an opening in the second interlayer
insulating film on the source planned region; and implanting
impurity ions of the second conductivity type obliquely with
respect to an upper surface of the semiconductor substrate from two
directions including a direction running from the source planned
region to the drain planned region and a direction opposite
thereto.
18. A method of manufacturing a nonvolatile semiconductor memory
device, the method comprising: forming a stacked layer by stacking
in order a gate insulating layer, a charge accumulation layer, an
interlayer insulating layer and a control gate layer on a
semiconductor substrate of a first conductivity type; by
selectively etching the stacked layer, arranging in one
predetermined direction a plurality of stacked structures having
gate insulating films, charge accumulation films, first interlayer
insulating films and control gates, while alternately forming a
source planned region and a drain planned region with one of the
stacked structures interposed therebetween on the semiconductor
substrate; forming a lightly-doped impurity region of a second
conductivity type only in the vicinity of a boundary between the
stacked structures and the drain planned region, by implanting
impurity ions of the second conductivity type obliquely with
respect to an upper surface of the semiconductor substrate; and
forming the source diffusion region in the source planned region
and the drain diffusion region in the drain planned region so as to
adjoin the lightly-doped impurity region, by ion-implanting
impurities of the second conductivity type perpendicularly to the
upper surface of the semiconductor substrate.
19. The method according to claim 18, wherein said forming the
lightly-doped impurity region includes: forming an ion implantation
blocking mask only on the source planned region; forming the
lightly-doped impurity region by ion-implanting impurities of the
second conductivity type in a low concentration obliquely with
respect to the upper surface of the semiconductor substrate from
two directions including a direction running from the source
planned region to the drain planned region and a direction opposite
thereto after said forming an ion implantation blocking mask; and
forming the source diffusion region and the drain diffusion region
such that the drain diffusion region adjoins the lightly-doped
impurity region, by ion-implanting impurities of the second
conductivity type having a concentration higher than the low
concentration perpendicularly to the upper surface of the
semiconductor substrate after removal of the ion implantation
blocking mask.
20. The method according to claim 18, wherein said forming a
lightly-doped impurity region includes: forming the second
interlayer insulating film so as to cover the plurality of stacked
structures, bury the source planned region having a small space,
and line the drain planned region having a large space and inner
surfaces of the stacked structures adjacent thereto; forming a
lightly-doped impurity region only in the vicinity of the boundary
between the drain planned region and the stacked structures, by
ion-implanting impurities of the second conductivity type in a low
concentration obliquely with respect to the upper surface of the
semiconductor substrate from two directions including a direction
running from the drain planned region to the source planned region
and a direction opposite thereto; and forming the source diffusion
region and the drain diffusion region such that the drain region
adjoins the lightly-doped impurity region, by ion-implanting
impurities of the second conductivity type having a concentration
higher than the low concentration perpendicularly to the upper
surface of the semiconductor substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2006-183658,
filed Jul. 3, 2006, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a NOR-type nonvolatile
semiconductor memory device and a manufacturing method thereof
capable of decreasing a power supply voltage without causing write
characteristics to deteriorate.
[0004] 2. Description of the Related Art
[0005] Recently, demands for NOR-type flash memories have been
rapidly increasing along with a rapid growth in markets of memory
media including digital cameras and portable audio equipment
including mobile telephones. At present, in order to achieve
smaller sizes, lighter weights and enhanced functions of these
devices, there are increasing requests for miniaturization, higher
integration, lower power supply voltages and enhanced reliability
in the NOR-type flash memories.
[0006] The NOR-type flash memory has a plurality of MOS type
nonvolatile semiconductor memory elements which are NOR-connected.
As is well known, one element comprises a source diffusion layer
and a drain diffusion layer oppositely formed on the surface of a
semiconductor substrate, and a gate insulating film, a floating
gate, an intergate insulating film and a control gate which are
stacked on the semiconductor substrate between the source diffusion
layer and the drain diffusion layer.
[0007] In contrast to a NAND-type flash memory which achieves
writing by FN tunneling, the NOR-type flash memory implants hot
electrons (HE) generated by use of electric field concentration at
a drain edge into the floating gate to write information. At this
point, because a voltage is applied to a drain electrode, there is
caused a problem of deterioration of the gate insulating film
located in the vicinity of the drain electrode. Thus, simple
miniaturization of a gate length causes the deterioration of write
characteristics.
[0008] While many reports have been made regarding problems and
improvements in the size reduction of the NOR-type flash memory, a
study has been conducted on the characteristics of writing achieved
by secondary electrons induced in a channel, for example, in IEEE
trans. Electron Devices, Vol. 50, No. 10, October 2003, pp.
2104-2111, wherein there are reported deterioration due to scaling
(size reduction), the optimization of device parameters, trade-off
for problems at the drain edge, etc.
[0009] However, it is known that write efficiency deteriorates as
the gate length decreases, and simple miniaturization in
conventional structures has already reached the limits. It has
therefore been desired to achieve a NOR-type nonvolatile
semiconductor memory device and a manufacturing method thereof
capable of improving the write efficiency of the micro NOR-type
flash memory.
BRIEF SUMMARY OF THE INVENTION
[0010] According to one aspect of the invention, there is provided
a nonvolatile semiconductor memory device, which includes:
[0011] a semiconductor substrate of a first conductivity type;
[0012] a pair of a source diffusion region and a drain diffusion
region of a second conductivity type oppositely formed on a surface
of the semiconductor substrate; and
[0013] a stacked structure having a gate insulating film, a charge
accumulation film, an interlayer insulating film and a control gate
which are formed in order on a channel region of the surface of the
semiconductor substrate interposed between the source diffusion
region and the drain diffusion region, an edge of the stacked
structure in the vicinity of the source region being formed away
from a junction position between the source diffusion region and
the channel region.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0014] FIG. 1 is a diagram showing write characteristics (threshold
voltages) of conventional NOR-type nonvolatile semiconductor memory
devices;
[0015] FIG. 2 is a diagram showing an electron velocity
distribution in a gate length direction on a substrate surface in
the conventional NOR-type nonvolatile semiconductor memory
devices;
[0016] FIG. 3 is a diagram showing the influence of an electron
saturation velocity on an electron velocity in the gate length
direction on the substrate surface in the conventional NOR-type
nonvolatile semiconductor memory devices;
[0017] FIG. 4 is a diagram showing the influence of the electron
saturation velocity on write characteristics in the conventional
NOR-type nonvolatile semiconductor memory devices;
[0018] FIG. 5 is a sectional view showing an element structure of a
NOR-type nonvolatile semiconductor memory device in a first
embodiment;
[0019] FIGS. 6A and 6B are sectional views showing device
structures used in a simulation in the first embodiment, wherein
FIG. 6A shows a source edge offset structure, and FIG. 6B shows a
drain edge offset structure;
[0020] FIG. 7 is a diagram showing an electric field distribution
in a gate length direction on a substrate surface in the
nonvolatile semiconductor memory device in the first
embodiment;
[0021] FIG. 8 is a diagram showing an electron velocity
distribution in the gate length direction on the substrate surface
in the nonvolatile semiconductor memory device in the first
embodiment;
[0022] FIG. 9 is a diagram of rising characteristics of threshold
voltages in the nonvolatile semiconductor memory device in the
first embodiment and shows that write characteristics are
improved;
[0023] FIG. 10 is a sectional view for explaining a factor of a
characteristic improvement in the nonvolatile semiconductor memory
device in the first embodiment;
[0024] FIG. 11 is a diagram showing current/voltage characteristics
of the nonvolatile semiconductor memory device in the first
embodiment;
[0025] FIG. 12 is a diagram showing that the electric field
distribution in the gate length direction on the substrate surface
changes depending on the size of a high-resistance region at a
source edge, in the nonvolatile semiconductor memory device in the
first embodiment;
[0026] FIG. 13 is a diagram showing that the velocity distribution
in the gate length direction on the substrate surface changes
depending on the size of the high-resistance region at the source
edge, in the nonvolatile semiconductor memory device in the first
embodiment;
[0027] FIG. 14 is a diagram showing that an electron temperature
distribution in the gate length direction on the substrate surface
changes depending on the size of the high-resistance region at the
source edge, in the nonvolatile semiconductor memory device in the
first embodiment;
[0028] FIG. 15 is a diagram showing that the write characteristics
(threshold voltages) change depending on the size of the
high-resistance region at the source edge, in the nonvolatile
semiconductor memory device in the first embodiment;
[0029] FIG. 16 is a plan view showing the arrangement of cell
transistors of the nonvolatile semiconductor memory device in the
first embodiment;
[0030] FIGS. 17A to 17G are sectional views along the A-A' line in
FIG. 16 showing stepwise a method of manufacturing the nonvolatile
semiconductor memory device in the first embodiment;
[0031] FIG. 18 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a second
embodiment;
[0032] FIGS. 19A to 19G are sectional views showing stepwise a
method of manufacturing the nonvolatile semiconductor memory device
in the second embodiment;
[0033] FIG. 20 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a third
embodiment;
[0034] FIGS. 21A to 21E are sectional views showing stepwise a
method of manufacturing the nonvolatile semiconductor memory device
in the third embodiment;
[0035] FIG. 22 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a fourth
embodiment;
[0036] FIG. 23 is a diagram showing that an electric field
distribution in a gate length direction on a substrate surface
changes due to the presence of a high-resistance impurity
concentration region at a source edge, in the nonvolatile
semiconductor memory device in the fourth embodiment;
[0037] FIG. 24 is a diagram showing that a velocity distribution in
the gate length direction on the substrate surface changes due to
the presence of the high-resistance impurity concentration region
at the source edge, in the nonvolatile semiconductor memory device
in the fourth embodiment;
[0038] FIG. 25 is a diagram showing that an electron temperature
distribution in the gate length direction on the substrate surface
changes due to the presence of the high-resistance impurity
concentration region at the source edge, in the nonvolatile
semiconductor memory device in the fourth embodiment;
[0039] FIG. 26 is a diagram showing that write characteristics
(threshold voltages) improve due to the presence of the
high-resistance impurity concentration region at the source edge,
in the nonvolatile semiconductor memory device in the fourth
embodiment;
[0040] FIGS. 27A to 27E are sectional views showing stepwise a
method of manufacturing the nonvolatile semiconductor memory device
in the fourth embodiment;
[0041] FIG. 28 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a fifth
embodiment;
[0042] FIGS. 29A to 29E are sectional views showing a method of
manufacturing the nonvolatile semiconductor memory device in the
fifth embodiment;
[0043] FIG. 30 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a sixth
embodiment;
[0044] FIGS. 31A to 31E are sectional views showing stepwise a
method of manufacturing the nonvolatile semiconductor memory device
in the sixth embodiment;
[0045] FIG. 32 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in a seventh
embodiment;
[0046] FIGS. 33A to 33E are sectional views showing a method of
manufacturing the nonvolatile semiconductor memory device in the
seventh embodiment;
[0047] FIGS. 34A to 34C are sectional views showing another method
of manufacturing the nonvolatile semiconductor memory device in the
seventh embodiment; and
[0048] FIG. 35 is a sectional view showing an element structure of
a nonvolatile semiconductor memory device in an eighth
embodiment.
DETAILED DESCRIPTION OF THE INVENTION
[0049] Before describing embodiments of the present invention,
problems of a hot electron implantation NOR-type flash memory will
be described. FIG. 1 shows data in which gate length dependency of
write characteristics of the NOR-type flash memory (using a p-type
substrate) is simulated. This graph shows how threshold values
change due to electrons written into a floating gate, wherein the
horizontal axis indicates time (writing time) of applying a drain
voltage. The voltage of a control gate is set at 9V. A greater
change in the threshold value means better write efficiency of hot
electrons. As is apparent from this graph, the write efficiency
deteriorates as the gate length decreases. Therefore, simple
miniaturization in conventional structures has already reached the
limit.
[0050] Thus, further miniaturization causes the write
characteristics to deteriorate because an electron velocity at a
drain edge significantly increases. FIG. 2 actually shows an
electron velocity distribution in a gate length direction on a
substrate surface. It can be understood that the electron velocity
at the drain edge increases as the gate length decreases. The
implantation of the hot electrons into the floating gate occurs at
the drain edge. Therefore, the electrons are implanted into a drain
as they are before becoming hot due to the increase in the electron
velocity at the drain edge, resulting in deteriorated write
efficiency. This suggests the possibility that the suppression of
overshoot of the electron velocity at the drain edge can improve
the write efficiency.
[0051] FIG. 3 actually shows the electron velocity distribution in
the gate length direction on the substrate surface when an electron
saturation velocity is halved as compared with that in a
conventional model. If the electron saturation velocity is halved,
the electron velocity at the drain edge becomes much lower. If the
electron saturation velocity is further halved, the write
efficiency can be improved, as shown in FIG. 4. Therefore, it can
be understood that the velocity overshoot has only to be suppressed
in order to improve the write efficiency.
[0052] In the present invention, the peak position of electric
field concentration is displaced to a source side due to the
presence of a high-resistance offset region formed by controlling
an impurity distribution at a source edge, so that the implantation
of the hot electrons into a drain diffusion region is suppressed,
and the velocity overshoot at the edge of the drain diffusion
region is also suppressed, thereby making it possible to provide a
NOR-type nonvolatile semiconductor memory device with significantly
improved write characteristics.
[0053] The embodiments of the present invention will hereinafter be
described with reference to the drawings.
First Embodiment
[0054] As shown in FIG. 5, in a NOR-type nonvolatile semiconductor
memory device according to a first embodiment of the present
invention, a source diffusion region 2 and a drain diffusion region
3 are oppositely formed in a semiconductor substrate 1, and on the
surface of the semiconductor substrate 1 between the source
diffusion region 2 and the drain diffusion region 3, there is
formed a stacked gate structure including a gate insulating film 4,
a floating gate (charge accumulation layer) 5, an intergate
(interlayer) insulating film 6 and a control gate 7. The
semiconductor substrate surface under the stacked gate structure is
a channel region 10 where a channel is formed when a drive voltage
is applied to the control gate 7. In this element structure, the
source diffusion region 2 is formed to be offset by .DELTA.y from
the edge of the floating gate 5.
[0055] It should be noted that in the NOR-type flash memory in
general, the conductivity type of the semiconductor substrate 1 is
p type, the source diffusion region 2 and the drain diffusion
region 3 are n type, and carriers are electrons, but the
conductivity types can be reversed and the carriers can be holes.
In the following description, the carriers are electrons.
[0056] Here, the overlapping position relation among the source
diffusion region 2, the drain diffusion region 3 and the floating
gate 5 is defined. As schematically shown in FIG. 5, the structure
in which the stacked gate structure does not overlap the source
diffusion region 2 but overlaps the edge of the drain diffusion
region 3 is called a source edge offset structure. In contrast, a
structure in which the drain diffusion region 3 does not overlap
the floating gate 5 but the source diffusion layer region 2
overlaps the floating electrode 5 is called a drain edge offset
structure.
[0057] First, a simulation will be described which has been carried
out to explain that the structure in FIG. 5 is effective in the
NOR-type flash memory. Models as shown in FIGS. 6A and 6B are used
for the simulation. FIG. 6A shows a source edge offset model, and
FIG. 6B shows a drain edge offset model. In addition to this, a
simulation has also been carried out for a conventional product in
which the floating gate 5 equally overlaps the source diffusion
region 2 and the drain diffusion region 3, but a structure thereof
is not shown.
[0058] In the source offset structure shown in FIG. 6A, overshoot
(excess over an expected value) of an electron velocity in a gate
length direction is suppressed at the gate edge in the vicinity of
the drain, as compared with the conventional structure. Such
effects can be understood from an electric field distribution in
the gate length direction, as shown in FIG. 7. In FIG. 7, the
center line of the gate electrode is set at 0 so that profiles of
electric field strength (Ex [V/cm]) in the gate length direction
are calculated. L1 is the electric field strength profile of the
conventional product, L2 is the electric field strength profile of
the source edge offset structure, and L3 is the electric field
strength profile of the drain edge offset structure. Dotted lines
drawn perpendicularly to the horizontal axis are the source side
edge and the drain side edge of the floating gate electrode 5.
[0059] As understood from FIG. 7, the peak position of an electric
field in the gate length direction is more displaced to the source
side in the source edge offset structure. Thus, the range of a
region where the electrons are accelerated is narrower, and the
increase of electron energy is suppressed, such that the velocity
overshoot is suppressed.
[0060] On the other hand, in the drain edge offset structure, the
drain diffusion layer 3 is farther away from the gate edge, so that
a peak of electric field concentration not only emerges at the gate
edge on the drain side but also emerges at a drain electrode edge.
This enlarges the electric field concentrated region where the
electrons are accelerated, and therefore, the electron energy
further increases. As a result, the velocity overshoot becomes more
obvious. Therefore, as shown in FIG. 8, while write efficiency is
improved in the source edge offset structure, the write efficiency
rather deteriorates in the drain edge offset structure. It should
be noted that the vertical axis indicates the velocity (Vx [cm/s])
of the electrons in FIG. 8.
[0061] Furthermore, FIG. 9 shows rising characteristics of Vth (1
.mu.A, Vd=1V) at a gate length of 100 nm for comparison among the
conventional product, the source edge offset structure and the
drain edge offset structure. It can be understood that the rising
characteristics, that is, write characteristics are improved by the
source edge offset structure.
[0062] Thus, the write characteristics can be improved by the
source edge offset structure shown in FIG. 5. The formation of the
offset structure at the source edge rather than at the drain edge
is effective.
[0063] However, when a high-resistance offset region is formed at
the source edge as in FIG. 5, there is concern over deterioration
of current drive force. However, as shown in FIG. 10, when the
source edge is moved by .DELTA.x to the source side to provide the
high-resistance offset region at the source edge, a drain diffusion
region can also be moved by .DELTA.x to the source side to suppress
the deterioration of the current drive force. FIG. 11 shows a drain
current (Id) when a drain voltage is 0.8V and the gate length is
100 nm in the structure shown in FIG. 10. The horizontal axis
indicates a floating gate voltage (Vg). It can be understood that
the current drive force hardly changes as compared with that in the
conventional structure.
[0064] Thus, in the first embodiment of the present invention, the
high-resistance offset region is provided at the source edge, and
the drain diffusion region profile is optimized, thereby making it
possible to improve the write characteristics of the NOR-type flash
memory without causing the current drive force to deteriorate.
[0065] FIGS. 12 to 15 are characteristic diagrams showing that a
distance .DELTA.y between the gate edge and a source junction
position shown in FIG. 5 can be adjusted to improve the write
characteristics. It should be noted that the gate length is 70 nm
in FIGS. 12 to 15. FIG. 12 shows profiles of electric field
strengths when the source offset .DELTA.y is changed to 0 nm
(conventional product), 7 nm and 10 nm. As understood from FIG. 12,
an increase of .DELTA.y displaces the peak position of the electric
field concentration to the source side, so that the velocity
overshoot is suppressed, as shown in FIG. 13.
[0066] Furthermore, as shown in FIG. 14, the peak position of
electron temperature is also more displaced to the source side. In
the conventional structure, since the peak position of the electron
temperature is present on the drain side, hot electrons flow into
the drain diffusion region as they are. The displacement of the
peak position of the electron temperature to the source side means
more displacement of an implanting position of the hot electrons to
the source side, such that there is an advantage of suppressing the
flowing of the hot electrons into the drain diffusion region.
[0067] Moreover, FIG. 15 shows rising characteristics of Vth (1
.mu.A, Vd=1V) at a gate length of 70 nm for comparison among the
conventional product, a source edge offset of 7 nm and a drain edge
offset of 10 nm. It can be understood that the rising
characteristics are improved as the source edge offset is
increased. Thus, the size of the high-resistance offset region at
the source edge can be controlled to control the write
characteristics.
[0068] FIGS. 17A to 17G are sectional views showing stepwise a
manufacturing method to form the device structure shown in FIG. 15
in which the offset region is provided at the source edge, and
FIGS. 17A to 17G correspond to sectional views along the A-A' line
in a plan view shown in FIG. 16. To explain the plan view (FIG. 16)
in more detail, memory elements (cell transistors) shown in FIG. 5
are arranged in matrix form so that the cell transistors adjacent
in the same column share the drain or source. In addition, the
control gates 7 of the cell transistors in the same row are
connected in common to a control gate line CG.
[0069] The manufacturing method is as follows. First, layers to be
the gate (tunnel) insulating film 4, the floating gate 5, the
intergate (interlayer) insulating film 6 and the control gate 7 are
stacked on the substrate 1 in order (FIG. 17A), and lithography is
used to carry out stacked gate patterning, and then a sidewall
insulating film 15 is formed by an oxidation process to form a
structure shown in FIG. 17B. Here, the floating gate 5 and the
control gate 7 are formed of, for example, polysilicon.
[0070] Next, as shown in FIG. 17C, an interlayer (embedded)
insulating film 16 is deposited, and a sidewall insulating film 17
is formed only on the side of a source diffusion region by
pattering using a mask as shown in FIG. 17D. Then, a sidewall
insulating film 18 is formed (FIG. 17E), and impurities (e.g.,
phosphorous [P] as n-type impurities) for the formation of the
source/drain diffusion regions are ion-implanted over the sidewall
insulating film 18 (FIG. 17F), such that a device structure can be
formed in which the high-resistance offset region is formed only at
the source edge (FIG. 17G). Here, the insulating film 17 and the
insulating film 18 used as the sidewall insulating films need to be
in a selected ratio. For example, when TEOS is used as the
insulating film 17, it is necessary to use a silicon nitride film
as the insulating film 18. In contrast, when the silicon nitride
film is used as the insulating film 17, TEOS is used as the
insulating film 18.
[0071] As described above, according to the first embodiment, the
provision of the high-resistance offset region at the source edge
can improve the write characteristics.
Second Embodiment
[0072] In a NOR-type nonvolatile semiconductor memory device
according to a second embodiment of the present invention, a
diffusion depth Ds of a source diffusion region 2 is formed to be
less (shallower) than a diffusion depth Dd of a drain diffusion
region 3, as shown in FIG. 18. Thus, a high-resistance region is
provided at a source edge, so that velocity overshoot is
suppressed, and write efficiency can be improved, as has been
described in the first embodiment of the present invention.
[0073] FIGS. 19A to 19G are sectional views showing stepwise a
method of manufacturing the NOR-type nonvolatile semiconductor
memory device according to the second embodiment of the present
invention, and a plan view thereof is similar to FIG. 16. First,
layers to be a tunnel insulating film 4, a floating gate 5, an
intergate insulating film 6 and a control gate 7 are stacked on a
substrate 1 in order (FIG. 19A), and lithography is used to carry
out stacked gate patterning, and then a sidewall insulating film 15
is formed by an oxidation process to form a structure shown in FIG.
19B.
[0074] Next, as shown in FIG. 19C, an interlayer (embedded)
insulating film 16 is deposited, so that air gaps between cell
transistors are filled. As required, an upper surface portion of
the interlayer insulating film 16 may be flattened by means such as
chemical mechanical polishing (CMP). Then, as shown in FIG. 19D,
the interlayer insulating film 16 on the drain diffusion region is
removed by pattering using a mask, thereby obtaining a structure
shown in FIG. 19E.
[0075] Next, as shown in FIG. 19F, the interlayer insulating film
16 remaining on the source diffusion region side is adjusted to a
desired height by removing means such as etching. Impurities (e.g.,
P) for the formation of the source and drain diffusion regions are
ion-implanted over the interlayer insulating film 16 remaining on
the source diffusion region side, such that the source diffusion
region 2 can be formed shallower than the drain diffusion region 3,
as shown in FIG. 19G. Thus, the element structure shown in FIG. 18
can be manufactured.
[0076] As described above, the depth of the source diffusion region
2 is shallower than the depth of the drain diffusion region 3, such
that the high-resistance offset region can be provided at the
source edge, and write characteristics can be improved, as in the
first embodiment.
Third Embodiment
[0077] A mask is added to form a desired device structure in the
manufacturing method of the second embodiment. However, it is
desirable to prevent the addition of the mask as much as possible
from the viewpoint of a manufacturing cost reduction. In a device
structure of a NOR-type nonvolatile semiconductor memory device
according to a third embodiment shown in FIG. 20, it is possible to
form a high-resistance offset region only at a source edge without
adding the mask. That is, in the device structure shown in FIG. 20,
an intercell distance on a source side is formed to be less than an
intercell distance on a drain side. Such a structure makes it
possible to form the high-resistance offset region only at the
source edge without adding the mask, as described below.
[0078] FIGS. 21A to 21E are sectional views showing stepwise a
method of manufacturing the NOR-type nonvolatile semiconductor
memory device according to the third embodiment of the present
invention, and a plan view thereof is similar to FIG. 16. First,
layers to be a tunnel insulating film 4, a floating gate 5, an
intergate insulating film 6 and a control gate 7 are stacked on a
substrate 1 in order, and lithography is used to carry out stacked
gate patterning, and then a sidewall insulating film 15 is formed
by an oxidation process to form a structure shown in FIG. 21A.
Here, in the gate patterning using the lithography, the intercell
distance on the source side is formed to be less than the intercell
distance on the drain side.
[0079] Next, as shown in FIG. 21B, an interlayer (embedded)
insulating film 19 is deposited. The insulating film 19 may be any
insulating film as long as it is in a selected ratio to the
sidewall insulating film 15 which covers the stacked structure
(hereinafter referred to as a cell transistor) comprising the
substrate 1, the tunnel insulating film 4, the floating gate 5, the
intergate insulating film 6 and the control gate 7, and such an
insulating film includes a silicon nitride film.
[0080] Next, as shown in FIG. 21C, the interlayer insulating film
19 is etched to form a sidewall insulating film 20. Now, since the
intercell distance on the source side is formed to be less than the
intercell distance on the drain side, the source region alone is
filled with the sidewall insulating film 20. Then, as shown in FIG.
21D, ions (e.g., P) are implanted over the sidewall insulating film
20. Since the source side is filled with the sidewall insulating
film 20, a source diffusion region 2 is formed to be shallower than
a drain diffusion region 3 and to have a low concentration. Thus,
the high-resistance region is formed at the source edge. Then, the
sidewall insulating film 20 is released, thereby obtaining a
structure shown in FIG. 21E.
[0081] As described above, according to the third embodiment, the
depth of the source diffusion region 2 is made shallower than the
depth of the drain diffusion region 3 without using the mask, and
the high-resistance offset region can be provided at the source
edge, so that write characteristics can be improved, as in the
first embodiment.
Fourth Embodiment
[0082] In an element structure in a fourth embodiment, a
heavily-doped impurity region 8 (source halo region) of the same
conductivity type as substrate impurities is provided at an edge
(source edge) in the vicinity of a floating gate of a source
diffusion region 2, as shown in FIG. 22. Owing to this
heavily-doped impurity region 8 formed at the source edge, a
high-resistance region is formed at the source edge. Thus, a peak
of electric field concentration in a gate length direction is
decreased as shown in FIG. 23, and velocity overshoot is suppressed
as shown in FIG. 24. Further, as shown in FIG. 25, since the peak
position of electron temperature is also more displaced to the
source side, an implanting point of hot electrons more moves to the
source side. Therefore, write characteristics are significantly
improved as compared with write characteristics in the conventional
structure, as shown in FIG. 26. Here, in FIGS. 23 to 26, a gate
length is 70 nm, and the impurity concentration in the
heavily-doped impurity region 8 is 2.times.10.sup.18/cm.sup.3.
Thus, the heavily-doped impurity region of the same conductivity
type as the substrate impurities is formed at the source edge, such
that the write characteristics of the NOR-type flash memory can be
improved.
[0083] FIGS. 27A to 27E are sectional views showing stepwise a
method of manufacturing the NOR-type nonvolatile semiconductor
memory device according to the fourth embodiment of the present
invention, and a plan view thereof is similar to FIG. 16. First,
layers to be a tunnel insulating film 4, a floating gate 5, an
intergate insulating film 6 and a control gate 7 are stacked on a
substrate 1 in order (FIG. 27A), and lithography is used to carry
out stacked gate patterning, and then a sidewall insulating film 15
is formed by an oxidation process to form a structure shown in FIG.
27B.
[0084] Next, as shown in FIG. 27C, an interlayer insulating film
(not shown) is deposited, and this is processed by anisotropic
etching such as RIE to form a sidewall insulating film region 18.
The kind of insulating film forming the sidewall insulating film
region 18 includes TEOS, a silicon nitride film, or the like. Then,
as shown in FIG. 27D, a mask 21 made of an insulating film or a
resist capable of blocking the ion implantation is provided by
patterning using lithography to cover a drain region. Owing to this
mask 21, it is possible to prevent high-concentration impurities
from being implanted into a drain edge by the ion implantation, and
the ion implantation oblique with respect to the gate length
direction is carried out from two directions, such that the
heavily-doped impurity region can be formed only at the source
edge. Then, as shown in FIG. 27E, the source/drain diffusion
regions are formed by the ion implantation, so that the device
structure shown in FIG. 22 can be formed.
[0085] As described above, according to the fourth embodiment, the
heavily-doped impurity region of the same conductivity type as the
substrate is provided at the source edge to provide the
high-resistance region at the source edge, so that write
characteristics can be improved, as in the first embodiment.
Fifth Embodiment
[0086] In an element structure of a NOR-type nonvolatile
semiconductor memory device according to a fifth embodiment, a
heavily-doped impurity region 8 (source halo region) of the same
conductivity type as substrate impurities is also provided at an
edge (source edge) in the vicinity of a floating gate of a source
diffusion region 2, as shown in FIG. 28. In this respect, this
element structure is similar to the element structure in the fourth
embodiment, but in addition to this, the distance between cell
transistors on a drain side is formed to be less than the distance
between cell transistors on a source side in the memory device of
the fifth embodiment. Owing to such a structural characteristic, it
is possible to provide the heavily-doped impurity region 8 (source
halo region) of the same conductivity type as the substrate
impurities only at the source edge without adding a mask.
[0087] FIGS. 29A to 29D are sectional views showing stepwise a
method of manufacturing the NOR-type nonvolatile semiconductor
memory device according to the fifth embodiment, and a plan view
thereof is similar to FIG. 16. First, layers to be a tunnel
insulating film 4, a floating gate 5, an intergate insulating film
6 and a control gate 7 are stacked on a substrate 1 in order, and
lithography is used to carry out stacked gate patterning, and then
a sidewall insulating film 15 is formed by an oxidation process to
form a structure shown in FIG. 29A. Here, in the stacked gate
patterning using the lithography, the intercell distance on the
side of a drain 3 is formed to be less than the intercell distance
on the side of a source 2.
[0088] Next, as shown in FIG. 29B, an interlayer insulating film 19
is deposited. The insulating film 19 may be any insulating film as
long as it is in a selected ratio to the sidewall insulating film
15 which covers a cell transistor region comprising the substrate
1, the tunnel insulating film 4, the floating gate 5, the intergate
insulating film 6 and the control gate 7, and such an insulating
film includes, for example, a silicon nitride film.
[0089] Next, as shown in FIG. 29C, the interlayer insulating film
19 is etched to form a sidewall insulating film 20. Now, since the
intercell distance on the side of the drain 3 is formed to be less
than the intercell distance on the side of the source 2, the drain
region alone is filled (buried) with the sidewall insulating film
20. Then, as shown in FIG. 29D, the ion implantation oblique with
respect to the gate length direction is carried out from two
directions, such that the heavily-doped impurity region 8 of the
same conductivity type as the substrate impurities is formed at the
source edge. At this point, because the drain region is filled
(buried) with the insulating film region 20, the heavily-doped
impurity region 8 is not formed at a drain edge.
[0090] Next, as shown in FIG. 29E, the source diffusion layer 2 and
the drain diffusion layer 3 are formed by ion implantation after
the insulating film region 20 is removed. Thus, it is possible to
manufacture the NOR-type nonvolatile semiconductor memory device
(FIG. 28) according to the fifth embodiment without adding the
mask.
[0091] As described above, according to the fifth embodiment, since
the distance between the cell transistors on the drain side is
formed to be less than the distance between the cell transistors on
the source side, the heavily-doped impurity region of the same
conductivity type as the substrate is provided at the source edge
without adding the mask, such that a high-resistance region can be
provided only at the source edge. Thus, a write characteristic
improving effect similar to that in the fourth embodiment can be
obtained without increasing manufacturing costs.
Sixth Embodiment
[0092] In a sixth embodiment, a lightly-doped second drain region
(LDD structure) with a low impurity concentration is provided at an
inner edge of a drain region 3, as shown in FIG. 30. In the present
embodiment, an LDD region 9 is formed only at a drain edge, and no
LDD region is formed at a source edge, so that the resistance of
the source edge is higher than the resistance of the region at the
drain edge where the LDD region 9 is formed. Therefore, write
characteristics are improved in the structure shown in FIG. 30 for
the reason similar to that described in the first to fifth
embodiments. It should be noted that in a conventional LDD
structure, a low resistance region is provided at inner edges of
both the source and drain regions, so that it is not possible to
obtain effects as in the present embodiment.
[0093] FIGS. 31A to 31E are sectional views showing stepwise a
method of manufacturing the NOR-type nonvolatile semiconductor
memory device according to the sixth embodiment, and a plan view
thereof is similar to FIG. 16. Layers to be a tunnel insulating
film 4, a floating gate 5, an intergate insulating film 6 and a
control gate 7 are stacked on a substrate 1 in order (FIG. 31A),
and lithography is used to carry out gate patterning, and then a
sidewall insulating film 15 is formed by an oxidation process to
form a structure shown in FIG. 31B. Next, as shown in FIG. 31C, an
interlayer insulating film (not shown) is deposited, and a sidewall
insulating film region 18 is formed by removing means such as
etching. The kind of insulating film forming the sidewall
insulating film region 18 includes TEOS, a silicon nitride film, or
the like.
[0094] Next, as shown in FIG. 31D, a mask 22 made of an insulating
film or a resist capable of blocking ion implantation is provided
by patterning using lithography to cover regions except for a drain
region. The presence of this mask 22 makes it possible to prevent
an LDD region from being formed in a source region, and the ion
implantation of impurities (e.g., P) oblique with respect to a gate
length direction is carried out from two directions, such that the
LDD region 9 can be formed only in the drain region. Then, as shown
in FIG. 31E, the source/drain diffusion layers are formed by the
ion implantation of impurities (e.g., P), so that a device
structure shown in FIG. 30 can be formed.
[0095] As described above, according to the sixth embodiment, the
LDD region is provided at the drain edge to provide the
high-resistance region at the source edge, so that write
characteristics can be improved, as in the first embodiment.
Seventh Embodiment
[0096] A NOR-type nonvolatile semiconductor memory device according
to a seventh embodiment is characterized in that the distance
between cell transistors on the side of a source 2 is formed to be
less than the distance between cell transistors on the side of a
drain 3, as shown in FIG. 32. A method of manufacturing an element
structure shown in FIG. 32 will be described using FIGS. 33A to
33E.
[0097] First, layers to be a tunnel insulating film 4, a floating
gate 5, an intergate insulating film 6 and a control gate 7 are
stacked on a substrate 1 in order, and lithography is used to carry
out stacked gate patterning, and then a sidewall insulating film 15
is formed by an oxidation process to form a structure shown in FIG.
33A. Here, in the gate patterning using the lithography, the
intercell distance on the source side is formed to be less than the
intercell distance on the drain side.
[0098] Next, as shown in FIG. 33B, an interlayer insulating film 19
is deposited. The insulating film 19 may be any insulating film as
long as it is in a selected ratio to the sidewall insulating film
15 which covers a cell transistor region comprising the substrate
1, the tunnel insulating film 4, the floating gate 5, the intergate
insulating film 6 and the control gate 7, and such an insulating
film includes, for example, a silicon nitride film. Then, as shown
in FIG. 33C, the interlayer insulating film 19 is etched to form a
sidewall insulating film 20. Now, since the intercell distance on
the source side is formed to be less than the intercell distance on
the drain side, the source region alone is filled with the sidewall
insulating film 20.
[0099] Next, as shown in FIG. 33D, ion implantation oblique with
respect to a gate length direction for forming an LDD region 9 is
carried out from two directions. Because the source side is filled
with the insulating film 20, no LDD region is formed at a source
edge. Then, as shown in FIG. 33E, ion implantation for forming a
source diffusion region 2 and a drain diffusion region 3 is carried
out after the insulating film 20 is removed. Thus, it is possible
to manufacture the element structure shown in FIG. 32. Here, as
shown in FIGS. 34A to 34C, the ion implantation for forming the
source diffusion region 2 and the drain diffusion region 3 may be
carried out before the insulating film 20 is removed. In this case,
as shown in FIG. 34C, the source diffusion region 2 has a lower
peak concentration than that of the drain diffusion region 3, and
is formed to be shallower than the drain diffusion region 3.
[0100] As described above, according to the seventh embodiment,
since the distance between the cell transistors on the source side
is formed to be less than the distance between the cell transistors
on the drain side, the LDD region can be provided only at the drain
edge without adding a mask, and a high-resistance region can be
provided only at the source edge. Thus, a write characteristic
improving effect similar to that in the fourth embodiment can be
obtained without increasing manufacturing costs.
Eighth Embodiment
[0101] The first to seventh embodiments assume, as a conventional
structure, a structure having a control gate, an intergate
insulating film, a floating gate, a tunnel insulating film and a
substrate. However, the first to seventh embodiments are also
effective in a metal-oxide-nitride-oxide semiconductor (MONOS)
structure. A nonvolatile semiconductor memory device using the
MONOS structure is called an NROM.
[0102] As shown in FIG. 35, a source diffusion region 2 and a drain
diffusion region 3 are oppositely formed on a semiconductor
substrate 1. On the surface of the semiconductor substrate 1
between the source diffusion region 2 and the drain diffusion
region 3, there is formed a stacked gate structure of a first
silicon oxide film (gate insulating film) 11, a silicon nitride
film (charge accumulation film) 12, a second silicon oxide film
(interlayer insulating film) 13 and a metal gate (control gate) 14.
In this element structure, the source diffusion region 2 is formed
to be offset by .DELTA.y from the edge of the silicon nitride film
(charge memory layer) 12, as in the first embodiment. However, it
should be understood that a structure similar to those in the
second to seventh embodiments can be employed.
[0103] In the MONOS structure, electrons are captured by a trap
site present in the silicon nitride film 12 to write information.
In the first to seventh embodiments, effects similar to those in
the first to seventh embodiments can also be obtained for the NROM
in which an upper structure of the substrate has the MONOS
structure.
[0104] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *