U.S. patent application number 11/849162 was filed with the patent office on 2007-12-20 for three dimensional six surface conformal die coating.
This patent application is currently assigned to Vertical Circuits, Inc.. Invention is credited to Marc Robinson, Al Vindasius.
Application Number | 20070290377 11/849162 |
Document ID | / |
Family ID | 35150641 |
Filed Date | 2007-12-20 |
United States Patent
Application |
20070290377 |
Kind Code |
A1 |
Vindasius; Al ; et
al. |
December 20, 2007 |
Three Dimensional Six Surface Conformal Die Coating
Abstract
Semiconductor die are typically manufactured as a large group of
integrated circuit die imaged through photolithographic means on a
semiconductor wafer or slice made of silicon. After manufacture,
the silicon wafer is thinned, usually by mechanical means, and the
wafer is cut, usually with a diamond saw, to singulate the
individual die. The resulting individual integrated circuit has six
exposed surfaces. The top surface of the die includes the circuitry
images and any passivation layers that have been added to the top
layer during wafer fabrication. The present invention describes a
method for protecting and insulating all six surfaces of the die to
reduce breakage, provide electrical insulation for these layers,
and to provide physical surfaces that can be used for bonding one
semiconductor die to another for the purpose of stacking die in an
interconnected module or component.
Inventors: |
Vindasius; Al; (Saratoga,
CA) ; Robinson; Marc; (San Jose, CA) |
Correspondence
Address: |
HAYNES BEFFEL & WOLFELD LLP
P O BOX 366
HALF MOON BAY
CA
94019
US
|
Assignee: |
Vertical Circuits, Inc.
Scotts Valley
CA
|
Family ID: |
35150641 |
Appl. No.: |
11/849162 |
Filed: |
August 31, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11016558 |
Dec 17, 2004 |
|
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11849162 |
Aug 31, 2007 |
|
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60561847 |
Apr 13, 2004 |
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Current U.S.
Class: |
257/788 ;
257/E21.502; 257/E23.117; 257/E23.133; 438/127 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/00 20130101; H01L 23/3185 20130101; H01L 23/3171
20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/788 ;
438/127; 257/E23.117; 257/E21.502 |
International
Class: |
H01L 23/29 20060101
H01L023/29; H01L 21/56 20060101 H01L021/56 |
Claims
1. A singulated integrated circuit die including six surfaces, the
die being free of permanent attachment and having an electrically
insulating material applied to all surfaces.
2. The die as in claim 1 wherein the electrically insulating
material is a polymer.
3. The die as in claim 2 wherein the electrically insulating
material is parylene.
4. The die as in claim 3, further comprising an opening in the
insulating material exposing a feature in an underlying
surface.
5. The die as in claim 4 wherein the opening exposes an electrical
connection pad in a top surface of the die.
6. The die as in claim 4 wherein the opening exposes an optical
emitter or sensor in a top surface of the die.
7. A method for preparing an electrically insulated semiconductor
die for use in a component, comprising providing a die having six
surfaces, and applying a conformal electrically insulating material
onto the die surfaces.
8. The method of claim 7 further comprising, prior to applying the
conformal coating, rerouting from original connection pads on the
die as provided to new locations at the edge of the die.
9. The method of claim 7 wherein applying the conformal
electrically insulating material onto the die surfaces comprises
forming a polymer onto the die surfaces.
10. The method of claim 9 wherein applying the conformal
electrically insulating material onto the die surfaces comprises
forming parylene onto the die surfaces.
11. The method of claim 7, further comprising making openings
through the insulating material exposing a feature on the
underlying surface.
12. The method of claim 11 wherein exposing a feature on the
underlying surface comprises exposing an electrical connection
pad.
13. The method of claim 11 wherein exposing a feature on the
underlying surface comprises exposing an optical emitter or sensor.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. application Ser.
No. 11/016,558, filed Dec. 17, 2004, titled "Three dimensional six
surface conformal die coating", which claimed priority from U.S.
Provisional Application No. 60/561,847, filed Apr. 13, 2004, titled
"Three dimensional six surface conformal die coating", and both of
which are hereby incorporated by reference.
BACKGROUND AND SUMMARY
[0002] Semiconductor die are typically manufactured as a large
group of integrated circuit die imaged through photolithographic
means on a semiconductor wafer or slice made of silicon. After
manufacture, the silicon wafer is thinned, usually by mechanical
means, and the wafer is cut, usually with a diamond saw, to
singulate the individual die. The resulting individual integrated
circuit has six exposed surfaces. The top surface of the die
includes the circuitry images and any passivation layers that have
been added to the top layer during wafer fabrication. The present
invention describes a method for protecting and insulating all six
surfaces of the die to reduce breakage, provide electrical
insulation for these layers, and to provide physical surfaces that
can be used for bonding one semiconductor die to another for the
purpose of stacking die in an interconnected module or
component.
[0003] The present invention provides the advantages of reducing
chipping, cracking, and physical damage to die during die handling
and processing operations such as burn-in, test, and assembly. The
present invention is useable for any semiconductor chips including,
but not limited to memory chips.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a diagram illustrating a single semiconductor die
with original connection pads running down the center of the die,
and rerouting lines connecting the original connection pads at the
center of the die with new connection pads located at the edges of
the die.
[0005] FIG. 2 is a diagram illustrating a cross sectional side view
of a semiconductor die showing the die coated with a conformal,
insulating coating.
[0006] FIG. 3 is a diagram illustrating a cross section view of the
semiconductor die showing the conformal coating and openings in the
conformal coating above the original connection pads which run down
the center of the semiconductor die.
[0007] FIG. 4 shows a semiconductor die with connection pads around
the periphery of the die.
[0008] FIG. 5 shows a semiconductor die with peripheral pads,
either original or relocated, coated with a conformal insulative
coating, and with openings in the insulative coating located above
the peripherally located electrical connection pads.
DETAILED DESCRIPTION
[0009] Referring to FIG. 1, semiconductor die 10, with original
connection pads 60 have had an insulating layer applied to the top
surface, 30 of all of the die while the die are still connected
together in a wafer form. A metal layer is deposited and defined
using photolithography, to reroute the electrical signals from the
original connection pads 60 to new locations at the edge of the
die. An additional layer of insulating material is optionally
applied above the metal layer, and openings are made in the top
layer of insulating material at the relocated pad locations at the
edge of the semiconductor die, and optionally at the original pad
locations down the center of the top surface of the die.
[0010] Referring to FIG. 2, the semiconductor die 10, has been
thinned by grinding or lapping, and has been singulated from the
semiconductor wafer, and said semiconductor die has been coated
with a conformal insulating coating 20.
[0011] Referring to FIG. 3, openings have been made in the coating
20, above original connection pads 60, of semiconductor die 10. The
electrical connection pads in this illustration run down the center
of the top surface of the die.
[0012] Referring to FIG. 4, this shows a semiconductor die 70 with
connection pads 80 located around the periphery of the die top
surface.
[0013] FIG. 5 shows openings in the conformal coating material at
locations 90 on a semiconductor die whose electrical connections
are located at the edges of the surface of the die. The electrical
connection points may be located anywhere on any of the surfaces of
the die, but are typically located on the top surface of the die
and are typically either at the peripheral edges of the top surface
or down the center of the top surface.
* * * * *