U.S. patent application number 11/471279 was filed with the patent office on 2007-12-20 for structure and method for forming a shielded gate trench fet with the shield and gate electrodes being connected together.
Invention is credited to Christopher Boguslaw Kocon, Nathan Kraft, Paul Thorup.
Application Number | 20070290257 11/471279 |
Document ID | / |
Family ID | 38834205 |
Filed Date | 2007-12-20 |
United States Patent
Application |
20070290257 |
Kind Code |
A1 |
Kraft; Nathan ; et
al. |
December 20, 2007 |
STRUCTURE AND METHOD FOR FORMING A SHIELDED GATE TRENCH FET WITH
THE SHIELD AND GATE ELECTRODES BEING CONNECTED TOGETHER
Abstract
A field effect transistor (FET) includes a plurality of trenches
extending into a semiconductor region. Each trench includes a gate
electrode and a shield electrode with an inter-electrode dielectric
therebetween, wherein the shield electrode and the gate electrode
are electrically connected together.
Inventors: |
Kraft; Nathan; (Pottsville,
PA) ; Kocon; Christopher Boguslaw; (Mountaintop,
PA) ; Thorup; Paul; (West Jordan, UT) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER, EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Family ID: |
38834205 |
Appl. No.: |
11/471279 |
Filed: |
June 19, 2006 |
Current U.S.
Class: |
257/330 ;
257/E21.621; 257/E27.06; 257/E29.133 |
Current CPC
Class: |
H01L 29/407 20130101;
H01L 29/7811 20130101; H01L 27/088 20130101; H01L 29/42368
20130101; H01L 29/66734 20130101; H01L 29/7813 20130101; H01L
21/823437 20130101 |
Class at
Publication: |
257/330 |
International
Class: |
H01L 29/94 20060101
H01L029/94 |
Claims
1. A field effect transistor (FET) comprising: a trench extending
into a semiconductor region; a shield electrode in a lower portion
of the trench, the shield electrode being insulated from the
semiconductor region by a shield dielectric; an inter-electrode
dielectric (IED) over the shield electrode; and a gate electrode in
an upper portion of the trench over the IED, the gate electrode
being insulated from the semiconductor region by a gate dielectric,
wherein the shield electrode is electrically connected to the gate
electrode, wherein the trench extends in an active region of the
FET, the shield electrode and gate electrode extending out of the
trench and into a non-active region of the FET where the shield
electrode and gate electrode are electrically connected together by
a first interconnect layer.
2. The FET of claim 1 wherein the semiconductor region comprises: a
drift region of a first conductivity type; a body region of a
second conductivity type extending over the drift region; and
source regions of the first conductivity type in the body region
adjacent to the trench.
3. The FET of claim 2 wherein the gate electrode is recessed in the
trench to below a top surface of the semiconductor region, the FET
further comprising: a second interconnect layer contacting the
source and body regions; and a dielectric material over the gate
electrode for insulating the gate electrode and the interconnect
layer from one another.
4. The FET of claim 2 further comprising a substrate of the first
conductivity type, the drift region extending over the substrate,
wherein the trench extends through the body region and terminates
within the drift region.
5. The FET of claim 2 further comprising a substrate of the first
conductivity type, the drift region extending over the substrate,
wherein the trench extends through the body region and the drift
region and terminates within the substrate.
6. (canceled)
7. The FET of claim 2 wherein the electrical connection between the
shield and gate electrodes is made through periodic contact
openings formed in a gate runner region of the non-active
region.
8. The FET of claim 2 wherein the shield electrode is electrically
connected to the gate electrode by an additional connection through
the IED in the trench.
9. The FET of claim 1 wherein the gate electrode is electrically
connected to the shield electrode through at least one opening in
the IED inside the trench.
10. The FET of claim 1 wherein the non-active region includes a
termination region extending along a perimeter of a die housing the
FET, the electrical connection between the shield electrode and
gate electrode being made in the termination region.
11. The FET of claim 10 wherein the electrical connection between
the shield and gate electrodes is made through one or more contact
openings in the termination region.
12. A field effect transistor (FET) in a semiconductor die
comprising: an active region housing active cells; a non-active
region with no active cells therein; a drift region of a first
conductivity type; a body region of a second conductivity type over
the drift region; and a plurality of trenches extending through the
body region and into the drift region, each trench including a
shield electrode and a gate electrode, the shield electrode being
disposed below the gate electrode; wherein the shield electrode and
the gate electrode extend out of each trench and into the
non-active region where the shield electrode and gate electrode are
electrically connected together by a gate interconnect layer.
13. The FET of claim 12 furhter comprising: source regions of the
first conductivity type in the body region adjacent to each trench;
and heavy body regions of the second conductivity type in the body
region adjacent the source regions.
14. The FET of claim 13 wherein the gate electrode is recessed in
the trench to below a top surface of the source regions, the FET
further comprising: an interconnect layer contacting the source
regions and heavy body regions; and a dielectric material over the
gate electrode for insulating the gate electrode and the
interconnect layer from one another.
15. The FET of claim 12 further comprising a substrate of the first
conductivity type, the drift region extending over the substrate,
wherein the trench terminates within the drift region.
16. The FET of claim 12 further comprising a substrate of the first
conductivity type, the drift region extending over the substrate,
wherein each trench terminates within the substrate.
17. The FET of claim 12 further comprising an inter-electrode
dielectric between the shield electrode and the gate electrode in
each trench, wherein the shield electrode is electrically connected
to the gate electrode by an additional connection through the
inter-electrode dielectric.
18. The FET of claim 12 wherein the non-active region includes a
gate runner region extending through a middle portion of the die,
the shield electrode and gate electrode extending out of each
trench and into the gate runner region where the shield electrode
and gate electrode are electrically connected together by the gate
interconnect layer.
19. The FET of claim 12 wherein the non-active region includes a
termination region extending along a perimeter of the die, the
shield electrode and gate electrode extending out of each trench
and into the termination region where the shield electrode and gate
electrode are electrically connected together by the gate
interconnect layer.
20. A field effect transistor (FET) comprising a plurality of
trenches extending into a semiconductor region, each trench having
a gate electrode and a shield electrode with an inter-electrode
dielectric therebetween, wherein the shield electrode and the gate
electrode are electrically connected together in a non-active
region of the FET.
21-30. (canceled)
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates in general to semiconductor
power field effect transistors (FETs) and in particular to shielded
gate trench FETs with their shield and gate electrodes connected
together.
[0002] Shielded gate trench FETs are advantageous over conventional
FETs in that the shield electrode reduces the gate-drain
capacitance (Cgd) and improves the breakdown voltage of the
transistor. FIG. 1 is a simplified cross sectional view of a
conventional shielded gate trench MOSFET. An n-type epitaxial layer
102 extends over n+ substrate 100. N+ source regions 108 and p+
heavy body regions 106 are formed in a p-type body region 104 which
is in turn formed in epitaxial layer 102. Trench 110 extends
through body region 104 and terminates in the drift region. Trench
110 includes a shield electrode 114 below a gate electrode 122.
Gate electrode 122 is insulated from its adjacent silicon regions
by gate dielectric 120, and Shield electrode 114 is insulated from
its adjacent silicon regions by a shield dielectric 112 which is
thicker than gate dielectric 120.
[0003] The gate and shield electrodes are insulated from one
another by a dielectric layer 116 also referred to as
inter-electrode dielectric or IED. IED layer 116 must be of
sufficient quality and thickness to support the potential
difference that may exist between shield electrode 114 and gate
electrode 122. In addition, interface trap charges and dielectric
trap charges in IED layer 116 or at the interface between the
shield electrode 114 and IED layer 116 are associated primarily
with the methods for forming the IED layer.
[0004] The IED is typically formed by various processing methods.
However, insuring a high-quality IED that is sufficiently robust
and reliable enough to provide the required electrical
characteristics results in complicated processes for forming the
shielded gate trench FET. Accordingly, there is a need for
structure and method of forming shielded gate trench FET that
eliminate the need for a high-quality IED while maintaining or
improving such electrical characteristics as on-resistance.
BRIEF SUMMARY OF THE INVENTION
[0005] According to an embodiment of the invention a field effect
transistor includes a plurality of trenches extending into a
semiconductor region. Each trench includes a gate electrode and a
shield electrode with an inter-electrode dielectric therebewteen,
wherein the shield electrode and the gate electrode are
electrically connected together.
[0006] In one embodiment, the shield electrode is in a lower
portion of each trench, and is insulated from the semiconductor
region by a shield dielectric. An inter-electrode dielectric
extends over each shield electrode. The gate electrode is in an
upper portion of each trench over the inter-electrode dielectric,
and is insulated from the semiconductor region by a gate
dielectric.
[0007] In another embodiment, the semiconductor region includes a
drift region of a first conductivity type, a body region of a
second conductivity type extending over the drift region, and
source regions of the first conductivity type in the body region
adjacent to the trench.
[0008] In another embodiment, the semiconductor region further
includes a substrate of the first conductivity type, with the drift
region extending over the substrate, wherein the trenches extend
through the body region and terminate within the drift region.
[0009] In another embodiment, the trenches extend through the body
region and the drift region and terminate within the substrate.
[0010] In another embodiment, the field effect transistor further
includes an active region wherein the trenches are formed and a
non-active region. The shield electrode and the gate electrode
extend out of each trench and into the non-active region where the
shield electrode and gate electrode are electrically connected
together by a gate interconnect layer.
[0011] In another embodiment, the electrical connection between the
shield and gate electrodes is made through periodic contact
openings formed in a gate runner region of the non-active
region.
[0012] In yet another embodiment, the shield electrode is
electrically connected to the gate electrode by an additional
connection through the inter-dielectric layer in each trench.
[0013] In another embodiment, the non-active region includes a
termination region extending along a perimeter of a die housing the
FET, the shield electrode and gate electrode extending out of each
trench and into the termination region where the shield electrode
and gate electrode are electrically connected together by a gate
interconnect layer.
[0014] In accordance with another embodiment of the invention, a
field effect transistor is formed as follows. A plurality of
trenches is formed extending into a semiconductor region. A shield
electrode is formed in a bottom portion of each trench. A gate
electrode is formed in an upper portion of each trench over the
shield electrode. A gate interconnect layer electrically connecting
the shield electrode and the gate electrode is formed.
[0015] In one embodiment, a shield dielectric layer lining lower
sidewalls and a bottom surface of each is formed prior to forming
the shield electrode. A dielectric layer lining upper trench
sidewalls and a surface of the shield electrode is formed before
forming the gate electrode.
[0016] In another embodiment, the shield electrode and the gate
electrode are formed so that both the shield electrode and gate
electrode extend out of the trench and over a mesa region. A
plurality of contact openings is formed in the portion of the gate
electrode extending over the mesa region so as to expose surface
areas of the shield electrode through the contact openings. The
interconnect layer is formed to fill the contact openings thereby
electrically connecting the shield and gate electrode to one
another.
[0017] In another embodiment, the mesa region is in a non-active
region of a die housing the FET.
[0018] In another embodiment, the dielectric layer is formed by
oxidation of silicon.
[0019] In another embodiment, one or more openings are formed in a
portion of the dielectric layer extending over the shield electrode
prior to forming the gate electrode so that upon forming the gate
electrode in the trench, the gate electrode electrically contacts
the shield electrode through the one or more openings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a cross sectional view of a conventional shielded
gate trench MOSFET;
[0021] FIGS. 2A-2H are simplified cross sectional views at various
steps of a process for forming a shielded gate trench FET according
to an embodiment of the invention; and
[0022] FIG. 3 is an isometric view of a portion of a gate runner in
a shielded gate trench FET, according to an embodiment of the
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0023] FIGS. 2A-2H are simplified cross sectional views at various
steps of a process for forming a shielded gate trench FET according
to an embodiment of the invention. In FIGS. 2A-2H, the left cross
section views depict the sequence of steps leading to formation of
the shield gate trench FET structure in the active region, and the
right cross section views depict corresponding views of a
transition region from active region to non-active region (from
right to left). In this disclosure, "active region" represents
areas of a die housing the active cells, and "non-active region"
represents areas of the die which do not include any active cells.
The non-active region includes the termination region extending
along the perimeter of the die and the gate runners extending along
the perimeter or middle of the die or along both the perimeter and
middle of the die.
[0024] In FIG. 2A, using conventional techniques, trench 210 is
formed in a semiconductor region 202, and then a shield dielectric
212 (e.g., comprising oxide) is formed lining the trench sidewalls
and bottom surface and extending over mesa regions adjacent the
trench. The right cross section view in each of FIGS. 2A-2H is
through the center of the trench in the left cross section view,
along a dimension perpendicular to the left cross section view.
Thus, the right cross section view shows the trench of the left
cross section view terminating at the edge of the active region.
Also, the cross section views are not to scale, and in particular,
the physical dimensions (e.g., thickness) of the same layers or
regions in the right and the left cross section views may not
appear the same. For example, in FIG. 2A, shield dielectric 212
appears thinner in the right cross section view than the left.
[0025] As shown in the right cross section view of FIG. 2A, shield
dielectric 212 extends along the bottom surface of trench 210, and
at the edge of the active region, extends up and out of trench 210
and over silicon region 202. In one embodiment semiconductor region
202 includes an n-type epitaxial layer (not shown) formed over a
highly doped n-type substrate (not shown), and trench 202 extends
into and terminates within epitaxial layer. In another variation,
trench 202 extends through the epitaxial layer and terminates
within the substrate.
[0026] In FIG. 2B, shield electrode 214 is formed along a bottom
portion of trench 210 and is made electrically accessible in the
non-active region of the die, as follows. Using known techniques, a
conductive material (e.g., comprising doped or undoped polysilicon)
is first formed filling the trench and extending over the mesa
regions, and subsequently recessed deep into trench 210 to form
shield electrode 214.
[0027] During recessing of the conductive material, a mask 211 is
used to protect portions of the conductive material extending in
the non-active region of the die. As a result, shield electrode 214
is thicker inside trench 210 than over the mesa surfaces in the
non-active region of the die, as depicted in the right cross
section view in FIG. 2B. Further mask 211 is applied such that, at
the edge of the active region, the shield electrode extends out of
trench 210 and over the mesa surface of the non-active region.
Shield electrode 214 inside trench 210 is thus made available for
electrical connectivity in the non-active region of the die.
[0028] In FIG. 2C, using known methods, shield dielectric 212 is
completely removed from along trench sidewalls and over mesa
surfaces in the active region, as depicted by the right cross
section view. The shield dielectric is thus recessed below the top
surface of shield electrode 214. In one embodiment, shield
electrode 214 is recessed so that its top surface becomes co-planar
with that of the shield dielectric layer 212. This provides a
planar surface for the subsequent formation of gate/inter-electrode
dielectric layer.
[0029] In FIG. 2D, a gate dielectric layer 216 extending along
upper trench sidewalls is formed using conventional techniques. In
one embodiment, gate dielectric 216 is formed using conventional
oxidation of silicon. This process also results in oxidation of
shield electrode 214 thus forming an inter-electrode dielectric
(IED) layer over gate electrode 214. As shown in the right cross
section view, dielectric layer 216 extends along all exposed
surfaces of the shield electrode 214 in the active and non-active
regions. As further discussed below, the additional process steps
typically required for forming a high-quality IED are
eliminated.
[0030] In FIG. 2E, recessed gate electrode 222 is formed in trench
210 and is made electrically accessible in the non-active region as
follows. Using conventional techniques, a second conductive layer
(e.g., comprising doped polysilicon) is formed filling trench 210
and extending over the mesa surfaces in the active and non-active
regions of the die. The second conductive layer is then recessed
into trench 210 to form gate electrode 222.
[0031] During recessing of the second conductive layer, a mask 219
is used to protect portions of the second conductive material
extending in the non-active region of the die. As a result, gate
electrode 222 is thicker inside trench 210 than over the mesa
surfaces in the non-active region of the die, as depicted in the
right cross section view in FIG. 2B. Further mask 219 is applied
such that, at the edge of the active region, the recessed gate
electrode 222 extends out of trench 210 and over the mesa surface
of the non-active region. Gate electrode 222 inside trench 210 is
thus made available for electrical connectivity in the non-active
region of the die. Note that mask 219 does not extend over the
entire shield electrode 214 in the non-active region. As will be
seen, this facilitates contacting both the gate electrode and
shield electrode through the same contact opening.
[0032] In FIG. 2E, p-type body regions 204 are formed in
semiconductor region 202 using conventional body implant and drive
in techniques. Highly doped n-type source regions 208 are then
formed in body regions 216 adjacent trench 210 using conventional
source implant techniques.
[0033] In FIG. 2F, a dielectric layer 224, such as BPSG, is formed
over the structure using known techniques. In FIG. 2G, dielectric
layer 224 is patterned and etched to form source/body contact
openings in the active region, followed by a dielectric flow. As
shown in the left cross section, a dielectric dome 225 extending
fully over gate electrode 222 and partially over source regions 208
is formed. P-type heavy body regions 206 are then formed in exposed
semiconductor regions 202 using conventional implant techniques.
The same masking/etching process for forming contact openings in
the active region is used to form a contact opening 221 in
dielectric layer 224 in the non-active region in order to expose a
surface region and sidewall of gate electrode 222 and a surface
region of shield electrode 214, as shown in the right cross section
view.
[0034] In FIG. 2H, an interconnect layer (e.g., comprising metal)
is formed over the structure and then patterned to form source/body
interconnect 226A and gate interconnect 226B. As shown in the left
cross section view, source/body interconnect 226A contacts source
regions 208 and heavy body regions 106 but is insulated from gate
electrode 222 by dielectric dome 224. As shown in the right cross
section view, gate metal 226B contacts both shield electrode 214
and gate electrode 222 through contact opening 221, thus shorting
the two electrodes to one another.
[0035] Thus, contrary to conventional shielded gate FETs wherein
the shield electrode either floats (i.e., is electrically unbiased)
or is biased to the source potential (e.g., ground potential), in
the FET embodiment shown in FIG. 2H, the shield electrode is
connected and biased to the same potential as the gate electrode.
In conventional FETs where the shield electrode is floating or
connected to ground potential, a high-quality IED is typically
required to support the potential difference between the shield and
gate electrodes. However, electrically connecting together the
shield and gate electrodes eliminates the need for a high-quality
IED. The shield electrode, although biased to the gate potential,
still serves as a charge balance structure enabling the reduction
of the on resistance for the same breakdown voltage. Thus, a low
on-resistance for the same breakdown voltage is obtained while the
process steps associated with forming a high quality IED are
eliminated. Theoretically, such a structure would not even need an
IED, but the IED is formed naturally during the formation of gate
dielectric. Thus, a high performance transistor is formed using a
simple manufacturing process.
[0036] The electrical contact between the gate and shield
electrodes may be formed in any non-active region, such as in the
termination or edge regions of the die, or in the middle of the die
where the gate runners extend as shown in FIG. 3. FIG. 3 is an
isometric view of a portion of a gate runner in a shielded gate
trench FET, according to an embodiment of the invention. The upper
layers (e.g., gate interconnect layer 326B and dielectric layer
324) are peeled back in order to reveal the underlying structures.
As shown, trenches 310 extending in parallel in the active region
341 terminate on either side of the gate runner region 340.
[0037] The gate runner region 340 is structurally symmetrical about
line 3-3, with each half being structurally similar to that shown
in FIG. 2H. Shield dielectric 312 extends out of the rows of
trenches 310 and onto the mesa surface in gate runner region 340.
Likewise, each of shield electrode 314, inter-electrode dielectric
316 and gate electrode 322 extend out of the rows of trenches 310
and onto the mesa surface in gate runner region 340. Regions 311
represent the mesas between adjacent trenches in the active region
341.
[0038] Contact openings 321 expose surface areas of shield
electrode 314 to which gate interconnect layer 326B (e.g.,
comprising metal) makes electrical contact. Additionally, gate
interconnect layer 326B makes electrical contact with surface areas
332 of gate electrodes 322 exposed through dielectric layer 324. It
is desirable to minimize the gate resistance in order to minimize
the delay in biasing the individual gate electrodes inside the
trenches. For the same reasons, it is desirable to minimize the
delay in biasing the individual shield electrodes inside the
trenches. Accordingly, the frequency and shape of contact openings
321 in gate runner region 340 can be optimized to minimize the
resistance and thus the delay from the gate pad to each of the gate
and shield electrodes. The delay in biasing the shield and gate
electrodes can be further reduced by forming the gate electrode to
shield electrode contacts in both the gate runner regions and in
the termination or edge regions of the die.
[0039] The shield and gate electrodes may be electrically connected
in other ways according to other embodiments of the invention. For
example, the IED in each trench may be etched in certain places
before forming the gate electrode over the IED. In this embodiment,
contact openings as shown in FIGS. 2H and 3 would not be necessary,
and a gate interconnect contact to the gate electrode in each
trench would also be coupled to the corresponding shield electrode
through shorts in the IED. According to the other embodiments, gate
and shield electrode contacts may be formed through openings in the
IED and through contact openings formed in the non-active regions
such as the termination and gate runner regions. The elimination of
the need to form a high-quality IED results in a simplified and
more controllable process for forming shielded gate trench MOSFETs
with improved drain-to-source on-resistance R.sub.DSon.
[0040] The principles of the invention may be applied to any
shielded gate FET structures such as those shown in FIGS. 3A, 3B,
4A, 4C, 6-8, 9A-9C, 11, 12, 15, 16, 24 and 26A-26C of patent
application Ser. No. 11/026,276, titled "Power Semiconductor
Devices and Methods of Manufacture," which disclosure is
incorporated herein by reference in its entirety for all
purposes.
[0041] While the above provides a complete description of the
preferred embodiments of the invention, many alternatives,
modifications, and equivalents are possible. Those skilled in the
art will appreciate that the same techniques can apply to other
types of super junction structures as well as more broadly to other
kinds of devices including lateral devices. For example, while
embodiments of the invention are described in the context of
n-channel MOSFETs, the principles of the invention may be applied
to p-channel MOSFETs by merely reversing the conductivity type of
the various regions. Therefore, the above description should not be
taken as limiting the scope of the invention, which is defined by
the appended claims.
* * * * *