U.S. patent application number 11/769408 was filed with the patent office on 2007-12-06 for method and system for high frequency clock signal gating.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Hayden C. JR. Cranford, Stacy J. Garvin, Vernon R. Norman, Samuel T. Ray, Wayne A. Utter.
Application Number | 20070279117 11/769408 |
Document ID | / |
Family ID | 37893098 |
Filed Date | 2007-12-06 |
United States Patent
Application |
20070279117 |
Kind Code |
A1 |
Cranford; Hayden C. JR. ; et
al. |
December 6, 2007 |
METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING
Abstract
A differential clock signal gating method and system is
provided, providing a clock gating signal with a timing
relationship to a clock signal and a differential pair current to a
buffer differential pair load element. Switching the differential
pair current from the load element to a buffer differential pair
responsive to a gating signal pulse, the gating signal pulse
correlated to a first clock signal pulse, the buffer differential
pair buffers a second clock signal pulse occurring immediately and
sequentially after the first clock signal pulse and successive
clock signal pulses as a buffer clock signal output, the output
comprising a plurality of pulses each having the clock signal
amplitude and the clock signal pulse width.
Inventors: |
Cranford; Hayden C. JR.;
(Cary, NC) ; Garvin; Stacy J.; (Durham, NC)
; Norman; Vernon R.; (Cary, NC) ; Ray; Samuel
T.; (Morgan Hill, CA) ; Utter; Wayne A.;
(Fuquay-Varina, NC) |
Correspondence
Address: |
DRIGGS, HOGG & FRY CO. L.P.A.
38500 CHARDON ROAD
DEPT. IRA
WILLOUGBY HILLS
OH
44094
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
37893098 |
Appl. No.: |
11/769408 |
Filed: |
June 27, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11235758 |
Sep 27, 2005 |
7279950 |
|
|
11769408 |
Jun 27, 2007 |
|
|
|
Current U.S.
Class: |
327/291 |
Current CPC
Class: |
G06F 1/04 20130101 |
Class at
Publication: |
327/291 |
International
Class: |
H03K 3/00 20060101
H03K003/00 |
Claims
1. A method, comprising: providing a clock signal having a clock
signal amplitude and a clock signal pulse width; providing a gating
signal with a timing relationship to the clock signal; sending a
differential pair current to a buffer differential pair load
element; switching the differential pair current from the load
element to a buffer differential pair responsive to a gating signal
pulse, the gating signal pulse correlated to a first clock signal
pulse; and in response to switching the differential pair current,
the buffer differential pair buffering a second clock signal pulse
occurring immediately and sequentially after the first clock signal
pulse and successive clock signal pulses as a buffer clock signal
output, the output comprising a plurality of pulses each having the
clock signal amplitude and the clock signal pulse width.
2. The method of claim 2, wherein switching the differential pair
current from the load element to the buffer differential pair is
responsive to the gating signal during a first clock signal pulse
negative half; further comprising providing normal differential
pair current to the buffer differential pair simultaneously with
removing the differential pair current from the load element.
3. The method of claim 2, further comprising: presetting a positive
buffer differential output and a negative buffer differential
output to a differential zero; and cutting off the positive buffer
differential output and negative buffer differential output from
the differential zero simultaneously with the steps of switching
the differential pair current from the load element to the buffer
differential pair and simultaneously providing normal differential
pair current to the buffer differential pair.
4. The method of claim 3 wherein the clock signal has a frequency
of about 2.5 GHz.
5. A circuit structure, comprising: a clock generator; a data
device having a clock input in communication with the clock
generator, a data input and a data output; a gating device in
communication with the data device data input and configured to
develop a gating signal with a timing relationship to the clock
signal; a buffer in circuit communication with the data device data
output and a clock generator differential clock signal; and the
buffer comprising a differential pair and a current load device;
wherein the data device is configured to provide a gating signal
data output to the buffer responsive to a first clock signal pulse;
and wherein, responsive to the first clock signal pulse, the buffer
is configured to switch differential pair source current from the
current load device to the buffer differential pair and buffer a
second immediately subsequent clock signal pulse as a buffered
clock signal output, the buffered clock signal output having the
clock amplitude and the clock pulse width.
6. The circuit structure of claim 5, wherein the data device is a
flip flop having a clock input in inverted circuit communication
with the clock generator; and wherein the gating device is a High
Speed SerDes (HSS) core comprising logic.
7. The circuit structure of claim 6 wherein the buffer comprises a
first transistor configured to conduct a highest circuit positive
voltage input to a subsequent buffer stage negative output
responsive to an inverted gating signal input, and a second
transistor configured to conduct a circuit ground potential to a
subsequent buffer stage positive output responsive to the inverted
gating signal input, the buffer pre-set to provide a zero output;
and a subsequent buffer stage clock input in circuit communication
with the buffer block stage outputs, a buffer block subsequent
buffer stage output pre-set to a differential zero.
8. The circuit structure of claim 7, the buffer further comprising:
a third transistor configured to cut off source current to the
first transistor and the second transistor responsive to the
inverted gating signal input; and a fourth transistor configured to
conduct source current to a current load device responsive to the
inverted clock gating signal input.
9. The circuit structure of claim 8 wherein the clock signal has a
frequency of about 2.5 GHz.
Description
RELATED APPLICATION
[0001] This application is a continuation of application Ser. No.
11/235,758, filed Sep. 27, 2005.
FIELD OF THE INVENTION
[0002] The present invention relates to differential clock signal
gating in serial link architecture, and more particularly to
synchronism across multiple High Speed SerDes (HSS) cores of very
high frequency clocks.
BACKGROUND OF THE INVENTION
[0003] High-speed data-communications systems typically incorporate
multiple robust (gigabit-rate) serializer/deserializer (SerDes)
chips that can send and receive parallel data over a serial link.
Jitter is one of the most important issues in the design and
operation of high-speed serial links. Although SerDes devices
implement a purely digital function--serial data
communications--they behave in an analog-like fashion, especially
in the low-voltage differential signaling used at 10-Gbits/s
speeds. And SerDes receivers and transmitters operate
asynchronously: receiver and transmitter system clocks must operate
within tolerances specified by the communications standard to which
they conform, but they are not locked.
[0004] Synchronism across multiple High Speed SerDes (HSS) cores,
requires clock signal gating finction methods and circuitry. Clock
gating in many applications is a necessity, and is typically
accomplished by the use of a selector circuit or other switching
devices inserted in the clock path, to switch between a "static"
differential clock OFF condition and the desired clock. However
problems arise through inserting an additional stage in the clock
path, which degrades clock path performance and results in lower
total system integrity while contributing additional jitter to the
clock path.
[0005] What is needed is a clock gating method and system for
synchronism across multiple High Speed SerDes (HSS) cores of very
high frequency clocks that do not contribute to clock path
jitter.
SUMMARY OF THE INVENTION
[0006] A differential clock signal gating method and system is
provided, providing a clock gating signal with a timing
relationship to a clock signal and a differential pair current to a
buffer differential pair load element. Switching the differential
pair current from the load element to a buffer differential pair
responsive to a gating signal pulse, the gating signal pulse
correlated to a first clock signal pulse, the buffer differential
pair buffers a second clock signal pulse occurring immediately and
sequentially after the first clock signal pulse and successive
clock signal pulses as a buffer clock signal output, the output
comprising a plurality of pulses each having the clock signal
amplitude and the clock signal pulse width.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a block diagram of a clock gating circuit
according to the present invention.
[0008] FIG. 2 is a block diagram of a VCO BUFR circuit according to
the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0009] Referring now to FIG. 1, a Clock Gating Block Diagram
according to the present invention is illustrated. HSS core 101
logic develops a C2GATECLK signal 100 with correct timing
relationship to a CLOCK (differential) signal 102 from a Voltage
Controlled Oscillator (VCO) 104. The C2GATECLK 100 is applied to
the data input D 106 of a D-type flip flop 108. The CLOCK 102 input
to the D type flip flop 110 clocks the input state of the D
terminal to the output (Q) when CLOCK 102 changes from positive
(high) to negative (low) and therefore on a negative going
transition of the CLOCK 102 clocking signal through inverter 112.
When C2GATECLK 100 is made active (high) at step 120 by the HSS
core 101 logic during the positive half cycle 122 of CLOCK 102, the
next negative transition 124 of the CLOCK 102 signal clocks the D
type flip flop ON, developing C2GATECLKQ signal 130 positive at
step 132, which provides the gating finction to a VCO BUFR block
140. With C2GATECLKQ 130 active during the negative portion 124 of
the CLOCK signal 102 from the VCO 104 and the VCO BUFR block 140
preset to provide a ZERO output, when C2GATECLK 100 becomes active
at step 120, the next positive CLOCK pulse 150 and subsequent CLOCK
pulses 152 switch the output of the VCO BUFR block 140 and provide
the VCO BUFR output 160 with a full amplitude and positive half
cycle clock width and subsequent outputs 162 as the CLOCK 102
signal, which is applied to the input of the next buffer stage 170
in the clock path.
[0010] The present embodiment provides a clock gating method that
does not require the insertion of switching components in the clock
path: rather, the function is applied to the control path of a
clock buffer circuit and as a result, does not contribute to clock
path jitter. The present embodiment provides a method to meet
differential clock signal gating requirement of very high frequency
clocks (up to 2.5 GHZ), while contributing zero additional jitter
to the clock path, allowing for extremely fast turn-on of the
buffer 140.
[0011] Implementation of the clock gating circuitry involves
minimal complexity with only a few additional components for the
differential clock buffer control path. FIG. 2 illustrates an
embodiment of VCO BUFR block 140 circuitry according to the present
invention. Resistors R1 270 and R2 272, paired transistors T1 201
and T2 202, and differential pair current source transistor T4 204
with bias input 264 define a prior art "differential pair
structure" within the VCO BUFR block 140: the functions of these
elements within the differential pair structure is well known to
one skilled in the art, and it is not believed that they need to be
described with particularity. VDD 262 is the most positive voltage
used by the circuit, and VSS 260 is the circuit ground
potential.
[0012] With the C2GATECLKQ signal 130 low (OFF), transistors T5 205
and T6 206 are both conducting relative to inputs VDD 262 and VSS
260, respectively, responsive to the inverted C2GATECLKQ 130 input
295 at T5 205 and inverter 296 signal at T6 206, "pre-setting" the
differential output of the VCO BUFR block (OUTN 210 and OUTP 212)
to a differential ZERO. The low (OFF) C2GATECLKQ signal 130 cuts
off transistor T3 203, with the inverted C2GATECLKQ signal 130
causing transistor T7 207 to conduct the differential pair current
220, otherwise sent through transistor T3 203 to the "dummy" load
resistance R3 230.
[0013] Inputs INP 240 and INN 242 are ignored since the
differential transistor pair T1 201 and T2 202 have no differential
pair current supplied by T4 204 and cannot affect the outputs. When
C2GATECLKQ 130 becomes active during the negative half 124 of the
CLOCK cycle 102, as shown in FIG. 1, T5 205 and T6 206 become
cutoff and at this time T7 207 becomes cutoff, removing R3 230 as a
load from T4 204 and T3 203 simultaneously becoming active (in the
same negative half of the CLOCK signal 124), provides the normal
differential pair current 250 to T1 201 and T2 202.
[0014] T7 207 switches current to the "dummy" load resistor R3 230,
allowing the differential pair current source device T4 204 to pass
the normal differential pair current with the buffer outputs in a
differential OFF condition. Thus when C2GATECLKQ 130 becomes
active, the normal nominal value of differential pair current 250
is available immediately to the differential pair T1 201 and T2
202, rather than the relatively slower turn on and ramp up of a
differential pair current device as typically provided by prior art
clock gating circuitry, which would take a few CLOCK 102 cycles if
T4 204 was simply switched ON from an OFF (cutoff) condition, with
no current flowing. In contrast, by accomplishing the switching of
the various transistor devices T1 201 through T7 207 internal to
the VCO BUFR 140 during the negative half 124 of the CLOCK signal
102 and thereby turning the VCO BUFR 140 ON, the present embodiment
allows the next positive CLOCK 102 pulse 150 and subsequent CLOCK
pulses 152 to be available at the differential outputs OUTP 212 and
OUTN 210 of the VCO BUFR 140, without distortion of the first
positive CLOCK 102 pulse 150 after gating the VCO BUFR 140 ON and
with no additional jitter inserted in the clock path.
[0015] Thus, while the C2GATECLKQ signal 130 is low (OFF) current
flows through a "dummy path" defined from VDD 262 through R3 230,
T7 207, and T4 204 to ground VSS 260. As this current flow is
already present at the time that Inputs INN 242 and INP 240 begin
processing, output distortion and jitter on the outputs OUTN 210
and OUTP 212 by clock gating control circuitry is avoided. Output
OUTN 210 is previously preconditioned by a direct tie into VDD 262
conducted through T5 205 responsive to the inverted C2GATECLKQ low
(OFF) signal 130, and OUTP 212 is previously preconditioned by a
direct tie into VSS 260 conducted through T6 206 responsive to the
inverted C2GATECLKQ low (OFF) signal 130.
[0016] When C2GATECLKQ signal 130 goes high (ON), both T5 205 and
T6 206 are cut off, T7 207 cuts off the dummy load current through
current sink R3 230 and T3 203 conducts making the differential
pair current 220 available from T4 204 to the differential pair T1
201 and T2 202, all happening during the negative half of the CLOCK
signal 102. As T4 204 is conducting full amplitude current with
insufficient time to reduce the current flow through the device,
the next CLOCK pulse 102 is buffered through the differential pair
T1 201 and T2 202 with full amplitude and full pulse width, without
introducing jitter in the buffering process.
[0017] Prior art clock gating methods include multiplexer
structures which introduce one or more additional stages in the
signal flow, and each additional stage presents a possible source
of jitter introduction in the signal flow. In contrast, the above
embodiment does not introduce an additional stage(s) in series with
the signal flow.
[0018] In the present embodiment the C2GATECLK signal 100 is
provided within a timing relationship to the CLOCK signal 102: more
particularly, the C2GATECLK signal 100 is timed to go high (ON)
with the positive half of a CLOCK signal 102 pulse, and the
C2GATECLKQ signal 130 to go high (ON) during the negative half of
the CLOCK signal 102, enabling the next CLOCK signal 102 pulse to
be buffered fully through the differential pair T1 201 and T2 202.
This timing relationship is established in the HSS logic providing
the control signal C2GATECLKQ 130.
[0019] While the invention has been described in combination with
embodiments thereof, it is evident that many alternatives,
modifications, and variations will be apparent to those skilled in
the art in light of the foregoing teachings. Accordingly, the
invention is intended to embrace all such alternatives,
modifications and variations as fall within the spirit and scope of
the appended claims.
* * * * *