U.S. patent application number 11/443144 was filed with the patent office on 2007-12-06 for compound semiconductor-on-silicon wafer with a thermally soft insulator.
This patent application is currently assigned to Sharp Laboratories of America, Inc.. Invention is credited to Sheng Teng Hsu, Jong-Jan Lee, Tingkai Li.
Application Number | 20070278574 11/443144 |
Document ID | / |
Family ID | 38789110 |
Filed Date | 2007-12-06 |
United States Patent
Application |
20070278574 |
Kind Code |
A1 |
Hsu; Sheng Teng ; et
al. |
December 6, 2007 |
Compound semiconductor-on-silicon wafer with a thermally soft
insulator
Abstract
A method is provided for forming a compound
semiconductor-on-silicon (Si) wafer with a thermally soft
insulator. The method forms a Si substrate, with a thermally soft
insulator layer overlying the Si substrate. A silicon oxide layer
is formed immediately overlying the thermally soft insulator layer,
a top Si layer overlies the silicon oxide, and a lattice mismatch
buffer layer overlies the top Si layer. A compound semiconductor
layer is formed overlying the lattice mismatch buffer layer. The
thermally soft insulator has a liquid phase temperature lower than
the liquid phase temperatures of Si and the compound semiconductor.
For example, the thermally soft insulator may have a flow
temperature in the range of about 500.degree. C. to 900.degree. C.,
where the flow temperature is greater than the solid phase
temperature and less than the liquid phase temperature.
Inventors: |
Hsu; Sheng Teng; (Camas,
WA) ; Li; Tingkai; (Vancouver, WA) ; Lee;
Jong-Jan; (Camas, WA) |
Correspondence
Address: |
SHARP LABORATORIES OF AMERICA, INC.;C/O LAW OFFICE OF GERALD MALISZEWSKI
P.O. BOX 270829
SAN DIEGO
CA
92198-2829
US
|
Assignee: |
Sharp Laboratories of America,
Inc.
|
Family ID: |
38789110 |
Appl. No.: |
11/443144 |
Filed: |
May 30, 2006 |
Current U.S.
Class: |
257/347 ;
257/E21.127; 257/E27.112; 438/149 |
Current CPC
Class: |
H01L 21/02529 20130101;
H01L 21/02381 20130101; H01L 21/02505 20130101; H01L 21/0245
20130101; H01L 21/7624 20130101; H01L 21/02538 20130101; H01L
21/02488 20130101 |
Class at
Publication: |
257/347 ;
438/149; 257/E27.112 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 21/84 20060101 H01L021/84 |
Claims
1. A method for forming a compound semiconductor-on-silicon (Si)
wafer with a thermally soft insulator, the method comprising:
forming a Si substrate; forming a thermally soft insulator layer
overlying the Si substrate; forming a compound semiconductor layer
overlying the thermally soft insulator layer; and, wherein the
thermally soft insulator has a liquid phase temperature lower than
the liquid phase temperatures of Si and the compound
semiconductor.
2. The method of claim 1 further comprising: forming a silicon
oxide layer immediately overlying the thermally soft insulator
layer; forming a top Si layer immediately overlying the silicon
oxide layer; and, forming a lattice mismatch buffer layer
interposed between the top Si layer and the compound semiconductor
layer.
3. The method of claim 2 wherein providing the substrate includes
providing a Si handle wafer with a top surface; wherein forming the
thermally soft insulator layer includes depositing the thermally
soft insulator overlying the Si handle wafer top surface.
4. The method of claim 1 wherein forming the thermally soft
insulator includes depositing a material having a flow temperature
in the range of about 500.degree. C. to 900.degree. C., where the
flow temperature is greater than the solid phase temperature and
less than the liquid phase temperature.
5. The method of claim 4 wherein depositing the thermally soft
insulator includes forming a doped silicate glass material selected
from a group consisting of boronsilicate glass (BSG),
phosphosilicate glass (PSG), and boronphosphosilicate glass
(BPSG).
6. The method of claim 5 wherein depositing the doped silicate
glass material includes forming the doped silicate glass material
to a thickness in the range of about 50 to 1000 nanometers
(nm).
7. The method of claim 5 wherein forming BPSG includes: depositing
silicate glass; and, doping the silicate glass with phosphorus in
the range of about 2 to 4 atomic percentage (at %) and boron in the
range of about 3 to 7 at %.
8. The method of claim 5 wherein forming PSG includes: depositing
silicate glass; and, doping the silicate glass with phosphorus in
the range of about 5 to 9 at %.
9. The method of claim 5 wherein forming BSG includes: depositing
silicate glass; and, doping the silicate glass with boron in the
range of about 5 to 8 at %.
10. The method of claim 3 further comprising: prior to forming the
thermally soft insulator layer, thermally oxidizing the handle
wafer top surface.
11. The method of claim 3 further comprising: providing a donor Si
wafer with a top surface; wherein forming the silicon oxide layer
includes thermally oxidizing the donor wafer top surface; the
method further comprising: implanting the donor wafer with hydrogen
ions, forming an j implant layer; bonding the thermally soft
insulator layer of the handle wafer to the silicon oxide layer of
the donor wafer; splitting the bonded wafers along the implant
layer, exposing the top Si layer; and, wherein forming the top Si
layer includes planarizing the top Si layer.
12. The method of claim 11 wherein providing the donor Si wafer
includes providing a donor Si wafer having a <111>
crystallographic orientation.
13. The method of claim 11 wherein thermally oxidizing the donor
wafer top surface includes forming a silicon oxide layer having a
thickness in the range of about 2 to 100 nm.
14. The method of claim 2 wherein forming the compound
semiconductor layer includes forming a compound semiconductor layer
from a material selected from a group consisting of GaN, GaAs,
GaAlN, and SiC.
15. The method of claim 2 wherein forming the lattice mismatch
buffer layer includes forming the lattice mismatch buffer layer
from a material selected from a group consisting of AlN, InGaN, and
AlGaN.
16. The method of claim 2 further comprising: following the
formation of the top Si layer, etching the top Si layer; and,
forming Si islands separated from adjacent Si islands by trenches
in the top Si layer.
17. A compound semiconductor-on-silicon (Si) wafer with a thermally
soft insulator, the thermally soft insulated wafer comprising: a Si
substrate; a thermally soft insulator layer overlying the Si
substrate; a compound semiconductor layer overlying the thermally
soft insulator layer; and, wherein the thermally soft insulator has
a liquid phase temperature lower than the liquid phase temperatures
of Si and the compound semiconductor.
18. The thermally soft insulator wafer of claim 17 further
comprising: a first silicon oxide layer immediately overlying the
thermally soft insulator layer; a top Si layer immediately
overlying the first silicon oxide layer; and, a lattice mismatch
buffer layer interposed between the top Si layer and the compound
semiconductor layer.
19. The thermally soft insulator wafer of claim 18 wherein the
thermally soft insulator layer has a flow temperature in the range
of about 500.degree. C. to 900.degree. C., where the flow
temperature is greater than the solid phase temperature and less
than the liquid phase temperature.
20. The thermally soft insulator wafer of claim 19 wherein the
thermally soft insulator is a doped silicate glass material
selected from a group consisting of boronsilicate glass (BSG),
phosphosilicate glass (PSG), and boronphosphosilicate glass
(BPSG).
21. The thermally soft insulator wafer of claim 20 wherein the
doped silicate glass material has a thickness in the range of about
50 to 1000 nanometers (nm).
22. The thermally soft insulator wafer of claim 20 wherein the
doped silicate glass material is BPSG, including phosphorus in the
range of about 2 to 4 atomic percentage (at %) and boron in the
range of about 3 to 7 at %.
23. The thermally soft insulator wafer of claim 20 wherein the
doped silicate glass is PSG, including phosphorus in the range of
about 5 to 9 at %.
24. The thermally soft insulator wafer of claim 20 wherein the
doped silicate glass is BSG, including boron in the range of about
5 to 8 at %.
25. The thermally soft insulator wafer of claim 18 further
comprising: a second silicon oxide layer interposed between the
thermally soft insulator layer and the Si substrate.
26. The thermally soft insulator wafer of claim 18 wherein the top
Si layer has a thickness in the range of about 5 and 20 nm.
27. The thermally soft insulator wafer of claim 18 wherein the top
Si layer has a <111> crystallographic orientation.
28. The thermally soft insulator wafer of claim 18 wherein the
first silicon oxide layer has a thickness in the range of about 2
to 100 nm.
29. The thermally soft insulator wafer of claim 17 wherein the
compound semiconductor layer is a material selected from a group
consisting of GaN, GaAs, GaAlN, and SiC.
30. The thermally soft insulator wafer of claim 18 wherein the
lattice mismatch buffer layer is a material selected from a group
consisting of AlN, InGaN, and AlGaN.
31. The thermally soft insulator wafer of claim 18 wherein the top
Si layer includes Si islands separated from adjacent Si islands by
trenches in the top Si layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention generally relates to integrated circuit (IC)
fabrication and, more particularly, to a wafer that uses a layer to
insulate a compound semiconductor from thermally-induced lattice
mismatches with an underlying silicon (Si) substrate.
[0003] 2. Description of the Related Art
[0004] Gallium nitride (GaN) is a Group III/Group V compound
semiconductor material with wide bandgap (3.4 eV), which has
optoelectronic, as well as other applications. Like other Group III
nitrides, GaN has a low sensitivity to ionizing radiation, and so,
is useful in solar cells. GaN is also useful in the fabrication of
blue light-emitting diodes (LEDs) and lasers. Unlike previous
indirect bandgap devices (e.g., silicon carbide), GaN LEDs are
bright enough for daylight applications. GaN devices also have
application in high power and high frequency devices, such as power
amplifiers.
[0005] GaN LEDs are conventionally fabricated using a metalorganic
chemical vapor deposition (MOCVD) for deposition on a sapphire
substrate. Zinc oxide and silicon carbide (SiC) substrate are also
used due to their relatively small lattice constant mismatch.
However, these substrates are expensive to make, and their small
size also drives fabrication costs. For example, the
state-of-the-art sapphire wafer size is only about 4 inches. To
minimize costs, it would be desirable to integrate GaN device
fabrication into more conventional Si-based IC processes, which has
the added cost benefit of using large-sized (Si) wafers.
[0006] There are two fundamental problems associated with GaN-on-Si
device technology. First, there is a lattice mismatch between Si
and GaN. This problem is solved by using a buffer layer of AlN,
InGaN, AlGaN, or the like, prior to the growth of GaN. The buffer
layer provides a transition region between the GaN and Si.
[0007] However, an additional and more serious problem exists, as
there is also a thermal mismatch between Si and GaN. The thermal
expansion coefficient mismatch between GaN and Si is about 54%.
Although the lattice buffer layer may absorb part of the thermal
mismatch, the necessity of using temperatures higher than
1000.degree. C. during epi growth and other device fabrication may
cause wafer deformation. The wafer deformation can be reduced with
a very slow rate of heating and cooling during wafer processing but
this adds additional cost to the process, and doesn't completely
solve the thermal stress and wafer deformation issues.
[0008] It would be advantageous if the thermal mismatch problem
associated with GaN-on-Si device technology could be practically
eliminated without using slow heating and cooling processes.
SUMMARY OF THE INVENTION
[0009] The present invention describes GaN grown on a Si wafer with
a soft buried insulator to absorb the thermal mismatches. The
structure is similar in concept to a buried oxide layer (BOX) of a
Si-on-insulator (SOI) wafer. That is, the so-called "thermally soft
insulator" (TSI) isolates mechanical stresses between the GaN layer
and the Si substrate, avoiding wafer deformation. In one aspect,
conventional boronphosphosilicate glass (BPSG) is used as the
thermal insulator. At high wafer temperatures, the BPSG becomes
mechanically soft, isolating the thermal expansion of the top GaN
layer and the bottom Si substrate. The temperature at which BPSG is
soft can be adjusted, dependent upon the density of boron and
phosphorous in the silicon oxide. With 4 atomic percentage (at %)
of P, and 7 at % of B, the BPSG flow temperature is about
700.degree. C. and the mechanically soft temperature is lower than
600.degree. C. Therefore, there is no mechanical stress when the
wafer temperature is higher than 600.degree. C.
[0010] Accordingly, a method is provided for forming a compound
semiconductor-on-silicon (Si) wafer with a thermally soft
insulator. The method forms a Si substrate, with a thermally soft
insulator layer overlying the Si substrate. A silicon oxide layer
is formed immediately overlying the thermally soft insulator layer,
a top Si layer overlies the silicon oxide, and a lattice mismatch
buffer layer overlies the top Si layer. A compound semiconductor
layer is formed overlying the lattice mismatch buffer layer. The
thermally soft insulator has a liquid phase temperature lower than
the liquid phase temperatures of Si and the compound semiconductor.
For example, the thermally soft insulator may have a flow
temperature in the range of about 500.degree. C. to 900.degree. C.,
where the flow temperature is greater than the solid phase
temperature and less than the liquid phase temperature.
[0011] More explicitly, the compound semiconductor-on-Si wafer is
fabricated using donor and handle wafers. The thermally soft
insulator is deposited on the handle Si wafer top surface. The
donor Si wafer top surface is thermally oxidized and implanted with
hydrogen ions. The thermally soft insulator layer of the handle
wafer is bonded to the silicon oxide layer of the donor wafer. The
bonded wafers are split along the implant layer, exposing the top
Si layer, which is planarized.
[0012] Besides BPSG, boronsilicate glass (BSG), and phosphosilicate
glass (PSG) may be used as the thermally soft insulator. The
compound semiconductor layer may be a material such as GaN, GaAs,
GaAlN, or SiC. The lattice mismatch buffer layer may be a material
such as AlN, InGaN, or AlGaN.
[0013] Additional details of the above-described method, and
compound semiconductor-on-silicon wafer with a thermally soft
insulator, are presented below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a partial cross-sectional view of a compound
semiconductor-on-silicon (Si) wafer with a thermally soft
insulator.
[0015] FIG. 2 is a partial cross-sectional view of a variation of
the compound semiconductor-on-Si TSI wafer of FIG. 1.
[0016] FIG. 3 is a partial cross-sectional view of a variation of
the compound semiconductor-on-Si TSI wafer of FIG. 2.
[0017] FIGS. 4 through 6 depict steps in the fabrication of an
exemplary GaN-on-Si wafer with a BPSG TSI.
[0018] FIG. 7 is a flowchart illustrating a method for forming a
compound semiconductor-on-Si wafer with a thermally soft
insulator.
DETAILED DESCRIPTION
[0019] FIG. 1 is a partial cross-sectional view of a compound
semiconductor-on-silicon (Si) wafer with a thermally soft
insulator. In a simple aspect, the thermally soft insulated (TSI)
wafer 100 comprises a Si substrate 102, a thermally soft insulator
layer 104 overlying the Si substrate 102, and a compound
semiconductor layer 106 overlying the thermally soft insulator
layer 104. The thermally soft insulator 104 has a liquid phase
temperature lower than the liquid phase temperatures of Si 102 or
the compound semiconductor 106.
[0020] The thermally soft insulator (TSI) layer 104 has a flow
temperature in the range of about 500.degree. C. to 900.degree. C.,
where the flow temperature is greater than the solid phase
temperature and less than the liquid phase temperature. The TSI
insulator layer 104 may be considered to be mechanically soft at
the flow temperature, soft enough to isolate any differences in
thermal expansion between the Si substrate 102 and the compound
semiconductor 106. That is, the TSI layer 104 may be considered to
be "soft" at the flow temperature. The compound semiconductor layer
106 can be a material such as GaN, GaAs, GaAlN, or SiC. However,
the basic principle of the invention can be applied to any wafer
with a thermal mismatch issue between film layers. While the
invention has practical application to Si substrates, it is not
limited to any particular type of underlying substrate
material.
[0021] FIG. 2 is a partial cross-sectional view of a first
variation of the compound semiconductor-on-Si TSI wafer of FIG. 1.
In this aspect, a first silicon oxide layer 200 immediately
overlies the thermally soft insulator layer 104. In one aspect, the
first silicon oxide layer 200 has a thickness 202 in the range of
about 2 to 100 nm. A top Si layer 204 immediately overlies the
first silicon oxide layer 200. The top Si layer 204 has a thickness
206 in the range of about 5 and 20 nm. In one aspect, the top Si
layer 202 has a <111> crystallographic orientation. A lattice
mismatch buffer layer 208 is interposed between the top Si layer
204 and the compound semiconductor layer 106. The lattice mismatch
buffer layer 208 can be a material such as AlN, InGaN, or AlGaN.
However, other materials could also be used that have a high
tolerance to lattice mismatch.
[0022] With respect to both FIGS. 1 and 2, the thermally soft
insulator 104 may be a doped silicate glass material such as
boronsilicate glass (BSG), phosphosilicate glass (PSG), or
boronphosphosilicate glass (BPSG). As shown in FIG. 2, the doped
silicate glass material 104 has a thickness 210 in the range of
about 50 to 1000 nanometers (nm). Other materials may also be used
that have a relatively low flow temperature.
[0023] If the doped silicate glass material is BPSG, then it
includes phosphorus in the range of about 2 to 4 atomic percentage
(at %) and boron in the range of about 3 to 7 at %. If the doped
silicate glass is PSG, then it includes phosphorus in the range of
about 5 to 9 at %. If BSG, the doped silicate glass includes boron
in the range of about 5 to 8 at %. The flow temperature of the TSI
material can be varied by adjusting the above-mentioned doping
ratios.
[0024] FIG. 3 is a partial cross-sectional view of a variation of
the compound semiconductor-on-Si TSI wafer of FIG. 2. In this
aspect, the top Si layer 204 includes Si islands 300 separated from
adjacent Si islands by etched trenches (cavities) 302 in the top Si
layer. The trenches 302 may be filed with a material such as
silicon oxide. In one aspect as shown, an optional second silicon
oxide layer 304 may be interposed between the thermally soft
insulator layer 104 and the Si substrate 102. Alternately, this
optional Si oxide layer may be used in the wafer of FIG. 2.
Functional Description
[0025] FIGS. 4 through 6 depict steps in the fabrication of an
exemplary GaN-on-Si wafer with a BPSG TSI. FIG. 4 is a partial
cross-sectional depicting a handle wafer prior to bonding. The BPSG
layer is similar to the conventional undoped silicon oxide BOX of a
SOI wafer. While conventional SOI may be used as a TSI in some
aspects, the BOX of a conventional SOI is undoped silicon oxide,
which only becomes soft at temperatures higher than 1000.degree. C.
Lower TSI flow temperature can be achieved using a BPSG layer.
[0026] FIG. 5 is a partial cross-sectional view of a donor wafer
ready for bonding. First, the handle wafer and a donor wafer are
cleaned. The handle wafer can be any type of silicon substrate. The
donor wafer may be a <111> oriented silicon substrate. The
size of the handle wafer is the same as that of the donor
wafer.
[0027] A thin layer of thermal oxide is grown on the donor wafer.
The thickness of this thermal oxide can be from about 2 nm to 100
nm. Optionally, a thin layer of thermal oxide (2 nm to 100 nm) may
also be grown onto the handle wafer.
[0028] BPSG, with 2 at % to 4 at % of phosphorus, and 3 at % to 7
at % boron, is deposited onto the handle wafer. The thickness of
the BPSG layer can be 50 nm to 1000 nm. The BPSG doping density may
be lower at the bottom and the top surfaces of the film, with a
maximum in the center portion of the film. If the GaN is formed by
epitaxial (epi) growth in subsequent processes, this form of
distribution is likely to occur, even the initial doping of the
thermally soft insulator is uniform across the thickness of the
film.
[0029] High energy hydrogen ions are implanted into the donor
wafers for wafer splitting. The donor wafer is bonded to the handle
wafer, and the donor wafer is split away to expose the top Si
layer.
[0030] FIG. 6 is a partial cross-sectional view wafer following the
splitting process. A chemical-mechanical polish (CMP) process is
performed to planarize the top silicon layer. The silicon thickness
remaining after planarization may be 5 nm to 50 nm.
[0031] Optionally, the top <111> Si layer may be etched to
form <111> Si islands prior to the formation of the GaN and
lattice mismatch buffer layer, in order to have better stress
release effect.
[0032] Any conventional method may be used to grow the lattice
mismatch buffer layer and the GaN layer. The BPSG BOX SOI wafer may
also used as substrate to grow any other compound material besides
the GaN shown in this example.
[0033] FIG. 7 is a flowchart illustrating a method for forming a
compound semiconductor-on-Si wafer with a thermally soft insulator.
Although the method is depicted as a sequence of numbered steps for
clarity, the numbering does not necessarily dictate the order of
the steps. It should be understood that some of these steps may be
skipped, performed in parallel, or performed without the
requirement of maintaining a strict order of sequence. The method
starts at Step 700.
[0034] Step 702 forms a Si substrate. Step 704 forms a thermally
soft insulator layer overlying the Si substrate. Step 706 forms a
compound semiconductor layer overlying the thermally soft insulator
layer. The compound semiconductor layer may be GaN, GaAs, GaAlN, or
SiC. The thermally soft insulator has a liquid phase temperature
lower than the liquid phase temperatures of Si and the compound
semiconductor.
[0035] In one aspect, Step 705b forms a silicon oxide layer
immediately overlying the thermally soft insulator layer. Step 705f
forms a top Si layer immediately overlying the silicon oxide layer,
and Step 705i forms a lattice mismatch buffer layer interposed
between the top Si layer and the compound semiconductor layer. For
example, the lattice mismatch buffer layer may be a material such
as AlN, InGaN, or AlGaN.
[0036] In one aspect, Step 702 provides a Si handle wafer with a
top surface, and forming the thermally soft insulator layer in Step
704 includes depositing the thermally soft insulator overlying the
Si handle wafer top surface. The thermally soft insulator may have
a flow temperature in the range of about 500.degree. C. to
900.degree. C., where the flow temperature is greater than the
solid phase temperature and less than the liquid phase temperature.
In one aspect, Step 703 thermally oxidizes the handle wafer top
surface, prior to forming the thermally soft insulator layer.
[0037] Some examples of a thermally soft insulator include
boronsilicate glass (BSG), phosphosilicate glass (PSG), and
boronphosphosilicate glass (BPSG). In one aspect, Step 704 deposits
the doped silicate glass material to a thickness in the range of
about 50 to 1000 nanometers (nm). For example, forming BPSG may
include substeps. Step 704a deposits silicate glass, and Step 704b
dopes the silicate glass with phosphorus in the range of about 2 to
4 atomic percentage (at %) and boron in the range of about 3 to 7
at %. Alternately, if PSG is formed, Step 704b dopes the silicate
glass with phosphorus in the range of about 5 to 9 at %. If BSG is
formed, Step 704b dopes the silicate glass with boron in the range
of about 5 to 8 at %.
[0038] In another aspect, Step 705a provides a donor Si wafer with
a top surface, and forming the silicon oxide layer in Step 705b
includes thermally oxidizes the donor wafer top surface. For
example, the thermally oxidized layer may have a thickness in the
range of about 2 to 100 nm. In one aspect, the donor wafer may have
a <111> crystallographic orientation.
[0039] Step 705c implants the donor wafer with hydrogen ions,
forming an implant layer. Step 705d bonds the thermally soft
insulator layer of the handle wafer to the silicon oxide layer of
the donor wafer. Step 705e splits the bonded wafers along the
implant layer, exposing the top Si layer. Then, forming the top Si
layer in Step 705f includes planarizing the top Si layer. In one
aspect, the planarized thickness is in the range of about 5 and 20
nm. In another aspect following the formation of the top Si layer,
Step 705g etches the top Si layer. Step 705h forms Si islands
separated from adjacent Si islands by trenches in the top Si
layer.
[0040] A compound semiconductor-on-Si substrate with a thermally
soft insulator has been provided, along with a corresponding method
of fabrication. Examples of specific layer orderings and materials
have been given to illustrate the invention. Although the invention
has been presented in the context of Si and GaN materials, the
general principles are applicable to the thermal expansion mismatch
between other materials. However, the invention is not limited to
merely these examples. Other variations and embodiments of the
invention will occur to those skilled in the art.
* * * * *