U.S. patent application number 11/628184 was filed with the patent office on 2007-11-15 for direct electron detector.
This patent application is currently assigned to Isis Innovation Limited. Invention is credited to Angus Ian Kirkland, Rudiger Reinhard Meyer.
Application Number | 20070262404 11/628184 |
Document ID | / |
Family ID | 32671203 |
Filed Date | 2007-11-15 |
United States Patent
Application |
20070262404 |
Kind Code |
A1 |
Meyer; Rudiger Reinhard ; et
al. |
November 15, 2007 |
Direct Electron Detector
Abstract
An electron detector (30) for detection of electrons comprises a
semiconductor wafer (11) having a central portion (12) with a
thickness of at most 150 .mu.m, preferably at most 100 .mu.m,
formed by etching an area of a thicker wafer. On opposite sides of
the central portion (12) there are n-type and p-type contacts (16,
31). In operation, a reverse bias is applied across the contacts
(16, 31) and electrons incident on the layer (15) of intrinsic
semiconductor material between the contacts (16, 31) generate
electron-hole pairs which accelerate towards the contacts (16, 31)
where they may detected as a signal. Conductive terminals (24, 32)
contact the contacts (16, 31) and are connected to a signal
processing circuit in IC chips (28, 37) mounted to the
semiconductor wafer (11) outside the active area of the detector
(30). The contacts (16, 31) are shaped as arrays of strips
extending orthogonally on the two sides of the intrinsic layer (15)
to provide two-dimensional spatial resolution. In an alternative
detector (10), there is a single contact (19) on one side to
provide one-dimensional spatial resolution.
Inventors: |
Meyer; Rudiger Reinhard;
(Oxford, GB) ; Kirkland; Angus Ian; (Oxford,
GB) |
Correspondence
Address: |
SALIWANCHIK LLOYD & SALIWANCHIK;A PROFESSIONAL ASSOCIATION
PO BOX 142950
GAINESVILLE
FL
32614-2950
US
|
Assignee: |
Isis Innovation Limited
Ewert House, Ewert Place, Summertown
Oxford
GB
OX2 7SG
|
Family ID: |
32671203 |
Appl. No.: |
11/628184 |
Filed: |
May 24, 2005 |
PCT Filed: |
May 24, 2005 |
PCT NO: |
PCT/GB05/02039 |
371 Date: |
February 12, 2007 |
Current U.S.
Class: |
257/429 ;
257/E21.001; 257/E31.086; 438/57 |
Current CPC
Class: |
H01L 31/115
20130101 |
Class at
Publication: |
257/429 ;
438/057; 257/E21.001; 257/E31.086 |
International
Class: |
H01L 31/115 20060101
H01L031/115; H01L 21/00 20060101 H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 27, 2004 |
GB |
0411926.0 |
Claims
1-22. (canceled)
23. An electron detector for detection of electrons, comprising a
semiconductor wafer having an active area with an array of contacts
on a first side of the active area being one of n-type or p-type
and at least one contact on a second, opposite side of the active
area being the other of n-type or p-type, wherein the thickness of
the active area of the semiconductor wafer is at most 150
.mu.m.
24. The electron detector according to claim 23, wherein the active
area of the semiconductor wafer is formed in a portion of the
semiconductor wafer which is thinner than the remainder of the
semiconductor wafer.
25. The electron detector according to claim 24, wherein said
portion of the semiconductor wafer is etched.
26. The electron detector according to claim 23, wherein said at
least one contact on the second side of the active area comprises a
single contact extending over the active area of the semiconductor
wafer.
27. The electron detector according to claim 26, wherein the
contacts in the array of contacts are shaped as strips.
28. The electron detector according to claim 23, further comprising
conductive terminals contacting respective contacts of the array of
contacts.
29. The electron detector according to claim 23, wherein said at
least one contact on the second side of the active area comprises
an array of contacts, the arrays of contacts on the first and
second sides of the active area having a different arrangement from
each other.
30. The electron detector according to claim 29, wherein the
contacts are shaped as strips extending in different directions on
the first and second sides of the active area of the semiconductor
wafer.
31. The electron detector according to claim 30, wherein the
contacts are shaped as strips extending in orthogonal directions on
the first and second sides of the active area of the semiconductor
wafer.
32. The electron detector according to claim 29, further comprising
conductive terminals contacting respective contacts of both arrays
of contacts.
33. The electron detector according to claim 32, wherein the
semiconductor wafer has vias and the conductive terminals
contacting the array of contacts on the second side of active area
of the semiconductor wafer extend through the vias to allow
connection to be made to all the conductive terminals on the first
side of the semiconductor wafer.
34. The electron detector according to claim 28, further comprising
a signal processing circuit connected to the conductive terminals
and arranged to process signals from the contacts contacted by the
conductive terminals to provide detection of electrons incident on
the active area of the semiconductor wafer.
35. The electron detector according to claim 32, further comprising
a signal processing circuit connected to the conductive terminals
and arranged to process signals from the contacts contacted by the
conductive terminals to provide detection of electrons incident on
the active area of the semiconductor wafer.
36. The electron detector according to claim 34, wherein at least
part of the signal processing circuit is formed in at least one
integrated circuit chip mounted on the semiconductor wafer outside
the active area of the semiconductor wafer.
37. The electron detector according to claim 34, wherein the signal
processing circuit includes amplifiers for amplifying signals from
the contacts contacted by the conductive terminals.
38. The electron detector according to claim 34, wherein the signal
processing circuit includes a split event discrimination circuit
arranged to discriminate between a signal from a single contact and
signals from two adjacent contacts.
39. The electron detector according to claim 35, wherein the signal
processing circuit includes a coincidence detector arranged to
detect coincident signals from overlapping contacts on opposite
sides of the of the active area of the semiconductor wafer.
40. The electron detector according to claim 34, wherein the signal
processing circuit includes a memory arranged to store a count of
detected electrons at different locations across the electron
detector.
41. The electron detector claim 23, wherein the active area of the
semiconductor wafer has a thickness of at most 100 .mu.m.
42. The electron detector according to claim 23, wherein the
semiconductor wafer includes, in at least the active area, a layer
of intrinsic material between the array of contacts on the first
side of the active area and the at least one contact on the second
side of the active area.
43. The electron detector according to claim 23, wherein the
contacts are deposited on the surface of the semiconductor
wafer.
44. The electron detector according to claim 23, wherein the
semiconductor wafer is made of silicon.
45. A method of operating of an electron detector, comprising
providing a semiconductor wafer having an active array of contacts
on a first side of the active area being one of n-type or p-type
and at least one contact on a second, opposite side of the active
area being the other of n-type or p-type, wherein the thickness of
the active area of the semiconductor wafer is at most 150 .mu.m;
and applying a reverse bias across at least one contact on each
side of the semiconductor wafer.
Description
[0001] The present invention relates to a detector capable of
detecting electrons with energies in the range from 100 eV to 5
MeV.
[0002] Detection of electrons with energies in the range from 100
eV to 5 MeV is needed in a number of applications, notably in an
electron microscope, for example a transmission electron microscope
(TEM), or in an electron energy loss spectrometer (EELS). Depending
on the application, it is desirable to achieve high spatial
resolution and in some cases counting of individual electrons
without requiring integration over time.
[0003] Currently, the detector normally used in applications such
as a TEM is an indirect detector consisting of a scintillator
coupled to a charge coupled device (CCD) detector by a fibre-optic
coupling or a lens coupling. An example of such an indirect
detector is disclosed de Ruijter, W. J., "Imaging properties and
application of slow-scan charge-coupled device cameras suitable for
electron microscopy", Micron, 1995. 26: p. 247-275. Electrons
incident on the scintillator cause generation of photons which are
detected by the CCD detector. Such indirect detection has serious
drawbacks for the resolution, especially at electron energies of
200 keV and above. This is because a broad distribution of photons
is generated from a sharp electron beam due to electron and photon
scattering. A particularly deleterious effect is the
back-scattering of electrons into the scintillator from the
supporting fibre-optical plate. This type of event generates a
bright and spot of light far from the incident point of the primary
electron, thereby strongly contributing to the high-frequency noise
while attenuating the high-frequency signal and thereby the high
frequency Detection Quantum Efficiency (which is a measure
comparing the signal-to noise ratio with that of an ideal
detector).
[0004] Additional noise sources in CCD detectors are dark current
noise and read out noise, which become significant at low dose and
short exposure time, respectively. For slow-scan CCD detectors the
beam has to be blanked while the image is read out, which typically
takes 1 s for a 2 k.times.2 k camera. Continuous acquisition and
read out is possible with frame-transfer CCD detectors, but at the
cost of drastically reduced resolution (due to the small active CCD
array) and large readout noise (due to the fast readout).
[0005] Before indirect electron detection with scintillator-coupled
CCD chips became established experiments to directly illuminate a
CCD chip with electrons were carried out as disclosed in Roberts,
P. T. E., J. N. Chapman, and A. M. Macleod, "A CCD-based image
recording-system for the CTEM. Ultramicroscopy", 1982. 8(4): p.
385-396. However, each electron generates so many electron-hole
pairs that the well capacity is reached with a dose of only 40
electrons per pixel. Furthermore, the MOS structures on the CCD
chip are very sensitive to beam damage by charge trapping in the
oxide layer. Finally, at medium and high energies, the lateral
scattering of the electrons severely reduces the spatial
resolution.
[0006] A recent proposal for direct electron detection is a
prototype pixel detector disclosed in Fan, G. Y., et al.,
"ASIC-based event-driven 2D digital electron counter for TEM
imaging", Ultramicroscopy, 1998. 70(3): p. 107-113. The detector
comprises a high-resistivity detector chip bump-bonded to a CMOS
ASIC which is aligned with the active area of the detector chip and
contains an amplifier and counter for each pixel. In this design,
the detector chip is thick enough to completely stop the incident
electrons in order to prevent them from damaging the sensitive CMOS
circuitry below. This again implies severe lateral spreading and
poor spatial resolution.
[0007] It would be desirable to produce a detector which alleviates
some or all of the problems with the current detectors, as
summarised above.
[0008] According to the present invention, there is provided an
electron detector for detection of electrons, comprising a
semiconductor wafer having an active area with an array of contacts
on a first side of the active area being one of n-type or p-type
and at least one contact on a second, opposite side of the active
area being the other of n-type or p-type, wherein the thickness of
the active area of the semiconductor wafer is at most 150
.mu.m.
[0009] In operation, a reverse bias is applied across the contacts
on each side of the semiconductor wafer and electrons incident on
the active area of the semiconductor wafer generate a signal at the
contacts. In particular, incident electrons interact with the
semiconductor material of the wafer to generate electron-hole
pairs. The electrons are accelerated towards the n-type contact(s)
and the holes are accelerated towards the p-type contact(s),
creating a signal which may be detected at either or both contacts.
Thus, the detector provides for direct detection of incident
electrons.
[0010] Use of an array of contacts provides for spatially resolved
detection. The electron or hole generated in the semiconductor
wafer by an incident electron are accelerated to an adjacent
contact thereby creating a signal at that contact. Thus,
discrimination of signals between different contacts resolves the
position of the incident electron. Conveniently, the contacts in
the array are shaped as strips to resolve position in a direction
perpendicular to the strips.
[0011] For the detection of electrons with energies in the range
from 100 eV to 5 MeV, the detector provides a number of advantages
over the indirect type of electron detector using a CCD detector
described above. The detector of the present invention has a
significantly higher detection quantum efficiency and is
sufficiently sensitive to directly detect and count individual
incident electrons without requiring integration over time. This
means that it is capable of time-resolved detection and images can
be obtained at arbitrarily high frame rates without additional
readout noise.
[0012] The detector may include, in the active area, a layer of
intrinsic material between the array of contacts on the first side
of the active area and the at least one contact on the second side
of the active area. In this case, a detector in accordance with the
invention may have a similar construction and operation to the type
of known PIN diode detector used to detect X-rays and high energy
charged particles in particle physics experiments. However, a
detector in accordance with the invention is thinner than such
known PIN diode detectors and, consequently, provides the
significant advantage of high spatial resolution in the detection
of electrons with energies in the range from 100 eV to 5 MeV. The
reasons for this are explained in more detail below.
[0013] Preferably, the active layer of the semiconductor wafer is
formed in a portion of the semiconductor wafer which is thinner
than the remainder of the semiconductor wafer.
[0014] This arrangement of the semiconductor wafer provides for
convenience of manufacture. It is possible to use a semiconductor
wafer produced by a conventional technique which will typically
have a thickness of 300 .mu.m to 600 .mu.m. A portion of the
semiconductor wafer which is to include the active area may be
thinned, for example by etching. In addition, this arrangement of
the semiconductor wafer increases the overall strength of the
detector by the thicker remainder of the semiconductor wafer
strengthening the thinner active area which is inevitably fragile
due to its low thickness.
[0015] To provide for electrical connection to the contacts for the
purpose of receiving the signals generated by incident electrons,
the detector may comprise conductive terminals contacting the
respective contacts of the array(s) of contacts.
[0016] In a first arrangement, said at least one contact on the
second side of the active area comprises a single contact extending
over the active area of the semiconductor wafer.
[0017] With this first arrangement, the detector allows
one-dimensional resolution by discrimination between signals from
respective contacts of the array. Such a one-dimensional detector
may be used for example in an EELS. The signal from the single
contact need not be monitored, thereby providing a significant
advantage of simplifying the construction and manufacture because
signals do not need to be routed from both sides of the
semiconductor wafer.
[0018] In a second, alternative arrangement, said at least one
contact on the second side of the active area comprises an array of
contacts, the arrays of contacts on the first and second sides of
the active area having a different arrangement from each other.
[0019] This second arrangement provides a further degree of
resolution and allows two-dimensional resolution. This is because
the electrons and holes of each pair generated in the semiconductor
wafer by an incident electron is accelerated to the adjacent the
contacts of both arrays on opposite sides of the semiconductor
wafer, thereby creating a simultaneous signal at each of those
adjacent contacts. Accordingly, by detecting coincident signals
from contacts on both sides, a higher degree of resolution is
achieved. Depending on the shape and arrangement of the contacts,
the resolution may be two-dimensional. Such a two-dimensional
detector may be used for example to record images and diffraction
patterns in electron microscopy such as TEM.
[0020] Conveniently, the contacts in each array are shaped as
strips extending in different directions on each side of the active
area of the semiconductor wafer, preferably in orthogonal
directions. Such an arrangement provides resolution in two
dimensions by way of the strips on one side of the semiconductor
wafer resolving the position in the first dimension and the strips
on the other side of the intrinsic resolving the position in the
second dimension.
[0021] Advantageously, the semiconductor wafer has vias and the
conductive terminals contacting the array of contacts on the second
side of active area of the semiconductor wafer extend through the
vias to allow connection to be made to all the conductive terminals
on the first side of the semiconductor wafer. This arrangement
greatly simplifies the routing of the conductive terminals to allow
the signals from the contacts to be monitored
[0022] Preferably, the detector includes a signal processing
circuit connected to the conductive terminals and arranged to
process signals from the contacts contacted by the conductive
terminals to provide detection of electrons incident on the active
area of the semiconductor wafer.
[0023] Advantageously, the signal processing circuit is formed in
at least one integrated circuit chip which is mounted on a surface
of the semiconductor wafer outside the active area of the
semiconductor wafer.
[0024] This location for the signal processing circuit outside the
active area of the detector has the significant advantage that it
is possible to prevent the incident electrons from reaching the
integrated circuit chip(s) in which the signal processing circuit
is formed without interfering with the detection of incident
electrodes in the active area of the semiconductor wafer. For
example, the integrated circuit chip(s) may be arranged at a
sufficient distance from the active area at which the incident
electrons are directed, or the integrated circuit chip(s) may be
protected by an appropriate shield. Otherwise, electrons having
energies in the range from 100 eV to 5 MeV, particularly at the
higher end of this range, would damage the integrated circuit
chip(s).
[0025] To allow better understanding, embodiments of the present
invention will now be described by way of non-limitative example
with reference to the accompanying drawings in which:
[0026] FIG. 1 is a schematic plan view of a first electron
detector;
[0027] FIG. 2 is a detailed plan view of a portion of the first
electron detector within the dashed outline in FIG. 1;
[0028] FIG. 3 is a cross-sectional view of the first electron
detector taken along line III-III in FIG. 2;
[0029] FIG. 4 is a cross-sectional view of the first electron
detector taken along line IV-IV in FIG. 2;
[0030] FIG. 5 is a schematic plan view of a second electron
detector;
[0031] FIG. 6 is a detailed plan view of a portion of the second
electron detector within the dashed outline in FIG. 5;
[0032] FIG. 7 is a detailed plan view of a portion of the second
electron detector within the dotted outline in FIG. 5 viewed from
the opposite side from FIGS. 5 and 6;
[0033] FIG. 8 is a cross-sectional view of the second electron
detector taken along line VIII-VIII in FIG. 6;
[0034] FIG. 9 is a cross-sectional view of the second electron
detector taken along line IX-IX in FIG. 6;
[0035] FIG. 10 is an image of a Monte-Carlo simulation for 300 keV
electrons incident on a semiconductor wafer of thickness 300
.mu.m;
[0036] FIG. 11 is an image of a Monte-Carlo simulation for 300 keV
electrons incident on a semiconductor wafer of thickness 50
.mu.m;
[0037] FIG. 12 is a diagram of the signal processing circuit for
the second electron detector;
[0038] FIG. 13 is a three-dimensional surface plot of the
probabilities of detection of an electron by a single pixel and
jointly by the single pixel and adjacent pixels;
[0039] FIG. 14 is a three-dimensional surface plot of the effective
probability of detection of an electron for the case that split
event discrimination is employed; and
[0040] FIG. 15 is a graph of the detection quantum efficiency of
first and second detector and of a CCD camera against spatial
frequency.
[0041] A first electron detector 10 in accordance with the present
invention is illustrated in FIGS. 1 to 4. The first detector 10 has
an arrangement of contacts to provide one-dimensional
detection.
[0042] The first detector 10 comprises a semiconductor wafer 11 of
intrinsic semiconductor material having a high resistivity. For
convenience of manufacture, the semiconductor wafer 11 is made of
silicon. As an alternative, any other semiconductor material could
be used. Semiconductor materials other than silicon may offer
better detection properties.
[0043] A central portion 12 in approximately the centre of the
semiconductor wafer 11 is thinner than the remaining, peripheral
portion 13 of the semiconductor wafer 11. The peripheral portion 13
strengthens the central portion 12 which is relatively fragile.
[0044] The semiconductor wafer 11 may be formed using conventional
techniques so that it has an original thickness in the range from
300 .mu.m to 600 .mu.m, this being the thickness of the peripheral
portion 13. The central portion 12 is formed by removing a portion
of the semiconductor wafer 11. Preferably, the central portion 12
is formed by etching which has the advantage of allowing precise
control of the thickness of the central portion 12 by selection of
the etching time. Such etching causes the edges 14 of the central
portion 12 to be tapered. The thickness of the central portion 12
is at most 150 .mu.m, preferably at most 100 .mu.m. The detection
process and reasons for this thickness limit are discussed further
below.
[0045] On a first side of the semiconductor wafer 11 (uppermost in
FIGS. 3 and 4), the first detector 10 is provided with an array of
contacts 16 arranged inside the central portion 12. The contacts 16
are shaped as strips extending parallel to one another. The
contacts 16 are arranged in two groups on opposite sides of the
central portion 12 of the semiconductor wafer 11, the groups being
separated by a gap 23 running perpendicular to the direction in
which the contacts 16 extend.
[0046] The contacts 16 are implanted in a first surface 17 of the
semiconductor wafer 11 and are disposed below an oxide layer 18
formed on the first surface 17 of the semiconductor wafer 11 for
insulation. The oxide layer 18 extends across the entire
semiconductor wafer 11, that is over both the central portion 12
and the peripheral portion 13. The oxide layer 18 is an oxide of
the material of the semiconductor wafer 11, for example silicon
oxide. As an alternative, the oxide layer 18 could be replaced by
any insulating layer for example a nitride or indeed any other
insulating dielectric.
[0047] On the second side of the semiconductor wafer 11 opposite
from the array of contacts 16 (lowermost in FIGS. 3 and 4), the
first detector 10 is provided with a further, single contact 19
facing the array of contacts 16 and extending across at least the
area of the array of contacts 16. For ease of manufacture, the
single contact 19 extends across the entire semiconductor wafer 11
including both the central portion 12 and the peripheral portion
13. The further contact 19 is implanted in the second surface 20 of
the semiconductor wafer 11 opposite to the first surface 17.
[0048] The contacts 16 and 19 are both formed of doped
semiconductor material, The contacts 16 and 19 are of an opposite
type from each other, that is either (1) the array of first
contacts 16 are n-type and the contact 19 is p-type or (2) the
array of contacts 16 are p-type and the contact 19 is n-type. The
material of the semiconductor wafer 11 between the contacts 16 and
19 is a layer 15 of intrinsic semiconductor material which in use
interacts with electrons for detection.
[0049] The first detector 10 is further provided with an array of
conductive terminals 24, each contacting a respective contact 16 of
the array of contacts 16. The conductive terminals 24 are deposited
on the oxide layer 18 and extend through a window in the oxide
layer 18 formed by etching to contact the respective contact 16.
Each conductive terminal 24 extends along the entire length of the
respective contact 16 and extends from the respective contact
across the edge of the central portion 12 to the peripheral portion
13 of the semiconductor wafer 11. Also, on the outermost surface of
the contact 19, there is provided a conductive terminal 29.
[0050] The first side of the semiconductor wafer 11 is also
provided with a set of guard contacts 21 each in the shape of a
ring enclosing both the active area of the semiconductor wafer 11
adjacent the contacts 16 in the central portion 12 and also
integrated circuit chips 28 which are described further below. The
guard contacts 21 are implanted in the first surface 17 of the
semiconductor wafer 11 and are disposed below the oxide layer 18. A
set of guard terminals 22, each contacting a respective guard
contact 21. The guard terminals 22 are deposited on the oxide layer
18 and extend through a window in the outside layer 18 formed by
etching to contact the respective contact 21. Each guard terminal
21 extends over the entirety of the respective contact 21. In
general, there may be two or more guard contacts 21. The individual
guard contacts 21 and guard terminals 22 are distinguished by the
lower case letters a, b and c. The innermost guard contact 21a
includes fingers 25 interdigitating with the end of the conductive
terminal 24, the fingers 25 extending up to the array of contact 16
without overlapping.
[0051] The conductive terminals 24 are connected to a group of
integrated circuit chips 28 mounted on a surface of the
semiconductor wafer 11 in the peripheral portion 13. The integrated
circuit chips 28 are connected to the terminals 24 by conventional
bump-bonding technology. The integrated circuit chips 28 are
desirably CMOS ASICs. The integrated circuit chips 28 provide some
elements of a signal processing circuit for processing signals from
the array of contacts 16 to provide detection of incident
electrons, as described in detail below. As a result of the
integrated circuit chips 28 being arranged outside the active area
of the first detector 10 which is within the central portion 12,
the integrated circuit chips 28 may be protected from electrons
incident on the active area of the first detector 10, either by
limiting beam of the incident electrons and/or providing the
integrated circuit chips 28 with appropriate shielding.
[0052] On the first side of the semiconductor wafer 11, deposited
on the oxide layer 18, are contact terminals 27 connected to and
extending outwardly from the integrated circuit chips 28. The
contact terminals 27, the guard terminals 22 and the conductive
terminal 29 contacting the contact 19 on the second side of the
semiconductor wafer 11 are all connected to an external circuit 26.
The external circuit 26 provides bias voltages for the array of
contacts 16 through some of the contact terminals 27, and also
receives digital output signals from the integrated circuit chips
28 through others of the contact terminals 27. In addition, the
external circuit 26 provides bias voltages for the further contact
19 and the guard contacts 21 through the conductive terminal 29 and
the guard terminals 22, respectively.
[0053] In the first detector 10, the signals received by the
contact 19 on the second side of the semiconductor wafer 11 are not
monitored. Consequently, it is not necessary to make any electrical
connection between the contact 19 and the signal processing
circuit. This greatly simplifies the structure and hence the
manufacture of the first detector 10.
[0054] A second detector 30 in accordance with the present
invention is illustrated in FIGS. 5 to 9. The second detector 30
has basically the same construction as the first detector 10 except
for some changes in the arrangement of contacts so as to provide
two-dimensional detection. For brevity, in respect of elements
which are common between the first detector 10 and the second
detector 30, the same reference numerals will be used and a
description thereof will not be repeated.
[0055] The second detector 30 has a semiconductor wafer 11 with the
same construction as in the first detector 10.
[0056] The second detector 30 also has an array of contacts 16 on
the first side of the semiconductor wafer 11 having the same
construction and arrangement as in the first detector 10. However,
the second detector 30 has contacts 31 on the second side of the
semiconductor wafer 11 which are different from the contact 19 of
the first detector 10. In particular, on the second side of the
semiconductor wafer 11, the second detector 30 is provided with a
further array of contacts 31 shaped as strips extending parallel to
one another. The further array of contacts 31 are shown in FIG. 5
in order to illustrate their relationship with the array of contact
16, although in fact the further array of contact 31 are formed on
the second side of the semiconductor wafer 11 as best seen in FIG.
7 to 9. The contacts 31 of the further array are implanted in the
second surface 20 of the semiconductor wafer 11 and are disposed
below an oxide layer 38 formed on the second surface 20 of the
semiconductor wafer 11. The oxide layer 38 extends across the
entire semiconductor wafer 11, that is over both the central
portion 12 and the peripheral portion 13. The oxide layer 38 is an
oxide of the material of the semiconductor wafer 11, for example
silicon oxide.
[0057] The further array of contacts 31 have the same arrangement
as the array of contacts 16 on the first side of the semiconductor
wafer 11 but extending in a direction orthogonal to the direction
in which the array of contacts 16 extend. The array of contacts 16
and the further array of contacts 31 face one another and extend
across substantially the same area of the semiconductor wafer 11
which area, in use, acts as the active area of the second detector
30.
[0058] Similarly, the second detector 30 has further conductive
terminals 32 each contacting a respective contact 31 of the further
array. The further conductive terminals 32 are deposited on the
oxide layer 38 and extend through a window in the oxide layer 38
formed by etching to contact the respective contact 31. Each
further conductive terminal 33 extends along the entire length of
the respective contact 31 and beyond the respective contacts 31
into the area of the central portion 12 outside the active area. In
addition, the further conductive terminals 32 are arranged as
follows to allow a connection to be made to all the conductive
terminals 24 and 32 on the same side of the semiconductor wafer
11.
[0059] The semiconductor wafer 11 is formed with vias 33 extending
through the semiconductor wafer 11 within the central portion 12
but outside the active area of the second detector 30 and outside
the guard contacts 21. A separate via 33 is aligned with each one
of the further contacts 33. During manufacture, the vias 33 are
formed by etching and so have a tapered inner surface 34. The oxide
layers 18 and 38 on each side of the semiconductor wafer 11 are
interconnected by extending around the tapered inner surface 34 of
the vias 33.
[0060] The further conductive terminals 32 each have a connecting
portion 35 deposited on the oxide layers 18 or 38. The connecting
portions 35 extend from the respective conductive terminals 32,
through the vias 33 and onto the first side of the semiconductor
wafer 11 on which the further array of contacts 16 are formed.
Furthermore, the further conductive terminals 32 each include an
arm 36 extending from a respective connecting portion 35, over the
central portion 12 of the semiconductor wafer 11 and onto the
peripheral portion 13 of the semiconductor wafer 11.
[0061] The arms 36 of the further conductive terminals 32 are
connected to further integrated circuit chips 37 mounted on the
first surface 17 of the semiconductor wafer 11 in the peripheral
portion 13. The integrated circuit chips 37 are connected to the
terminals 24 by conventional bump-bonding technology. The
integrated circuit chips 37 are desirably CMOS ASICs. Thus, the
formation of the further conductive terminals 32 through the vias
33 allows the connection to be made to both arrays of contacts 16
and 31 on the same side of the semiconductor wafer 11, i.e. the
first side 17. In the second detector 30, elements of the signal
processing circuit are formed in the further integrated circuit
chips 37 connected to the further conductive terminals 32, as well
as the integrated circuit chips 28 connected to the first
conductive terminals 24.
[0062] On the second side of the semiconductor wafer 11, deposited
on the oxide layer 18, are further contact terminals 39 connected
to and extending outwardly from the further integrated circuit
chips 37. The further contact terminals 39 are additionally
connected to the external circuit 26.
[0063] Next, the operation of the two detectors 10 and 30 will be
described.
[0064] To use the detectors 10 and 30, a reverse bias is applied by
a source (not shown) across the contacts 16 and 19, or across the
contacts 16 and 31, on opposite sides of the semiconductor wafer
11. Under this reverse bias, the layer 15 of intrinsic material in
the active area of the detector 10 or 30 becomes depleted of charge
carriers.
[0065] Bias voltages are also applied to the guard contacts 21a,
21b, and 21c as follows. The innermost guard contact 21a is held at
the same potential as the contact 16 on the first side of the
semiconductor wafer 11. This is to prevent leakage current
generated outside the active area of the semiconductor wafer 11
from reaching the contacts 16. The outermost guard contact 21c is
held at the same potential as the contacts 19 or 31 on the second
side of the semiconductor wafer 11. This is to prevent leakage
current across the sawn die edges of the semiconductor wafer 11.
The intermediate guard contact 21b is held at a potential
intermediate that of the innermost and outermost contact 21a and
21c. Further intermediate guard contacts 21b could be used, if
desired.
[0066] When electrons with energies in the range from 100 eV to 5
MeV (at least) are incident on the active area of the detector 10
or 30, the electrons interact with the layer 15 of intrinsic
material and generate electron-hole pairs at a rate of one pair per
3.65 eV (in silicon) of energy lost by the electrons. Thus, a large
number of electron-hole pairs are generated. For example, in the
case of an active area of the semiconductor wafer within the
central portion 12 having a thickness of 50 .mu.m, electrons may
lose an energy of around 15 keV which equates to the generation of
around 4,000 electron-hole pairs.
[0067] In the electric field imposed by the reverse bias, the holes
are accelerated towards the adjacent p-type contact (which may be
any of the contacts 16, 19 or 31 depending on the specific
construction) and similarly the electrons are accelerated towards
the adjacent n-type contact (which again may be any of the contacts
16, 19 or 33). The electrons and holes reaching the respective,
adjacent contact 16 or 31 of the arrays of contacts 16 and 31
generate a signal which passes via the respective conductive
terminal 24 or 32 to the signal processing circuit. These signals
are processed by the signal processing circuit to provide detection
of the electrons incident on the detector 10 or 30. Accordingly,
the active area of the first detector 10 is the area of the layer
15 of intrinsic material which is adjacent the contacts 16 and,
similarly, the active area of the second detector 30 is the area of
the layer 15 of intrinsic material which is adjacent the contacts
16 and 19.
[0068] As incident electrons create a signal on the adjacent ones
of the contacts 16 and 31, discrimination of the signals from
different contacts 16 in the array of contacts 16 and different
contacts 31 in the further array of contacts 31 provide for spatial
resolution in the detection result.
[0069] In the case of the first detector 10, the array of contacts
16 provide spatial resolution in a single dimension, that is
perpendicular to the direction in which the contacts 16 extend. The
arrangement of the contacts 16 in two separate groups provides for
limited spatial resolution in the perpendicular direction and has
the advantage of facilitating alignment of the first detector 10
with a beam of incident electrons.
[0070] In the case of the second detector 30, the array of contacts
16 provides spatial resolution in one direction and the further
array of contacts 31 provides resolution in an orthogonal
direction, thereby providing two-dimensional spatial resolution. Of
course, other arrangements for the contacts 16 and 31 could
similarly provide spatial resolution, but the particular
arrangement of the contacts 16 and 31 in the described embodiment
are particularly convenient and simple to implement.
[0071] It has been appreciated that the relatively small thickness
of the semiconductor wafer 11 in the active area inside the central
portion 12 provides significant advantages as compared to the use
of an equivalent structure having a typical thickness for a
semiconductor wafer manufactured using conventional techniques in
the range from 300 .mu.m to 600 .mu.m. In particular, the spatial
resolution is increased significantly, because the electron
trajectories undergo a significantly lower spatial spread, most
electron trajectories being relatively straight. This has been
demonstrated using a detailed Monte-Carlo simulation to predict the
performance of the detector. The results of such a simulation is
shown in FIGS. 10 and 11. Both FIGS. 10 and 11 show a Monte-Carlo
simulation for 50 trajectories of a 300 keV electron in silicon.
FIG. 10 illustrates the case that the thickness of the intrinsic
layer is 300 .mu.m which is not in accordance with the present
invention but is around the low end of the range of typical
thicknesses for a wafer of silicon manufactured using conventional
techniques. FIG. 11 illustrates the case that the semiconductor
wafer 11 has a thickness of 50 .mu.m in the active area and is
therefore in accordance with the present invention.
[0072] From FIGS. 10 and 11, it is clear that the trajectories for
the thick semiconductor wafer 11 illustrated in FIG. 10 undergo a
large lateral spreading, whereas for the example of the present
invention illustrated in FIG. 11 the spreading is much less and
most electrons pass through the detector on a relatively straight
path. As electron-hole pairs are generated along substantially the
entire trajectory, the large lateral spreading in the thick case
illustrated in FIG. 10 would preclude a resolution of better than
around 100-200 .mu.m. In contrast, in the example of the present
invention illustrated in FIG. 11, a much improved resolution is
obtained.
[0073] Accordingly, the present invention involves the use of an
semiconductor wafer 11 having a thickness in the active area of at
most 150 .mu.m. It is expected that most useful devices would have
a thickness of at most 100 .mu.m. Surprisingly, detectors having
such a thickness produce a sufficient signal to allow detection of
individual electrons without requiring integration over time.
[0074] The thickness of the active area of the semiconductor wafer
11 can be reduced to increase the resolution. As to a minimum
thickness, in principle the thickness of the active area of the
semiconductor wafer 11 can be reduced as much as is desired, but
there are two practical considerations to take into account. The
first consideration is to maintain sufficient strength in the
active area of the semiconductor wafer 11, as thin semiconductor
layers become very fragile. However, the higher thickness of the
peripheral portion 13 does reinforce the central portion 12. The
second consideration is to obtain a signal of sufficient magnitude
as the number of electron-hole pairs generated decreases with the
thickness of the active area of the semiconductor wafer 11. Based
on these considerations, it is expected that most detectors will
have a thickness of at least 20 .mu.m, but lower thicknesses could
nonetheless be used provided the increased fragility is acceptable
and provided a sufficiently sensitive signal processing circuit is
used.
[0075] As to the dimensions of the contacts 16 and further contacts
31, the pitches of the array of contacts 16 and the further array
of contacts 31 may be chosen to match or be slightly greater than
the resolution resulting from the spreading of electron
trajectories in the semiconductor wafer 11. The spreading will
depend on the thickness of the active area of the semiconductor
wafer 11 and the semiconductor material chosen. The spreading may
be predicted using a simulation, such as a Monte-Carlo simulation
of the type shown in FIG. 11, or alternatively may be determined
experimentally. It is expected that for most practical devices the
pitch would be at most 100 .mu.m, or more usually at most 50 .mu.m,
a typical value being around 20 .mu.m. It is expected that the
pitch will be at least 10 .mu.m.
[0076] As to the width of the contacts 16 and 31, for a given pitch
in the array of contacts 16 or 31, there is a balance between (a)
decreasing the width of the contacts 16 or 31 which is desirable to
decrease the capacitance, and (b) increasing the width of the
contacts 16 or 31 which is desirable to decrease the resistance of
the contacts 16 or 31. In fact, it is expected that the optimal
ratio of the width of the contacts 16 or 31 to the gap between the
contacts 16 or 31 will be around 1:1.
[0077] In the detectors 10 and 30, the contacts 16, 19 and 31 are
implanted in the respective surfaces 17 and 20 of the semiconductor
wafer 11. However, as an alternative, contacts having basically the
same arrangement and effect could be deposited or could be formed
as an integral part of the semiconductor wafer by conventional
techniques. Similarly, as an alternative to the simple PIN
(p-intrinsic-n) diode construction of the detector 10, more
complicated constructions could be used to achieve the detection in
the same way. One possibility is to use an avalanche diode
construction which has a similar construction to the detector 10
except for an additional avalanche layer adjacent the contacts 19
or 31 on the rear side of the detector. The avalanche layer is of
opposite type from the adjacent contact.
[0078] The first and second detectors 10 and 30 may be manufactured
using conventional semiconductor techniques which will now be
described.
[0079] To manufacture the first detector 10, firstly the
semiconductor wafer 11 is produced using conventional techniques.
Initially the semiconductor wafer 11 has the same thickness over
its entire area, typically 300 .mu.m to 600 .mu.m. Both surfaces of
the semiconductor wafer 11 are polished and oxidised to produce the
oxide layer 18 and also an oxide layer on the second side of the
semiconductor wafer, both with a thickness of around 1-2 .mu.m. The
oxide layer on the second side of the semiconductor wafer 11 in the
desired area of the central portion 12, is removed by
lithographically providing an etchback mask and plasma etching.
Subsequently, the central portion 12 is formed by TMAH etching of
the exposed material of the semiconductor wafer 11. Precise control
of the etching time allows control of the thickness of the central
portion 12. For example, if the original thickness of the
semiconductor wafer 11 is 350 .mu.m and the desired thickness of
the central portion 12 is 50 .mu.m, then at an etching rate of 0.38
.mu.m/min, this takes around 11 hours.
[0080] Next a mask is lithographically formed on the oxide layer 18
on the first side of the semiconductor wafer 11 to expose the
desired shape of all the contacts on that side, namely form the
array of contacts 16 and the guard contacts 21. Then a plasma etch
is performed to remove the exposed portions of the oxide layer 18
leaving windows. The remaining oxide on the second side of the
semiconductor wafer 11 is also removed by plasma etching.
[0081] Next, the contacts 16 and 19 are formed by implanting
appropriate dopants. On the first side of the semiconductor wafer
11, the implantation occurs through the windows formed in the oxide
layer 18 to form the array of contacts 16 and the guard contacts
21.
[0082] After performing rapid thermal annealing, the entire surface
on both sides of the semiconductor wafer 11 is metalised, typically
with a thickness of around 2 .mu.m on the first side and a
thickness of 1 .mu.m on the second side. The deposited metal layer
on the second side constitutes the conductive terminal 29. On the
first side of the semiconductor wafer 11, the deposited metal layer
is lithographically plasma etched to provide the various terminals
on the first side of the semiconductor wafer into the desired
shape.
[0083] In summary, the manufacture of the first detector 10 may be
summarised by the following process flow: [0084] 0 FZ High-Res
n-type 4'' wafer, both sides polished [0085] 1 Wet oxidation, 1-2
.mu.m, both sides [0086] 2 Lithography with etchback mask (back
side) [0087] 3 Plasma etch exposed oxide layer on back side [0088]
4 TMAH etchback to desired thickness of active area [0089] 5
Lithography with oxide mask (front side) [0090] 6 Plasma etch
exposed oxide layer on front side [0091] 7 Plasma etch remaining
oxide layer on back side [0092] 8 Strip resist [0093] 9 Grow thin
protective oxide layer on both sides [0094] 10 Front side contact
implant (front side) [0095] 11 Back side contact implant [0096] 12
Rapid Thermal Annealing [0097] 13 Short oxide etch (50-100 nm)
[0098] 14 Metal deposition on front side (2 .mu.m) [0099] 15 Metal
deposition on back side (1 .mu.m) [0100] 16 Resist on front side
[0101] 17 Lithography with metal mask (front side) [0102] 18 Plasma
etch exposed A1 on front side and remove resist
[0103] The second detector 30 may be manufactured using an
equivalent process with an additional etching step to form the vias
33 and with additional steps to form the further array of contact
31 on the second side of the semiconductor wafer 11 in the same
manner as forming the array of contacts 16 on the first side of the
semiconductor wafer 11. In this case, for the lithography steps on
the second side of the semiconductor wafer 11, the photo-resistive
mask is applied by spraying rather than by a spin-on technique in
order to ensure proper coverage over the different heights of the
central portion 12 and the peripheral portion 13. The process flow
for the second detector 30 may therefore be summarised as follows.
[0104] 1 Thermal oxidation (both sides) [0105] 2 Spin on resist
front side [0106] 3 Spin on resist back side [0107] 4
Photolithography via mask front side [0108] 5 Photolithography
cavity mask back side [0109] 6 Develop resist [0110] 7 Etch exposed
oxide [0111] 8 TMAH etch to form central portion 12 from the back
side and vias 33 from the front side [0112] 9 Ion implantation of
p-type counter dopant on back side [0113] 10 Etch remaining oxide
[0114] 11 Thermal oxidation (both sides) [0115] 12 Spin on resist
front side [0116] 13 Spray on resist back side [0117] 14
Photolithography front strip mask (front side) [0118] 15
Photolithography back strip mask (back side) [0119] 16 Develop
resist [0120] 17 Etch exposed oxide to form windows [0121] 18 Ion
implantation, p-type, front side [0122] 19 Ion implantation,
n-type, back side [0123] 20 Thermal annealing to drive in all
implants [0124] 21 Deposit metal on front side [0125] 22 Deposit
metal on back side [0126] 23 Spin on resist front side [0127] 24
Spray on resist back side [0128] 25 Photolithography front metal
mask [0129] 26 Photolithography back metal mask [0130] 27 Develop
resist [0131] 28 Etch exposed metal (both sides) [0132] 29
Passivate (both sides) [0133] 30 Spin on resist front side [0134]
31 Photolithography window mask front side [0135] 32 Develop resist
[0136] 33 Window etch front side
[0137] The counter-dopant implanted in step 9 avoids a conductive
surface channel between the further contacts 31 on the second side.
It is similar to the channel-stop implant in CMOS technology. The
dose used for the n-strip implantation in step 19 is larger than
that in step 9 to ensure that the strips formed are n-type,
surrounded by moderately p-type material.
[0138] The signal processing circuits for the detectors 10 and 30
will now be described. It is most convenient first to describe the
signal processing circuit for the second detector 30 which is
illustrated in FIG. 12. The signal processing circuit is formed in
the integrated circuit chips 28, the further integrated circuit
chips 37 and the external circuit 26 as shown in dashed outline in
FIG. 12.
[0139] In FIG. 12, the semiconductor wafer 11 is shown
schematically as an array of diodes 41. Each diode 41 represents a
portion of the continuous layer 15 of semiconductor material
between a respective contact 16 and a respective contact 31 which
effectively constitutes a diode. The conductive terminals 24
contacting the contacts 16 and the further conductive terminals 32
contacting the contacts 31 are also shown in FIG. 12. The elements
outside the semiconductor wafer 11 in FIG. 12 constitute the signal
processing circuit. All the elements of the signal processing
circuit may be formed in the integrated circuit chips 28 and 37, or
alternatively some of the elements may be formed in a separate
component connected to the integrated circuit chips 28 and 37
through an output terminal 58.
[0140] The conductive terminals 24 and 32 are connected to
respective amplifier circuits 42 and 43. Each amplifier circuit 42
and 43 includes a plurality of amplifiers 44 each connected to a
respective conductive terminal 24 or 32. The amplifiers 44 amplify
the signal from a respective contact 16 or 31 and are arranged to
convert received charge pulses above a certain threshold value into
a digital output signal. For example, each amplifier 44 may be
formed by an amplifier stage which amplifies the received signal
and a threshold detection stage which outputs a digital output
signal representing whether the received signal is above or below
the threshold.
[0141] The signals output from the amplifier circuits 42 and 43 are
supplied to respective split event discriminations circuits 45 and
46 arranged to discriminate between (1) a signal from a single
contact 16 or 31, caused by detection of an electron on a portion
of the layer 15 of semiconductor material aligned with a respective
contact 16 or 31, and (2) signals from both of two adjacent
contacts 16 or 31, caused by an electron being incident on a
portion of the layer 15 of semiconductor material intermediate two
adjacent contacts 16 or 31.
[0142] In particular, the split event discrimination circuits 45
and 46 is constituted by main AND gates 47 and intermediate AND
gates 48.
[0143] The signal from each contact 16 or 31 is supplied to an
input of a respective main AND gate 47 associated with that contact
16 or 31. In addition, inverting inputs of each given main AND gate
47 are supplied with the signal from the two contacts 16 or 31
adjacent the contact 16 or 31 associated with the given main AND
gate 47 (except of course for the contacts 16 and 31 on the edge of
the arrays). Accordingly, the main AND gates 47 output a signal
when the associated contact 16 or 31 outputs a signal indicating a
detection event, but neither of the adjacent contacts 16 or 31
output such a signal indicating a detection event.
[0144] In addition, the signals from each pair of adjacent contacts
16 or 31 are supplied to an input of a respective intermediate AND
gate 48. Accordingly, the intermediate AND gates 48 output a signal
when both of two adjacent contacts 16 or 31 output a signal
indicating a detection event.
[0145] Therefore, the overall effect of the split event
discrimination circuits 45 and 46 is to discriminate between (1) a
signal from a single contact 16 or 19 detected as a signal output
from an associated main AND gate 47, and (2) signals from two
adjacent contacts 16 or 31 detected as a signal output from an
intermediate AND gate 48. Thus, the use of the split event
discrimination circuits 45 and 46 increases the spatial resolution
by combining information from adjacent contacts 16 or 31. When an
electron is incident on a portion of the layer 15 of semiconductor
material intermediate adjacent contacts 16 or 31, the charge is
distributed between those two adjacent contacts 16 or 31. The split
event discrimination circuits exploit this for extra resolution.
This extra resolution is only possible because the detector 10 is
arranged to count electrons rather than collect charge.
[0146] In addition, the split event discrimination circuits 45 and
46 have the benefit of improving sensitivity. This benefit is
illustrated in FIGS. 13 and 14 which are three-dimensional surface
plots of the probability of detection of an electron as a function
of the incident position relative to the pixel boundaries shown in
thick black lines. FIG. 13 has four curves, one for the probability
of detection in a single pixel alone, one for joint detection by
the single pixel and an adjacent pixel in the z-direction, one for
joint detection by the single pixel and an adjacent pixel in the
y-direction, and one for joint detection by the single pixel and
the diagonally adjacent pixel. In the case that no split event
discrimination circuit is provided, effectively only the single
pixel is used. Thus the point spread function is relatively broad,
as shown by the curve for the single pixel alone, the information
in the other curves being effectively lost. In contrast, FIG. 14
illustrates the case that the split event discrimination circuits
45 and 46 are present. It can be seen from FIG. 13 that for some
incident positions there is a probability of detection on two
adjacent pixels and thus as shown in FIG. 14, when a split event
discrimination circuit is used, the point spread function is
sharper than that of an ideal independent pixel which is
illustrated by the horizontal plane in FIG. 14. In fact, the point
spread function is sharper than the physical pixel size defined by
the pitch of the contacts 16 and 31. As the number of pixels is
effectively twice the number of contacts 16 or 31 in the particular
array of contacts 16 or 31, the resultant image contains the
information beyond the conventional Nyquist limit.
[0147] Whilst the particular logic circuit of the split event
discrimination circuits 45 and 46 described above is preferred for
simplicity, similar effects can be achieved by other logic
circuits.
[0148] The signals from the split event discrimination circuits 45
and 46 are supplied to respective binary encoders 49 and 50 which
convert the logical signal output by the split event discrimination
circuits 45 and 46 into an address representing the one-dimensional
position of the detection event along the respective array of
contacts 16 or 31. In addition, each binary encoder 49 or 50
generates an event signal when any detection event is detected and
a veto signal when more than one detection event is detected
simultaneously.
[0149] The signals from both binary encoders 49 and 50 are supplied
to a coincidence detector 51. The signals from one of the binary
encoders 50 are supplied to the coincidence detector 51 through a
coupling circuit 52 which decouples the absolute potential of the
two binary encoders 49 and 50, the absolute potentials being
different due to the reverse bias applied across the contacts 16
and 31.
[0150] The coincidence detector 51 detects when signals from the
array of contacts 16 are coincident in time with signals from the
array of contacts 31. Such coincidence is detected by monitoring
the two event signals from the two binary encoders 49 and 50. On
detecting such coincidence signals, the coincidence detector 51
outputs an event signal, together with the pixel number of the
pixel representing the address of the pixel in two dimensions
representing the position in both the arrays of contacts 16 and
31.
[0151] However, the coincidence detector 51 produces no output when
it receives a veto signal from either one of the binary encoders 49
or 50 indicating that more than one event signal has been
simultaneously detected. The reason is that it is difficult to
resolve the position in the case of simultaneous detection of two
electrons, because there are various possible positions
corresponding to different combinations of the contacts of contacts
16 and 31. Such rejection prevents the occurrence of errors in the
detected position at the expense of reducing the detection
efficiency.
[0152] The signals from the coincidence detector 51 are supplied to
a FIFO (first-in-first-out) buffer 53. The pixels addresses stored
in the FIFO buffer 53 are supplied to the address input of a frame
memory 54. The frame memory is preferably a fast (e.g 200 MHz)
pipelined Zero Bus Turnaround Static Random Access Memory which can
handle event rates of up to 100.times.10.sup.6 events per second.
An incrementor 55 is connected to the data input/output of the
frame memory 54 to cause the pixels in the frame memory 54
corresponding to the detection event to be incremented. As a
result, the frame memory 54 stores a count of the detected
electrons at the respective pixels identified by the pixel
addresses.
[0153] The frame memory 54 contain several image banks so that a
preceding frame may be read out while a later frame is being
accumulated.
[0154] To provide for readout of the stored images, the signal
processing circuit has a read-out address generator 56 which
incrementally reads out each address of a frame. The addresses from
the read-out generator 56 and the FIFO buffer 53 are multiplexed
together in an address multiplexer 57 before supply to the address
input of the frame memory 54. The signal read out from the frame
memory 54 is supplied to the output terminal 58 which may be formed
on the surface of the semiconductor wafer 11.
[0155] In the signal processing circuit shown in FIG. 12: the
amplifier circuit 42, the split event discrimination circuit 45 and
the binary encoder 49 are arranged in the integrated circuit chips
28; the amplifier circuit 43, the split event discrimination
circuit 46, the binary encoder 50 and the coupling circuit 52 are
arranged in the further integrated circuit chips 37; and the
coincidence detector 51 and elements downstream thereof are formed
in the external circuit 26, preferably in a field programmable gate
array. As an alternative, all the signal processing circuit could
be formed in the integrated circuit chips 28 and 37 mounted on the
semiconductor wafer 11.
[0156] The signal processing circuit for the first detector 10 is
the same as for the second detector 30 as shown in FIG. 12 and
described above, except that the amplifier circuit 43, the split
event discrimination circuit 46, the coupling circuit 52 and the
coincidence detector are omitted because the signal from the single
contact 19 on the second side of the semiconductor wafer 11 is not
monitored. In this case, another alternative is to connect counter
circuits to directly count events detected on each contact 16,
which alternative has the advantage of providing a high count
rate.
[0157] The detectors 10 and 30 described above are primarily
intended to detect electrons having an energy greater than 10 keV,
which is a typical energy for electrons detected in a transmission
electron microscope (TEM). In other applications it is desirable to
detect electrons below 10 keV, for example electrons which are
back-scattered. In the low part of the range below 10 keV,
particularly approaching 100 eV, there may be insufficient
sensitivity for detection. However, it is expected that the
sensitivity may be improved to achieve sufficient sensitivity by
taking measures such as (a) using an alternative semiconductor
construction such as an avalanche diode construction mentioned
above; (b) measuring the sensitivity of the amplifiers 44 and/or
(c) operating at low temperatures to reduce background noise.
Subject to this proviso about the low part of the range, the
detectors 10 and 30 are capable of detecting electrons with an
energy in the range from 100 eV to 5 MeV. They are sufficiently
sensitive to directly detect and count incident electrons without
requiring integration over time. As such the detectors 10, 30 can
be used in any application requiring such detection of electrons.
One particular application is in electron microscopy, in particular
transmission electron microscopy (TEM). However, the detectors 10,
30 are equally applicable to other applications requiring detection
of electrons such as electron energy loss spectrometers (EELS).
[0158] The detectors 10 and 30 are capable of achieving a
relatively high spatial resolution and relatively high quantum
efficiency. The reason for achieving a relatively high spatial
resolution is described above with reference to FIGS. 10 and 11.
The relatively high quantum efficiency is shown in FIG. 15 which
illustrates Detection Quantum Efficiency (DQE) as a function of
spatial frequency in the detection of 300 keV electrons for both
the detector 10 or 30 with a 15 .mu.m pixel size shown by a
continuous line and a CCD camera with a 30 .mu.m pixel size shown
by a dotted line. The Nyquist limits are marked with vertical
lines. Due to the split event discrimination, the detector 10 or 30
can provide information beyond its Nyquist frequency. From FIG. 15,
it is clear that the DQE of the detector 10 or 30 is expected to be
dramatically higher than that of current CCD cameras. It should be
noted that for the CCD camera, the displayed graph is the high dose
limit. For low doses, and for short exposure times, the DQE is
further deteriorated by dark current and readout noise. For the
detector 10 or 30, the displayed graph is the limit for low dose
rate and the DQE is reduced at very high dose rate because of the
increasing number of overlapping events. Unlike CCD cameras, the
detector 10 or 30 can be read out simultaneously with image
acquisition at a frame rate that is only limited by the transfer
speed to the computer. This high frame rate is of particular
importance for the application of the one-dimensional detector 10
for EELS. Alternatively, record of each event can be kept at a
timing resolution of 10 ns or faster, possibly enabling novel
experiments to be performed by an electron microscope.
[0159] Whilst the detectors 10 and 30 in accordance with the
present invention have been designed for detecting electrons with
energies in the range from 100 eV to 5 MeV, they are expected to be
suitable for detecting electrons with energies outside this range
and also for detecting other charged particles with corresponding
energies. The interaction of other charged particles with the
semiconductor will be similar resulting in the same advantages as
for detection of electrons.
* * * * *