U.S. patent application number 11/432116 was filed with the patent office on 2007-11-15 for flat panel display and fabrication method and thereof.
This patent application is currently assigned to Toppoly Optoelectronics Corp.. Invention is credited to Chun-Yen Liu, Chang-Ho Tseng.
Application Number | 20070262311 11/432116 |
Document ID | / |
Family ID | 38684284 |
Filed Date | 2007-11-15 |
United States Patent
Application |
20070262311 |
Kind Code |
A1 |
Liu; Chun-Yen ; et
al. |
November 15, 2007 |
Flat panel display and fabrication method and thereof
Abstract
The method for fabricating a flat panel display includes
performing a first crystallization process to re-crystallize an
amorphous silicon layer on a glass substrate to make the amorphous
silicon layer become a polysilicon layer, forming a patterned
absorbing layer to cover an active area pattern of a driving TFT
and to expose portions of the polysilicon layer, performing a
second crystallization process to re-crystallization the exposed
portions of the polysilicon layer so that the exposed portions of
the polysilicon layer has a different grain structure from the
grain structure of the driving TFT, removing the patterned
absorbing layer, and removing portions of the polysilicon layer to
form an active area of the driving TFT and an active area of a
switching TFT area in the exposed portions of the polysilicon layer
of each sub-pixel.
Inventors: |
Liu; Chun-Yen; (Zhubei City,
TW) ; Tseng; Chang-Ho; (Tao-Yuan Hsien, TW) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
100 GALLERIA PARKWAY, NW
STE 1750
ATLANTA
GA
30339-5948
US
|
Assignee: |
Toppoly Optoelectronics
Corp.
|
Family ID: |
38684284 |
Appl. No.: |
11/432116 |
Filed: |
May 11, 2006 |
Current U.S.
Class: |
257/66 ; 257/72;
257/E29.003; 438/166; 438/486 |
Current CPC
Class: |
H01L 27/1296 20130101;
H01L 29/04 20130101; H01L 27/1285 20130101 |
Class at
Publication: |
257/066 ;
438/486; 438/166; 257/072 |
International
Class: |
H01L 29/786 20060101
H01L029/786; H01L 21/84 20060101 H01L021/84 |
Claims
1. A method for fabricating a flat panel display, the flat panel
display comprising a plurality of sub-pixels, the method
comprising: providing a substrate; forming an amorphous silicon
layer on the substrate; performing a first crystallization process
to re-crystallize the amorphous silicon layer so that the amorphous
silicon layer becomes a polysilicon layer; forming a patterned
absorbing layer to cover an active area pattern of a driving thin
film transistor (TFT) in each of the sub-pixels and to expose
portions of the polysilicon layer; performing a second
crystallization process to re-crystallize the exposed portions of
the polysilicon layer so that the grain structure of the exposed
portions of the polysilicon layer is different from the grain
structure of a plurality of active areas covered by the active area
patterns of the driving TFTs; removing the patterned absorbing
layer; and removing portions of the polysilicon layer to form the
active area of the driving TFT and to form an active area of a
switching TFT in the exposed portions of the polysilicon layer of
each sub-pixel; wherein each of the active areas comprises a
channel region, a source region, and a drain region.
2. The method as claimed in claim 1, wherein the method further
comprises: forming a gate insulating layer and a metal layer on the
substrate sequentially; and removing portions of the metal layer to
form a plurality of gates of the switching TFTs and the driving
TFTs.
3. The method as claimed in claim 1, wherein the flat panel display
comprises a periphery circuit area, and the step of removing
portions of the polysilicon layer further comprises forming at
least an active area of a peripheral driving TFT in the periphery
circuit area.
4. The method as claimed in claim 3, wherein the grain structure of
a channel region of the peripheral driving TFT in the periphery
circuit area is the same as the grain structure of the channel
region of the switching TFT in each of the sub-pixels.
5. The method as claimed in claim 1, wherein the first
crystallization process comprises a solid-phase crystallization
(SPC) process.
6. The method as claimed in claim 5, wherein the SPC process
comprises a furnace annealing process, a rapid thermal process
(RTP), or an alternating magnetic field crystallization (AMFC)
process.
7. The method as claimed in claim 1, wherein the second
crystallization process comprises an excimer laser annealing (ELA)
process.
8. The method as claimed in claim 7, wherein the ELA process
comprises a solid-state laser (SSL) or an excimer laser
processes.
9. The method as claimed in claim 1, wherein the grain structure of
the channel regions of the driving TFTs comprises a dendrite grain
structure, and the grain structure of the channel regions of the
switching TFTs comprises a columnar grain structure.
10. The method as claimed in claim 1, wherein the standard
deviation of the carrier mobility in the channel regions of the
driving TFTs is smaller than the standard deviation of the carrier
mobility in the channel regions of the switching TFTs.
11. A flat panel display comprising: a pixel array area comprising
a plurality of sub-pixels, each of the sub-pixels comprising a
first TFT that comprises a channel region with a first grain
structure; and a periphery circuit area comprising at least a
peripheral driving TFT that comprises a channel region with a
second grain structure, the second grain structure being different
from the first grain structure.
12. The flat panel display as claimed in claim 11, wherein the
first grain structure comprises a dendrite grain structure, and the
second grain structure comprises a columnar grain structure.
13. The flat panel display as claimed in claim 11, wherein the
first TFT is a driving TFT of each of the sub-pixels.
14. The flat panel display as claimed in claim 11, wherein the flat
panel display further comprises a second TFT in each of the
sub-pixels, the grain structure of a channel region of the second
TFT being different from the first grain structure.
15. The flat panel display as claimed in claim 14, wherein the
second TFTs are switching TFTs of the sub-pixels.
16. The flat panel display as claimed in claim 14, wherein the
grain structure of the channel region of the second TFT is the same
as the second grain structure.
17. The flat panel display as claimed in claim 11, wherein the flat
panel display is an active matrix organic light-emitting panel
display or active matrix polymer light-emitting panel display.
18. A flat panel display comprising a plurality of sub-pixels, each
of the sub-pixels comprising: a driving TFT, a channel region of
the driving TFT comprising a dendrite grain structure; and a
switching TFT, a channel region of the switching TFT comprising a
grain structure different from the dendrite grain structure.
19. The flat panel display as claimed in claim 18, wherein the
channel region of each of the switching TFTs comprises a columnar
grain structure.
20. The flat panel display as claimed in claim 18, wherein the flat
panel display further comprises a periphery circuit area, and the
periphery circuit area comprises at least a peripheral driving TFT
having a channel region that has a grain structure different from
the dendrite grain structure.
21. The flat panel display as claimed in claim 20, wherein the
channel region of the peripheral driving TFT comprises a columnar
grain structure.
22. The flat panel display as claimed in claim 18, wherein the
standard deviation of the carrier mobility in the channel regions
of the driving TFTs is smaller than the standard deviation of the
carrier mobility in the channel regions of the switching TFTs.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a flat panel display that comprises
thin film transistors with different carrier mobility.
[0003] 2. Description of the Prior Art
[0004] An OLED uses organic luminous devices, such as organic
light-emitting diodes, as the light source of the display. An
organic luminous device is an electrically driven lighting element
having a brightness that depends on the magnitude of a related
current. The magnitude of the brightness, also called the
gray-scale value, is controlled by the magnitude of the driving
current of each sub-pixel, and the sub-pixels are arranged in a
matrix or array in an OLED, which is called a matrix display. As a
result, the OLED utilizes this characteristic of the organic
luminous devices to generate red, blue, and green lights with
different intensities of gray level to produce stunning images.
[0005] The matrix display is classified as a passive matrix or an
active matrix display according to the driving method. Passive
matrix displays adopt the method of driving the scan lines of the
display in sequence, driving pixels in different rows sequentially.
Since the light-emitting time of each pixel is restricted by the
scanning frequency and the numbers of scan lines, the passive
matrix method is not suitable for large-sized and high
dots-per-inch (dpi) displays with a high amount of scan lines. In
contrast, active matrix displays possess an independent sub-pixel
circuit for each sub-pixel, which includes a capacitor (Cs), an
organic light-emitting element, and at least two TFTs that are used
to adjust the OLED driving current. With this arrangement, even in
large-sized and high dpi displays, a steady driving current is
provided for each sub-pixel.
[0006] FIG. 1 is a schematic diagram of an active matrix OLED panel
10 according to the prior art. As shown in FIG. 1, a panel display
12 comprises a matrix composed of a plurality of data lines 22
(such as D1, D2, and D3) and scan lines 24 (such as S1, S2, and
S3). The panel display 12 also comprises a plurality of sub-pixel
circuits 26, wherein each sub-pixel circuit 26 has at least two
TFTs, a storage capacitor (Cs), and an organic light-emitting
element 20 at each intersection of a data line 22 and a scan line
24. Each sub-pixel circuit 26 is electrically connected to a
corresponding data line 22 and a corresponding scan line 24 for
driving the organic light-emitting element 20 in the corresponding
sub-pixel. The data lines D1, D2, and D3 connect to a data line
driver 16 for receiving an image data signal, and the scan lines
S1, S2, and S3 connect to a scan line driver 18 for receiving a
switch/address signal.
[0007] FIG. 2 is a schematic diagram of the sub-pixel circuit 26
shown in FIG. 1. As shown in FIG. 2, the sub-pixel circuit 26
comprises a switching TFT 28, a driving TFT 30, and a storage
capacitor 32. In the prior art, generally, the switching TFT 28 and
driving TFT 30 are NMOS and PMOS transistors respectively. The gate
of the switching TFT 28 is electrically connected to the scan line
24, and the source, point A, of the switching TFT 28 is
electrically connected to the data line 22. In addition, the gate,
point B, of the driving TFT 30 is electrically connected to the
source of the switching TFT 28 and one end of the storage capacitor
32. The source, point C, and the drain, point D, of the driving TFT
30 are electrically connected to the organic light-emitting element
20 and an external power supply respectively.
[0008] The driving method of the conventional OLED panel 10 is
described in the following. Referring to FIG. 1 and FIG. 2, when a
video data signal is inputted into a control circuit 14, the
control circuit 14 generates corresponding control signals to the
data line driver 16 and the scan line driver 18 according to the
video data of each sub-pixel. Then, the scan line driver 18 outputs
corresponding scan signals to each scan line 24 (S1, S2, . . . and
Sn) in sequence for turning on the sub-pixel circuits 26 in each
row in order and thereby making the corresponding pixels perform
the display operation. For example, when the OLED panel 10 is going
to drive a sub-pixel positioned in the intersection of D2 and S2,
the control circuit 14 sends a scan signal through the scan line 22
to the gate of the switching TFT 28 of the sub-pixel circuit 26,
and sends a corresponding data signal, normally a voltage signal
with a predetermined intensity, to the drain of the switching TFT
28 through the data line driver 16 and the data line 22 according
to the video data.
[0009] Since the switching TFT 28 conduct, the video data will
charge the storage capacitor 32 to have a first voltage through the
switching TFT 28 and generate a corresponding driving current at
point C, which is then output to the organic light-emitting element
20 to make the light-emitting element 20 generate light beams with
a corresponding brightness. When the OLED panel 10 performs in
continuous operation, such as driving the sub-pixels in the next
row, the storage capacitor 32 still has the first voltage although
the voltage on scan line 53 decreases resulted in the switching TFT
28 becoming closed. Therefore, the driving TFT 30 still conducts.
Furthermore, since there is a voltage difference between point D
and point B, a current is continuously passing through the driving
TFT 30 to the organic light-emitting element 20 to continuously
keep the organic light-emitting element 20 emitting light
beams.
[0010] In conclude, although a sub-pixel circuit may have various
design structures of an AMOLED panel and the amount of TFTs in a
sub-pixel circuit may be different, a sub-pixel circuit usually
contains at least two TFTs for driving the organic light-emitting
element, such as the driving TFT 30, and for switching the
sub-pixel, such as the switching TFT 30. In the driving method of
an OLED panel as described above, the sub-pixel circuit used for
driving the organic light-emitting element is one of the key
devices for displaying video data on time and correctly.
Furthermore, since the driving TFTs and the switching TFTs control
the switch of each sub-pixel and the organic light-emitting element
of each sub-pixel, the quality of the switching TFTs and driving
TFTs is a key factor in the performance of the OLED panel.
[0011] Generally, the switching TFTs and the driving TFTs are low
temperature polysilicon (LTPS) TFTs and fabricated simultaneously
with the same fabrication processes in the prior art. The
polysilicon layer of the channel region of one LTPS TFT is formed
under a low temperature. The prior-art method for forming the
channel region includes using laser beams with various energies or
utilizing a laser machine including a mask to mask and adjust the
laser beams so as to form the polysilicon layer.
[0012] Since the switching TFTs and the driving TFTs have different
functionalities in a sub-pixel, they actually requires different
electrical properties in operation. For example, one switching TFT
is used for turning on its corresponding sub-pixel, and therefore
it requires a high carrier mobility and a high driving current. On
the other hand, a driving TFT is used to drive the organic
light-emitting element and controls the brightness of the light
beams of the organic light-emitting element in the sub-pixel.
Accordingly, all the driving TFTs in the flat panel display should
have similar driving capability, and the carrier mobility of the
driving TFTs should be moderate for maintain the lifetime of the
organic light-emitting elements longer. However, the channel
regions of the driving TFTs and the switching TFTs are
conventionally formed by a laser irradiation in the fabrication
method of the prior art, thus the grain structures of the channel
regions have a large carrier mobility, about 100 cm.sup.2/Vs and a
large deviation.
[0013] Therefore, the driving TFTs including the grain structure of
the channel regions with a large deviation may have different
carrier mobility in a large range, which affect the organic
light-emitting elements in all of the sub-pixels may have different
brightness of largest magnitude. Since the driving TFTs have
different driving currents in a large range, it is difficult for
the whole flat panel display to have a brightness uniformity, which
is called a mura problem. Furthermore, the lifetime of the organic
light-emitting elements in each sub-pixel is hard to be controlled.
Accordingly, the witching properties of the switching TFTs and the
driving TFTs cannot be satisfied simultaneously.
SUMMARY OF THE INVENTION
[0014] It is therefore a primary objective of the claimed invention
to provide a flat panel display and the fabrication method thereof
to solve the above-mentioned problem.
[0015] Accordingly to the claimed invention, the method for
fabricating a flat panel display comprises providing a substrate,
forming an amorphous silicon layer on the substrate, performing a
first crystallization process to re-crystallize the amorphous
silicon layer so that the amorphous silicon layer becomes a
polysilicon layer, forming a patterned absorbing layer in each
sub-pixel of the flat panel display to define an active area
pattern of a driving TFT of each sub-pixel and to expose portions
of the polysilicon layer, performing a second crystallization
process to re-crystallization the exposed portions of the
polysilicon layer so that the exposed portions of the polysilicon
layer have a different grain structure from the grain structure of
the driving TFT, removing the patterned absorbing layer, and
removing portions of the polysilicon layer to form an active area
of the driving TFT and an active area of a switching TFT area in
the exposed portions of the polysilicon layer of each
sub-pixel.
[0016] It is an advantage of the claimed invention that the channel
regions of the driving TFTs and the switching TFTs are formed with
different crystallization processes . Therefore, the channel
regions of the driving TFTs comprise a dendrite grain structure
which has a low carrier mobility but a smaller standard deviation
of the carrier mobility as compared that of the switching TFTs.
Accordingly, all the driving TFTs provide similar currents to
corresponding organic light-emitting elements in each sub-pixel so
that the mura problem can be solved. Furthermore, since the channel
regions of the switching TFTs comprise a columnar grain structure
which has a high carrier mobility, all sub-pixels may have
preferable response time.
[0017] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a schematic diagram of an active matrix OLED panel
according to the prior art.
[0019] FIG. 2 is a schematic diagram of the sub-pixel circuit shown
in FIG. 1.
[0020] FIGS. 3-9 are schematic diagrams of sectional views of the
fabrication method of the flat panel display according to the
present invention.
[0021] FIG. 10 is a schematic diagram of the dendrite grain
structure and a columnar grain structure according to the present
invention.
DETAILED DESCRIPTION
[0022] In a preferable embodiment of the present invention, the
fabrication method is applied to fabricating a flat panel display,
which is an active matrix OLED (AMOLED). However, in other
embodiments, the present invention can be applied to an active
matrix polymer light-emitting panel displays. The flat panel
display comprises a periphery circuit area and a pixel array area,
which includes a plurality of sub-pixels. Each of the sub-pixels
comprises at least two TFTs and an organic light-emitting elements,
wherein one of the TFTs is a driving TFT for driving the organic
light-emitting element, and one of the TFTS is a switching TFT for
switching the sub-pixel.
[0023] Referring to FIGS. 3-9, FIGS. 3-9 are schematic diagrams of
the sectional views of the fabrication method of the flat panel
display 50 according to the present invention. As shown in FIG. 3,
the flat panel display 50 comprises a pixel array area 52, and a
periphery circuit area 54, wherein the pixel array area 52
comprises a plurality of sub-pixels. Each sub-pixel includes at
least two TFTs in each sub-pixel. In FIG. 3, only a switching TFT
region 52a and a driving TFT region 52b are defined and illustrated
for explanation. First, a substrate 56 is provided, wherein the
substrate 56 is a transparent glass substrate. Then, a buffer layer
58 and an amorphous silicon layer 60 are formed in the pixel array
area 52 and the periphery circuit area 54 on the substrate 56
sequentially. The buffer layer 58 and the amorphous silicon layer
60 may be formed by using plasma enhanced chemical vapor deposition
(PECVD) processes, wherein the buffer layer 58 can be a silicon
oxide layer for insulating the semiconductor heat sinks from the
amorphous silicon layer 60. After forming the buffer layer 58 and
the amorphous silicon layer 60, a dehydrogenation process is
performed to reduce the hydrogen content in the amorphous silicon
layer 60.
[0024] Referring to FIG. 4, a first crystallization process is
performed to re-crystallize the amorphous silicon layer 60 for
forming a polysilicon layer 62 on the buffer layer 58. The first
crystallization process is preferably a solid-phase crystallization
(SPC) process, comprising a furnace annealing process, a rapid
thermal process (RTP), or an alternating magnetic field
crystallization (AMFC) process. For example, when the SPC process
is performed by a furnace annealing process, the substrate 52 may
be heated by the furnace under 600.degree. C. with 12-24 hours so
that the amorphous silicon layer 60 is completely melted and
re-crystallized to become the polysilicon layer 62 with a dendrite
grain structure.
[0025] Then, an absorbing layer 64 and a photoresist layer 66 are
sequentially formed on the polysilicon layer 62. A photo-etching
process is performed to pattern the photoresist layer 66 and the
absorbing layer 64 for defining an active area pattern in each
driving TFT region 52b. Accordingly, the patterned absorbing layer
64 only covers the active area of the driving TFT following formed,
while the other portions of the polysilicon layer 62 are exposed,
as shown in FIG. 5. The absorbing layer 64 comprises silicon oxide
or other materials that can block a laser irradiation in the
following process.
[0026] Please refer to FIG. 6. The photoresist layer 66 is
selectively removed. A second crystallization process is then
performed to re-crystallize the exposed portions of the polysilicon
layer 62. The second crystallization process is different from the
first crystallization process. In a preferable embodiment, the
second crystallization process is an excimer laser annealing
process, and which is practiced by an excimer laser or a
solid-stated laser (SSL). During this process, the portions of the
polysilicon layer 62 not covered by the absorbing layer 64 are
melted and re-crystallized to become a polysilicon layer 68, while
the portions of the polysilicon layer 62 covered by the absorbing
layer 64 is not melted because the absorbing layer 64 blocks the
laser irradiation. Since the polysilicon layer 68 is formed by the
ELA process, it comprises a columnar grain structure, which has a
high carrier mobility.
[0027] Referring to FIG. 7, the absorbing layer 64 is removed. A
second photo-etching process is then performed to define the active
area 70 of every switching TFT in the switching TFT regions 52a,
the active area 72 of every driving TFT in the driving TFT regions
52b in all the sub-pixels and to define the active areas 74 of each
peripheral driving TFTs in the periphery circuit area 54. The
active areas 70, 72, 74 comprise a channel region 70c, 72c, 74c, a
source region 70a, 72a, 74a, and a drain region 70b, 72b, 74b
respectively.
[0028] As shown in FIG. 8, a plasma enhanced chemical vapor
deposition (PECVD) process is thereafter performed to form a
silicon oxide layer 76 on the surface of the active areas 70, 72,
74 formed with the polysilicon layers 62, 68. The silicon oxide
layer 76 serves as a gate insulating layer for separating channel
regions and gates in every TFT. After that, a metal layer 78 is
formed on the surface of the silicon oxide layer 76, which may be
formed by a sputtering process. The metal layer 78 may be a
tungsten (W) layer, a chrome (Cr) layer, or another conductive
metal layer.
[0029] Referring to FIG. 9, a photoresist layer (not shown) is then
formed on the surface of the metal layer 78. A photo-etching
process is thereafter performed to define gate patterns in the
photoresist layer (not shown). The gate patterns are on top of the
channel regions 70c, 72c, 74c. After that, a dry etching process is
performed to remove portions of the metal layer 78 so as to form
gates 80, 82, 84 on top of the silicon oxide layer 76. After
removing the gate patterns of the photoresist layer, an ion
implantation process is selectively performed to form sources and
drains of TFTs, in the source regions 70a, 72a, 74a and in the
drain regions 70b, 72b, 74b of the polysilicon layer 62, 68
respectively by utilizing the gates 80, 82, 84 as implantation
masks. Then, a pasivation layer 86 is formed on the substrate 56.
Therefore, the formation of the switching TFTs 88, the driving TFTs
90, and the peripheral driving TFTs 92 are completed in the
switching TFT regions 52a, the driving TFT regions 52b, and the
periphery circuit area 54 respectively.
[0030] It should be noted that the grain structures of the channel
regions of the driving TFTs 90 are different from the grain
structures of the channel regions of the switching TFTs 88, or the
peripheral driving TFTs 92 because the formation methods are
different. Referring to FIG. 10, which is a schematic diagram of
the dendrite and columnar grain structures. The grain structure of
the channel regions of the driving TFTs 90 comprises a dendrite
grain structure, which is formed by the first crystallization
process, the SPC process. Although the dendrite grain structures
have a low carrier mobility, about 10-40 cm.sup.2/Vs, they also
have a small standard deviation of the carrier mobility. The
driving TFTs 90 usually have large channel lengths, and require
uniform driving currents and a small standard deviation to provide
uniformity of the brightness in each sub-pixels, which is
approximately smaller than 5 cm.sup.2/Vs. Therefore, the dendrite
grain structures formed by the SPC process can meet the requirement
of the driving TFTs 90. On the other hand, the channel regions 70c,
74c of the switching TFTs 88 and the peripheral driving TFTs 92 are
columnar grain structures formed by the second crystallization
process, the ELA process, and which have a high carrier mobility
and a high driving current, thus the response time of each of the
switching TFTs 88 and the peripheral driving TFTs 92 is short.
Accordingly, the response time of the whole flat panel display 50
is preferable according to the present invention.
[0031] In contrast to the prior art, the present invention provide
a flat panel display, such as a AMOLED or active matrix polymer
light-emitting panel display, that has at least two grain
structures of the channel regions of the TFTs, wherein the two
grain structures may be included in one sub-pixel, or be included
in the periphery circuit area and the pixel array area
respectively. Therefore, each TFT in the sub-pixel or the periphery
circuit area can have an appropriate property in operation. For
example, the channel regions of the driving TFTs have a dendrite
structure having a low carrier mobility and a small standard
deviation of carrier mobility, thus all the sub-pixels have a
preferable uniformity of the brightness. Furthermore, the low
driving currents of the dendrite grain structure can extend the
lifetime of the organic light-emitting elements in each sub-pixels.
The present invention can be applied to various flat panel
displays, even when each sub-pixel includes more than two TFTs.
Those skilled in the art should know that the spirit of the present
invention is to provide different and appropriate grain structures
to the channel regions for TFTs with different functionalities
through different fabrication processes.
[0032] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *