U.S. patent application number 11/416534 was filed with the patent office on 2007-11-08 for voltage regulator with suspend mode.
Invention is credited to Edward Burton, Anant Deval, Robert Greiner, Doug Huard.
Application Number | 20070260898 11/416534 |
Document ID | / |
Family ID | 38662503 |
Filed Date | 2007-11-08 |
United States Patent
Application |
20070260898 |
Kind Code |
A1 |
Burton; Edward ; et
al. |
November 8, 2007 |
Voltage regulator with suspend mode
Abstract
A system is disclosed. The system includes a central processing
unit (CPU) to operate in one or more low power sleep states, and a
power converter. The power converter includes phase inductors; and
one or more power switches to drive the phase inductors. The one or
more power switches are deactivated during the CPU sleep state.
Inventors: |
Burton; Edward; (Hillsboro,
OR) ; Greiner; Robert; (Beaverton, OR) ;
Deval; Anant; (Beaverton, OR) ; Huard; Doug;
(Portland, OR) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 OAKMEAD PARKWAY
SUNNYVALE
CA
94085-4040
US
|
Family ID: |
38662503 |
Appl. No.: |
11/416534 |
Filed: |
May 3, 2006 |
Current U.S.
Class: |
713/300 |
Current CPC
Class: |
Y02B 70/16 20130101;
H02M 2001/0032 20130101; Y02B 70/10 20130101; H02M 3/1584
20130101 |
Class at
Publication: |
713/300 |
International
Class: |
G06F 1/00 20060101
G06F001/00 |
Claims
1. A system comprising: a central processing unit (CPU) to operate
in one or more low power sleep states; and a power converter
having: phase inductors; and one or more power switches to drive
the phase inductors, wherein the one or more power switches are
deactivated during the CPU sleep state.
2. The system of claim 1 wherein the CPU comprises a power control
unit to regulate the output voltage from the power converter and to
suspend operation of the power converter whenever the CPU enters
into the sleep state.
3. The system of claim 2 wherein a clock that supplies the power
control unit is deactivated in the CPU sleep state.
4. The system of claim 2 wherein the one or more power switches are
field effect transistors (FETs);
5. The system of claim 4 wherein the power converter further
comprises: a set of phases, wherein each phase includes: a phase
inductor having an upper FET coupling a primary power supply
voltage to a first terminal of the phase inductor, and a lower FET
coupling ground to the first terminal of the phase inductor; and
output filter capacitors.
6. The system of claim 5 wherein charge stored at the output
capacitors supply power to the CPU whenever the operation of the
power converter is suspended.
7. The system of claim 6 wherein the power control unit activates
the power switches once the CPU exits the sleep state.
8. The system of claim 6 wherein the power control unit monitors
the voltage level at the CPU whenever the operation of the power
converter is suspended.
9. The system of claim 8 wherein the power control unit activates
the power FETs upon detecting that the voltage at the CPU has
fallen below a predetermined threshold voltage.
10. The system of claim 9 wherein the power control unit suspends
operation of the power converter after the voltage has risen to the
predetermined threshold voltage.
11. The system of claim 8 wherein whenever the CPU is in the sleep
state and the CPU voltage is above a threshold voltage the power
converter will enter an adaptive diode emulation mode.
12. A method comprising: determining whether a central processing
unit (CPU) has entered a sleep state; and a power control unit
suspending operation of power switches within a power converter if
the CPU has entered into the sleep state.
13. The method of claim 12 wherein suspending the operation of the
power converter further comprises supplying power to the CPU via
charge stored at output capacitors within the power converter.
14. The method of claim 12 further comprising the power control
unit activating the power switches once the CPU exits the sleep
state.
15. The method of claim 12 further comprising the power control
unit monitoring the voltage level at the CPU whenever the operation
of the power converter has been suspended.
16. The method of claim 15 further comprising the power control
unit activating the FETs upon detecting that the voltage at the CPU
has fallen below a predetermined threshold voltage.
17. The method of claim 15 further comprising the power converter
entering an adaptive diode emulation mode whenever the CPU is in
the sleep state and the CPU voltage is above a threshold
voltage.
18. A power converter comprising: phase inductors; and one or more
power switches to drive the phase inductors, wherein the one or
more power switches are deactivated upon receiving a signal
indicating that a central processing unit (CPU) has entered a sleep
state.
19. The power converter of claim 18 wherein the one or more power
switches are field effect transistors (FETs).
20. The power converter of claim 19 wherein the power converter
further comprises: a set of phases, wherein each phase includes: a
phase inductor having an upper FET coupling a primary power supply
voltage to a first terminal of the phase inductor, and a lower FET
coupling ground to the first terminal of the phase inductor; and
output filter capacitors.
21. The power converter of claim 20 wherein charge stored at the
output capacitors supply power to the CPU whenever the operation of
the power converter is suspended.
22. The power converter of claim 18 wherein whenever the CPU is in
the sleep state and the CPU voltage is above a threshold voltage
the power converter will enter an adaptive diode emulation mode.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to computer systems; more
particularly, the present invention relates to regulating voltage
in a microprocessor.
BACKGROUND
[0002] Growing demand for integrated circuits (ICs), for example
microprocessors, with ever higher levels of performance and
functionality have driven these devices to circuit densities beyond
100 million transistors per die. This number may soon exceed one
billion transistors on a single die. The growth in transistor
density has been made possible by the use of MOSFET transistors
with gate lengths below 100 nm. As gate length has shortened, power
supply voltages have fallen, in some cases, to below 1 V.
[0003] Even in a mobile computing environment (laptop), high-speed
microprocessors, with clock speeds in excess of 2 GHz, may require
in excess of 100 watts of power when operating at maximum load.
With operating voltages below 1 V, this translates to power supply
currents that reach beyond 100 A. Nevertheless, when used in a
mobile environment, the same microprocessor must often draw less
than 1 watt of "average power" due to battery considerations.
[0004] Integrated circuits are typically powered from one or more
DC supply voltages provided by external supplies and converters.
The power is provided through pins, leads, lands, or bumps on the
integrated circuit package. The traditional method for providing
such high power to integrated circuits may involve the use of a
high-efficiency, programmable DC-to-DC (switch-mode) power
converter located near the IC package.
[0005] This type of converter (buck regulator) may use a DC input
voltage as high as 48V and provide a DC output voltage below 2 V.
Conventional DC-to-DC power converters use switching frequencies in
the neighborhood of 200 KHz, with some high-end units in the 1-2
MHz range. Such converters usually require a handful of relatively
large components, including a pulse-width modulation (PWM)
controller, one or more power transistors, filter and decoupling
capacitors, and one or more large inductors and/or
transformers.
[0006] Typical switch-mode power converters include one or more
phases to supply the full output current. However, in many
instances it may be inefficient to implement full operation of the
converter, especially in applications that have low (e.g., nearly
0) current draw.
DESCRIPTION OF THE DRAWINGS
[0007] The invention is illustrated by way of example and not
limitation in the figures of the accompanying drawings, in which
like references indicate similar elements, and in which:
[0008] FIG. 1 is a block diagram of one embodiment of a computer
system;
[0009] FIG. 2 illustrates a block diagram of one embodiment of a
central processing unit;
[0010] FIG. 3 illustrates one embodiment of a power converter;
and
[0011] FIG. 4 illustrates a block diagram of one embodiment of a
power control unit.
DETAILED DESCRIPTION
[0012] A voltage regulator having a suspend mode is described. In
the following detailed description of the present invention,
numerous specific details are set forth in order to provide a
thorough understanding of the present invention. However, it will
be apparent to one skilled in the art that the present invention
may be practiced without these specific details. In other
instances, well-known structures and devices are shown in block
diagram form, rather than in detail, in order to avoid obscuring
the present invention.
[0013] Reference in the specification to "one embodiment" or "an
embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the invention. The
appearances of the phrase "in one embodiment" in various places in
the specification are not necessarily all referring to the same
embodiment.
[0014] FIG. 1 is a block diagram of one embodiment of a computer
system 100. Computer system 100 includes a central processing unit
(CPU) 102 coupled to interconnect 105. In one embodiment, CPU 102
is a processor in the Itanium.RTM. family of processors including
the Itanium.RTM. 2 processor available from Intel Corporation of
Santa Clara, Calif. Alternatively, other CPUs may be used.
[0015] A chipset 107 may also be coupled to bus 105. Chipset 107
includes a memory control hub (MCH) 110. MCH 110 may include a
memory controller 112 that is coupled to a main system memory 115.
Main system memory 115 stores data and sequences of instructions
that are executed by CPU 102 or any other device included in system
100. In one embodiment, main system memory 115 includes dynamic
random access memory (DRAM); however, main system memory 115 may be
implemented using other memory types. Additional devices may also
be coupled to interconnect 105, such as multiple CPUs and/or
multiple system memories.
[0016] MCH 110 is coupled to an input/output control hub (ICH) 140
via a hub interface. ICH 140 provides an interface to input/output
(I/O) devices within computer system 100. In addition, computer
system 100 includes a power supply 165 to provide power to CPU 102
and chipset 107. In one embodiment, power supply 165 is implemented
as multiple cascaded supplies, where a first supply converts the AC
input from a wall outlet to a set of standard voltage rails, and a
set of downstream supplies (often referred to as a point-of-load
regulators) convert the standard voltages to the less standardized
voltages directly used by advanced logic ICs.
[0017] FIG. 2 illustrates one embodiment of CPU 102 coupled to
power converter 210. In one embodiment, power converter 210 is a
programmable DC-to-DC (switch-mode) power converter located near
the CPU 102 IC package to provide high power to CPU 102. However in
other embodiments, power converter 210 may be located on the CPU
102 package.
[0018] FIG. 3 illustrates one embodiment of power converter 210.
Power converter 210 is a 2-phase converter that receives a 12V
voltage input at each phase, which is converted to a 1.2V output
voltage. According to one embodiment, each phase includes a set of
power field effect transistors (FETs) and an inductor. The phases
all couple into a shared bank of output filter capacitors,
represented in FIG. 3 as a single capacitor C.
[0019] Referring back to FIG. 2, CPU 102 includes processing cores
0-3 coupled to receive power from power converter 210, and a power
control unit 250. Each processing core operates as an independent
microprocessor to permit thread-level parallelism. Power control
unit 250 regulates the voltage applied to CPU 102 by power
converter 210, based at least in part on the potential of the
operational frequency of all or a subset of the operational
circuit(s) of CPU 102.
[0020] FIG. 4 illustrates one embodiment of power control unit 250.
Power control unit 250 includes a voltage regulator (VR)
microcontroller 410, a finite state machine (FSM) control block 420
and a VR 430. VR microcontroller 410 provides voltage control
configuration parameters that are implemented to control voltage.
According to one embodiment, VR microcontroller 410 provides the
configuration parameters via input/output (I/O) writes to addresses
to add coefficients that define voltage control functionality.
[0021] FSM control block 420 implements various FSMs to control
various voltage control parameters. In one embodiment, FSM control
block 420 includes ramp rate control, power throttle and loadline
adjust current. VR 430 includes a compensator 432 and a pulsewidth
modulator 436. Compensator 432 receives a target voltage from
control block and compares the target voltage to an actual voltage
received from one or more of the cores 0-3.
[0022] In response, compensator 432 generates an error term that is
used to drive to zero error using negative feedback. Pulsewidth
modulator 436 generates pulse signals to control current based upon
the error term received from compensator 432. The pulse signals are
transmitted from pulsewidth modulator 436 to power converter 210 to
control the activation of the power FETs at each phase.
[0023] In normal operation, CPU 102 components may demand a very
high current from power converter 210, which is generally the
motivation for designing a voltage regulator with multiple phases.
In normal operation, the current demand is generally high enough
that multiple phases can continuously be pulsed, and the energy
lost in continuous pulsing is small compared to the total current
draw.
[0024] However at certain instances (e.g., where CPU 102 goes into
a sleep state), it would be inefficient for power converter 210 to
continuously pulse even a single phase. According to one
embodiment, whenever the CPU 102 cores go into a sleep state, power
control unit 250 and power converter 210 go into a suspend mode. In
such an embodiment, a clock supplying power control unit 250 is
deactivated.
[0025] In such an embodiment, the current draw at CPU 102 is
sufficiently low so as to enable the charge stored at the output
filter capacitors to supply power to CPU for a predetermined period
of time. For example, if the CPU 102 sleep state duration is in a
range of a few (e.g., 2-4) milliseconds operation at power control
unit 250 and power converter 210 may be suspended until CPU 102 is
reactivated. Thus, the power FET switches at power converter 210
are deactivated (e.g., no current generated by power converter 210)
until CPU 102 is reactivated.
[0026] In another embodiment, power control unit 250 monitors the
CPU 102 voltage whenever it and power converter 210 are in the
suspend state. In this embodiment, power converter 210 remains in
the suspend state until the voltage falls below a predetermined
threshold (e.g., 1.2V). Once the voltage falls below the threshold,
VR 430 exits the suspend state and transmits a pulse to activate
one or both of the phases at power converter 210 in order to supply
current to CPU 102. In a further embodiment, VR 430 may reenter the
suspend state once current is supplied to CPU 102 as long as CPU
102 remains in the sleep state. Subsequently, the CPU 102 is again
monitored by power control unit 250.
[0027] In yet another embodiment, whenever CPU 102 is in the
suspend state and the CPU 102 voltage is above the threshold
voltage, power converter 210 will enter an adaptive diode emulation
mode. In such a mode, one phase is repeatedly sequenced through the
following states: only upper FET on (UPPER state), only lower FET
on (LOWER state), both FETs off (OFF state). Further, the repeated
sequencing is performed at a largely fixed frequency, and the
portion of time spent in each state is adapted to maintain a
desired voltage. In another embodiment, the UPPER state time and
the LOWER state time may be largely fixed, while the OFF state time
is adapted to maintain a desired voltage.
[0028] The above-described power management mechanism yields an
increase in battery life in a mobile computer system.
[0029] Whereas many alterations and modifications of the present
invention will no doubt become apparent to a person of ordinary
skill in the art after having read the foregoing description, it is
to be understood that any particular embodiment shown and described
by way of illustration is in no way intended to be considered
limiting. Therefore, references to details of various embodiments
are not intended to limit the scope of the claims which in
themselves recite only those features regarded as essential to the
invention.
* * * * *