U.S. patent application number 11/469066 was filed with the patent office on 2007-10-11 for digital-to-analog converter.
Invention is credited to Jianzhong Chen, Yong Ping Xu.
Application Number | 20070236377 11/469066 |
Document ID | / |
Family ID | 38789470 |
Filed Date | 2007-10-11 |
United States Patent
Application |
20070236377 |
Kind Code |
A1 |
Chen; Jianzhong ; et
al. |
October 11, 2007 |
DIGITAL-TO-ANALOG CONVERTER
Abstract
Embodiments of a digital-to-analog converter are disclosed.
Inventors: |
Chen; Jianzhong; (Singapore,
SG) ; Xu; Yong Ping; (Singapore, SG) |
Correspondence
Address: |
BERKELEY LAW & TECHNOLOGY GROUP, LLP
17933 NW Evergreen Parkway, Suite 250
BEAVERTON
OR
97006
US
|
Family ID: |
38789470 |
Appl. No.: |
11/469066 |
Filed: |
August 31, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11318082 |
Dec 23, 2005 |
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11469066 |
Aug 31, 2006 |
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60639085 |
Dec 23, 2004 |
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Current U.S.
Class: |
341/144 |
Current CPC
Class: |
H03M 3/338 20130101;
H03M 3/464 20130101; H03M 3/424 20130101; H03M 3/502 20130101; H03M
3/368 20130101 |
Class at
Publication: |
341/144 |
International
Class: |
H03M 1/66 20060101
H03M001/66 |
Claims
1. An apparatus comprising: a digital-to-analog converter (DAC);
said DAC having a feedback path that includes an accumulator to
employ spectral shaping in connection with dynamic element matching
and a differentiator to substantially offset said accumulator.
2. The apparatus of claim 1, wherein said DAC comprises a
sigma-delta modulator.
3. The apparatus of claim 2, wherein said sigma-delta modulator
comprises a multi-bit sigma-delta modulator.
4. The apparatus of claim 1, wherein said DAC comprises a low-pass
DAC.
5. The apparatus of claim 1, wherein said DAC comprises a band-pass
DAC.
6. The apparatus of claim 1, wherein said DAC comprises a high-pass
DAC.
7. An apparatus comprising: a digital-to-analog converter (DAC);
said DAC having a feedback path comprising means for applying
spectral shaping to dynamic element matching and means for
substantially offsetting said spectral shaping.
8. The apparatus of claim 7, wherein said DAC comprises a
sigma-delta modulator.
9. A method comprising: spectrally shaping a signal prior to
application to randomizing logic; and substantially offsetting the
spectral shaping prior to application of said signal as
feedback.
10. The method of claim 9, wherein said randomized logic is
employed to perform dynamic element matching for a
digital-to-analog converter.
11. The method of claim 9, wherein said spectral shaping comprises
an order higher than one.
12. The method of claim 11, wherein said order higher than one
comprises an order higher than two.
13. A lowpass sigma-delta modulator comprising: a summing circuit
for receiving an input and a feedback signal and producing an
output; a loop filter receiving the output of said summing circuit
as an input and producing an output; a quantizer receiving the
output of said loop filter and producing an N-bit digital output
which is the output of said modulator, N being an integer with a
value greater than one; a digital integrator receiving the output
of said quantizer as an input and producing an output; a randomizer
block receiving the output of said digital integrator as an input
and produce an output; a digital-to-analog converter receiving said
output of said randomizer block as an input and producing an
output; an analog differentiator receiving the output of said
digital-to-analog converter as an input and producing said feedback
signal.
14. A lowpass sigma-delta modulator comprising: a summing circuit
for receiving an input and a feedback signal and producing an
output; a loop filter receiving the output of said summing circuit
as an input and producing an output; a quantizer receiving the
output of said loop filter and producing an N-bit digital output
which is the output of said modulator, N being an integer with a
value greater than one; a digital L.sup.th-order lowpass filter
receiving the output of said quantizer as an input and producing an
output, L being an integer with a value greater than zero; a
randomizer block receiving the output of said digital
L.sup.th-order lowpass filter as an input and produce an output; a
digital-to-analog converter receiving said output of said
randomizer block as an input and producing an output; an analog
L.sup.th-order highpass filter receiving the output of said
digital-to-analog converter as an input and producing said feedback
signal, L being an integer with a value greater than zero.
15. A bandpass sigma-delta modulator comprising: a summing circuit
for receiving an input and a feedback signal and producing an
output; a loop filter receiving the output of said summing circuit
as an input and producing an output; a quantizer receiving the
output of said loop filter and producing an N-bit digital output
which is the output of said modulator, N being an integer with a
value greater than one; a digital L.sup.th-order bandpass filter
receiving the output of said quantizer as an input and producing an
output, L being an integer with a value greater than zero; a
randomizer block receiving the output of said digital
L.sup.th-order bandpass filter as an input and produce an output; a
digital-to-analog converter receiving said output of said
randomizer block as an input and producing an output; an analog
L.sup.th-order band rejection filter receiving the output of said
digital-to-analog converter as an input and producing said feedback
signal, L being an integer with a value greater than zero.
16. The sigma-delta modulator of claim 15, wherein said loop filter
can be realized in either discrete-time or continuous-time
circuits.
17. A lowpass sigma-delta digital-to-analog converter comprising:
an interpolation filter for receiving an input and producing an
output; a summing circuit for receiving the output of said
interpolation filter and a feedback signal and producing an output;
a loop filter receiving the output of said summing circuit as an
input and producing an output; a truncator receiving the output of
said loop filter and producing said feedback signal, an N-bit
truncated digital signal, N being an integer with a value greater
than one; a digital integrator receiving the output of said
truncator as an input and producing an output; a randomizer block
receiving the output of said digital integrator as an input and
produce an output; a digital-to-analog converter receiving said
output of said randomizer block as an input and producing an
output; an analog differentiator receiving the output of said
digital-to-analog converter as an input and producing an output; an
analog post filter receiving the output of said analog
differentiator and producing the output of said lowpass sigma-delta
digital-to-analog converter.
18. A lowpass sigma-delta digital-to-analog converter comprising:
an interpolation filter for receiving an input and producing an
output; a summing circuit for receiving the output of said
interpolation filter and a feedback signal and producing an output;
a loop filter receiving the output of said summing circuit as an
input and producing an output; a truncator receiving the output of
said loop filter and producing said feedback signal, an N-bit
truncated digital signal, N being an integer with a value greater
than one; a digital L.sup.th-order lowpass filter receiving the
output of said truncator as an input and producing an output, L
being an integer with a value greater than zero; a randomizer block
receiving the output of said digital L.sup.th-order lowpass filter
as an input and produce an output; a digital-to-analog converter
receiving said output of said randomizer block as an input and
producing an output; an analog L.sup.th-order highpass filter
receiving the output of said digital-to-analog converter as an
input and producing an output, L being an integer with a value
greater than zero; an analog post filter receiving the output of
said analog L.sup.th-order highpass filter and producing the output
of said lowpass sigma-delta digital-to-analog converter.
19. A bandpass sigma-delta digital-to-analog converter comprising:
an interpolation filter for receiving an input and producing an
output; a summing circuit for receiving the output of said
interpolation filter and a feedback signal and producing an output;
a loop filter receiving the output of said summing circuit as an
input and producing an output; a truncator receiving the output of
said loop filter and producing said feedback signal, an N-bit
truncated digital signal, N being an integer with a value greater
than one; a digital L.sup.th-order bandpass filter receiving the
output of said truncator as an input and producing an output, L
being an integer with a value greater than zero; a randomizer block
receiving the output of said digital L.sup.th-order bandpass filter
as an input and produce an output; a digital-to-analog converter
receiving said output of said randomizer block as an input and
producing an output; an analog L.sup.th-order band rejection filter
receiving the output of said digital-to-analog converter as an
input and producing an output, L being an integer with a value
greater than zero; an analog post filter receiving the output of
said analog L.sup.th-order band rejection filter and producing the
output of said bandpass sigma-delta digital-to-analog converter.
Description
CLAIM FOR PRIORITY
[0001] The current patent application claims priority to U.S.
provisional patent application No. 60/639,085, filed on Dec. 23,
2004, titled "Methods for Shaping and Reduction of
Digital-to-Analog Converter Noise," assigned to the assignee of the
presently claimed subject matter.
FIELD
[0002] This disclosure is related to digital-to-analog
converters.
BACKGROUND
[0003] Digital-to-analog converters, such as, for example,
sigma-delta modulators, are subject to errors and/or noise from a
variety of sources, including device mismatch.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Subject matter is particularly pointed out and distinctly
claimed in the concluding portion of the specification. Claimed
subject matter, however, both as to organization and method of
operation, together with objects, features, and advantages thereof,
may best be understood by reference of the following detailed
description if read with the accompanying drawings in which:
[0005] FIG. 1 is a schematic diagram illustrating an embodiment of
a k-bit DAC with dynamic element matching;
[0006] FIG. 2 is a schematic diagram illustrating an embodiment of
a multi-bit sigma-delta ADC structure;
[0007] FIG. 3 is a schematic diagram illustrating an embodiment of
a sigma-delta ADC with spectrally shaping;
[0008] FIG. 4 is a schematic diagram illustrating an embodiment of
a sigma-delta modulator linear model;
[0009] FIG. 5 is a schematic diagram of an embodiment of a DAC with
noise shaping;
[0010] FIG. 6 is a plot of an output power spectral density of a
fifth-order 5-bit low-pass sigma-delta modulator with an internal
DAC, from simulation;
[0011] FIG. 7 is a plot of an output power spectral density of a
fifth-order 5-bit low-pass sigma-delta modulator with an internal
DAC having 2% mismatch, from simulation;
[0012] FIG. 8 is a plot of an output power spectrum density of a
fifth-order 5-bit low-pass sigma-delta modulator with an internal
DAC having 2% mismatch, with an embodiment of spectral shaping
applied, from simulation;
[0013] FIG. 9 is a plot of an output power spectral density of a
sixth-order 4-bit band-pass sigma-delta modulator with an internal
DAC, from simulation;
[0014] FIG. 10 is a plot of an output power spectral density of a
sixth-order 4-bit band-pass sigma-delta modulator with an internal
DAC having 2% mismatch, from simulation;
[0015] FIG. 11 is a plot of an output power spectral density of a
sixth-order 4-bit band-pass sigma-delta modulator with an internal
DAC having 2% mismatch, with an embodiment of spectral shaping
applied, from Matlab simulation.
[0016] FIG. 12 is a schematic diagram of an embodiment of a
multi-bit sigma-delta DAC structure; and
[0017] FIG. 13 is a schematic diagram of an embodiment of a
sigma-delta DAC with spectral shaping.
DETAILED DESCRIPTION
[0018] Due at least in part to device mismatch, monolithic
digital-to-analog converters (DACs) may exhibit non-linear
characteristics. Thus, a transfer characteristic or transfer
function describing conversion from an digital to analog domain may
be nonlinear. Such nonlinearities may introduce errors and/or
result distortion of an analog signal and may, likewise, degrade
performance of a DAC. Nonlinearity, together with other potential
noise sources, such as thermal noise, for example, may be
considered noise generated inherently. In multi-bit sigma-delta
modulator, the digitized signal is converted back to analog domain
in the feedback path, typically through an internal DAC, and
subsequently subtracted or offset from an input signal. If the
feedback signal includes noise, it may degrade performance of the
sigma-delta modulator. Thus, advantage attributed to employing
multi-bit quantization may be reduced.
[0019] Several methods have been proposed to address this issue.
They may be divided at a high level into two categories. One may be
referred to as an element calibration approach and the other may be
referred to as a Dynamic Element Matching (DEM) technique.
[0020] In the first category, different methods may be employed
depending at least in part on implementation of the DAC. For
example, resistor elements may be laser-trimmed in the fabrication,
but this may raise cost of manufacture. Current sources may be
calibrated by changing the gate voltage or by combining coarse DAC
with a fine DAC for calibration. Capacitors may be trimmed by
switching in small additional capacitors. However, typically, this
method incurs additional chip fabrication cost. In addition, both
factory-trimming and calibration at startup may also suffer from
element matching variations associated with, for example, age and
temperature changes. Periodical or continuous background
calibration may be employed; however, circuit complexity and cost
may be further increased.
The second category may be referred to as Dynamic Element Matching
(DEM). With DEM, integral and differential linearity may be
achieved, with modest matching of the components.
[0021] The principle is illustrated in FIG. 1. A binary input-code
of a DAC is transformed into a thermometer-code of 2.sup.k-1 lines.
In a DAC without DEM, these bit lines control one specific unit
element of the DAC. Due at least in part to fabrication process
variations, the values of these unit elements may not be equal and
may introduce nonlinearity errors. If DEM is employed, this
one-to-one correspondence may be broken by the element selection
block. Hence, the element selecting block selects different unit
elements to represent a certain input code. Instead of having a
fixed error for this certain input code, in a clock period a
time-varying error signal may result. For example, some of the unit
elements may have a positive contribution to the error, while
others may have a negative contribution. The element selection
logic may make this time-varying error signal to average to close
to zero over multiple clock periods. The averaged output signal may
therefore approaches an ideal output signal. In other words, errors
due to component mismatch are "whitened" in a wide frequency band
or moved out of signal band. Therefore, error may be removed by
filtering, such as via oversampling. An averaged output signal may
be a few orders of magnitude better.
[0022] An advantage of DEM is that it may work without specific
knowledge of the actual mismatch of the unit elements, in contrast
to calibration techniques that employ an exact measurement to
compensate for errors. Therefore, DEM is, in general, less
sensitive to matching variation attributable to age and
temperature, for example.
[0023] A sigma-delta modulator employing DEM DAC was first reported
in L. R. Carley and J. Kenney, "A 16-bit 4.sup.th order
noise-shaping D/A conver", in Proceeding Custom Integrated Circuit
Conference, June 1988, pp. 21.7.1-21.7.4; and L. R. Carley, "A
noise-shaping coder topology for 15+ bit converters", IEEE Journal
of Solid-State Circuits, vol. 28, no, 2, pp. 267-273, Apr. 1989. A
three-stage eight-line butterfly randomizer is used to randomly
select unit elements. The dc-error and harmonic distortion
components in this modulator are spread across the frequency band.
Thus, the tone related noise power is reduced, but the noise floor
is increased. From applying DEM DAC tp sigma-delta modulation, the
signal-to-noise-and-distortion Ratio (SNDR) is improved while the
signal-to-noise Ratio (SNR) is degraded due to the increased noise
floor.
[0024] Another approach to DEM is the Data Weighted Averaging
(DWA). DWA tries to have the elements used with substantially equal
probability for a digital input code. This is done by sequentially
selection elements from an array, beginning with the next available
unused element. Using elements at a relatively high rate may assist
in having DAC errors quickly average to zero, moving distortion to
high frequencies. It has been demonstrated that DWA provides
first-order shaping of the DAC nonlinear error. A digital dither is
employed to whiten the noise so that it may be shaped.
[0025] Some modified DWA approaches have also bee proposed, among
them are the incremental DWA (IDWA), DWA with rotated cycles, and
bi-directional data weighted averaging (biDWA). In IDWA, m extra
unit elements are added to the DAC such that during a clock cycle
at least k unit elements are not used. In this method, the drop in
performance near 0.01V.sub.REF is removed. However, a drop in the
SNDR curve now occurs for larger input amplitudes. This shows that
the location of the tones is difficult to accurately controlled and
in-band tones may still occur. In DWA with rotated cycles, the
element access cycles rotate through the elements similar to DWA,
but occasionally changes the sequence of the elements. This results
in the removal of the tones. However, if te sequence is changed too
frequently, performance will be degraded. The hardware
implementation for this method is complex. BiDWA is a modified
version of DWA. It uses two pointers, one for the even clock cycles
and the other for the odd. While the even clock cycles rotate the
used elements in one direction, the odd clock cycles rotates in the
other direction, unlike DWA that empoys one direction pointer.
Compared to DWA, biDWA involves more hardware. The in-band DAC
error of biDWA is larger than that of DWA, but the biDWA's DAC
error contains no tones or peaks. This results in a worse SNR and
SNDR, but a slightly better Spurious Free Dynamic Range (SFDR).
BiDWA also suffers from variations of the DAC error versus the
signal amplitude similar to DWA.
[0026] A second-order low-pass DEM technique, referred to as DWA
02, has also been proposed. This technique has some unit elements
contribute multiple times in one clock cycle. To implement this,
the clock period is divided into sub-periods. In a sub-period, a
specific unit element may have either a positive, negative or zero
contribution. Since contributions of the different elements involve
a certain time to be integrated within the desired accuracy, the
maximum clock speed of the converter may be degraded. Therefore,
this technique is typically not suitable for high speed converters.
However, it offers a performance improvement over DWA in low speed
sigma-delta modulators. The in-band DAC error is typically smaller
than that of DWA due to the second-order shaping.
[0027] Another DEM approach uses a tree-structure to perform the
shuffling operation of the selected unit elements of DAC. The
tree-structure for a DAC comprises unit elements and a "tree"
shaped switching network formed by multiple sub-switching blocks
and used to select these unit elements. A sub-switching block may
include a high-pass noise shaping function to generate a control
signal for subsequent switching blocks in the network. Therefore,
different shaped DAC errors may be achieved by employing different
high-pass noise shaping functions, such as first- and second-order
noise shaping. The first-order noise shaping with the
tree-structure shows similar characteristics and comparable
performance as DWA. However, DWA is typically preferred due to less
complex hardware for implementation. The second-order noise shaping
may potentially be overloaded for large input signals. If overload
occurs, second-order noise-shaped DAC can no longer obtained
usually.
[0028] In summary, DWA seems to offer good performance if DAC
nonlinearity error is first-order shaped. Due to its simplicity, it
includes an advantage of a small amount of hardware overhead and
being suitable for high speed converter. A drawback of DWA is
performance degradation if the input signal is near 0.01V.sub.REF.
Although this potentially addressed by modified DWA approaches, it
usually involves increased hardware complexity.
[0029] These DEM approaches are limited in shaping the DAC
nonlinearity error at low frequency and, therefore, are typically
limited to low-pass sigma-delta ADC. Furthermore, these approaches
do not address inherent DAC noise other than nonlinearity, such as
thermal noise, for example.
[0030] FIG. 2 is a schematic diagram illustrating a multi-bit
sigma-delta analog-to-digital conversion (ADC) structure. Multi-bit
i DAC 4 converts the digital output signal of quantizer 2 to an
analog signal. This analog signal may be subtracted from the input
signal and passes through a loop filter 1. Quantization noise
generated by quantizer 2 may be shaped out of the signal band.
However, the DAC noise cannot be shaped and may corrupt the
sigma-delta input signal. Hence, the dynamic range of the
sigma-delta modulator may be reduced.
[0031] FIG. 3 is a schematic diagram illustrating an embodiment of
a possible architecture for a sigma-delta modulator. In FIG. 3, two
signal processing blocks, 7 and 10, are inserted in the front of a
randomizing element selection logic block 8 and after DAC block 9,
respectively. HD(z) 10 is used to shape DAC noise out of signal
band. The zeros of HD(z) 10 should be located in the signal band to
reduce the in band DAC noise. HI(z) 7 in the digital domain is used
to counteract the function of HD(z) 10 in the analog domain. Hence,
the modulator output signal may be feedback through DAC 9 without
being changed by these additional blocks. Such an embodiment may be
employed in low-pass or band-pass sigma-delta modulators by
shifting the zeros of HD(z) 10 to the signal band of interest.
High-orders of HI(z) 7 and HD(z) 10 may also be employed for better
noise shaping effect.
[0032] If DAC nonlinearity error is whitened by randomly selecting
the DAC element, a linear model of a sigma-delta modulator may be
derived, such as illustrated in FIG. 4, for example. The noise of
quantizer 12 and DAC 14, shown here as Q(z) and D(z), are modelled
as additive white noise.
[0033] For example, the transfer function of the modulator may be
expressed as follows: V .function. ( z ) = H .function. ( z ) 1 + H
.function. ( z ) .times. HI .function. ( z ) .times. HD .function.
( z ) .times. U .function. ( z ) + 1 1 + H .function. ( z ) .times.
HI .function. ( z ) .times. HD .function. ( z ) .times. Q
.function. ( z ) - H .function. ( z ) .times. HD .function. ( z ) 1
+ H .function. ( z ) .times. HI .function. ( z ) .times. HD
.function. ( z ) .times. D .function. ( z ) ##EQU1##
[0034] Likewise, the transfer function of signal U(z) may be
expressed as: H s = H .function. ( z ) 1 + H .function. ( z )
.times. HI .function. ( z ) .times. HD .function. ( z )
##EQU2##
[0035] The transfer function of the quantization error may be
expressed as: H Q = 1 1 + H .function. ( z ) .times. HI .function.
( z ) .times. HD .function. ( z ) ##EQU3##
[0036] Likewise, the noise transfer function for the DAC may be
expressed as: H D = - H .function. ( z ) .times. HD .function. ( z
) 1 + H .function. ( z ) .times. HI .function. ( z ) .times. HD
.function. ( z ) ##EQU4##
[0037] If HI(z) 7 and HD(z) 10 cancelled one another,
HI(z)HD(z)=1.
[0038] Thus, the previous expressions may be rewritten as: V
.function. ( z ) = H .function. ( z ) 1 + H .function. ( z )
.times. U .function. ( z ) + 1 1 + H .function. ( z ) .times. D
.function. ( z ) - H .function. ( z ) .times. HD .function. ( z ) 1
+ H .function. ( z ) .times. E .function. ( z ) ##EQU5## H s = H
.function. ( z ) 1 + H .function. ( z ) ##EQU5.2## H Q = 1 1 + H
.function. ( z ) ##EQU5.3## H D = - H .function. ( z ) .times. HD
.function. ( z ) 1 + H .function. ( z ) ##EQU5.4## For low-pass
sigma-delta ADC, high-pass noise shaping may be applied. Thus,
HD(z) may comprise a differentiator, such as one with a transfer
function, for example, as: HD.sub.lp(z)=1-z.sup.-1 To substantially
offset HD(z), HI(z) may comprise an accumulator, such as one with a
transfer function, for example, as: HI lp .function. ( z ) = 1 1 -
z - 1 ##EQU6## Here resulting noise shaping is of first order. For
simplicity, the zero of HD(z) is placed at dc, though it may be
spread to the center of the signal band for better noise shaping
effect, for example. FIG. 5 illustrates DAC noise spectrally shaped
by such a differentiator for this particular embodiment, although,
claimed subject matter is not limited in scope to this example or
embodiment, of course.
[0039] Simulation has been employed to model an embodiment in
accordance with claimed subject matter. For example, a multi-bit
fifth-order low-pass sigma-delta modulator with a 5-bit quantizer
and 8-bit DAC is used as an example, although, of course, claimed
subject matter is not limited in scope to this particular example.
FIG. 6 shows a plot of an output power spectral density (PSD) with
a DAC produced by simulation. FIG. 7 a plot of the output PSD with
a DAC where 2% mismatch has been included. FIG. 8 shows a plot of
the output PSD with the DAC having 2% mismatch, but in which an
embodiment of spectral shaping has also been applied. Again, these
plots were generated by simulation. Inspection of these plots
illustrates performance improvement.
[0040] In a situation involving band-pass which a sampling
frequency of 4 times of a signal center frequency, f.sub.s=4
f.sub.0, is employed, a transfer function may be obtained by
substituting z with -z.sup.2 with respect to HD.sub.lp and
HI.sub.lp in the above mentioned low-pass example.
[0041] The resulting HD(z) and HI(z) may be expressed as follows:
HI bp .function. ( z ) = 1 1 + z - 2 .times. .times. and .times.
.times. HD bp .function. ( z ) = 1 + z - 2 ##EQU7## Simulation
results, for a multi-bit sixth-order band-pass sigma-delta ADC with
a 4-bit quantizer and a DAC with DEM, are shown in FIGS. 9 to 11.
FIG. 9 shows an output power spectral density (PSD) with a DAC.
FIG. 10 shows an output PSD with a DAC having 2% mismatch. FIG. 11
shows an output PSD with a DAC having 2% mismatch, but spectrally
shaped via an embodiment in accordance with claimed subject
matter.
[0042] In an alternate embodiment, spectral shaping may also be
applied to a sigma-delta DAC. FIG. 13 shows an embodiment of a
sigma-delta DAC with an embodiment of a noise shaping DAC. HD(z) 22
may be used to shape the DAC noise out of signal band, while HI(z)
19 may be used to offset the function of HD(z), so that the output
signal of the DAC would not significantly be affected by the
additional blocks, here HD(z) and HI(z). For comparison, FIG. 12
illustrates a multi-bit sigma-delta DAC without these
components.
* * * * *