U.S. patent application number 11/396622 was filed with the patent office on 2007-10-04 for contact for memory cell.
Invention is credited to Jun Liu.
Application Number | 20070232015 11/396622 |
Document ID | / |
Family ID | 38559690 |
Filed Date | 2007-10-04 |
United States Patent
Application |
20070232015 |
Kind Code |
A1 |
Liu; Jun |
October 4, 2007 |
Contact for memory cell
Abstract
A contact for memory cells and integrated circuits having a
conductive layer supported by the sidewall of a dielectric mesa,
memory cells incorporating such a contact, and methods of forming
such structures.
Inventors: |
Liu; Jun; (Boise,
ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO LLP
1825 EYE STREET, NW
WASHINGTON
DC
20006
US
|
Family ID: |
38559690 |
Appl. No.: |
11/396622 |
Filed: |
April 4, 2006 |
Current U.S.
Class: |
438/396 ;
257/E21.589; 257/E45.002 |
Current CPC
Class: |
H01L 21/76885 20130101;
H01L 45/144 20130101; H01L 45/1273 20130101; H01L 45/16 20130101;
H01L 45/1233 20130101; H01L 45/06 20130101 |
Class at
Publication: |
438/396 |
International
Class: |
H01L 21/20 20060101
H01L021/20 |
Claims
1. A contact for an integrated circuit, comprising: a mesa
structure having at least one sidewall surface and an upper planar
surface; and a conductive layer at least partially surrounding said
mesa structure on said at least one sidewall surface and having an
upper surface substantially planar with the upper planar surface of
said mesa structure.
2. The contact of claim 1, wherein the at least one sidewall
surface of said mesa structure is substantially circular and
defines a perimeter of said mesa structure.
3. The contact of claim 1, wherein said conductive layer is
substantially circular.
4. The contact of claim 1, wherein said conductive layer surrounds
said mesa structure along said at least one sidewall surface.
5. The contact of claim 1, wherein said conductive layer is
surrounded by a dielectric layer.
6. The contact of claim 1, wherein said mesa structure comprises a
nitride.
7. The contact of claim 1, wherein said mesa structure comprises an
oxide.
8. The contact of claim 1, wherein said mesa structure comprises a
material selected from the group consisting of silicon nitride,
tantalum oxide, aluminum oxide, titanium dioxide, magnesium oxide,
silicon carbide, zirconia, and strontium titanate.
9. The contact of claim 1, wherein said conductive layer comprises
at least one of titanium nitride, titanium aluminum nitride, and
tantalum nitride.
10. The contact of claim 1, wherein said contact is an electrode
for a memory cell.
11. The contact of claim 10, wherein said memory cell is a
phase-change memory cell.
12. A phase-change memory device, comprising: a phase-change memory
element positioned between a first electrode and a second
electrode; and said first electrode comprising a conductive layer
on a sidewall of a mesa structure, at least partially surrounding
said mesa structure, and having a surface in contact with said
memory element.
13. The memory device of claim 12, wherein the sidewall of said
mesa structure is substantially circular and the conductive layer
is also substantially circular.
14. The memory device of claim 12, wherein said conductive layer
surrounds said mesa structure along said sidewall.
15. The memory device of claim 14, wherein said conductive layer is
surrounded by a dielectric layer.
16. The memory device of claim 12, wherein said mesa structure
comprises a nitride.
17. The memory device of claim 12, wherein said mesa structure
comprises a material selected from the group consisting of silicon
nitride, tantalum oxide, aluminum oxide, titanium dioxide,
magnesium oxide, silicon carbide, zirconia, and strontium
titanate.
18. The memory device of claim 12, wherein said conductive layer
comprises at least one of titanium nitride, titanium aluminum
nitride, and tantalum nitride.
19. The memory device of claim 12, wherein said memory element
comprises a phase-change material.
20. A processor system, comprising: a processor and a memory
circuit, wherein said memory circuit comprises a memory device,
which comprises: a memory element positioned between a first
electrode and a second electrode; and said first electrode
comprising a conductive layer on a sidewall of a mesa structure, at
least partially surrounding said mesa structure, and having a
surface in contact with said memory element.
21. The processor system of claim 20, wherein the sidewall of said
mesa structure is substantially circular and the conductive layer
is also substantially circular.
22. The processor system of claim 20, wherein said conductive layer
surrounds said mesa structure along said sidewall.
23. The processor system of claim 22, wherein said conductive layer
is surrounded by a dielectric layer.
24. The processor system of claim 20, wherein said mesa structure
comprises a nitride.
25. The processor system of claim 20, wherein said mesa structure
comprises a material selected from the group consisting of silicon
nitride, tantalum oxide, aluminum oxide, titanium dioxide,
magnesium oxide, silicon carbide, zirconia, and strontium
titanate.
26. The processor system of claim 20, wherein said conductive layer
comprises at least one of titanium nitride, titanium aluminum
nitride, and tantalum nitride.
27. The processor system of claim 20, wherein said memory element
comprises a phase-change material.
28. A method of forming a contact for an integrated circuit,
comprising: forming a mesa structure over a substrate, said mesa
structure having at least one sidewall; forming a conductive layer
over said mesa structure and said substrate; and removing said
conductive layer from surfaces of said mesa structure and said
substrate to leave said conductive layer at least partially
surrounding said mesa on said sidewall.
29. The method of claim 28, further comprising forming a dielectric
layer over said mesa structure and said conductive layer and
planarizing said dielectric layer using said mesa structure as a
stop.
30. The method of claim 28, further comprising utilizing a hard
mask and an etching step to form said mesa structure.
31. The method of claim 30, wherein said hard mask and said mesa
structure are selectively etchable and planarized by chemical
mechanical polishing with respect to each other.
32. The method of claim 31, wherein one of said hard mask and said
mesa structure comprises an oxide and the other comprises a
nitride.
33. The method of claim 28, wherein said conductive layer is
removed using a dry etch.
34. The method of claim 28, wherein after said removing of said
conductive layer, the remaining conductive layer surrounds said
mesa structure at a sidewall thereof.
35. The method of claim 28, wherein said mesa structure is formed
to be substantially circular in shape.
36. The method of claim 28, further comprising forming a memory
cell over said contact.
37. The method of claim 36, further comprising forming a
phase-change memory element over said contact and an electrode
layer over said phase-change memory element.
38. The method of claim 28, wherein said mesa structure comprises a
material selected from the group consisting of silicon nitride,
tantalum oxide, aluminum oxide, titanium dioxide, magnesium oxide,
silicon carbide, zirconia, and strontium titanate.
39. The method of claim 28, wherein said conductive layer comprises
at least one of titanium nitride, titanium aluminum nitride, and
tantalum nitride.
40. A method of forming a memory cell, comprising: providing a
substrate; providing an electrically conductive region supported by
said substrate; forming a first dielectric layer over said
substrate and said electrically conductive region; forming a hard
mask layer over said first dielectric layer; removing a portion of
said first dielectric layer and said hard mask layer to form a mesa
structure of said first dielectric layer over said electrically
conductive region, wherein said hard mask layer remains over said
mesa structure and said mesa structure has at least one sidewall;
forming a conductive layer over said sidewall of said mesa
structure and at least a portion of said electrically conductive
region; forming a second dielectric layer over said mesa structure,
said conductive layer, and said electrically conductive region;
planarizing said second dielectric layer to expose said conductive
layer and remove said hard mask layer, using said mesa structure as
a stop; and forming a memory element layer over said conductive
layer and said mesa structure.
41. The method of claim 40, wherein said electrically conductive
region is an active area of said substrate.
42. The method of claim 40, wherein said electrically conductive
region is an interconnect line.
43. The method of claim 40, wherein said electrically conductive
region is a contact plug.
44. The method of claim 40, wherein said first dielectric layer
comprises a nitride.
45. The method of claim 40, wherein said first dielectric layer
comprises an oxide.
46. The method of claim 40, wherein said first dielectric layer
comprises a material selected from the group consisting of silicon
nitride, tantalum oxide, aluminum oxide, titanium dioxide,
magnesium oxide, silicon carbide, zirconia, and strontium
titanate.
47. The method of claim 40, wherein said hard mask layer is an
oxide.
48. The method of claim 40, wherein said hard mask is a
nitride.
49. The method of claim 40, wherein said first dielectric layer and
said hard mask layer comprise materials that are selectively
etchable and planarized by chemical mechanical polishing with
respect to each other.
50. The method of claim 40, wherein said conductive layer is
removed from surfaces, other than the sidewall of said mesa
structure, by a dry etch.
51. The method of claim 40, wherein said conductive layer comprises
at least one of titanium nitride, titanium aluminum nitride, and
tantalum nitride.
52. The method of claim 40, wherein said hard mask is removed after
forming said conductive layer by chemical mechanical polishing.
53. The method of claim 40, wherein said second dielectric layer
comprises an oxide.
54. The method of claim 40, wherein said planaraizing of said
second dielectric layer comprises a stop on nitride chemical
mechanical polishing step.
55. The method of claim 40, wherein said memory element layer
comprises a phase-change material.
56. The method of claim 40, further comprising forming an electrode
layer over said memory element layer.
57. The method of claim 40, further comprising forming a plurality
of second memory cells during the same sequence of acts as used to
form said memory cell.
58. The method of claim 40, wherein said plurality of second memory
cells have respective second conductive layers of substantially the
same shape and size as the conductive layer of said memory cell.
Description
FIELD OF THE INVENTION
[0001] The invention relates to semiconductor devices. In
particular, the invention relates to contacts for memory
devices.
BACKGROUND OF THE INVENTION
[0002] Non-volatile memories are a desirable evolution in
integrated circuit design due to their ability to maintain data
absent a power supply. Phase-change materials, as well as other
resistance variable materials, have been investigated for use in
non-volatile memory cells. Phase-change memory cells include
phase-change materials, such as chalcogenide alloys, which are
capable of stably transitioning between amorphous and crystalline
phases. Each phase exhibits a particular resistance state and the
resistance states distinguish the logic values of the memory cell.
For example, a memory element in an amorphous state exhibits a
relatively high resistance and a memory element in a crystalline
state exhibits a relatively low resistance, each of which can be
sensed as stored data.
[0003] A typical phase-change memory cell has a layer of
phase-change material between first and second electrodes. As an
example, the phase-change material can be a chalcogenide alloy,
such as Ge.sub.2Sb.sub.2Te.sub.5 or AgInSbTe. When used in a memory
device, a portion of the phase-change material is set to a
particular resistance state according to the amount of current
applied via the electrodes. To obtain an amorphous state, a
relatively high write current pulse (a reset pulse) is applied
through the phase-change cell to melt a portion of the material for
a first period of time. The current is removed and the cell cools
rapidly to a temperature below its crystallization temperature,
which results in a portion of the material having an amorphous
phase. To obtain a crystalline state, a lower current write pulse
(a set pulse) is applied to the phase-change cell for a second
period of time (typically longer in duration than the first period
of time) to heat the material to a temperature below its melting
point, but above its crystallization temperature. This causes the
amorphous portion of the material to re-crystallize to a
crystalline phase that is maintained once the current is removed
and the cell is cooled.
[0004] The typically large programming current of phase-change
memory devices is a limiting factor in reducing the memory cell
size. The programmable volume of phase-change memory cell and
programming current requirement are dependent on the area of the
bottom electrode in contact with the memory element of the cell. To
reduce such current, it is desirable to reduce the effective bottom
electrode area in contact with the cell.
[0005] One issue effecting resistance-based memory, such as phase
change memory, functionality is the non-uniformity of bottom
electrode area. Non-uniformity in bottom electrode size across a
memory array leads to non-uniformity of programming current
requirement for different memory cells of the array, which makes it
difficult to design a circuit that can accommodate the variation
between bits. Undesired variation in bottom electrode size causes
set and reset resistance distribution overlap, which, in the worst
case, makes establishing a sensing scheme for all bits of an array
impossible. Reduction in bottom electrode size should be combined
with electrode size uniformity to achieve an ideal contact for a
resistance memory device.
[0006] One technique used to reduce bottom electrode size has been
to employ anisotropically etched spacers in a via to make contacts
smaller than the photolithographic limit. This technique gives rise
to large variations in contact size since variations in chemical
mechanical polishing (CMP) and via edge rounding cause the contacts
to have different heights and cross-sections and thus different
contact areas with respect to an overlying memory element.
[0007] Another technique used to reduce bottom electrode size has
been to use ring shaped contacts. FIGS. 1a-1d show two such ring
shaped contacts 20 formed over the same substrate simultaneously,
but having different dimensions due to processing variances. FIG.
1c shows the contact 20 shown in cross section a-a' of FIG. 1a from
above. FIG. 1d shows the contact 20 shown in cross section b-b' of
FIG. 1b from above. Such contacts 20 have been formed
simultaneously by etching a via 14 into a dielectric layer 12 to
expose a conductive layer 10 (which can be over a substrate 1). A
conductive liner 16 is deposited conformally within the via 14,
along its bottom, over the conductive layer 10, and along the via's
sidewalls. Another dielectric material 18, such as silicon oxide,
is deposited over the conductive liner 16 and within the via 14. A
CMP step removes both the conductive liner 14 and dielectric
material 18, stopping in the dielectric layer 12, so that an
exposed ring of conductive liner 16 remains as a contact 20 as
shown in FIGS. 1c and 1d.
[0008] As shown in the side-by-side comparisons of the contact 20
of FIGS. 1a and 1c and the contact 20 of FIGS. 1b and 1d, ring
shaped contacts 20 formed simultaneously over the same substrate 10
can have different cross sectional areas even when the conductive
liner 16 is the same thickness in both vias 14 due to process
variations in CMP height in combination with via 14 sidewall slope
variation and rounding of via 14 edges.
[0009] There have been attempts to resolve the problems of the
prior art relating to the rounded edge of via and CMP height
variations. For example, a two-step CMP process, as shown in FIGS.
2a-2d, has been proposed where a layer of silicon oxide 12b is
formed over a layer of silicon oxynitride 12a and the contact via
14a is formed through both to an underlying conductive layer 10a.
FIG. 2c shows the contact 20a shown in cross section c-c' of FIG.
2a from above. FIG. 2d shows the contact 20a shown in cross section
d-d' of FIG. 2b from above. After forming the conformal conductive
liner 16b in the via 14a, with a conformal silicon nitride layer
16a thereunder, and a silicon oxide plug 18a over each, a first CMP
step is used to remove the conformal conductive liner 16b, the
silicon oxide plug 18a, and part of the silicon oxide layer 12a,
stopping part-way through the silicon oxide layer 12b. An etch-back
step removes the silicon oxide layer 12b and exposes the silicon
oxynitride layer 12a. A second CMP step flattens the contacts 20a
to a uniform height.
[0010] The above proposed process does potentially resolve CMP
height variation and via edge rounding issues. However, due to via
14a slope variation, the contacts 20a formed simultaneously by such
a technique will still tend to vary in size and shape, as shown by
the comparison between the contact 20a shown in FIGS. 2a and 2c and
the contact shown in FIGS. 2b and 2d, which leads to the same
programming problems as the other techniques discussed above.
[0011] It is desirable to mitigate processing variability and
provide more consistently shaped contacts for electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIGS. 1a-1d show a contact of the prior art.
[0013] FIGS. 2a-2d show a contact of the prior art.
[0014] FIGS. 3-9 show a portion of a wafer during the fabrication
of a memory cell in accordance with the invention.
[0015] FIG. 10 shows a processor system incorporating at least one
contact constructed in accordance with an embodiment of the
invention.
DETAILED DESCRIPTION
[0016] The invention relates to electrodes for memory cells. The
electrodes are formed, in part, by chemical mechanical polishing
techniques and also, in part, by selective etching techniques to
provide support mesas for ring shaped conductive layers. The
electrodes formed in accordance with the invention have more
consistently sized surface areas across an array of memory cells.
Using dielectric mesas as a support structure for the electrodes
allows surface area variation due to CMP height and via size and
curvature to be mitigated. These and other features of the
invention will be better understood from the following detailed
description, which is provided in connection with the accompanying
drawings.
[0017] Although this invention will be described in terms of
certain exemplary embodiments, other embodiments will be apparent
to those of ordinary skill in the art, which also are within the
scope of this invention. Accordingly, the scope of the invention is
defined only by reference to the appended claims.
[0018] The term "substrate" in the following description refers to
any supporting layer suitable for fabricating an integrated
circuit, typically semiconductor based, but not necessarily so. A
substrate may be silicon-based, may include epitaxial layers of
silicon supported by a base semiconductor foundation, can be
sapphire-based, silicon-on-insulator (SOI), metal, polymer, or any
other materials suitable for supporting an integrated circuit. When
reference is made to a substrate or wafer in the following
description, previous process steps may have been utilized to form
regions or junctions in or over a base semiconductor or
foundation.
[0019] Although this invention will be described primarily in
relation to phase-change memories, the invention is not limited to
such uses. The contacts and methods of forming contacts described
herein are suitable for use in any integrated circuit and would be
advantageous wherever a reduction of size or increased uniformity
in electrodes would be desirable, particularly in memory cells.
Although the invention is described in relation to a single memory
cell and the forming thereof, it can be utilized in an array of
such memory cells, which can be formed simultaneously, or in parts
of an integrated circuit not used for memory.
[0020] The invention will now be explained with reference to the
accompanying figures wherein like reference numbers are used
consistently for like features throughout the drawings. FIG. 9
shows a completed memory cell 122, which is typically one of many
like cells of a memory array, supported by a substrate 100. The
memory cell 122 is preferably a phase-change memory having a memory
element 118 made of a material that changes between an amorphous
and crystalline state in response to applied current. The memory
cell 122 can also be other memory types as well, such as a
non-phase change variable resistance chalcogenide-based memory or
other variable resistance memories. In the preferred phase-change
memory cell 122, the memory element 118 includes a chalcogenide
alloy, such as Ge.sub.xSb.sub.yTe.sub.z (where x is about 2, y is
about 2, and z is about 5) or AgInSbTe. Other phase-change
materials can be used also.
[0021] The memory cell 122 also includes a bottom electrode layer
114, which is preferably shaped like a ring, but not necessarily
so, supported by a dielectric material mesa 112. The mesa 112
structure is preferably substantially circular shaped in top view
such that it has a single, continuous sidewall; however, this is
not necessarily so and the mesa 112 can be other shapes as well,
e.g., rectangular. The bottom electrode layer 114 is preferably
titanium nitride (TiN), but can also be other conductive materials
that can be selectively removed from horizontally planar surfaces
by etching, such as titanium aluminum nitride (TiAlN) or tantalum
nitride (TaN), for example. The bottom electrode layer 114 is
configured so that it has a surface area 114a in contact with the
memory element 118 of the memory cell 122. The surface area 114a of
the bottom electrode layer 114 is determined by the thickness of
the layer 114, which is preferably about 100 .ANG., and the
interior radius "r" of the electrode ring (FIG. 8), based on the
formula .pi.(r+t).sup.2-.pi.r.sup.2 (t being the layer 114
thickness), if the electrode 114 is ring shaped. In accordance with
the invention, the surface area 114a of the bottom electrode layer
114 in contact with the memory element 118 is consistent throughout
the similar memory cells (e.g., 122) of a memory array, formed in
the same processing sequence.
[0022] The ring-shaped bottom electrode layer 114 has a surface
area 114a consistent with respective surface areas of other bottom
electrode layers of a memory array formed during the same
processing acts because CMP variations during processing are
mitigated and CMP height is controlled, and the overall surface
area 114a depends primarily on the thickness of the bottom
electrode layer 114, not on any via formation shape (FIGS. 1a-2d).
Mesa 112 size (as characterized by r; FIG. 8) is consistent across
the array because it is determined by standard photolithographic
techniques. This consistency in electrode surface area 114a
mitigates undesirable inconsistency in set and reset resistance
distributions in the operation of the memory cell 122, as compared
to conventional phase-change memory devices.
[0023] The memory cell 122 shown in FIG. 9 also has a top electrode
layer 120, which can be any conductive material known in the art as
suitable for an electrode, such as titanium nitride, for example.
The bottom electrode layer 114 is over a conductive region 104,
which can be a conductive interconnect line or a plug to an active
area of the substrate 100, for example. The conductive region 104
is in electrical communication with a voltage source for generating
the current required to operate the memory cell 122.
[0024] The memory element 118 and top electrode layer 120 provided
over the bottom electrode layer 114 and mesa 112 can be
electrically isolated from other memory cells of an array, as well
as from other parts of the same integrated circuit, by another
dielectric layer 124. This dielectric layer 124 can be any
insulating material, such as an oxide, nitride or BPSG, for
example.
[0025] A sequence of processing steps for forming a ring-shaped
electrode 114 and memory cell 122 as shown in FIG. 9 is shown in
FIGS. 3-8. FIG. 3 shows a substrate 100, which can be semiconductor
based or other materials suitable to support an integrated circuit.
A layer of dielectric material 102 is formed over the substrate
100. The dielectric material can be silicon oxide or another
insulating material. A via is formed in the dielectric layer 102
and a conductive layer 104 is formed over the dielectric layer 102
and the exposed substrate 100. The conductive layer 104 can be
polysilicon, metal, metal alloy, or other materials suitable for
use as a conductive line or plug. The conductive layer 104 and
dielectric layer 102 are planarized, for example, by CMP, using the
dielectric layer 102 as a stop. The conductive layer 104 can be a
plug to contact an underlying active region of the substrate 100 or
can be an electrical interconnect line of an integrated
circuit.
[0026] Another dielectric layer 106 is formed over the conductive
layer 104 and dielectric layer 102. This dielectric layer 106 can
be many materials, as discussed above in relation to FIG. 9, but
should be a material which can be removed or retained selectively
with respect to other dielectric materials, for instance in a
stop-on-nitride (SON) CMP procedure. For example, the dielectric
layer 106 is preferably silicon nitride (Si.sub.xN.sub.y) and is
formed to be about 1,000 .ANG.thick. Other suitable materials for
layer 106 include oxides (if a stop on oxide CMP is used in later
processing), such as tantalum oxide, aluminum oxide, titanium
dioxide, magnesium oxide. Layer 106 may also include silicon
carbide, zirconia, and strontium titanate, for examples. This layer
106 will be formed into mesas 112 in later processing (FIG. 4).
[0027] A layer of hard mask material 108 is formed over the
dielectric layer 106. If the dielectric layer 106 is silicon
nitride, the hard mask layer 108 is preferably silicon oxide so
that the dielectric layer 106 can be selectively etched relative to
the hard mask 108 and also so the hard mask 108 can be selectively
removed by CMP relative to the dielectric layer 106. Silicon oxide
and silicon nitride are materials having such characteristics for
this selectivity. It is also possible to use these materials in the
reverse order, i.e., an oxide for the dielectric layer 106 and a
nitride for the hard mask 108. Other such combinations of materials
are also possible, so long as the selective etch and selective CMP
can be used.
[0028] A layer of photoresist 110 is formed over the hard mask
layer 108. The photoresist layer 110 is patterned (see solid
portion), for example, by known photolithographic techniques, to
leave a mask to define the area where a mesa 112 is to be formed
(FIG. 4). A dry etch step transfers the pattern into the hard mask
layer 108 and the photoresist 110 is stripped. Another etching step
removes the dielectric layer 106 that is not protected by the hard
mask layer 108, stopping at the conductive layer 104 and dielectric
layer 102. This will leave a mesa 112 with the hard mask layer 108
there over, as shown in FIG. 4. The mesa 112 can be any shape, with
round or substantially round in top view being preferred.
[0029] A layer of conductive material 114 is formed over the mesa
112, conductive layer 104, and dielectric layer 102. This layer 114
will eventually become the bottom electrode layer 114 shown in FIG.
9. Titanium nitride is preferred for layer 114 and it is preferably
about 100 .ANG. thick. The conductive layer 114 can be other
materials also, for example, titanium aluminum nitride (TiAlN) or
tantalum nitride (TaN). The conductive material of layer 114 can be
different and the thickness varied to suit performance demands.
[0030] Now referring to FIG. 5, a dry etch removes the conductive
material of layer 114 from horizontal surfaces of the wafer. The
conductive material of layer 114 is removed from over the
dielectric layer 102, from over a portion of the conductive layer
104, and from over the hard mask layer 108. The conductive layer
114 is left on the sides of the mesa 112 so as to become a ring
shaped bottom electrode (FIG. 8). The dry etch can be a CF.sub.4,
Cl.sub.2 or Cl.sub.2/CF.sub.4 plasma etch, for example.
[0031] FIG. 6 shows that another dielectric layer 116 is formed
over the mesa 112, the bottom electrode layer 114, and hard mask
layer 108. When the mesa 112 is a nitride and the hard mask layer
108 is an oxide, the dielectric layer 116 should be an oxide. The
dielectric layer 116 should have CMP selectivity characteristics
similar to the hard mask layer 108, regardless of the specific
materials used for any layers. The dielectric layer 116 can be
deposited by high density plasma (HDP), which is a chemical vapor
deposition (CVD) process, so as to provide a good gap fill. Other
CVD processes can be used as well, such as PECVD (plasma enhanced),
LPCVD (low pressure), and ALD (atomic layer deposition). The
dielectric layer 116 is preferred to be at least 500 .ANG. thicker
than the mesa 112 above the substrate 100, so when the mesa 112 is
about 1,000 .ANG. thick, the dielectric layer should be about 1,500
.ANG. thick, measured from over the dielectric layer 102.
[0032] FIG. 7 shows the wafer after an SON CMP (stop on nitride
CMP). The dielectric layer 116, hard mask 110, and possibly some of
the bottom electrode layer 114 are removed to planarize the wafer,
stopping once the mesa 112 material is reached. If the mesa 112 is
some material other than a nitride, a different selective CMP can
be used to planarize the wafer, but still stopping at the mesa 112.
FIG. 8 shows the wafer of FIG. 7 from above (FIG. 7 shows the wafer
through cross section e-e' of FIG. 8). As shown in FIG. 8, the
planarization by CMP leaves the bottom electrode layer 114 as a
ring-shaped structure surrounding the mesa 112 (dielectric material
106) and the electrode layer 114 is surrounded by the dielectric
layer 116. FIG. 8 shows the ring-shaped bottom electrode layer 114
and mesa 112 being substantially round in shape, however, such is
not necessary and any shape can be used.
[0033] FIG. 9 shows the formation of a completed memory cell 122,
as discussed above. A memory element 118 is formed over the bottom
electrode layer 114 and mesa 112. If the memory cell 122 is to be a
phase-change memory, a chalcogenide based material, such as, for
example, Ge.sub.xSb.sub.yTe.sub.z or
Ag.sub.aIn.sub.bSb.sub.cTe.sub.d, is deposited as a layer over the
wafer and physically defined to form memory element 118. The memory
element 118 layer can be deposited by sputtering, evaporation, or
other techniques. Over the memory element 118 layer, a top
electrode layer 120 is deposited. The top electrode layer 120 is a
conductive material, but is not limited to any specific material;
it can be titanium nitride, polysilicon, tungsten, TiW, gold, or
aluminum, for example. The memory element 118 layer and top
electrode layer 120 can be blanket deposited, patterned and etched
together to leave a stack structure over the bottom electrode layer
114 and mesa 112. The memory element 118 is in contact with the
bottom electrode layer 114 at the electrode's surface area 114a. An
insulating and protective dielectric layer 124 can then be formed
over the memory cell 122.
[0034] FIG. 10 illustrates a simplified processor system 400 which
includes a memory circuit 448, e.g., a phase-change memory device,
which employs resistance variable memory devices (e.g., memory cell
122) fabricated in accordance with the invention, having
ring-shaped electrode contacts 114 (FIG. 7-9). A processor system,
such as a computer system, generally comprises a central processing
unit (CPU) 444, such as a microprocessor, a digital signal
processor, or other programmable digital logic devices, which
communicates with an input/output (I/O) device 446 over one or more
bus and/or bridge structures 452. The memory circuit 448
communicates with the CPU 444 over bus/bridge 452 typically through
a memory controller.
[0035] In the case of a computer system, the processor system may
include peripheral devices such as a hard disk drive 454 and a
compact disc (CD) ROM drive 456, which also communicate with CPU
444 over the bus 452. Memory circuit 448 is preferably constructed
as an integrated circuit, which includes one or more resistance
variable memory devices, e.g., device 122. If desired, the memory
circuit 448 may be combined with the processor, for example CPU
444, in a single integrated circuit.
[0036] Various embodiments of the invention have been described
above. Although this invention has been described with reference to
these specific embodiments, the descriptions are intended to be
illustrative of the invention and are not intended to be limiting.
Various modifications and applications may occur to those skilled
in the art without departing from the spirit and scope of the
invention as defined in the appended claims.
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