U.S. patent application number 11/750830 was filed with the patent office on 2007-09-27 for structure and method of three dimensional hybrid orientation technology.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Oh-jung KWON.
Application Number | 20070224754 11/750830 |
Document ID | / |
Family ID | 37064236 |
Filed Date | 2007-09-27 |
United States Patent
Application |
20070224754 |
Kind Code |
A1 |
KWON; Oh-jung |
September 27, 2007 |
STRUCTURE AND METHOD OF THREE DIMENSIONAL HYBRID ORIENTATION
TECHNOLOGY
Abstract
A method and device for increasing pFET performance without
degradation of nFET performance. The method includes forming a
first structure on a substrate using a first plane and direction
and forming a second structure on the substrate using a second
plane and direction. In use, the device includes a nFET stack on a
substrate using a first plane and direction, e.g., (100)<110>
and a pFET stack on the substrate using a second plane and
direction, e.g., (111)/<112>. An isolation region within the
substrate is provided between the nFET stack and the pFET
stack.
Inventors: |
KWON; Oh-jung; (Hopewell
Junction, NY) |
Correspondence
Address: |
GREENBLUM & BERNSTEIN, P.L.C.
1950 ROLAND CLARKE PLACE
RESTON
VA
20191
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
10504
|
Family ID: |
37064236 |
Appl. No.: |
11/750830 |
Filed: |
May 18, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10907622 |
Apr 8, 2005 |
|
|
|
11750830 |
May 18, 2007 |
|
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Current U.S.
Class: |
438/224 ;
257/E21.632; 257/E21.633; 257/E21.634; 257/E21.635; 257/E21.643;
257/E29.052; 257/E29.158; 257/E29.162 |
Current CPC
Class: |
H01L 29/495 20130101;
H01L 21/823814 20130101; H01L 21/823807 20130101; H01L 29/51
20130101; H01L 21/823885 20130101; H01L 29/1037 20130101; H01L
21/823828 20130101 |
Class at
Publication: |
438/224 ;
257/E21.632 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238 |
Claims
1. A method of manufacturing a semiconductor structure, comprising
forming a first structure from a poly layer on a substrate using a
first plane and direction and forming a second structure from the
poly layer on the substrate using a second plane and direction.
2. The method of claim 1, wherein the first structure is a stack
for a nFET and the second structure is a stack for a pFET.
3. The method of claim 1, wherein the first plane and direction
differ from the second plane and direction and the first structure
and the second structure are formed simultaneously.
4. The method of claim 3, wherein the first plane and direction is
(100)/<110> and the second plane and direction is
(111)/<112>.
5. The method of claim 1, wherein forming the second structure on
the substrate using a second plane and direction comprises etching
the substrate to form an angled sidewall and building the second
structure at least partially on the angled sidewall.
6. The method of claim 5, wherein forming the angled sidewall
comprises an anisotropic etching of the substrate at an active area
of a pFET.
7. The method of claim 5, wherein forming the angled sidewall
comprises etching the substrate to result in an angled of
approximately 57.5 degrees from a plane of the substrate.
8. The method of claim 5, wherein the forming of the angled
sidewall comprises etching through an oxide layer deposited over
the substrate, a block material deposited over the oxide layer and
into the substrate.
9. The method of claim 8, further comprising: etching a photoresist
deposited over the block material, performing a selective etch of
the block material using the oxide layer as a etch stop layer to
form an etched area; stripping the photoresist layer; forming a
spacer in the etched area; and anisotropic etching the substrate to
a depth of approximately 200 .ANG. to 900 .ANG. to form a trench in
the substrate which has the angled sidewall.
10. The method of claim 1, wherein forming the first structure and
the second structure comprises: forming at least one n-well and one
p-well for pFET and nFET devices, respectively; depositing a gate
dielectric on a surface of the substrate including in a trench with
an angled sidewall with respect to a plane of the surface of the
substrate, the trench is formed in an active area of the pFET;
depositing the poly layer over the gate dielectric; etching
portions of the poly layer to form a nFET stack comprising the
first structure on a plane of the substrate and a pFET stack
comprising the second structure on the angled sidewall of the
trench; forming spacers on sidewalls of the nFET stack and the pFET
stack; and doping source and drain regions in the substrate for
nFET and pFET devices on sides of the nFET stack and the pFET
stack, respectively.
11. The method of claim 10, wherein the pFET stack and the nFET
stack are in a (111) plane and a <112> direction and in a
(100) plane and <110> direction.
12. A method of manufacturing a semiconductor device, comprising:
building a nFET stack on a gate dielectric layer on a substrate in
a first plane and direction; building a pFET stack on the gate
dielectric layer on the substrate in a second plane and direction,
which is different from the first plane and direction; and
providing an isolation region within the substrate between the nFET
stack and the pFET stack.
13. The method of claim 12, wherein the first plane and direction
is (100)/<110> and the second plane and direction is
(111)/<112>.
14. The method of claim 12, wherein forming the pFET stack
comprises etching the substrate to form a trench with an angled
sidewall and building the pFET stack at least partially on the
angled sidewall.
15. The method of claim 14, wherein forming the angled sidewall
comprises anisotropic etching of the substrate using basic wet
chemicals at an active area of a pFET.
16. The method of claim 14, wherein the angled sidewall is etched
at an angle of approximately 57.5 degrees from a plane of the
substrate.
17. The method of claim 14, wherein the forming of the angled
sidewall comprises: etching through an oxide layer deposited over
the substrate, a block material deposited over the oxide layer
using the oxide layer as a etch stop layer to form an etched area;
stripping a photoresist deposited over the block material after
etching the block material, forming a spacer in the etched area;
and anisotropic etching the substrate using wet chemicals to a
depth of approximately 200 .ANG. to 900 .ANG. to form the trench in
the substrate having the angled sidewall.
18. The method of claim 14, wherein forming the nFET stack and the
pFET stack comprises: forming at least one n-well and one p-well
for pFET and nFET, respectively; depositing the gate dielectric
layer on a surface of the substrate including in the trench with an
angled sidewall with respect to a plane of the surface of the
substrate, the trench being formed in an active area of the pFET;
depositing a poly layer over the gate dielectric layer; etching
portions of the poly layer to form the nFET stack and the pFET
stack on the angled sidewall of the trench using an isolation
region as a basis for alignment; forming spacers on sidewalls of
the nFET stack and the pFET stack; implanting extensions in the
substrate on the side of the nFET stack and the pFET stack; and
doping source and drain regions in the substrate for nFET and pFET
on sides of the nFET stack and the pFET stack, respectively.
19. A method of manufacturing a semiconductor structure,
comprising: depositing a gate dielectric layer on a substrate;
depositing a poly layer on the gate dielectric layer on the
substrate; and forming a nFET structure from the poly layer on the
gate dielectric layer on the substrate in a first plane and
direction; and forming a pFET structure from the poly layer on the
gate dielectric layer on the substrate in a second plane and
direction, which is different from the first plane and
direction.
20. The method of claim 19, wherein the nFET structure and the pFET
structure are formed simultaneously.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/907,622, filed Apr. 8, 2005, the disclosure of which is
expressly incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to semiconductor devices, and more
particularly to semiconductor devices having increased pFET
performance without degradation of the nFET performance and a
method of manufacture.
[0004] 2. Background Description
[0005] Field effect transistors (FET's) are a fundamental building
block in the field of integrated circuits. FET's can be classified
into two basic structural types: horizontal and vertical.
Horizontal, or lateral, FET's exhibit carrier flow from source to
drain in a direction parallel (e.g., horizontal) to the plane of
the substrate and vertical FET's exhibit carrier flow from source
to drain in a direction transverse to the plane of the substrate
(e.g., vertical) on which they are formed. FET structures may
include a single gate (e.g., for forming a single channel) or a
pair of gates (e.g., for forming a pair of channels), with
double-gate versions providing an advantage of an increased current
carrying capacity (e.g. typically greater than twofold over the
single-gate versions).
[0006] A FET typically consists of source and drain electrodes
interconnected by semiconductor material. Conduction between the
drain and source electrodes occurs basically within the
semiconductor, and the length between the source and drain is the
conduction channel. In particular, the output current is inversely
proportional to the channel length, while the operating frequency
is inversely proportional to the square of the channel length.
[0007] The basic metal-oxide-semiconductor field-effect transistor
(MOSFET) structure has a so-called "flat design". A nFET structure
is a four-terminal device and consists of a p-type semiconductor
substrate, into which two n-regions, a source electrode and drain
electrode are formed (e.g., by ion implantation). The metal contact
on the insulator is a gate. Heavily doped polysilicon or a
combination of silicide and polysilicon can also be used as the
gate electrode.
[0008] The basic device parameters are the channel length L, which
is the distance between the two metallurgical n-p junctions, the
channel width W, the gate oxide thickness t, the junction depth,
and the substrate doping. When voltage is applied to the gate, the
source-to-drain electrodes correspond to two p-n junctions
connected back to back. The only current that can flow from source
to drain is the reverse leakage current. When a sufficiently
positive bias is applied to the gate so that a surface inversion
layer (or channel) is formed between the two n-regions, the source
and the drain are connected by the conducting surface of the
n-channel through which a current can flow.
[0009] It is known, though, that the nFETs are optimized in the
horizontal plane of the substrate. That is, the electron mobility
across the channel is optimized when the nFET is fabricated on the
100 plane and the 110 direction. This is a typical flat structure
fabrication. The pFET device, on the other hand, has significantly
decreased performance characteristics when it is fabricated on the
100 plane and the 110 direction; namely, the hole mobility is
significantly decreased, thereby degrading the performance of the
entire device. However, it is typical in semiconductor fabrication
to build both the nFET and pFET structures in the 100 plane and the
110 direction, using well-known processes.
SUMMARY OF THE INVENTION
[0010] In a first aspect of the invention, a method of fabricating
a semiconductor structure comprising forming a first structure on a
substrate using a first plane and direction and forming a second
structure on the substrate using a second plane and direction.
[0011] In another aspect of the invention, a method of
manufacturing a semiconductor device comprising building a nFET
stack on a substrate using a first plane and direction and building
a pFET stack on the substrate using a second plane and direction,
different from the first plane and first direction. The method
further includes providing an isolation region within the substrate
between the nFET stack and the pFET stack.
[0012] In another aspect of the invention, a semiconductor
structure includes a nFET stack on a substrate using a first plane
and direction and a pFET stack on the substrate using a second
plane and direction, different from the first plane and first
direction. An isolation region within the substrate is provided
between the nFET stack and the pFET
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIGS. 1-15 illustrates steps in manufacturing a device in
accordance with the invention; and
[0014] FIG. 16 illustrates a final structure and manufacturing in
accordance with the invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0015] The invention is directed to semiconductor structures and
more particularly to semiconductor structures and methods of
manufacture using three dimensional hybrid orientation
technologies. In one aspect of the invention, the performance of a
pFET is improved or optimized by increasing carrier mobility for
the pFET without any degradation in the performance of the nFET. To
accomplish the invention, the nFET is formed in a first
plane/direction and the pFET is formed in a second plane/direction
using similar processing steps. For example, in one non-limiting
aspect of the invention, the nFET will be formed in the
(100)/<110> plane/direction and the pFET will be formed in
the (111)/<112> plane/direction. In this manner, the channel
length of the pFET may be longer than the channel length of nFET
using the same processes. The invention is compatible with CMOS
technologies such as, for example, SOI, strained Si, dual spacer
and the like.
[0016] FIG. 1 shows a beginning structure in accordance with the
invention. In this structure, a shallow trench isolation structure
(STI) 12 is formed in a substrate 10 having a (100) plane. In one
exemplary illustration, the depth of the STI 12 is between 2000
.ANG.-5000 .ANG., depending on the required device performance. The
depth of the STI 12 may be shallower in SOI process technologies.
In the embodiment described herein, a nFET will be formed on one
side of the STI 12 and a pFET will be formed on an opposing side of
the STI 12.
[0017] By an exemplary illustration, the STI 12 may be formed by
depositing a pad oxide and pad nitride over the substrate 10. A
photo mask or a hard mask is formed over the pad nitride and an
etching process etches to the substrate through the formed layers.
An additional etching process etches into the substrate to form the
trench. An oxide, for example, is deposited in the trench to fill
the trench. The surface is planarized using a chemical mechanical
polishing (CMP) process. The pad nitride may then be removed,
resulting in the structure of FIG. 1.
[0018] FIG. 2 represents a well implantation process. In one
implementation, the p-well is doped using boron, which later forms
part of the nFET. The n-well may be doped with phosphorous, which
later forms part of the pFET. The doping is performed using
well-known processes in the industry.
[0019] In FIG. 3, an oxide material 14 is formed over the substrate
10 using well-known processes such as, for example, thermal
oxidation or chemical vapor deposition. In one aspect of the
invention, the oxide layer 14 is approximately 10 .ANG. to 100
.ANG. in thickness; although other thickness or dimensions are
contemplated by the invention. A block material 16 such as nitride
is deposited over the oxide layer 14 using a CVD process, for
example. The block material 16 may be in the range of 200 .ANG. to
2000 .ANG., although other thickness and dimensions are also
contemplated for use with the invention. A photoresist 18 is
deposited over the block material 16. After patterning, only pFET
region is opened for subsequent anisotropic etching.
[0020] FIG. 4 is representative of a selective anisotropic etch of
the block material 16. In this process, the etching is selective to
the nitride block layer 16, and the oxide layer 14 acts as a etch
stop layer. In this process, an etched area 20 is formed in the
block material 16.
[0021] The photoresist layer 18 is then stripped using a dry
stripping process, for example (FIG. 5). In FIG. 6, a spacer
nitride deposition and etching process is performed. In this
process, spacers 22 are formed in the etched area 20 to reduce the
spacing and smooth the active area of the to be formed pFET.
Forming spacer nitride may be skipped if the etched area 20 is
controllable by litho process in FIG. 3.
[0022] Referring to FIG. 7, the oxide layer 14 is then removed in
the etched area 20 using, for example, a wet etch process. This wet
etch process may utilize, for example, diluted HF. A preferential
etching process is then performed in the substrate using for
example a KOH, or ammonia. This etching step is an anisotropic
etching which, in non-limiting embodiments, etches to a depth of
200 .ANG. to 900 .ANG., although other etching depths and
dimensions are contemplated by the invention depending on the
device requirements. In one aspect of the invention, the etched
area, which forms a trench 24, will have a smooth transition with
the STI 12; however, it is contemplated by the invention that a
stepped portion can be present between the STI 12 and the etched
trench 24.
[0023] FIG. 8 represents one embodiment of the etch geometry as
discussed with reference to FIG. 7. In this non-limiting
embodiment, an anisotropic wet etch is used to etch in the
substrate 100, forming a sidewall 24a having an angle of
approximately 57.5.degree. with respect to the plane (100) of the
substrate 10.
[0024] In FIG. 9, the nitride block material 16 is removed using
well-known hot phosphoric acid etching. It is well-known that hot
phosphoric acid etches only nitride without loss of oxide and
silicon. The oxide layer 14 may be removed.
[0025] Referring to FIG. 10, after the etching of the nitride block
and the oxide layer, a gate dielectric 26 is formed on the surface
of the substrate 10, including in the trench 24. The gate
dielectric 26 may be an oxide, oxynitride or high-K material, for
example. In one example, the gate dielectric 26 may be
approximately 10 .ANG. to 100 .ANG.. A poly 28 is deposited over
the gate dielectric 26. In case of high-K material, metallic
electrode can be deposited over the high-K material.
[0026] FIG. 11 shows the formation of the beginning structures
(e.g., stacks) of the nFET and the pFET. In this process, the poly
28 is etched in well-known processes such as lithography and poly
RIE. The STI 12 may be used as a basis for alignment of the pFET
stack as should be understood to those of ordinary skill in the
art, i.e., to ensure that the formation of the pFET stack is formed
on the angled sidewall 24a. In this manner, the pFET stack 28a will
be formed in the (111) plane and a <112> direction; whereas,
the nFET 28b stack will be formed in the (100) plane and
<110> direction, simultaneously.
[0027] FIG. 12 shows a spacer 30 formation. Depending on the
particular requirements, the spacers 30 may be a nitride or an
oxide. The spacers 30 are formed in processes well-known in the art
to those of skill such that further discussion is not required
herein for a complete understanding of the invention. Extension
implantation is performed, as representative of the steps of FIG.
13. In this process, phosphorous or arsenic may be implanted for
the nFET and boron may be implanted for the pFET.
[0028] FIG. 14 is representative of a spacer 32 formation on the
sides of the stacks 28a and 28b of the pFET and nFET, respectively.
It is also contemplated that different material can be used as 28a
and 28b respectively for improving device performance. Some nitride
with tensile stress for nFET and other nitride with compressive
stress for pFET will be one of the examples. In one non-limiting
aspect of the invention, the spacers 32 are formed of nitride using
processes well-known in the art to those of skill such that further
discussion is not required for a complete understanding of the
invention. FIG. 15 represents the source/drain formation for both
the nFET and pFET. Again, the processes for forming the
source/drain regions are well known in the art to those of skill
such that further discussion is not required for a complete
understanding of the invention.
[0029] FIG. 16 illustrates the final structure of the device in
accordance with the invention. In FIG. 16, metal contacts 34 are
formed to the source drain/regions of the nFET and pFET. In one
exemplary process, a RIE process is used to etch the inter layer
dielectric 35 and the gate dielectric. A metal is then deposited to
fill the contact hole such as, for example, tungsten. TiN may be
used to form the barrier material between source/drain and metal
contact prior to tungsten deposition, as one illustrative example.
As represented in FIG. 16, the resultant pFET stack is formed in
the (111) plane and carrier transport direction is the <112>
direction as a result of the etching step formed in FIG. 6, in
addition to the remaining stack formation steps. Also, the nFET
stack is formed in the (100) plane and carrier transport direction
is <110> direction.
[0030] It has been found that the hole mobility for a pFET in the
(111) plane and <112> direction is superior than in the (100)
plane and <110> direction, but worse than in the (110) plane
and <110> direction; whereas, the electron mobility for a
nFET in the (111) plane and <112> direction is worse than in
the (100) plane and <110> direction, but superior than in the
(110) plane and <110> direction. To thus optimize the pFET
performance without degrading the nFET performances, in the present
invention, the pFET is formed in the (111) plane and the
<112> direction and the nFET is optimized in the (100) plane
and the <110> direction.
[0031] While the invention has been described in terms of exemplary
embodiments, those skilled in the art will recognize that the
invention can be practiced with modifications and in the spirit and
scope of the appended claims.
* * * * *