U.S. patent application number 11/680596 was filed with the patent office on 2007-09-27 for method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry.
This patent application is currently assigned to University of Southern California. Invention is credited to Adam L. Cohen.
Application Number | 20070221505 11/680596 |
Document ID | / |
Family ID | 29420501 |
Filed Date | 2007-09-27 |
United States Patent
Application |
20070221505 |
Kind Code |
A1 |
Cohen; Adam L. |
September 27, 2007 |
Method of and Apparatus for Forming Three-Dimensional Structures
Integral With Semiconductor Based Circuitry
Abstract
Enhanced Electrochemical fabrication processes are provided that
can form three-dimensional multi-layer structures using
semiconductor based circuitry as a substrate. Electrically
functional portions of the structure are formed from structural
material (e.g. nickel) that adheres to contact pads of the circuit.
Aluminum contact pads and silicon structures are protected from
copper diffusion damage by application of appropriate barrier
layers.
Inventors: |
Cohen; Adam L.; (Los
Angeles, CA) |
Correspondence
Address: |
MICROFABRICA INC.;ATT: DENNIS R. SMALLEY
7911 HASKELL AVENUE
VAN NUYS
CA
91406
US
|
Assignee: |
University of Southern
California
|
Family ID: |
29420501 |
Appl. No.: |
11/680596 |
Filed: |
February 28, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10434292 |
May 7, 2003 |
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11680596 |
Feb 28, 2007 |
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60379183 |
May 7, 2002 |
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Current U.S.
Class: |
205/135 ;
205/118; 257/E21.175; 257/E21.508; 257/E21.589; 257/E23.021 |
Current CPC
Class: |
C25D 5/022 20130101;
H01L 2924/01073 20130101; H01L 2924/00 20130101; B81C 1/00246
20130101; H01L 2224/13099 20130101; B81C 2201/019 20130101; B81C
1/00126 20130101; H01L 2924/3025 20130101; H01L 2924/01029
20130101; H01L 24/11 20130101; H01L 2924/01047 20130101; H01L
2224/13 20130101; H01L 21/2885 20130101; H01L 2924/01013 20130101;
H01L 24/13 20130101; H01L 2924/0103 20130101; H01L 2924/01015
20130101; H01L 2924/01079 20130101; H01L 2924/04953 20130101; C25D
1/003 20130101; H01L 2924/01039 20130101; H01L 2924/01005 20130101;
H01L 2924/01006 20130101; B81C 2201/053 20130101; H01L 2924/04941
20130101; H01L 2924/01022 20130101; H01L 2924/01078 20130101; H01L
2924/14 20130101; H01L 2224/13 20130101; H01L 24/10 20130101; B81C
2203/0735 20130101; H01L 2924/01011 20130101; H01L 2924/01027
20130101; H01L 2924/01019 20130101; H01L 2924/01033 20130101; H01L
21/76885 20130101 |
Class at
Publication: |
205/135 ;
205/118 |
International
Class: |
C25D 5/02 20060101
C25D005/02 |
Goverment Interests
GOVERNMENT SUPPORT
[0002] This invention was made with Government support under Grant
Numbers DABT63-97-C-0051 and DABT63-99-C0042 awarded by DARPA. The
Government has certain rights.
Claims
1. An electrochemical fabrication process for producing a
three-dimensional structure from at least one structural material
on a semiconductor wafer, or portion thereof, from a plurality of
adhered layers formed from at least one structural material and at
least one sacrificial material, the process comprising: (A)
supplying a substrate, which comprises a semiconductor wafer, or
portion thereof, containing electrical circuitry and having contact
pads to which a first structural material is to connect, wherein
the substrate may comprise previously deposited material and
wherein forming a connection between the contact pads and the first
structural material comprises in order: (a) placing a protective
coating over the contact pads; (b) applying the first sacrificial
material to a surface of the substrate, (c) removing the protective
coating from the contact pads; and (d) applying the first
structural material to the contact pads; and (B) forming a
plurality of layers, with the first layer of the plurality of
layers being formed on the first sacrificial material and on the
first structural material, such that successive layers are formed
adjacent to and adhered to previously formed layers, wherein the
formation of at least some of the plurality of layers includes a
selective depositing operation which deposits at least one of a
second structural material or a second sacrificial material;
wherein at least a plurality of the selective depositing operations
comprise: (1) locating a selected preformed contact mask on or in
proximity to a previously formed layer; (2) in presence of a
plating solution, conducting an electric current between an anode
and the previously formed layer through at least one opening in the
mask such that a selected deposition material, selected from the
second structural material and the second sacrificial material, is
deposited onto the previously formed layer to form at least a
portion of a layer; and (3) separating the selected preformed
contact mask from the previously formed layer.
2. The process of claim 1 wherein the applying of the first
sacrificial material in (b) is thin compared to a desired coating
thickness, and wherein after (b) and before (c), the process
additionally comprises: (b2) thickening the applied layer of
sacrificial material to many times its original thickness via
electroplating.
3. The process of claim 2, wherein after performance of (b2) and
before (c), the process additionally comprises: (b3) planarizing
the sacrificial material of (b2) and the protective coating of
(a).
4. The process of claim 3, wherein after performance of (d), the
process additionally comprises: (e) planarizing the first
structural material of (d) and sacrificial material of (b2).
5. The process of claim 1 additionally comprising: supplying a
plurality of preformed contact masks, wherein each preformed
contact mask comprises a patterned dielectric material that
includes at least one opening through which the deposition of the
selected deposition material can take place during the formation of
at least a portion of a layer, and wherein each preformed contact
mask comprises a support structure that supports the patterned
dielectric material; and wherein the locating of the selected
preformed contact mask on or in proximity to the previously formed
layer comprises contacting the previously formed layer and the
dielectric material of the selected preformed contact mask.
6. The process of claim 1 wherein prior to (d), the process
additionally comprises applying a transition material to the
contact pads.
7. The process of claim 6 wherein the applying of the transition
material comprises application of an adhesion promoter.
8. The process of claim 6 wherein the applying of the transition
material comprises application of a diffusion barrier.
9. An electrochemical fabrication process for producing a
three-dimensional structure from at least one structural material
on a semiconductor wafer, or portion thereof, from a plurality of
adhered layers formed from at least one structural material and at
least one sacrificial material, the process comprising: (A)
supplying a substrate which comprises a semiconductor wafer, or
portion thereof, containing electrical circuitry and having contact
pads to which a first structural material is to connect, wherein
the substrate may comprise previously deposited material and
wherein forming a connection between the contact pads and the first
structural material comprises, in order: (a) depositing a first
sacrificial material onto a surface of the substrate in regions
excluding contact pad regions; and (b) depositing the first
structural material to at least selected contact pad regions; and
(B) forming a plurality of layers, with the first layer of the
plurality of layers being formed on the first sacrificial material
and on the first structural material, such that successive layers
are formed adjacent to and adhered to previously formed layers,
wherein the formation of at least some of the plurality of layers
includes a selective depositing operation which deposits at least
one of a second structural material or a second sacrificial
material; wherein at least a plurality of the selective depositing
operations comprise: (1) locating a selected preformed contact mask
on or in proximity to a previously formed layer; (2) in presence of
a plating solution, conducting an electric current between an anode
and the previously formed layer through at least one opening in the
mask such that a selected deposition material, selected from the
second structural material and the second sacrificial material, is
deposited onto the previously formed layer to form at least a
portion of a layer; and (3) separating the selected preformed
contact mask from the previously formed layer;
10. The process of claim 9 wherein prior to performance of (a), the
process additionally comprises placing a protective coating over
the contact pads.
11. The process of claim 10 wherein after performance of (a), the
process additionally comprises removing the protective coating from
at least selected contact pads.
12. The process of claim 10 wherein (a) comprises depositing the
first sacrificial material to a thickness less than a desired
thickness using a first deposition operation and then increasing
the thickness of the deposited first sacrificial material using a
second deposition operation.
13. The process of claim 12 wherein the first deposition operation
comprises a non-electroplating operation and wherein the second
deposition operation comprises an electroplating operation.
14. The process of claim 9 wherein after depositing the first
sacrificial material of (a) and depositing the first structural
material of (b), planarizing the deposited materials to yield a
modified substrate comprising selective regions of the first
sacrificial material and the first structural material on to which
additional layers of the second structural material and the second
sacrificial material will be deposited.
15. The process of claim 9 additionally comprising, prior to (b),
applying a transition material to the contact pad regions.
16. The process of claim 15 wherein the applying of the transition
material comprises applying an adhesion promoter.
17. The process of claim 15 wherein the applying of the transition
material comprises applying a diffusion barrier.
18. The process of claim 9 wherein the first structural material
deposited in (b) comprises nickel.
19. The process of claim 9 wherein the first sacrificial material
deposited in (a) comprises copper.
20. The process of claim 9 additionally comprising: supplying a
plurality of preformed contact masks, wherein each preformed
contact mask comprises a patterned dielectric material that
includes at least one opening through which the deposition of the
selected deposition material can take place during the formation of
at least a portion of a layer, and wherein each preformed contact
mask comprises a support structure that supports the patterned
dielectric material; and wherein the locating of the selected mask
on or in proximity to the previously formed layer comprises
contacting the previously formed layer and the dielectric material
of the selected preformed contact mask.
21. An electrochemical fabrication process for producing a
three-dimensional structure from at least one structural material
on a semiconductor wafer, or portion thereof, from a plurality of
adhered layers formed from at least one structural material and at
least one sacrificial material, the process comprising: (A)
supplying a substrate which comprises a semiconductor wafer, or
portion thereof, containing electrical circuitry and having contact
pads to which a first structural material is to connect, wherein
the substrate may comprise previously deposited material and
wherein forming a connection between the contact pads and the first
structural material comprises in order: (a) locating an electroless
plating catalyst for the first sacrificial material on at least a
portion of the surface of a passivation layer on the semiconductor
wafer, or portion thereof; (b) electroless plating the first
sacrificial material on to the passivation layer; and (c) applying
the first structural material over the contact pads; and (B)
forming a plurality of layers, with the first layer of the
plurality of layers being formed on the first sacrificial material
and on the first structural material, such that successive layers
are formed adjacent to and adhered to previously formed layers,
wherein the formation of at least some of the plurality of layers
includes a selective depositing operation which deposits at least
one of a second structural material or a second sacrificial
material; wherein at least a plurality of the selective depositing
operations comprise: (1) locating a selected preformed contact mask
on or in proximity to a previously formed layer; (2) in presence of
a plating solution, conducting an electric current between an anode
and the previously formed layer through at least one opening in the
mask such that a selected deposition material, selected from the
second structural material and the second sacrificial material, is
deposited onto the previously formed layer to form at least a
portion of a layer; and (3) separating the selected preformed
contact mask from the previously formed layer.
22. The process of claim 21 wherein the first sacrificial material
of (b) comprises copper.
23. The process of claim 21 wherein the structural material of (c)
comprises nickel.
24. The process of claim 21 wherein the applying of the first
structural material of (c) comprises electroplating the first
structural material.
25. The process of claim 21 wherein after performance of (b), the
process additionally comprises: (b2) increasing the thickness of
the first sacrificial material of (b) by electroplating additional
sacrificial material onto the electroless plated first sacrificial
material.
26. The process of claim 25 wherein after performance of (c), the
process additionally comprises: (d) planarizing the deposited
sacrificial material of (b2) and first structural material of
operation (c).
27. The process of claim 21 additionally comprising: supplying a
plurality of preformed contact masks, wherein each preformed
contact mask comprises a patterned dielectric material that
includes at least one opening through which the deposition of the
selected deposition material can take place during the formation of
at least a portion of a layer, and wherein each preformed contact
mask comprises a support structure that supports the patterned
dielectric material; and wherein the locating of the selected
preformed contact mask on or in proximity to the previously formed
layer comprises contacting the previously formed layer and the
dielectric material of the selected preformed contact mask.
Description
RELATED APPLICATIONS
[0001] This application is a continuation of U.S. Non-Provisional
patent application Ser. No. 10/434,292 which in turn claims benefit
of Provisional Patent Application No. 60/379,183, filed on May 7,
2002. Both applications above are hereby incorporated herein by
reference as if set forth in full.
FIELD OF THE INVENTION
[0003] This invention relates to the field of electrochemical
deposition and more particularly to the field of electrochemical
fabrication which includes electrochemical deposition of one or
more materials according to desired cross-sectional configurations
so as to build up three-dimensional structures from a plurality of
at least partially adhered layers of deposited material. More
particularly the invention relates to the integration of multilayer
electrochemically fabricated structures with semiconductor
circuitry and in particular to the formation of such structures on
integrated circuits.
BACKGROUND
[0004] A technique for forming three-dimensional structures (e.g.
parts, components, devices, and the like) from a plurality of
adhered layers was invented by Adam L. Cohen and is known as
Electrochemical Fabrication. It is being commercially pursued by
MEMGen.RTM. Corporation of Burbank, Calif. under the name EFAB.TM..
This technique was described in US Pat. No. 6,027,630, issued on
Feb. 22, 2000. This electrochemical deposition technique allows the
selective deposition of a material using a unique masking technique
that involves the use of a mask that includes patterned conformable
material on a support structure that is independent of the
substrate onto which plating will occur. When desiring to perform
an electrodeposition using the mask, the conformable portion of the
mask is brought into contact with a substrate while in the presence
of a plating solution such that the contact of the conformable
portion of the mask to the substrate inhibits deposition at
selected locations. For convenience, these masks might be
generically called conformable contact masks; the masking technique
may be generically called a conformable contact mask plating
process. More specifically, in the terminology of MEMGen.RTM.
Corporation of Burbank, Calif. such masks have come to be known as
INSTANT MASKS.TM. and the process known as INSTANT MASKING.TM. or
INSTANT MASK.TM. plating. Selective depositions using conformable
contact mask plating may be used to form single layers of material
or may be used to form multi-layer structures. The teachings of the
'630 patent are hereby incorporated herein by reference as if set
forth in full herein. Since the filing of the patent application
that led to the above noted patent, various papers about
conformable contact mask plating (i.e. INSTANT MASKING) and
electrochemical fabrication have been published:
[0005] 1. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and
P. Will, "EFAB: Batch production of functional, fully-dense metal
parts with micro-scale features", Proc. 9th Solid Freeform
Fabrication, The University of Texas at Austin, p161, August
1998.
[0006] 2. A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and
P. Will, "EFAB: Rapid, Low-Cost Desktop Micromachining of High
Aspect Ratio True 3-D MEMS", Proc. 12th IEEE Micro Electro
Mechanical Systems Workshop, IEEE, p244, January 1999.
[0007] 3. A. Cohen, "3-D Micromachining by Electrochemical
Fabrication", Micromachine Devices, March 1999.
[0008] 4. G. Zhang, A. Cohen, U. Frodis, F. Tseng, F. Mansfeld, and
P. Will, "EFAB: Rapid Desktop Manufacturing of True 3-D
Microstructures", Proc. 2nd International Conference on Integrated
MicroNanotechnology for Space Applications, The Aerospace Co.,
April 1999.
[0009] 5. F. Tseng, U. Frodis, G. Zhang, A. Cohen, F. Mansfeld, and
P. Will, "EFAB: High Aspect Ratio, Arbitrary 3-D Metal
Microstructures using a Low-Cost Automated Batch Process", 3rd
International Workshop on High Aspect Ratio MicroStructure
Technology (HARMST'99), June 1999.
[0010] 6. A. Cohen, U. Frodis, F. Tseng, G. Zhang, F. Mansfeld, and
P. Will, "EFAB: Low-Cost, Automated Electrochemical Batch
Fabrication of Arbitrary 3-D Microstructures", Micromachining and
Microfabrication Process Technology, SPIE 1999 Symposium on
Micromachining and Microfabrication, September 1999.
[0011] 7. F. Tseng, G. Zhang, U. Frodis, A. Cohen, F. Mansfeld, and
P. Will, "EFAB: High Aspect Ratio, Arbitrary 3-D Metal
Microstructures using a Low-Cost Automated Batch Process", MEMS
Symposium, ASME 1999 International Mechanical Engineering Congress
and Exposition, November, 1999.
[0012] 8. A. Cohen, "Electrochemical Fabrication (EFABTM)", Chapter
19 of The MEMS Handbook, edited by Mohamed Gad-El-Hak, CRC Press,
2002.
[0013] 9. "Microfabrication-Rapid Prototyping's Killer
Application", pages 1-5 of the Rapid Prototyping Report, CAD/CAM
Publishing, Inc., June 1999.
[0014] The disclosures of these nine publications are hereby
incorporated herein by reference as if set forth in full
herein.
[0015] The electrochemical deposition process may be carried out in
a number of different ways as set forth in the above patent and
publications. In one form, this process involves the execution of
three separate operations during the formation of each layer of the
structure that is to be formed:
[0016] Selectively depositing at least one material by
electrodeposition upon one or more desired regions of a
substrate.
[0017] Then, blanket depositing at least one additional material by
electrodeposition so that the additional deposit covers both the
regions that were previously selectively deposited onto, and the
regions of the substrate that did not receive any previously
applied selective depositions.
[0018] Finally, planarizing the materials deposited during the
first and second operations to produce a smoothed surface of a
first layer of desired thickness having at least one region
containing the at least one material and at least one region
containing at least the one additional material.
[0019] After formation of the first layer, one or more additional
layers may be formed adjacent to the immediately preceding layer
and adhered to the smoothed surface of that preceding layer. These
additional layers are formed by repeating the first through third
operations one or more times wherein the formation of each
subsequent layer treats the previously formed layers and the
initial substrate as a new and thickening substrate.
[0020] Once the formation of all layers has been completed, at
least a portion of at least one of the materials deposited is
generally removed by an etching process to expose or release the
three-dimensional structure that was intended to be formed.
[0021] The preferred method of performing the selective
electrodeposition involved in the first operation is by conformable
contact mask plating. In this type of plating, one or more
conformable contact (CC) masks are first formed. The CC masks
include a support structure onto which a patterned conformable
dielectric material is adhered or formed. The conformable material
for each mask is shaped in accordance with a particular
cross-section of material to be plated. At least one CC mask is
needed for each unique cross-sectional pattern that is to be
plated.
[0022] The support for a CC mask is typically a plate-like
structure formed of a metal that is to be selectively electroplated
and from which material to be plated will be dissolved. In this
typical approach, the support will act as an anode in an
electroplating process. In an alternative approach, the support may
instead be a porous or otherwise perforated material through which
deposition material will pass during an electroplating operation on
its way from a distal anode to a deposition surface. In either
approach, it is possible for CC masks to share a common support,
i.e. the patterns of conformable dielectric material for plating
multiple layers of material may be located in different areas of a
single support structure. When a single support structure contains
multiple plating patterns, the entire structure is referred to as
the CC mask while the individual plating masks may be referred to
as "submasks". In the present application such a distinction will
be made only when relevant to a specific point being made.
[0023] In preparation for performing the selective deposition of
the first operation, the conformable portion of the CC mask is
placed in registration with and pressed against a selected portion
of the substrate (or onto a previously formed layer or onto a
previously deposited portion of a layer) on which deposition is to
occur. The pressing together of the CC mask and substrate occur in
such a way that all openings, in the conformable portions of the CC
mask contain plating solution. The conformable material of the CC
mask that contacts the substrate acts as a barrier to
electrodeposition while the openings in the CC mask that are filled
with electroplating solution act as pathways for transferring
material from an anode (e.g. the CC mask support) to the
non-contacted portions of the substrate (which act as a cathode
during the plating operation) when an appropriate potential and/or
current are supplied.
[0024] An example of a CC mask and CC mask plating are shown in
FIGS. 1(a)-1(c). FIG. 1(a) shows a side view of a CC mask 8
consisting of a conformable or deformable (e.g. elastomeric)
insulator 10 patterned on an anode 12. The anode has two functions.
FIG. 1(a) also depicts a substrate 6 separated from mask 8. One is
as a supporting material for the patterned insulator 10 to maintain
its integrity and alignment since the pattern may be topologically
complex (e.g., involving isolated "islands" of insulator material).
The other function is as an anode for the electroplating operation.
CC mask plating selectively deposits material 22 onto a substrate 6
by simply pressing the insulator against the substrate then
electrodepositing material through apertures 26a and 26b in the
insulator as shown in FIG. 1(b). After deposition, the CC mask is
separated, preferably non-destructively, from the substrate 6 as
shown in FIG. 1(c). The CC mask plating process is distinct from a
"through-mask" plating process in that in a through-mask plating
process the separation of the masking material from the substrate
would occur destructively. As with through-mask plating, CC mask
plating deposits material selectively and simultaneously over the
entire layer. The plated region may consist of one or more isolated
plating regions where these isolated plating regions may belong to
a single structure that is being formed or may belong to multiple
structures that are being formed simultaneously. In CC mask plating
as individual masks are not intentionally destroyed in the removal
process, they may be usable in multiple plating operations.
[0025] Another example of a CC mask and CC mask plating is shown in
FIGS. 1(d)-1(f). FIG. 1(d) shows an anode 12' separated from a mask
8' that comprises a patterned conformable material 10' and a
support structure 20. FIG. 1(d) also depicts substrate 6 separated
from the mask 8'. FIG. 1(e) illustrates the mask 8' being brought
into contact with the substrate 6. FIG. 1(f) illustrates the
deposit 22' that results from conducting a current from the anode
12' to the substrate 6. FIG. 1(g) illustrates the deposit 22' on
substrate 6 after separation from mask 8'. In this example, an
appropriate electrolyte is located between the substrate 6 and the
anode 12' and a current of ions coming from one or both of the
solution and the anode are conducted through the opening in the
mask to the substrate where material is deposited. This type of
mask may be referred to as an anodeless INSTANT MASK.TM. (AIM) or
as an anodeless conformable contact (ACC) mask.
[0026] Unlike through-mask plating, CC mask plating allows CC masks
to be formed completely separate from the fabrication of the
substrate on which plating is to occur (e.g. separate from a
three-dimensional (3D) structure that is being formed). CC masks
may be formed in a variety of ways, for example, a
photolithographic process may be used. All masks can be generated
simultaneously, prior to structure fabrication rather than during
it. This separation makes possible a simple, low-cost, automated,
self-contained, and internally-clean "desktop factory" that can be
installed almost anywhere to fabricate 3D structures, leaving any
required clean room processes, such as photolithography to be
performed by service bureaus or the like.
[0027] An example of the electrochemical fabrication process
discussed above is illustrated in FIGS. 2(a)-2(f). These figures
show that the process involves deposition of a first material 2
which is a sacrificial material and a second material 4 which is a
structural material. The CC mask 8, in this example, includes a
patterned conformable material (e.g. an elastomeric dielectric
material) 10 and a support 12 which is made from deposition
material 2. The conformal portion of the CC mask is pressed against
substrate 6 with a plating solution 14 located within the openings
16 in the conformable material 10. An electric current, from power
supply 18, is then passed through the plating solution 14 via (a)
support 12 which doubles as an anode and (b) substrate 6 which
doubles as a cathode. FIG. 2(a), illustrates that the passing of
current causes material 2 within the plating solution and material
2 from the anode 12 to be selectively transferred to and plated on
the cathode 6. After electroplating the first deposition material 2
onto the substrate 6 using CC mask 8, the CC mask 8 is removed as
shown in FIG. 2(b). FIG. 2(c) depicts the second deposition
material 4 as having been blanket-deposited (i.e. non-selectively
deposited) over the previously deposited first deposition material
2 as well as over the other portions of the substrate 6. The
blanket deposition occurs by electroplating from an anode (not
shown), composed of the second material, through an appropriate
plating solution (not shown), and to the cathode/substrate 6. The
entire two-material layer is then planarized to achieve precise
thickness and flatness as shown in FIG. 2(d). After repetition of
this process for all layers, the multi-layer structure 20 formed of
the second material 4 (i.e. structural material) is embedded in
first material 2 (i.e. sacrificial material) as shown in FIG. 2(e).
The embedded structure is etched to yield the desired device, i.e.
structure 20, as shown in FIG. 2(f).
[0028] Various components of an exemplary manual electrochemical
fabrication system 32 are shown in FIGS. 3(a)-3(c). The system 32
consists of several subsystems 34, 36, 38, and 40. The substrate
holding subsystem 34 is depicted in the upper portions of each of
FIGS. 3(a) to 3(c) and includes several components: (1) a carrier
48, (2) a metal substrate 6 onto which the layers are deposited,
and (3) a linear slide 42 capable of moving the substrate 6 up and
down relative to the carrier 48 in response to drive force from
actuator 44. Subsystem 34 also includes an indicator 46 for
measuring differences in vertical position of the substrate which
may be used in setting or determining layer thicknesses and/or
deposition thicknesses. The subsystem 34 further includes feet 68
for carrier 48 which can be precisely mounted on subsystem 36.
[0029] The CC mask subsystem 36 shown in the lower portion of FIG.
3(a) includes several components: (1) a CC mask 8 that is actually
made up of a number of CC masks (i.e. submasks) that share a common
support/anode 12, (2) precision X-stage 54, (3) precision Y-stage
56, (4) frame 72 on which the feet 68 of subsystem 34 can mount,
and (5) a tank 58 for containing the electrolyte 16. Subsystems 34
and 36 also include appropriate electrical connections (not shown)
for connecting to an appropriate power source for driving the CC
masking process.
[0030] The blanket deposition subsystem 38 is shown in the lower
portion of FIG. 3(b) and includes several components: (1) an anode
62, (2) an electrolyte tank 64 for holding plating solution 66, and
(3) frame 74 on which the feet 68 of subsystem 34 may sit.
Subsystem 38 also includes appropriate electrical connections (not
shown) for connecting the anode to an appropriate power supply for
driving the blanket deposition process.
[0031] The planarization subsystem 40 is shown in the lower portion
of FIG. 3(c) and includes a lapping plate 52 and associated motion
and control systems (not shown) for planarizing the
depositions.
[0032] In addition to the above teachings, the '630 patent sets
forth a process for integrating EFAB production with integrated
circuits. In this process the structural EFAB material is plated
onto and in electrical contact with aluminum contact pads on the
integrated circuit. These contact pads may be considered primary
contact pads and the locations to which contact with the EFAB
structural material will be made. In the described process the
integrated circuit design is modified to include secondary contact
pads (i.e. one or more pads) that are electrically connected to the
primary pads but are spaced therefrom by a distance. The secondary
contact pads provide connection points for feeding current to the
primary contact pads so that the primary pads may function as
cathodes during electroplating operations. The process is
illustrated in FIGS. 13a-13i of that patent and is outlined as
follows: [0033] 1. The process starts with [0034] a. An integrated
circuit that includes a silicon wafer 38, a primary contact pad 40,
and a secondary contact pad 41 connected to the primary pad by
conductor 42. With the exception of the contact pads 40 and 41 the
integrated circuit is covered by passivation layer 44 (FIG. 13a
& 13b); and [0035] b. A polyimide 34 coated copper disk 36. The
polyimide may be coated onto the disk by spin coating. [0036] 2.
The copper disk 36 is adhered to the bottom surface of the silicon
wafer 38 with the polyimide 34 coated surface of the copper disk
located between the copper and the silicon. [0037] 3. The silicon
wafer is partially sawed through which assists in separation of the
die after processing. [0038] 4. A photosensitive polyimide 35 is
spin coated onto the top surface of wafer 38. This coating provides
an additional passivation layer and potentially protects aluminum
pads 40 and 41 during subsequent etching operations and it fills
saw line 46. [0039] 5. The polyimide 35 is patterned by selective
exposure to light and subsequent development to expose contact pads
40 and 41. [0040] 6. The wafer is degreased and immersed in zincate
plating solution which provides a thin coating over the exposed
aluminum contact pads to increase adhesion of subsequently
deposited material. [0041] 7. A photoresist is applied and
patterned leaving a valley into which copper may be deposited to
form a bus 48 that connects contact pads 41 (FIG. 13d). Copper is
deposited, for example by sputtering and the photoresist is removed
leaving behind copper bus 48. [0042] 8. A photoresist is applied
and patterned to cover most of bus 48 to prevent nickel from
depositing thereon. [0043] 9. Electrical contact is made with the
portion of the bus 48 that is not covered by photoresist and then
plating enough nickel 50 (FIG. 13e) on aluminum pad 40 to allow
subsequent planarization [0044] 10. The photoresist is removed
thereby exposing the entire copper bus 48. [0045] 11.A thin plating
base of copper 51 is deposited, e.g. by sputtering, over the entire
surface of the integrated circuit. [0046] 12. Electrical contact is
made with the copper and a sufficient amount of copper 52 is then
electroplated over the entire wafer surface to allow planarization
(FIG. 13F). [0047] 13. The surface is planarized to expose the
nickel 50 (FIG. 13g). [0048] 14. Layers of the microstructure are
electroplated (FIG. 13h). [0049] 15. The copper deposited by
electroplating and sputtering is removed by etching. [0050] 16. The
polyimide 35 is stripped thereby exposing the resulting
microstructure device 54 attached to wafer 38 (FIG. 13i).
[0051] Another method for forming microstructures from
electroplated metals (i.e. using electrochemical fabrication
techniques) is taught in U.S. Pat. No. 5,190,637 to Henry Guckel,
entitled "Formation of Microstructures by Multiple Level Deep X-ray
Lithography with Sacrificial Metal layers. This patent teaches the
formation of metal structure utilizing mask exposures. A first
layer of a primary metal is electroplated onto an exposed plating
base to fill a void in a photoresist, the photoresist is then
removed and a secondary metal is electroplated over the first layer
and over the plating base. The exposed surface of the secondary
metal is then machined down to a height which exposes the first
metal to produce a flat uniform surface extending across the both
the primary and secondary metals. Formation of a second layer may
then begin by applying a photoresist layer over the first layer and
then repeating the process used to produce the first layer. The
process is then repeated until the entire structure is formed and
the secondary metal is removed by etching. The photoresist is
formed over the plating base or previous layer by casting and the
voids in the photoresist are formed by exposure of the photoresist
through a patterned mask via X-rays or UV radiation.
[0052] Even in view of these teachings a need remains in the
electrochemical fabrication arts for alternative processes and
simpler processes for integrating electrochemically fabricated
structures with integrated circuits and particularly for processes
that allow formation of multilayer electrochemically fabricated
structures on and in electrical contact with semiconductor produced
circuitry.
SUMMARY OF THE INVENTION
[0053] It is an object of various aspects of the present invention
to provide alternative processes for integrating electrochemically
fabricated multilayer structures with integrated circuits.
[0054] It is an object of various aspects of the present invention
to provide simpler processes for integrating electrochemically
fabricated multilayer structures with integrated circuits.
[0055] It is an object of various aspects of the present invention
to provide simpler processes that allow formation of multilayer
electrochemically fabricated structure on and in electrical contact
with semiconductor produced circuitry.
[0056] Other objects and advantages of various aspects of the
invention will be apparent to those of skill in the art upon review
of the teachings herein. The various aspects of the invention, set
forth explicitly herein or otherwise ascertained from the teachings
herein, may address any one of the above objects alone or in
combination, or alternatively may not address any of the objects
set forth above but instead address some other object ascertained
from the teachings herein. It is not intended that all of these
objects be addressed by any single aspect of the invention even
though that may be the case with regard to some aspects.
[0057] A first aspect of the invention provides an electrochemical
fabrication process for producing a three-dimensional structure
from a plurality of adhered layers, the process including: (A)
selectively depositing at least a portion of a layer onto the
substrate, wherein the substrate may include previously deposited
material; (B) forming a plurality of layers such that successive
layers are formed adjacent to and adhered to previously deposited
layers, wherein said forming includes repeating operation (A) a
plurality of times; wherein at least a plurality of the selective
depositing operations include: (1) locating a mask on or in
proximity to a substrate; (2) in presence of a plating solution,
conducting an electric current between an anode and the substrate
through the at least one opening in the mask, such that a selected
deposition material is deposited onto the substrate to form at
least a portion of a layer; and (3) separating the selected
preformed mask from the substrate; wherein the substrate includes a
semiconductor wafer or single die containing electrical circuitry
and having contact pads to which structural material is to connect;
and wherein the process of contacting the contact pads with
structural material includes in order: (a) placing a protective
coating over the contact pads; (b) applying a layer of sacrificial
material to a surface of the wafer, (c) removing the protective
coating from the contact pads; and (d) applying a coating of
structural material to the contact pads.
[0058] A second aspect of the invention provides an electrochemical
fabrication process for producing a three-dimensional structure
from a plurality of adhered layers, the process including: (A)
selectively depositing at least a portion of a layer onto the
substrate, wherein the substrate may include previously deposited
material; (B) forming a plurality of layers such that successive
layers are formed adjacent to and adhered to previously deposited
layers, wherein said forming includes repeating operation (A) a
plurality of times; wherein at least a plurality of the selective
depositing operations include: (1) locating a mask on or in
proximity to a substrate; (2) in presence of a plating solution,
conducting an electric current between an anode and the substrate
through the at least one opening in the mask, such that a selected
deposition material is deposited onto the substrate to form at
least a portion of a layer; and (3) separating the selected
preformed mask from the substrate; wherein the substrate includes a
semiconductor wafer or single die containing electrical circuitry
and having contact pads to which structural material is to connect;
and wherein the process of contacting the contact pads with
structural material includes, in order: (a) depositing sacrificial
material onto a surface of the wafer or die in regions excluding
contact pad regions; and (b) depositing structural material to at
least selected contact pad regions.
[0059] A third aspect of the invention provides an electrochemical
fabrication process for producing a three-dimensional structure
from a plurality of adhered layers, the process including: (A)
selectively depositing at least a portion of a layer onto the
substrate, wherein the substrate may include previously deposited
material; (B) forming a plurality of layers such that successive
layers are formed adjacent to and adhered to previously deposited
layers, wherein said forming includes repeating operation (A) a
plurality of times; wherein at least a plurality of the selective
depositing operations include: (1) locating a mask on or in
proximity to a substrate; (2) in presence of a plating solution,
conducting an electric current between an anode and the substrate
through the at least one opening in the mask, such that a selected
deposition material is deposited onto the substrate to form at
least a portion of a layer; and (3) separating the selected
preformed mask from the substrate; wherein the substrate includes a
semiconductor wafer or single die containing electrical circuitry
and having contact pads to which structural material is to connect
and having a passivation layer; and wherein the process of
contacting the contact pads with structural material includes in
order: (a) locating an electroless plating catalyst for a
sacrificial material on at least a portion of the surface of the
passivation layer; (b) electroless plating the sacrificial material
on to the passivation layer; (c) applying a structural material
over the contact pads.
[0060] Further aspects of the invention will be understood by those
of skill in the art upon reviewing the teachings herein. Other
aspects of the invention may involve combinations of the above
noted aspects of the invention and/or addition of various features
of one or more embodiments. Other aspects of the invention may
involve apparatus that can be used in implementing one or more of
the above method aspects of the invention. These other aspects of
the invention may provide various combinations of the aspects
presented above as well as provide other configurations,
structures, functional relationships, and processes that have not
been specifically set forth above.
BRIEF DESCRIPTION OF THE DRAWINGS
[0061] FIGS. 1(a)-1(c) schematically depict side views of various
stages of a CC mask plating process, while FIGS. 1(d)-(g)
schematically depict a side views of various stages of a CC mask
plating process using a different type of CC mask.
[0062] FIGS. 2(a)-2(f) schematically depict side views of various
stages of an electrochemical fabrication process as applied to the
formation of a particular structure where a sacrificial material is
selectively deposited while a structural material is blanket
deposited.
[0063] FIGS. 3(a)-3(c) schematically depict side views of various
example subassemblies that may be used in manually implementing the
electrochemical fabrication method depicted in FIGS. 2(a)-2(f).
[0064] FIGS. 4(a)-4(i) schematically depict the formation of a
first layer of a structure using adhered mask plating where the
blanket deposition of a second material overlays both the openings
between deposition locations of a first material and the first
material itself.
[0065] FIGS. 5(a)-5(l) schematically depict side views of various
stages of a process according to a first embodiment for forming
electrochemically fabricated structures on integrated circuits.
[0066] FIGS. 6(a)-6(f) schematically depict side views of various
stages of a process according to one variation of a second
embodiment for forming electrochemically fabricated structures on
integrated circuits.
DETAILED DESCRIPTION
[0067] FIGS. 1(a)-1(g), 2(a)-2(f), and 3(a)-3(c) illustrate various
features of one form of electrochemical fabrication that are known.
Other electrochemical fabrication techniques are set forth in the
'630 patent referenced above, in the various previously
incorporated publications, in various other patents and patent
applications incorporated herein by reference, still others may be
derived from combinations of various approaches described in these
publications, patents, and applications, or are otherwise known or
ascertainable by those of skill in the art from the teachings set
forth herein. All of these techniques may be combined with those of
the various embodiments of various aspects of the invention to
yield enhanced embodiments. Still other embodiments may be derived
from combinations of the various embodiments explicitly set forth
herein.
[0068] FIGS. 4(a)-4(i) illustrate various stages in the formation
of a single layer of a multi-layer fabrication process where a
second metal is deposited on a first metal as well as in openings
in the first metal where its deposition forms part of the layer. In
FIG. 4(a), a side view of a substrate 82 is shown, onto which
patternable photoresist 84 is cast as shown in FIG. 4(b). In FIG.
4(c), a pattern of resist is shown that results from the curing,
exposing, and developing of the resist. The patterning of the
photoresist 84 results in openings or apertures 92(a)-92(c)
extending from a surface 86 of the photoresist through the
thickness of the photoresist to surface 88 of the substrate 82. In
FIG. 4(d), a metal 94 (e.g. nickel) is shown as having been
electroplated into the openings 92(a)-92(c). In FIG. 4(e), the
photoresist has been removed (i.e. chemically stripped) from the
substrate to expose regions of the substrate 82 which are not
covered with the first metal 94. In FIG. 4(f), a second metal 96
(e.g., silver) is shown as having been blanket electroplated over
the entire exposed portions of the substrate 82 (which is
conductive) and over the first metal 94 (which is also conductive).
FIG. 4(g) depicts the completed first layer of the structure which
has resulted from the planarization of the first and second metals
down to a height that exposes the first metal and sets a thickness
for the first layer. In FIG. 4(h) the result of repeating the
process steps shown in FIGS. 4(b)-4(g) several times to form a
multi-layer structure are shown where each layer consists of two
materials. For most applications, one of these materials is removed
as shown in FIG. 4(i) to yield a desired 3-D structure 98 (e.g.
component or device).
[0069] The various electrochemical fabrication processes used in
various embodiments, alternatives, and techniques disclosed herein
may have application to conformable contact masks and masking
operations, proximity masks and masking operations (i.e. operations
that use masks that at least partially selectively shield a
substrate by their proximity to the substrate even if contact is
not made), non-conformable masks and masking operations (i.e. masks
and operations based on masks whose contact surfaces are not
significantly conformable), and adhered masks and masking
operations (masks and operations that use masks that are adhered to
a substrate onto which selective deposition or etching is to occur
as opposed to only being contacted to it).
[0070] Various embodiments are directed to techniques for
interfacing or integrating the electrochemical fabrication of
multi-layer three dimensional structures with semiconductor devices
(e.g. integrated circuits) or devices produced by semiconductor
manufacturing techniques. In the various embodiments presented
hereafter, the semiconductor devices are provided in wafer form or
die form and are used as substrates for the electrochemical
fabrication build up process. These devices may be supplied with a
passivation layer of adequate thickness already applied or such
layers may be thickened prior to beginning the integration
process.
[0071] An integration process of a first preferred embodiment is
depicted in FIGS. 5(a)-5(l). A wafer 102 (or single die) is
received from a standard IC fabrication process as shown in FIG.
5(a). The wafer includes electronic circuitry (not shown) with
interface contact pads 104 and connected bus contact pads 106
exposed. The pads are connected by runners 108 which travel under a
passivation layer 112 which covers the surface of the wafer 102.
Pads 104 and runners 108 may have been specifically designed with
the intent of integrating a device made by electrochemical
fabrication, or alternatively pre-designed pads and interconnects
that can serve as runners may be used. Other pads (not shown) may
be located on wafer 102 for purposes of wire bonding, flip chip
packaging, etc.
[0072] A photoresist layer 122 is applied to the upper surface of
the wafer as shown in FIG. 5(b). The photoresist is patterned so
that the interface pads 104 remain covered with hardened
photoresist 124 as shown in FIG. 5(c). These covered pads are the
ones to which the multilayer electrochemically fabricated structure
will be interfaced.
[0073] A thin layer of copper 126 is deposited over the entire
surface as shown in FIG. 5(d). The deposition of the copper may for
example occur via a physical vapor deposition process (e.g.
evaporated or sputtered), via electroless copper plating, or via
direct metallization (i.e. direct plating). As the adhesion between
the copper and the exposed aluminum bus contact pads is not
critical it may be unnecessary to apply a coating of zincate to the
surface prior to copper deposition. But a zincate coating can be
applied if desired or found necessary. Furthermore, as the bus
contact pads 106 are located some distance from the interface
contact pads, some damage by the copper to the bus contact pads may
be acceptable. If such damage is a concern or found to be a problem
a barrier layer can be applied prior to the copper deposition. The
barrier layer can then be removed toward the end of the process
after removal of the copper.
[0074] Next, electrical contact is made to the thin copper coating
126 and thick copper 128 is plated as shown in FIG. 5(e) with a
sufficient depth to allow planarization to occur.
[0075] Next the applied coatings of copper are planarized to expose
the resist 124 overlaying the interface contact pads 104 as shown
in FIG. 5(f). The resist 124 is then removed as shown in FIG.
5(g).
[0076] Next, a transition/barrier layer 132 is deposited onto the
wafer as shown in FIG. 5(h). The transition/barrier layer may
include one or both of a coating of an adhesion promoter (such as
zincate) and a diffusion barrier such as titanium nitride (TiN),
tantalum (Ta), and/or tantalum Nitride (TaN).
[0077] Next, electrical contact is made to the barrier layer and an
electrochemical fabrication structural material 134 (e.g., Ni) is
plated thickly as shown in FIG. 5(i).
[0078] The deposits are again planarized as shown FIG. 50) exposing
the thickly plated copper 128, and removing the barrier layer 132
except near where it bounds the remaining nickel deposit 134 near
the interface contact pads 104.
[0079] After again making electrical contact with the deposited
metal, the electrochemical fabrication process is performed to
build up the multiple layers of the three dimensional structure.
The multilayer deposition process is shown as completed in FIG.
5(k). The electrochemical fabrication process may be performed in a
variety of manners and may include a variety of operations, such
as, for example, selective depositions, selective etchings, blanket
depositions, blanket etchings, planarization operations, and the
like. It may also include various cleaning, activation,
passivation, and other treatment operations. The selection of
operations and the ordering of the operations may vary from build
process to build process or even from layer-to-layer within a
single build process. Any selective deposition operations,
selective etching operations, or selective treatment operations may
make use of contact masks (e.g. of the conformable or
non-conformable type), proximity masks, and/or adhered masks.
[0080] Next, all of the deposited copper is removed by etching as
indicated in FIG. 5(l). Only the structural material from the
electrochemical fabrication process is left behind along with the
transition/barrier layer and the wafer or (single die) material
deposited between the nickel and interface contact pads 104 and
covering a portion of the sides of the nickel around the interface
contact pads. In this way the structure produced by electrochemical
fabrication is mechanically and electrically interfaced to the
metallization of the wafer.
[0081] Various alternatives to this first embodiment are possible.
For example, a diffusion barrier layer could be deposited prior to
the thin copper deposit 126 but after formation of the patterned
resist 124, it could be removed by controlled etching as its
surface area would be largely exposed compared to the amount of
exposure that a coating between the interface contact pads 104 and
the electrochemically fabricated structure would have. Due to this
differential in exposure, it is believed that controlled etching
may be performed, after layer formation is complete and the
sacrificial material has been removed, to remove the
barrier/transition layer from non-contact regions of the
electrochemically fabricated structure without excessive damage to
the contact regions after layer formation.
[0082] In another alternative embodiment, a barrier layer could be
applied prior to the application of the photoresist thereby
obviating the need for a potential barrier layer prior to thin
copper deposition of FIG. 5(d) and prior to the structural material
deposition of FIG. 5(i). In this alternative the uncovered portion
of the barrier layer would be removed after the removal of the
copper.
[0083] In other alternative embodiments an adhesion transition
layer may also be formed at different stages of the process.
[0084] In another alternative embodiment the runner and bus pad
would not be needed. In this alternative, the interface pad is made
larger than the area intended for deposition of the structural
material (e.g. Ni). In this alternative, the portion of the
interface contact pad 104 that is not covered by the structural
material serves as the contact pad (rather than having a remote
contact pad). However, since Al metallization used in the
integrated circuit device may be attacked by the Cu stripper,
etching of the Cu surrounding the structural material may damage
the pad near the structural material. Using the runner and remote
contact pad avoids this problem. Also this alternative embodiment
could benefit from the previous alternative embodiment where the
pre-photoresist application of a barrier layer would inhibit the
attack.
[0085] A second group of embodiments may take an alternative
approach to interfacing the wafer 102 to the initial conductive
deposits onto which the multiple layers of the structure will be
formed. FIGS. 6(a)-6(f) show one variation of the second group of
embodiments. FIG. 6(a) shows wafer 102 which may be prepared for
the interfacing process by, for example, coating pads 140 with a
material that facilitates electrodeposition or enhances adhesion
(e.g., zincate treatment for aluminum pads) or adding additional
passivation or barrier layers to protect wafer 102 from materials
(e.g., sodium) which may be present in plating or etching baths. In
FIG. 6(b), a catalyst 142 for an electroless plating bath that is
suitable for depositing the sacrificial material has been applied
to the surface of the IC passivation layer 112. Catalyst 142 may be
selectively located on the passivation layer away from contact pads
140 so that sacrificial material will not be inadvertently
deposited onto the contact pads. However, if catalyst 142 coats
only the perimeter of pads 140 this is acceptable and may be
desirable in some embodiments. Catalyst 142 may be selectively
applied, for example, by contacting the protruding surface of
passivation 112 with a plate or stamp coated with a thin film of
catalyst 142, or by selectively dispensing catalyst 142 (e.g. via
an ink jet or an extrusion head).
[0086] In FIG. 6(c), sacrificial material 144 has been deposited
onto the catalyzed surface, which is assumed to be confined to the
top surface of passivation 112. In FIG. 6(d) the deposit has been
continued until material 144 `mushrooms` out and makes contact with
the perimeter of pads 140. Once such contact is made, pads 140 are
in electrical contact with one another and with material 144 and
can be electrodeposited with another material. In FIG. 6(e),
structural material has been electrodeposited onto pads 140.
Finally, in FIG. 6(f), sacrificial and structural materials have
been planarized so as to create a relatively flat and smooth
substrate--as in FIG. 5(j)--suitable as a starting layer for
further electrochemical fabrication operations where the starting
layer includes regions of sacrificial material (e.g., copper) and
regions of structural material (e.g., nickel). In other words, the
starting layer includes a structural material in regions that
contact the pads and are intended to be electrically active, while
a temporary presence of copper is located in all other regions.
[0087] An integration process of a first preferred embodiment is
depicted in FIGS. 5(a)-5(l). A wafer 102 (or single die) is
received from a standard IC fabrication process as shown in FIG.
5(a). The wafer includes electronic circuitry (not shown) with
interface contact pads 104 and connected bus contact pads 106
exposed. The pads are connected by runners 108 which travel under a
passivation layer 112 which covers the surface of the wafer
102.
[0088] A photoresist layer 122 is applied to the upper surface of
the wafer as shown in FIG. 5(b). The photoresist is patterned so
that the interface pads 104 remained covered with hardened
photoresist 124 as shown in FIG. 5(c). These covered pads are the
ones to which the multilayer electrochemically fabricated structure
will be interfaced.
[0089] A thin layer of copper 126 is deposited over the entire
surface as shown in FIG. 5(d). The deposition of the copper may for
example occur via a physical vapor deposition process (e.g.
evaporated or sputtered) or electroless copper plating. As the
adhesion between the copper and the exposed aluminum bus contact
pads is not critical it may be unnecessary to apply a coating of
zincate to the surface prior to copper deposition. But a Zincate
coating can be applied is desired or found necessary. Furthermore,
as the bus contact pads 106 are located some distance from the
interface contact pads, some damage by the copper to the bus
contact pads may be acceptable. If such damage is a concern or
found to be a problem a barrier layer can be applied prior to the
copper deposition. The barrier layer can then be removed toward the
end of the process after removal of the copper.
[0090] Next, electrical contact is made to the thin copper coating
126 and thick copper 128 is plated as shown in FIG. 5.(e) with a
sufficient depth to allow planarization to occur.
[0091] Next the applied coatings of copper are planarized to expose
the resist overlaying the interface contact pads 104 as shown in
FIG. 5(f). The resist is then removed as shown in FIG. 5(g).
[0092] Next, a transition/barrier layer 132 is deposited onto the
wafer as shown in FIG. 5(h). The transition/barrier layer may
include one or both of a coating of an adhesion promoter (such as
zincate) amid a diffusion barrier such as titanium nitride (TiN),
tantalum (Ta), and/or tantalum Nitride (TaN).
[0093] Next, electrical contact is made to the barrier layer and an
electrochemical fabrication structural material 134 (e.g., Ni) is
plated thickly as shown in FIG. 5(i).
[0094] Though the present embodiments have focused on
electrochemically fabricated structures containing a structural
material of nickel and a sacrificial material of copper, other
embodiments are possible where different structural and/or
sacrificial materials are used. Furthermore, interfacing between a
wafer or die and electrochemically produced structures utilizing
different structural and/or sacrificial materials may occur via the
nickel and copper materials exemplified herein or may occur via the
different materials according to the generalized applicability of
the processes set forth herein to those materials. Still other
embodiments will be apparent to those of skill in the art upon
reviewing the teaching herein, such as processes that involves
various combinations of the operations used in the different
embodiments disclosed herein.
[0095] Various alternatives to and variations of the above noted
embodiments exist. In some alternative embodiments, the structural
material of choice is nickel and the sacrificial material of choice
is copper, and in other embodiments other or additional structural
materials may be chosen and other or additional sacrificial
materials may be chosen.
[0096] Various other embodiments exist. Some of these embodiments
may be based on a combination of the teachings herein with various
teachings incorporated herein by reference. Some embodiments may
not use any blanket deposition process and/or they may not use a
planarization process. Some embodiments may involve the selective
deposition of a plurality of different materials on a single layer
or on different layers. Some embodiments may use blanket
depositions processes that are not electrodeposition processes.
Some embodiments may use selective deposition processes on some
layers that are not conformable contact masking processes and are
not even electrodeposition processes. Some embodiments may use
nickel as a structural material while other embodiments may use
different materials such as gold, silver, or any other
electrodepositable materials that can be separated from the copper
and/or some other sacrificial material. Some embodiments may use
copper as the structural material with or without a sacrificial
material. Some embodiments may remove a sacrificial material while
other embodiments may not. In some embodiments the anode may be
different from the conformable contact mask support and the support
may be a porous structure or other perforated structure. Some
embodiments may use multiple conformable contact masks with
different patterns so as to deposit different selective patterns of
material on different layers and/or on different portions of a
single layer. In some embodiments, the depth of deposition will be
enhanced by pulling the conformable contact mask away from the
substrate as deposition is occurring in a manner that allows the
seal between the conformable portion of the CC mask and the
substrate to shift from the face of the conformal material to the
inside edges of the conformable material.
[0097] In view of the teachings herein, many further embodiments,
alternatives in design and uses of the invention will be apparent
to those of skill in the art. As such, it is not intended that the
invention be limited to the particular illustrative embodiments,
alternatives, and uses described above but instead that it be
solely limited by the claims presented hereafter.
* * * * *