U.S. patent application number 11/796248 was filed with the patent office on 2007-09-20 for adaptive storage system including hard disk drive with flash interface.
Invention is credited to Sehat Sutardja, Yun Yang.
Application Number | 20070220202 11/796248 |
Document ID | / |
Family ID | 38694480 |
Filed Date | 2007-09-20 |
United States Patent
Application |
20070220202 |
Kind Code |
A1 |
Sutardja; Sehat ; et
al. |
September 20, 2007 |
Adaptive storage system including hard disk drive with flash
interface
Abstract
A data storage system for a device including low power and high
power modes comprises low power (LP) nonvolatile memory that
includes a LP hard disk drive (HDD) having a non-volatile
semiconductor memory interface, wherein said LP HDD communicates
with said device via said non-volatile semiconductor memory
interface. High power (HP) nonvolatile memory communicates with
said device.
Inventors: |
Sutardja; Sehat; (Los Altos
Hills, CA) ; Yang; Yun; (Los Altos, CA) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE P.L.C.
5445 CORPORATE DRIVE
SUITE 200
TROY
MI
48098
US
|
Family ID: |
38694480 |
Appl. No.: |
11/796248 |
Filed: |
April 27, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11503016 |
Aug 11, 2006 |
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11796248 |
Apr 27, 2007 |
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10865368 |
Jun 10, 2004 |
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11796248 |
Apr 27, 2007 |
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11322447 |
Dec 29, 2005 |
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11796248 |
Apr 27, 2007 |
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60820867 |
Jul 31, 2006 |
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60799151 |
May 10, 2006 |
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60678249 |
May 5, 2005 |
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Current U.S.
Class: |
711/113 ;
713/320 |
Current CPC
Class: |
G06F 3/0635 20130101;
G06F 1/3203 20130101; Y02D 10/00 20180101; G06F 3/0685 20130101;
G06F 1/3221 20130101; Y02D 10/154 20180101; G06F 3/0625 20130101;
G06F 1/3268 20130101 |
Class at
Publication: |
711/113 ;
713/320 |
International
Class: |
G06F 13/00 20060101
G06F013/00; G06F 1/32 20060101 G06F001/32 |
Claims
1. A data storage system for a device including low power and high
power modes, comprising: low power (LP) nonvolatile memory that
includes a LP hard disk drive (HDD) having a non-volatile
semiconductor memory interface, wherein said LP HDD communicates
with said device via said non-volatile semiconductor memory
interface; and high power (HP) nonvolatile memory that communicates
with said device.
2. The data storage device of claim 1 further comprising: a cache
control module that communicates with said LP and HP nonvolatile
memory and that includes an adaptive storage module, wherein when
write data is to be written to one of said LP and HP nonvolatile
memory, said adaptive storage module generates an adaptive storage
decision that selects one of said LP and HP nonvolatile memory.
3. The data storage system of claim 2 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said device via
said non-volatile semiconductor memory interface.
4. The data storage system of claim 2 wherein said adaptive
decision is based on at least one of power modes associated with
prior uses of said write data, a size of said write data, a date of
last use of said write data and a manual override status of said
write data.
5. The data storage system of claim 1 wherein said LP HDD includes
one or more platters, wherein said one or more platters have a
diameter that is less than or equal to 1.8'' and wherein said HP
nonvolatile memory comprises a hard disk drive including one or
more platters, wherein said one or more platters have a diameter
that is greater than 1.8''.
6. The data storage system of claim 1 further comprising: a cache
control module that communicates with said LP and HP nonvolatile
memory and that includes a drive power reduction module, wherein
when read data is read from said HP nonvolatile memory during said
low power mode and said read data includes a sequential access data
file, said drive power reduction module calculates a burst period
for transfers of segments of said read data from said HP
nonvolatile memory to said LP nonvolatile memory.
7. The data storage system of claim 6 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said device via
said non-volatile semiconductor memory interface.
8. The data storage system of claim 6 wherein said drive power
reduction module selects said burst period to reduce power
consumption during playback of said read data during said low power
mode.
9. The data storage system of claim 6 wherein said HP nonvolatile
memory comprises a high power disk drive (HPDD).
10. The data storage system of claim 9 wherein said burst period is
based on at least one of spin-up time of said LP HDD, spin-up time
of said HPDD, power consumption of said LP HDD, power consumption
of said HPDD, playback length of said read data, and capacity of
said LP HDD.
11. The data storage system of claim 1 further comprising: an
operating system that communicates with said LP and HP nonvolatile
memory and that includes a drive power reduction module, wherein
when read data is read from said HP nonvolatile memory during said
low power mode and said read data includes a sequential access data
file, said drive power reduction module calculates a burst period
for transfers of segments of said read data from said HP
nonvolatile memory to LP nonvolatile memory.
12. The data storage system of claim 11 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said non-volatile
semiconductor memory interface.
13. The data storage system of claim 11 wherein said drive power
reduction module selects said burst period to reduce power
consumption during playback of said read data during said low power
mode.
14. The data storage system of claim 11 wherein said HP nonvolatile
memory comprises a high power disk drive (HPDD).
15. The data storage system of claim 14 wherein said burst period
is based on at least one of spin-up time of said LP HDD, spin-up
time of said HPDD, power consumption of said LP HDD, power
consumption of said HPDD, playback length of said read data, and
capacity of said LP HDD.
16. The data storage system of claim 1 further comprising: a host
control module that communicates with said LP and HP nonvolatile
memory and that includes an adaptive storage module, wherein when
write data is to be written to one of said LP and HP nonvolatile
memory, said adaptive storage module generates an adaptive storage
decision that selects one of said LP and HP nonvolatile memory.
17. The data storage system of claim 16 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said non-volatile
semiconductor memory interface.
18. The data storage system of claim 16 wherein said adaptive
decision is based on at least one of power modes associated with
prior uses of said write data, a size of said write data, a date of
last use of said write data and a manual override status of said
write data.
19. The data storage system of claim 1 further comprising: a host
control module that communicates with said LP and HP nonvolatile
memory and that includes a drive power reduction module, wherein
when read data is read from said HP nonvolatile memory during said
low power mode and said read data includes a sequential access data
file, said drive power reduction module calculates a burst period
for transfers of segments of said read data from said HP
nonvolatile memory to LP nonvolatile memory.
20. The data storage system of claim 19 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said non-volatile
semiconductor memory interface.
21. The data storage system of claim 19 wherein said drive power
reduction selects said burst period to reduce power consumption
during playback of said read data during said low power mode.
22. The data storage system of claim 19 wherein said HP nonvolatile
memory comprises a high power disk drive (HPDD).
23. The data storage system of claim 22 wherein said burst period
is based on at least one of spin-up time of said LP HDD, spin-up
time of said HPDD, power consumption of said LP HDD, power
consumption of said HPDD, playback length of said read data, and
capacity of said LP HDD.
24. The data storage system of claim 1 further comprising: an
operating system that communicates with said LP and HP nonvolatile
memory and that includes an adaptive storage module, wherein when
write data is to be written to one of said LP and HP nonvolatile
memory, said adaptive storage module generates an adaptive storage
decision that selects one of said LP and HP nonvolatile memory.
25. The data storage system of claim 24 wherein said HP nonvolatile
memory includes a HP HDD that communicates with said non-volatile
semiconductor memory interface.
26. The data storage system of claim 24 wherein said adaptive
decision is based on at least one of power modes associated with
prior uses of said write data, a size of said write data, a date of
last use of said write data and a manual override status of said
write data.
27. A method for operating a data storage system for a device
including low power and high power modes, comprising: providing low
power (LP) nonvolatile memory that includes a LP hard disk drive
(HDD) having a non-volatile semiconductor memory interface, wherein
said LP HDD communicates with said device via said non-volatile
semiconductor memory interface; providing a high power (HP)
nonvolatile memory; and selecting at least one of said LP
nonvolatile memory and HP nonvolatile memory based on a selected
power mode of said device.
28. The method of claim 27 further comprising generating an
adaptive storage decision that selects one of said LP and HP
nonvolatile memory when write data is to be written to one of said
LP and HP nonvolatile memory.
29. The method of claim 28 wherein said HP nonvolatile memory
includes a HP HDD that communicates with said device via said
non-volatile semiconductor memory interface.
30. The method of claim 29 wherein said adaptive decision is based
on at least one of power modes associated with prior uses of said
write data, a size of said write data, a date of last use of said
write data and a manual override status of said write data.
31. The method of claim 27 further comprising calculating a burst
period for transfers of segments of said read data from said HP
nonvolatile memory to LP nonvolatile memory when read data is read
from said HP nonvolatile memory during said low power mode and said
read data includes a sequential access data file.
32. The method of claim 31 wherein said HP nonvolatile memory
includes a HP HDD that communicates with said device via said
non-volatile semiconductor memory interface.
33. The method of claim 31 further comprising selecting said burst
period to reduce power consumption during playback of said read
data during said low power mode.
34. The method of claim 31 wherein said HP nonvolatile memory
comprises a high power disk drive (HPDD).
35. The method of claim 34 wherein said burst period is based on at
least one of spin-up time of said LP HDD, spin-up time of said
HPDD, power consumption of said LP HDD, power consumption of said
HPDD, playback length of said read data, and capacity of said LP
HDD.
36. The method of claim 27 further comprising calculating a burst
period for transfers of segments of said read data from said HP
nonvolatile memory to LP nonvolatile memory when read data is read
from said HP nonvolatile memory during said low power mode and said
read data includes a sequential access data file.
37. The method of claim 36 wherein said HP nonvolatile memory
includes a HP HDD that communicates with said flash interface.
38. The method of claim 36 further comprising selecting said burst
period to reduce power consumption during playback of said read
data during said low power mode.
39. The method of claim 36 wherein said HP nonvolatile memory
comprises a high power disk drive (HPDD).
40. The method of claim 39 wherein said burst period is based on at
least one of spin-up time of said LP HDD, spin-up time of said
HPDD, power consumption of said LP HDD, power consumption of said
HPDD, playback length of said read data, and capacity of said LP
HDD.
41. The data storage system of claim 1 wherein said non-volatile
semiconductor memory interface includes a flash memory
interface.
42. The method of claim 27 wherein said non-volatile semiconductor
memory interface includes a flash memory interface.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/503,016, filed Aug. 11, 2006, which claims
of the benefit of Provisional Application Ser. No. 60/820,867 filed
on Jul. 31, 2006, and Provisional Application Ser. No. 60/799,151
filed on May 10, 2006, is a continuation-in-part of U.S. patent
application Ser. No. 10/865,368, filed on Jun. 10, 2004, and also
is a continuation-in-part of U.S. patent application Ser. No.
11/322,447, which was filed on Dec. 29, 2005 and which claims the
benefit of Provisional Application Ser. No. 60/678,249 filed on May
5, 2005, is related to U.S. patent application Ser. No. 10/779,544,
which was filed on Feb. 13, 2004, and is related to U.S. patent
application Ser. No. 10/865,732, which was filed on Jun. 10, 2004.
The disclosures of these applications are all hereby incorporated
by reference in their entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to data storage systems, and
more particularly to low power data storage systems.
BACKGROUND OF THE INVENTION
[0003] Laptop computers are powered using both line power and
battery power. The processor, graphics processor, memory and
display of the laptop computer consume a significant amount of
power during operation. One significant limitation of laptop
computers relates to the amount of time that the laptop can be
operated using batteries without recharging. The relatively high
power dissipation of the laptop computer usually corresponds to a
relatively short battery life.
[0004] Referring now to FIG. 1A, an exemplary computer architecture
4 is shown to include a processor 6 with memory 7 such as cache.
The processor 6 communicates with an input/output (I/O) interface
8. Volatile memory 9 such as random access memory (RAM) 10 and/or
other suitable electronic data storage also communicates with the
interface 8. A graphics processor 11 and memory 12 such as cache
increase the speed of graphics processing and performance.
[0005] One or more I/O devices such as a keyboard 13 and a pointing
device 14 (such as a mouse and/or other suitable device)
communicate with the interface 8. A high power disk drive (HPDD) 15
such as a hard disk drive having one or more platters with a
diameter greater than 1.8'' provides nonvolatile memory, stores
data and communicates with the interface 8. The HPDD 15 typically
consumes a relatively high amount of power during operation. When
operating on batteries, frequent use of the HPDD 15 will
significantly decrease battery life. The computer architecture 4
also includes a display 16, an audio output device 17 such as audio
speakers and/or other input/output devices that are generally
identified at 18.
[0006] Referring now to FIG. 1B, an exemplary computer architecture
20 includes a processing chipset 22 and an I/O chipset 24. For
example, the computer architecture may be a Northbridge/Southbridge
architecture (with the processing chipset corresponding to the
Northbridge chipset and the I/O chipset corresponding to the
Southbridge chipset) or other similar architecture. The processing
chipset 22 communicates with a processor 25 and a graphics
processor 26 via a system bus 27. The processing chipset 22
controls interaction with volatile memory 28 (such as external DRAM
or other memory), a Peripheral Component Interconnect (PCI) bus 30,
and/or Level 2 cache 32. Level 1 cache 33 and 34 may be associated
with the processor 25 and/or the graphics processor 26,
respectively. In an alternate embodiment, an Accelerated Graphics
Port (AGP) (not shown) communicates with the processing chipset 22
instead of and/or in addition to the graphics processor 26. The
processing chipset 22 is typically but not necessarily implemented
using multiple chips. PCI slots 36 interface with the PCI bus
30.
[0007] The I/O chipset 24 manages the basic forms of input/output
(I/O). The I/O chipset 24 communicates with an Universal Serial Bus
(USB) 40, an audio device 41, a keyboard (KBD) and/or pointing
device 42, and a Basic Input/Output System (BIOS) 43 via an
Industry Standard Architecture (ISA) bus 44. Unlike the processing
chipset 22, the I/O chipset 24 is typically (but not necessarily)
implemented using a single chip, which is connected to the PCI bus
30. A HPDD 50 such as a hard disk drive also communicates with the
I/O chipset 24. The HPDD 50 stores a full-featured operating system
(OS) such as Windows XP.RTM. Windows 2000.RTM., Linux and
MAC.RTM.-based OS that is executed by the processor 25.
SUMMARY OF THE INVENTION
[0008] A disk drive system for a device with high power and low
power modes, comprises a low power disk drive (LPDD). A high power
disk drive (HPDD). At least one of the LPDD and the HPDD
communicates with the device via a non-volatile semiconductor
memory interface.
[0009] In other features, a control module includes a least used
block (LUB) module that identifies a LUB in the LPDD and that
selectively transfers the LUB to the HPDD during the low power mode
when at least one of a data storing request and a data retrieving
request is received. During the storing request for write data, the
control module transfers the write data to the LPDD if sufficient
space is available on the LPDD for the write data. If there is
insufficient space available for the write data on the LPDD, the
control module powers the HPDD and transfers the LUB from the LPDD
to the HPDD and transfers the write data to the LPDD. The control
module includes an adaptive storage module that determines whether
the write data is likely to be used before the LUB when there is
insufficient space available for the write data on the LPDD. If the
write data is likely to be used after the LUB, the control module
stores the write data on the HPDD. If the write data is likely to
be used before the LUB, the control module powers the HPDD and
transfers the LUB from the LPDD to the HPDD and then transfers the
write data to the LPDD.
[0010] In other features, during the data retrieving request for
read data, the control module retrieves the read data from the LPDD
if the read data is stored in the LPDD. The control module includes
an adaptive storage module that determines whether the read data is
likely to be used once when the read data is not located on the
LPDD and wherein the control module retrieves the read data from
the HPDD if the read data is likely to be used once. If the
adaptive storage module determines that the read data is likely to
be used more than once, the control module transfers the read data
from the HPDD to the LPDD if sufficient space is available on the
LPDD for the read data. If the adaptive storage module determines
that the read data is likely to be used more than once, the control
module transfers the LUB from the LPDD to the HPDD and the read
data from the HPDD to the LPDD if sufficient space is not available
on the LPDD for the read data. The control module transfers the
read data from the HPDD to the LPDD if sufficient space is
available on the LPDD for the read data. The control module
transfers the LUB from the LPDD to the HPDD and the read data from
the HPDD to the LPDD if sufficient space is not available on the
LPDD for the read data. If the read data is not located on the
LPDD, the control module retrieves the read data from the HPDD.
[0011] In other features, the HPDD includes one or more platters,
wherein the one or more platters have a diameter that is greater
than 1.8'' and wherein the LPDD includes one or more platters,
wherein the one or more platters have a diameter that is less than
or equal to 1.8''. The HPDD and the LPDD communicate with the
device via the non-volatile semiconductor memory interface. A
control module communicates with the LPDD and the HPDD. During a
storing request for write data in the low power mode, the control
module determines whether there is sufficient space available on
the LPDD for the write data and transfers the write data to the
LPDD if sufficient space is available. The HPDD and the LPDD
communicate with the device via the non-volatile semiconductor
memory interface. The control module stores the write data on the
HPDD if insufficient space is available. The control module further
includes a LPDD maintenance module that transfers data files from
the LPDD to the HPDD during the high power mode to increase
available disk space on the LPDD. The LPDD maintenance module
transfers the data files based on at least one of age, size and
likelihood of future use in the low power mode.
[0012] In other features, the HPDD includes one or more platters,
wherein the one or more platters have a diameter that is greater
than 1.8'' and wherein the LPDD includes one or more platters,
wherein the one or more platters have a diameter that is less than
or equal to 1.8''.
[0013] A method for operating a disk drive system for a device with
high power and low power modes, comprises providing a low power
disk drive (LPDD) and a high power disk drive (HPDD); and
communicating between at least one of the LPDD and the HPDD and the
device via a non-volatile semiconductor memory interface.
[0014] In other features, the method comprises identifying a LUB in
the LPDD; and selectively transferring the LUB to the HPDD during
the low power mode when at least one of a data storing request and
a data retrieving request is received. The method includes
transferring the write data to the LPDD if sufficient space is
available on the LPDD for the write data during the storing request
for write data. The method includes powering the HPDD and
transferring the LUB from the LPDD to the HPDD and transferring the
write data to the LPDD if there is insufficient space available for
the write data on the LPDD. The method includes determining whether
the write data is likely to be used before the LUB when there is
insufficient space available for the write data on the LPDD. The
method includes storing the write data on the HPDD if the write
data is likely to be used after the LUB. The method includes
powering the HPDD and transferring the LUB from the LPDD to the
HPDD and then transferring the write data to the LPDD if the write
data is likely to be used before the LUB. The method includes
retrieving the read data from the LPDD if the read data is stored
in the LPDD during the data retrieving request for read data. The
method includes determining whether the read data is likely to be
used once when the read data is not located on the LPDD; and
retrieving the read data from the HPDD if the read data is likely
to be used once.
[0015] In other features, the method comprises transferring the
read data from the HPDD to the LPDD if sufficient space is
available on the LPDD for the read data if the read data is likely
to be used more than once. The method includes transferring the LUB
from the LPDD to the HPDD and the read data from the HPDD to the
LPDD if sufficient space is not available on the LPDD for the read
data if the read data is likely to be used more than once. The
method includes transferring the read data from the HPDD to the
LPDD if sufficient space is available on the LPDD for the read
data. The method includes transferring the LUB from the LPDD to the
HPDD and the read data from the HPDD to the LPDD if sufficient
space is not available on the LPDD for the read data. The method
includes retrieving the read data from the HPDD if the read data is
not located on the LPDD. The HPDD and the LPDD communicate with the
device via the non-volatile semiconductor memory interface. The
method includes determining whether there is sufficient space
available on the LPDD for the write data and transferring the write
data to the LPDD if sufficient space is available during a storing
request for write data in the low power mode.
[0016] In other features, the HPDD and the LPDD communicate with
the device via the non-volatile semiconductor memory interface. The
method includes storing the write data on the HPDD if insufficient
space is available. The method includes transferring data files
from the LPDD to the HPDD during the high power mode to increase
available disk space on the LPDD. The method includes transferring
the data files based on at least one of age, size and likelihood of
future use in the low power mode.
[0017] A disk drive system for a device with high power and low
power modes comprises non-volatile semiconductor memory interface
means for interfacing memory; a low power disk drive (LPDD); and a
high power disk drive (HPDD), wherein at least one of the LPDD and
the HPDD communicates with the device via the non-volatile
semiconductor memory interface means.
[0018] In other features, control means for controlling includes
least used block (LUB) means for identifying a LUB in the LPDD. The
control means selectively transfers the LUB to the HPDD during the
low power mode when at least one of a data storing request and a
data retrieving request is received. During the storing request for
write data, the control means transfers the write data to the LPDD
if sufficient space is available on the LPDD for the write data. If
there is insufficient space available for the write data on the
LPDD, the control means powers the HPDD and transfers the LUB from
the LPDD to the HPDD and transfers the write data to the LPDD. The
control means includes adaptive storage means for determining
whether the write data is likely to be used before the LUB when
there is insufficient space available for the write data on the
LPDD. If the write data is likely to be used after the LUB, the
control means stores the write data on the HPDD. If the write data
is likely to be used before the LUB, the control means powers the
HPDD and transfers the LUB from the LPDD to the HPDD and then
transfers the write data to the LPDD. During the data retrieving
request for read data, the control means retrieves the read data
from the LPDD if the read data is stored in the LPDD. The control
means includes adaptive storage means for determining whether the
read data is likely to be used once when the read data is not
located on the LPDD and wherein the control means retrieves the
read data from the HPDD if the read data is likely to be used
once.
[0019] In other features, if the adaptive storage means determines
that the read data is likely to be used more than once, the control
means transfers the read data from the HPDD to the LPDD if
sufficient space is available on the LPDD for the read data. If the
adaptive storage means determines that the read data is likely to
be used more than once, the control means transfers the LUB from
the LPDD to the HPDD and the read data from the HPDD to the LPDD if
sufficient space is not available on the LPDD for the read data.
The control means transfers the read data from the HPDD to the LPDD
if sufficient space is available on the LPDD for the read data. The
control means transfers the LUB from the LPDD to the HPDD and the
read data from the HPDD to the LPDD if sufficient space is not
available on the LPDD for the read data. If the read data is not
located on the LPDD, the control means retrieves the read data from
the HPDD. The HPDD includes one or more platters, wherein the one
or more platters have a diameter that is greater than 1.8'' and
wherein the LPDD includes one or more platters, wherein the one or
more platters have a diameter that is less than or equal to
1.8''.
[0020] In other features, the HPDD and the LPDD communicate with
the device via the non-volatile semiconductor memory interface
means. Control means for controlling communicates with the LPDD and
the HPDD. During a storing request for write data in the low power
mode, the control means determines whether there is sufficient
space available on the LPDD for the write data and transfers the
write data to the LPDD if sufficient space is available. The HPDD
and the LPDD communicate with the device via the non-volatile
semiconductor memory interface means. The control means stores the
write data on the HPDD if insufficient space is available. The
control means further includes LPDD maintenance means for
transferring data files from the LPDD to the HPDD during the high
power mode to increase available disk space on the LPDD.
[0021] In other features, the LPDD maintenance means transfers the
data files based on at least one of age, size and likelihood of
future use in the low power mode. The HPDD includes one or more
platters, wherein the one or more platters have a diameter that is
greater than 1.8'' and wherein the LPDD includes one or more
platters, wherein the one or more platters have a diameter that is
less than or equal to 1.8''.
[0022] A data storage system for a device including low power and
high power modes comprises low power (LP) nonvolatile memory that
includes a LP hard disk drive (HDD) having a non-volatile
semiconductor memory interface. The LP HDD communicates with the
device via the non-volatile semiconductor memory interface. High
power (HP) nonvolatile memory communicates with the device.
[0023] In other features, a cache control module communicates with
the LP and HP nonvolatile memory and that includes an adaptive
storage module. When write data is to be written to one of the LP
and HP nonvolatile memory, the adaptive storage module generates an
adaptive storage decision that selects one of the LP and HP
nonvolatile memory. The HP nonvolatile memory includes a HP HDD
that communicates with the device via the non-volatile
semiconductor memory interface. The adaptive decision is based on
at least one of power modes associated with prior uses of the write
data, a size of the write data, a date of last use of the write
data and a manual override status of the write data. The LP HDD
includes one or more platters. The one or more platters have a
diameter that is less than or equal to 1.8''. The HP nonvolatile
memory comprises a hard disk drive including one or more platters.
The one or more platters have a diameter that is greater than
1.8''.
[0024] In other features, a cache control module communicates with
the LP and HP nonvolatile memory and includes a drive power
reduction module. When read data is read from the HP nonvolatile
memory during the low power mode and the read data includes a
sequential access data file, the drive power reduction module
calculates a burst period for transfers of segments of the read
data from the HP nonvolatile memory to the LP nonvolatile memory.
The HP nonvolatile memory includes a HP HDD that communicates with
the device via the non-volatile semiconductor memory interface. The
drive power reduction module selects the burst period to reduce
power consumption during playback of the read data during the low
power mode. The HP nonvolatile memory comprises a high power disk
drive (HPDD). The burst period is based on at least one of spin-up
time of the LP HDD, spin-up time of the HPDD, power consumption of
the LP HDD, power consumption of the HPDD, playback length of the
read data, and capacity of the LP HDD.
[0025] In other features, an operating system communicates with the
LP and HP nonvolatile memory and includes a drive power reduction
module. When read data is read from the HP nonvolatile memory
during the low power mode and the read data includes a sequential
access data file, the drive power reduction module calculates a
burst period for transfers of segments of the read data from the HP
nonvolatile memory to LP nonvolatile memory. The HP nonvolatile
memory includes a HP HDD that communicates with the non-volatile
semiconductor memory interface. The drive power reduction module
selects the burst period to reduce power consumption during
playback of the read data during the low power mode. The HP
nonvolatile memory comprises a high power disk drive (HPDD). The
burst period is based on at least one of spin-up time of the LP
HDD, spin-up time of the HPDD, power consumption of the LP HDD,
power consumption of the HPDD, playback length of the read data,
and capacity of the LP HDD.
[0026] In other features, a host control module communicates with
the LP and HP nonvolatile memory and includes an adaptive storage
module. When write data is to be written to one of the LP and HP
nonvolatile memory, the adaptive storage module generates an
adaptive storage decision that selects one of the LP and HP
nonvolatile memory. The HP nonvolatile memory includes a HP HDD
that communicates with the non-volatile semiconductor memory
interface. The adaptive decision is based on at least one of power
modes associated with prior uses of the write data, a size of the
write data, a date of last use of the write data and a manual
override status of the write data.
[0027] In other features, a host control module communicates with
the LP and HP nonvolatile memory and includes a drive power
reduction module. When read data is read from the HP nonvolatile
memory during the low power mode and the read data includes a
sequential access data file, the drive power reduction module
calculates a burst period for transfers of segments of the read
data from the HP nonvolatile memory to LP nonvolatile memory. The
HP nonvolatile memory includes a HP HDD that communicates with the
non-volatile semiconductor memory interface. The drive power
reduction selects the burst period to reduce power consumption
during playback of the read data during the low power mode. The HP
nonvolatile memory comprises a high power disk drive (HPDD). The
burst period is based on at least one of spin-up time of the LP
HDD, spin-up time of the HPDD, power consumption of the LP HDD,
power consumption of the HPDD, playback length of the read data,
and capacity of the LP HDD.
[0028] In other features, an operating system communicates with the
LP and HP nonvolatile memory and includes an adaptive storage
module. When write data is to be written to one of the LP and HP
nonvolatile memory, the adaptive storage module generates an
adaptive storage decision that selects one of the LP and HP
nonvolatile memory. The HP nonvolatile memory includes a HP HDD
that communicates with the non-volatile semiconductor memory
interface. The adaptive decision is based on at least one of power
modes associated with prior uses of the write data, a size of the
write data, a date of last use of the write data and a manual
override status of the write data.
[0029] A method for operating a data storage system for a device
including low power and high power modes comprises providing low
power (LP) nonvolatile memory that includes a LP hard disk drive
(HDD) having a non-volatile semiconductor memory interface, wherein
the LP HDD communicates with the device via the non-volatile
semiconductor memory interface; providing a high power (HP)
nonvolatile memory; and selecting at least one of the LP
nonvolatile memory and HP nonvolatile memory based on a selected
power mode of the device.
[0030] In other features, the method comprises generating an
adaptive storage decision that selects one of the LP and HP
nonvolatile memory when write data is to be written to one of the
LP and HP nonvolatile memory. The HP nonvolatile memory includes a
HP HDD that communicates with the device via the non-volatile
semiconductor memory interface. The adaptive decision is based on
at least one of power modes associated with prior uses of the write
data, a size of the write data, a date of last use of the write
data and a manual override status of the write data. The method
includes calculating a burst period for transfers of segments of
the read data from the HP nonvolatile memory to LP nonvolatile
memory when read data is read from the HP nonvolatile memory during
the low power mode and the read data includes a sequential access
data file. The HP nonvolatile memory includes a HP HDD that
communicates with the device via the non-volatile semiconductor
memory interface. The method includes selecting the burst period to
reduce power consumption during playback of the read data during
the low power mode. The HP nonvolatile memory comprises a high
power disk drive (HPDD).
[0031] In other features, the burst period is based on at least one
of spin-up time of the LP HDD, spin-up time of the HPDD, power
consumption of the LP HDD, power consumption of the HPDD, playback
length of the read data, and capacity of the LP HDD. The method
includes calculating a burst period for transfers of segments of
the read data from the HP nonvolatile memory to LP nonvolatile
memory when read data is read from the HP nonvolatile memory during
the low power mode and the read data includes a sequential access
data file. The HP nonvolatile memory includes a HP HDD that
communicates with the non-volatile semiconductor memory interface.
The method includes selecting the burst period to reduce power
consumption during playback of the read data during the low power
mode. The HP nonvolatile memory comprises a high power disk drive
(HPDD). The burst period is based on at least one of spin-up time
of the LP HDD, spin-up time of the HPDD, power consumption of the
LP HDD, power consumption of the HPDD, playback length of the read
data, and capacity of the LP HDD.
[0032] A data storage system for a device including low power and
high power modes comprises low power (LP) nonvolatile storing means
for storing data that includes a LP hard disk drive (HDD) having
non-volatile semiconductor memory interface means for interfacing,
wherein the LP HDD communicates with the device via the
non-volatile semiconductor memory interface means; and high power
(HP) nonvolatile storing means for storing data that communicates
with the device.
[0033] In other features, cache control means for controlling cache
communicates with the LP and HP nonvolatile storing means and
includes adaptive storage means for generating an adaptive storage
decision that selects one of the LP and HP nonvolatile means when
write data is to be written to one of the LP and HP nonvolatile
means. The HP nonvolatile storing means includes a HP HDD that
communicates with the device via the non-volatile semiconductor
memory interface means. The adaptive decision is based on at least
one of power modes associated with prior uses of the write data, a
size of the write data, a date of last use of the write data and a
manual override status of the write data. The LP HDD includes one
or more platters, wherein the one or more platters have a diameter
that is less than or equal to 1.8'' and wherein the HP nonvolatile
storing means comprises a hard disk drive including one or more
platters, wherein the one or more platters have a diameter that is
greater than 1.8''.
[0034] In other features, cache control means communicates with the
LP and HP nonvolatile storing means and includes drive power
reduction means for calculating a burst period for transfers of
segments of the read data from the HP nonvolatile storing means to
LP nonvolatile storing means when read data is read from the HP
nonvolatile storing means during the low power mode and the read
data includes a sequential access data file. The HP nonvolatile
storing means includes a HP HDD that communicates with the device
via the non-volatile semiconductor memory interface means. The
drive power reduction means selects the burst period to reduce
power consumption during playback of the read data during the low
power mode. The HP nonvolatile storing means comprises a high power
disk drive (HPDD). The burst period is based on at least one of
spin-up time of the LP HDD, spin-up time of the HPDD, power
consumption of the LP HDD, power consumption of the HPDD, playback
length of the read data, and capacity of the LP HDD.
[0035] In other features, an operating system communicates with the
LP and HP nonvolatile storing means and includes drive power
reduction means for calculating a burst period for transfers of
segments of the read data from the HP nonvolatile storing means to
LP nonvolatile storing means when read data is read from the HP
nonvolatile storing means during the low power mode and the read
data includes a sequential access data file. The HP nonvolatile
storing means includes a HP HDD that communicates with the
non-volatile semiconductor memory interface means. The drive power
reduction means selects the burst period to reduce power
consumption during playback of the read data during the low power
mode. The HP nonvolatile storing means comprises a high power disk
drive (HPDD). The burst period is based on at least one of spin-up
time of the LP HDD, spin-up time of the HPDD, power consumption of
the LP HDD, power consumption of the HPDD, playback length of the
read data, and capacity of the LP HDD.
[0036] In other features, host control means for controlling
communicates with the LP and HP nonvolatile storing means and
includes adaptive storage means for generating an adaptive storage
decision that selects one of the LP and HP nonvolatile storing
means when write data is to be written to one of the LP and HP
nonvolatile storing means. The HP nonvolatile storing means
includes a HP HDD that communicates with the non-volatile
semiconductor memory interface means. The adaptive decision is
based on at least one of power modes associated with prior uses of
the write data, a size of the write data, a date of last use of the
write data and a manual override status of the write data.
[0037] In other features, host control means for controlling
communicates with the LP and HP nonvolatile storing means and
includes drive power reduction means for calculating a burst period
for transfers of segments of the read data from the HP nonvolatile
storing means to LP nonvolatile storing means when read data is
read from the HP nonvolatile storing means during the low power
mode and the read data includes a sequential access data file. The
HP nonvolatile storing means includes a HP HDD that communicates
with the non-volatile semiconductor memory interface means. The
drive power reduction means selects the burst period to reduce
power consumption during playback of the read data during the low
power mode. The HP nonvolatile storing means comprises a high power
disk drive (HPDD). The burst period is based on at least one of
spin-up time of the LP HDD, spin-up time of the HPDD, power
consumption of the LP HDD, power consumption of the HPDD, playback
length of the read data, and capacity of the LP HDD.
[0038] In other features, an operating system communicates with the
LP and HP nonvolatile storing means and includes adaptive storage
means for generating an adaptive storage decision that selects one
of the LP and HP nonvolatile storing means when write data is to be
written to one of the LP and HP nonvolatile storing means. The HP
nonvolatile storing means includes a HP HDD that communicates with
the non-volatile semiconductor memory interface means. The adaptive
decision is based on at least one of power modes associated with
prior uses of the write data, a size of the write data, a date of
last use of the write data and a manual override status of the
write data.
[0039] A device that operates in low power and high power modes
comprises volatile memory; nonvolatile memory that includes at
least one of a low power (LP) hard disk drive (HDD) with a
non-volatile semiconductor memory interface and a high power HDD
with a non-volatile semiconductor memory interface; and an
operating system that includes a virtual memory adjustment module
that enables designation of at least a portion of the nonvolatile
memory for paging files to increase virtual memory of the device
system.
[0040] A processing device has high power and low power modes and
comprises a first nonvolatile memory that communicates with the
processing device and that stores a first operating system that is
executed by the processing device during the high power mode; and a
second nonvolatile memory that communicates with the processing
device and that that stores a second operating system that is
executed by the processing device during the low power mode,
wherein the second nonvolatile memory includes a low power (LP)
hard disk drive (HDD) with a non-volatile semiconductor memory
interface.
[0041] In other features, the first nonvolatile memory includes a
high power (HP) HDD that communicates with the non-volatile
semiconductor memory interface and that stores the first operating
system. A primary processing device communicates with the first
nonvolatile memory and executes the first operating system during
the high power mode. A secondary processing device communicates
with the second nonvolatile memory and executes the second
operating system during the low power mode. The first operating
system is a full-featured operating system and the second operating
system is a restricted-feature operating system. A primary graphics
processing device communicates with the first nonvolatile memory
and supports full-featured graphics processing during the high
power mode; and a secondary graphics processing device that
communicates with the second nonvolatile memory and that supports
restricted-feature graphics processing during the low power mode.
The full-featured operating system and the restricted-feature
operating system share a common data format.
[0042] A device that operates in low power and high power modes
comprises volatile storing means for storing data; nonvolatile
storing means for storing data that includes at least one of a low
power (LP) hard disk drive (HDD) with non-volatile semiconductor
memory interface means for interfacing and a high power HDD with
non-volatile semiconductor memory interface means for interfacing;
and an operating system that includes virtual storage adjustment
means for enabling designation of at least a portion of the
nonvolatile storing means for paging files to increase virtual
storage of the device system.
[0043] A processing device having high power and low power modes
comprises first nonvolatile storing means for storing data that
communicates with the processing device and that stores a first
operating system that is executed by the processing device during
the high power mode; and second nonvolatile storing means for
storing data that communicates with the processing device and that
stores a second operating system that is executed by the processing
device during the low power mode, wherein the second nonvolatile
storing means includes a low power (LP) hard disk drive (HDD) with
non-volatile semiconductor memory interface means for
interfacing.
[0044] In other features, the first nonvolatile storing means
includes a high power (HP) HDD that communicates with the
non-volatile semiconductor memory interface means and that stores
the first operating system. Primary processing means communicates
with the first nonvolatile storing means for executing the first
operating system during the high power mode. Secondary processing
means communicates with the second nonvolatile storing means for
executing the second operating system during the low power mode.
The first operating system is a full-featured operating system and
the second operating system is a restricted-feature operating
system.
[0045] In other features, primary graphics processing means
communicates with the first nonvolatile storing means for
supporting full-featured graphics processing during the high power
mode. Secondary graphics processing means communicates with the
second nonvolatile storing means for supporting restricted-feature
graphics processing during the low power mode. The full-featured
operating system and the restricted-feature operating system share
a common data format.
[0046] A method for operating a device in low power and high power
modes comprises providing volatile memory and nonvolatile memory
that includes at least one of a low power (LP) hard disk drive
(HDD) with a non-volatile semiconductor memory interface and a high
power HDD with a non-volatile semiconductor memory interface; and
enabling designation of at least a portion of the nonvolatile
memory for paging files using an operating system to increase
virtual memory of the device.
[0047] A method for operating a processing device having high power
and low power modes comprises providing a first nonvolatile memory
that communicates with the processing device; storing a first
operating system in the first non-volatile memory; executing the
first operating system using the processing device during the high
power mode; providing a second nonvolatile memory that communicates
with the processing device; storing a second operating system n the
second nonvolatile memory; executing the second operating using the
processing device during the low power mode. The second nonvolatile
memory includes a low power (LP) hard disk drive (HDD) with a
non-volatile semiconductor memory interface.
[0048] In other features, the first nonvolatile memory includes a
high power (HP) HDD that communicates with the non-volatile
semiconductor memory interface and stores the first operating
system. The method includes providing a primary processing device
that communicates with the first nonvolatile memory and that
executes the first operating system during the high power mode; and
providing a secondary processing device that communicates with the
second nonvolatile memory and that executes the second operating
system during the low power mode. The first operating system is a
full-featured operating system and the second operating system is a
restricted-feature operating system. The method includes providing
a primary graphics processing device that communicates with the
first nonvolatile memory and that supports full-featured graphics
processing during the high power mode; and providing a secondary
graphics processing device that communicates with the second
nonvolatile memory and that supports restricted-feature graphics
processing during the low power mode. The method includes sharing a
common data format between the full-featured operating system and
the restricted-feature operating system.
[0049] In any of the foregoing implementations, a HDD with the
non-volatile semiconductor memory interface includes a non-volatile
semiconductor memory interface, wherein the non-volatile
semiconductor memory interface includes interface signal lines in
communication with the control module. A buffer memory stores data
received from the control module and from the LPDD. A flash
controller emulates data transfer protocols of the LPDD using the
interface signal lines over the non-volatile semiconductor memory
interface. A memory wrapper communicates with the interface
controller and a buffer manager. The memory wrapper controls the
buffer memory according to data transfer rates of the control
module and the HDD.
[0050] In other features, the flash controller controls the
interface signal lines to implement a random read of the HDD and
controls the interface signal lines to implement a random write of
the HDD. The flash controller controls the interface signal lines
to implement a sequential read of the HDD and controls the
interface signal lines to implement a sequential write of the HDD.
The flash controller controls the interface signal lines to
implement a transfer of commands between the control module and the
HDD.
[0051] In other features, the flash controller maps a set of HDD
commands to a corresponding set of flash memory commands. A
register memory communicates with the interface controller and a
HDD processor via a processor bus. The register memory stores
commands programmed by the HDD processor and the control module.
The flash controller stores read data from the HDD in the buffer
memory to compensate for differences in data transfer rates between
the control module and the HDD and sends a data ready signal to the
control module to indicate there is data in the memory buffer. The
flash controller stores write data from the control module in the
buffer memory to compensate for differences in data transfer rates
between the control module and the HDD and sends a data ready
signal to the control module to indicate there is data in the
memory buffer. The non-volatile semiconductor memory interface is a
NAND type non-volatile semiconductor memory interface.
[0052] In other features, the non-volatile semiconductor memory
interface includes a flash memory interface. The non-volatile
semiconductor memory interface means includes a flash memory
interface.
[0053] Further areas of applicability of the present invention will
become apparent from the detailed description provided hereinafter.
It should be understood that the detailed description and specific
examples, while indicating the preferred embodiment of the
invention, are intended for purposes of illustration only and are
not intended to limit the scope of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The present invention will become more fully understood from
the detailed description and the accompanying drawings,
wherein:
[0055] FIGS. 1A and 1B illustrate exemplary computer architectures
according to the prior art;
[0056] FIG. 2A illustrates a first exemplary computer architecture
according to the present invention with a primary processor, a
primary graphics processor, and primary volatile memory that
operate during a high power mode and a secondary processor and a
secondary graphics processor that communicate with the primary
processor, that operate during a low power mode and that employ the
primary volatile memory during the low power mode;
[0057] FIG. 2B illustrates a second exemplary computer architecture
according to the present invention that is similar to FIG. 2A and
that includes secondary volatile memory that is connected to the
secondary processor and/or the secondary graphics processor;
[0058] FIG. 2C illustrates a third exemplary computer architecture
according to the present invention that is similar to FIG. 2A and
that includes embedded volatile memory that is associated with the
secondary processor and/or the secondary graphics processor;
[0059] FIG. 3A illustrates a fourth exemplary architecture
according to the present invention for a computer with a primary
processor, a primary graphics processor, and primary volatile
memory that operate during a high power mode and a secondary
processor and a secondary graphics processor that communicate with
a processing chipset, that operate during the low power mode and
that employ the primary volatile memory during the low power
mode;
[0060] FIG. 3B illustrates a fifth exemplary computer architecture
according to the present invention that is similar to FIG. 3A and
that includes secondary volatile memory connected to the secondary
processor and/or the secondary graphics processor;
[0061] FIG. 3C illustrates a sixth exemplary computer architecture
according to the present invention that is similar to FIG. 3A and
that includes embedded volatile memory that is associated with the
secondary processor and/or the secondary graphics processor;
[0062] FIG. 4A illustrates a seventh exemplary architecture
according to the present invention for a computer with a secondary
processor and a secondary graphics processor that communicate with
an I/O chipset, that operate during the low power mode and that
employ the primary volatile memory during the low power mode;
[0063] FIG. 4B illustrates an eighth exemplary computer
architecture according to the present invention that is similar to
FIG. 4A and that includes secondary volatile memory connected to
the secondary processor and/or the secondary graphics
processor;
[0064] FIG. 4C illustrates a ninth exemplary computer architecture
according to the present invention that is similar to FIG. 4A and
that includes embedded volatile memory that is associated with the
secondary processor and/or the secondary graphics processor;
and
[0065] FIG. 5 illustrates a caching hierarchy according to the
present invention for the computer architectures of FIGS.
2A-4C;
[0066] FIG. 6 is a functional block diagram of a drive control
module that includes a least used block (LUB) module and that
manages storage and transfer of data between the low-power disk
drive (LPDD) and the high-power disk drive (HPDD);
[0067] FIG. 7A is a flowchart illustrating steps that are performed
by the drive control module of FIG. 6;
[0068] FIG. 7B is a flowchart illustrating alternative steps that
are performed by the drive control module of FIG. 6;
[0069] FIGS. 7C and 7D are flowcharts illustrating alternative
steps that are performed by the drive control module of FIG. 6;
[0070] FIG. 8A illustrates a cache control module that includes an
adaptive storage control module and that controls storage and
transfer of data between the LPDD and HPDD;
[0071] FIG. 8B illustrates an operating system that includes an
adaptive storage control module and that controls storage and
transfer of data between the LPDD and the HPDD;
[0072] FIG. 8C illustrates a host control module that includes an
adaptive storage control module and that controls storage and
transfer of data between the LPDD and HPDD;
[0073] FIG. 9 illustrates steps performed by the adaptive storage
control modules of FIGS. 8A-8C;
[0074] FIG. 10 is an exemplary table illustrating one method for
determining the likelihood that a program or file will be used
during the low power mode;
[0075] FIG. 11A illustrates a cache control module that includes a
disk drive power reduction module;
[0076] FIG. 11B illustrates an operating system that includes a
disk drive power reduction module;
[0077] FIG. 11C illustrates a host control module that includes a
disk drive power reduction module;
[0078] FIG. 12 illustrates steps performed by the disk drive power
reduction modules of FIGS. 11A-11C;
[0079] FIG. 13 illustrates a multi-disk drive system including a
high-power disk drive (HPDD) and a lower power disk drive
(LPDD);
[0080] FIGS. 14-17 illustrate other exemplary implementations of
the multi-disk drive system of FIG. 13;
[0081] FIG. 18 illustrates the use of low power nonvolatile memory
such as flash memory or a low power disk drive (LPDD) for
increasing virtual memory of a computer;
[0082] FIGS. 19 and 20 illustrates steps performed by the operating
system to allocate and use the virtual memory of FIG. 18;
[0083] FIG. 21 is a functional block diagram of a Redundant Array
of Independent Disks (RAID) system according to the prior art;
[0084] FIG. 22A is a functional block diagram of an exemplary RAID
system according to the present invention with a disk array
including X HPDD and a disk array including Y LPDD;
[0085] FIG. 22B is a functional block diagram of the RAID system of
FIG. 22A where X and Y are equal to Z;
[0086] FIG. 23A is a functional block diagram of another exemplary
RAID system according to the present invention with a disk array
including Y LPDD that communicates with a disk array including X
HPDD;
[0087] FIG. 23B is a functional block diagram of the RAID system of
FIG. 23A where X and Y are equal to Z;
[0088] FIG. 24A is a functional block diagram of still another
exemplary RAID system according to the present invention with a
disk array including X HPDD that communicate with a disk array
including Y LPDD;
[0089] FIG. 24B is a functional block diagram of the RAID system of
FIG. 24A where X and Y are equal to Z;
[0090] FIG. 25 is a functional block diagram of a network
attachable storage (NAS) system according to the prior art;
[0091] FIG. 26 is a functional block diagram of a network
attachable storage (NAS) system according to the present invention
that includes the RAID system of FIGS. 22A, 22B, 23A, 23B, 24A
and/or 24B and/or a multi-drive system according to FIGS. 6-17;
[0092] FIG. 27 is a functional block diagram of a disk drive
controller incorporating a flash memory and disk drive interface
controller;
[0093] FIG. 28 is a functional block diagram of the interface
controller of FIG. 27;
[0094] FIG. 29 is a functional block diagram of a multi-disk drive
system with a flash interface; and
[0095] FIG. 30 is a flowchart illustrating steps performed by the
multi-disk drive of FIG. 30.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0096] The following description of the preferred embodiment(s) is
merely exemplary in nature and is in no way intended to limit the
invention, its application, or uses. For purposes of clarity, the
same reference numbers will be used in the drawings to identify
similar elements. As used herein, the term module and/or device
refers to an application specific integrated circuit (ASIC), an
electronic circuit, a processor (shared, dedicated, or group) and
memory that execute one or more software or firmware programs, a
combinational logic circuit, and/or other suitable components that
provide the described functionality.
[0097] As used herein, the term "high power mode" refers to active
operation of the host processor and/or the primary graphics
processor of the host device. The term "low power mode" refers to
low-power hibernating modes, off modes, and/or non-responsive modes
of the primary processor and/or primary graphics processor when a
secondary processor and a secondary graphics processor are
operable. An "off mode" refers to situations when both the primary
and secondary processors are off.
[0098] The term "low power disk drive" or LPDD refers to disk
drives and/or microdrives having one or more platters that have a
diameter that is less than or equal to 1.8''. The term "high power
disk drive" or HPDD refers to hard disk drives having one or more
platters that have a diameter that is greater than 1.8''. LPDDs
typically have lower storage capacities and dissipate less power
than the HPDDs. The LPDDs are also rotated at a higher speed than
the HPDDs. For example, rotational speeds of 10,000-20,000 RPM or
greater can be achieved with LPDDs.
[0099] The term HDD with non-volatile memory interface (IF) refers
to a hard disk drive that is connectable to a host device via a
standard semiconductor memory interface of the host. For example,
the semiconductor memory interface can be a flash interface.
[0100] The HDD with a non-volatile memory IF communicates with the
host via the non-volatile memory interface using a non-volatile
memory interface protocol. The non-volatile memory interface used
by the host and the HDD with non-volatile memory interface can
include flash memory having a flash interface, NAND flash with a
NAND flash interface or any other type of semiconductor memory
interface. The HDD with a non-volatile memory IF can be a LPDD
and/or a HPDD. The HDD with a non-volatile memory IF will be
described further below in conjunction with FIGS. 27 and 28.
Additional details relating to the operation of a HDD with a flash
IF can be found in U.S. patent application Ser. No. 11/322,447,
filed on Dec. 29, 2005, which is hereby incorporated by reference
in its entirety. In each of the implementations set forth below,
the LPDD can be implemented using the HDD (implemented as a HPDD
and/or LPDD) with a non-volatile memory IF. Alternately, the HDD
with a non-volatile memory IF can be a LPDD and/or HPDD used in
addition to the disclosed LPDD and/or HPDD.
[0101] The computer architecture according to the present invention
includes the primary processor, the primary graphics processor, and
the primary memory (as described in conjunction with FIGS. 1A and
1B), which operate during the high power mode. A secondary
processor and a secondary graphics processor are operated during
the low power mode. The secondary processor and the secondary
graphics processor may be connected to various components of the
computer, as will be described below. Primary volatile memory may
be used by the secondary processor and the secondary graphics
processor during the low power mode. Alternatively, secondary
volatile memory, such as DRAM and/or embedded secondary volatile
memory such as embedded DRAM can be used, as will be described
below.
[0102] The primary processor and the primary graphics processor
dissipate relatively high power when operating in the high power
mode. The primary processor and the primary graphics processor
execute a full-featured operating system (OS) that requires a
relatively large amount of external memory. The primary processor
and the primary graphics processor support high performance
operation including complex computations and advanced graphics. The
full-featured OS can be a Windows.RTM.-based OS such as Windows
XP.RTM., a Linux-based OS, a MAC.RTM.-based OS and the like. The
full-featured OS is stored in the HPDD 15 and/or 50.
[0103] The secondary processor and the secondary graphics processor
dissipate less power (than the primary processor and primary
graphics processor) during the low power mode. The secondary
processor and the secondary graphics processor operate a
restricted-feature operating system (OS) that requires a relatively
small amount of external volatile memory. The secondary processor
and secondary graphics processor may also use the same OS as the
primary processor. For example, a pared-down version of the
full-featured OS may be used. The secondary processor and the
secondary graphics processor support lower performance operation, a
lower computation rate and less advanced graphics. For example, the
restricted-feature OS can be Windows CE.RTM. or any other suitable
restricted-feature OS. The restricted-feature OS is preferably
stored in nonvolatile memory such as flash memory, a HDD with a
non-volatile memory IF, a HPDD and/or a LPDD. In a preferred
embodiment, the full-featured and restricted-feature OS share a
common data format to reduce complexity.
[0104] The primary processor and/or the primary graphics processor
preferably include transistors that are implemented using a
fabrication process with a relatively small feature size. In one
implementation, these transistors are implemented using an advanced
CMOS fabrication process. Transistors implemented in the primary
processor and/or primary graphics processor have relatively high
standby leakage, relatively short channels and are sized for high
speed. The primary processor and the primary graphics processor
preferably employ predominantly dynamic logic. In other words, they
cannot be shut down. The transistors are switched at a duty cycle
that is less than approximately 20% and preferably less than
approximately 10%, although other duty cycles may be used.
[0105] In contrast, the secondary processor and/or the secondary
graphics processor preferably include transistors that are
implemented with a fabrication process having larger feature sizes
than the process used for the primary processor and/or primary
graphics processor. In one implementation, these transistors are
implemented using a regular CMOS fabrication process. The
transistors implemented in the secondary processor and/or the
secondary graphics processor have relatively low standby leakage,
relatively long channels and are sized for low power dissipation.
The secondary processor and the secondary graphics processor
preferably employ predominantly static logic rather than dynamic
logic. The transistors are switched at a duty cycle that is greater
than 80% and preferably greater than 90%, although other duty
cycles may be used.
[0106] The primary processor and the primary graphics processor
dissipate relatively high power when operated in the high power
mode. The secondary processor and the secondary graphics processor
dissipate less power when operating in the low power mode. In the
low power mode, however, the computer architecture is capable of
supporting fewer features and computations and less complex
graphics than when operating in the high power mode. As can be
appreciated by skilled artisans, there are many ways of
implementing the computer architecture according to the present
invention. Therefore, skilled artisans will appreciate that the
architectures that are described below in conjunction with FIGS.
2A-4C are merely exemplary in nature and are not limiting.
[0107] Referring now to FIG. 2A, a first exemplary computer
architecture 60 is shown. The primary processor 6, the volatile
memory 9 and the primary graphics processor 11 communicate with the
interface 8 and support complex data and graphics processing during
the high power mode. A secondary processor 62 and a secondary
graphics processor 64 communicate with the interface 8 and support
less complex data and graphics processing during the low power
mode. Optional nonvolatile memory 65 such as a LPDD 66 and/or flash
memory and/or a HDD with a non-volatile memory IF 69 communicates
with the interface 8 and provides low power nonvolatile storage of
data during the low power and/or high power modes. The HDD with a
non-volatile memory IF can be a LPDD and/or a HPDD. The HPDD 15
provides high power/capacity nonvolatile memory. The nonvolatile
memory 65 and/or the HPDD 15 are used to store the restricted
feature OS and/or other data and files during the low power
mode.
[0108] In this embodiment, the secondary processor 62 and the
secondary graphics processor 64 employ the volatile memory 9 (or
primary memory) while operating in the low-power mode. To that end,
at least part of the interface 8 is powered during the low power
mode to support communications with the primary memory and/or
communications between components that are powered during the low
power mode. For example, the keyboard 13, the pointing device 14
and the primary display 16 may be powered and used during the low
power mode. In all of the embodiments described in conjunction with
FIGS. 2A-4C, a secondary display with reduced capabilities (such as
a monochrome display) and/or a secondary input/output device can
also be provided and used during the low power mode.
[0109] Referring now to FIG. 2B, a second exemplary computer
architecture 70 that is similar to the architecture in FIG. 2A is
shown. In this embodiment, the secondary processor 62 and the
secondary graphics processor 64 communicate with secondary volatile
memory 74 and/or 76. The secondary volatile memory 74 and 76 can be
DRAM or other suitable memory. During the low power mode, the
secondary processor 62 and the secondary graphics processor 64
utilize the secondary volatile memory 74 and/or 76, respectively,
in addition to and/or instead of the primary volatile memory 9
shown and described in FIG. 2A.
[0110] Referring now to FIG. 2C, a third exemplary computer
architecture 80 that is similar to FIG. 2A is shown. The secondary
processor 62 and/or secondary graphics processor 64 include
embedded volatile memory 84 and 86, respectively. During the low
power mode, the secondary processor 62 and the secondary graphics
processor 64 utilize the embedded volatile memory 84 and/or 86,
respectively, in addition to and/or instead of the primary volatile
memory. In one embodiment, the embedded volatile memory 84 and 86
is embedded DRAM (eDRAM), although other types of embedded volatile
memory can be used.
[0111] Referring now to FIG. 3A, a fourth exemplary computer
architecture 100 according to the present invention is shown. The
primary processor 25, the primary graphics processor 26, and the
primary volatile memory 28 communicate with the processing chipset
22 and support complex data and graphics processing during the high
power mode. A secondary processor 104 and a secondary graphics
processor 108 support less complex data and graphics processing
when the computer is in the low power mode. In this embodiment, the
secondary processor 104 and the secondary graphics processor 108
employ the primary volatile memory 28 while operating in the low
power mode. To that end, the processing chipset 22 may be fully
and/or partially powered during the low power mode to facilitate
communications therebetween. The HPDD 50 may be powered during the
low power mode to provide high power volatile memory. Low power
nonvolative memory 109 (LPDD 110 and/or flash memory and/or HDD
with a non-volatile memory IF 113) is connected to the processing
chipset 22, the I/O chipset 24 or in another location and stores
the restricted-feature operating system for the low power mode. The
HDD with a non-volatile memory IF can be a LPDD and/or a HPDD.
[0112] The processing chipset 22 may be fully and/or partially
powered to support operation of the HPDD 50, the LPDD 110, and/or
other components that will be used during the low power mode. For
example, the keyboard and/or pointing device 42 and the primary
display may be used during the low power mode.
[0113] Referring now to FIG. 3B, a fifth exemplary computer
architecture 150 that is similar to FIG. 3A is shown. Secondary
volatile memory 154 and 158 is connected to the secondary processor
104 and/or secondary graphics processor 108, respectively. During
the low power mode, the secondary processor 104 and the secondary
graphics processor 108 utilize the secondary volatile memory 154
and 158, respectively, instead of and/or in addition to the primary
volatile memory 28. The processing chipset 22 and the primary
volatile memory 28 can be shut down during the low power mode if
desired. The secondary volatile memory 154 and 158 can be DRAM or
other suitable memory.
[0114] Referring now to FIG. 3C, a sixth exemplary computer
architecture 170 that is similar to FIG. 3A is shown. The secondary
processor 104 and/or secondary graphics processor 108 include
embedded memory 174 and 176, respectively. During the low power
mode, the secondary processor 104 and the secondary graphics
processor 108 utilize the embedded memory 174 and 176,
respectively, instead of and/or in addition to the primary volatile
memory 28. In one embodiment, the embedded volatile memory 174 and
176 is embedded DRAM (eDRAM), although other types of embedded
memory can be used.
[0115] Referring now to FIG. 4A, a seventh exemplary computer
architecture 190 according to the present invention is shown. The
secondary processor 104 and the secondary graphics processor 108
communicate with the I/O chipset 24 and employ the primary volatile
memory 28 as volatile memory during the low power mode. The
processing chipset 22 remains fully and/or partially powered to
allow access to the primary volatile memory 28 during the low power
mode.
[0116] Referring now to FIG. 4B, an eighth exemplary computer
architecture 200 that is similar to FIG. 4A is shown. Secondary
volatile memory 154 and 158 is connected to the secondary processor
104 and the secondary graphics processor 108, respectively, and is
used instead of and/or in addition to the primary volatile memory
28 during the low power mode. The processing chipset 22 and the
primary volatile memory 28 can be shut down during the low power
mode.
[0117] Referring now to FIG. 4C, a ninth exemplary computer
architecture 210 that is similar to FIG. 4A is shown. Embedded
volatile memory 174 and 176 is provided for the secondary processor
104 and/or the secondary graphics processor 108, respectively in
addition to and/or instead of the primary volatile memory 28. In
this embodiment, the processing chipset 22 and the primary volatile
memory 28 can be shut down during the low power mode.
[0118] Referring now to FIG. 5, a caching hierarchy 250 for the
computer architectures illustrated in FIGS. 2A-4C is shown. The HP
nonvolatile memory HPDD 50 is located at a lowest level 254 of the
caching hierarchy 250. Level 254 may or may not be used during the
low power mode if the HPDD 50 is disabled and will be used if the
HPDD 50 is enabled during the low power mode. The LP nonvolatile
memory such as LPDD 110, flash memory and/or HDD with a
non-volatile memory IF 113 is located at a next level 258 of the
caching hierarchy 250. External volatile memory such as primary
volatile memory, secondary volatile memory and/or secondary
embedded memory is a next level 262 of the caching hierarchy 250,
depending upon the configuration. Level 2 or secondary cache
comprises a next level 266 of the caching hierarchy 250. Level 1
cache is a next level 268 of the caching hierarchy 250. The CPU
(primary and/or secondary) is a last level 270 of the caching
hierarchy. The primary and secondary graphics processor use a
similar hierarchy.
[0119] The computer architecture according to the present invention
provides a low power mode that supports less complex processing and
graphics. As a result, the power dissipation of the computer can be
reduced significantly. For laptop applications, battery life is
extended.
[0120] Referring now to FIG. 6, a drive control module 300 or host
control module for a multi-disk drive system includes a least used
block (LUB) module 304, an adaptive storage module 306, and/or a
LPDD maintenance module 308. The drive control module 300 controls
storage and data transfer between a high-powered disk drive (HPDD)
310 such as a hard disk drive and a low-power disk drive (LPDD) 312
such as a microdrive based in part on LUB information. The drive
control module 300 reduces power consumption by managing data
storage and transfer between the HPDD and LPDD during the high and
low power modes. As can be seen in FIG. 6, a HDD with a
non-volatile memory IF 317 may be used as the LPDD and/or in
addition to the LPDD. The drive control module 300 communicates
with the HDD with a non-volatile memory IF 317 via a host
non-volatile memory IF 315 and a host 313. The drive control module
300 may be integrated with the host 313 and/or the host
non-volatile memory IF 315.
[0121] The least used block module 304 keeps track of the least
used block of data in the LPDD 312. During the low-power mode, the
least used block module 304 identifies the least used block of data
(such as files and/or programs) in the LPDD 312 so that it can be
replaced when needed. Certain data blocks or files may be exempted
from the least used block monitoring such as files that relate to
the restricted-feature operating system only, blocks that are
manually set to be stored in the LPDD 312, and/or other files and
programs that are operated during the low power mode only. Still
other criteria may be used to select data blocks to be overwritten,
as will be described below.
[0122] During the low power mode during a data storing request the
adaptive storage module 306 determines whether write data is more
likely to be used before the least used blocks. The adaptive
storage module 306 also determines whether read data is likely to
be used only once during the low power mode during a data retrieval
request. The LPDD maintenance module 308 transfers aged data from
the LPDD to the HPDD during the high power mode and/or in other
situations as will be described below.
[0123] Referring now to FIG. 7A, steps performed by the drive
control module 300 are shown. Control begins in step 320. In step
324, the drive control module 300 determines whether there is a
data storing request. If step 324 is true, the drive control module
300 determines whether there is sufficient space available on the
LPDD 312 in step 328. If not, the drive control module 300 powers
the HPDD 310 in step 330. In step 334, the drive control module 300
transfers the least used data block to the HPDD 310. In step 336,
the drive control module 300 determines whether there is sufficient
space available on the LPDD 312. If not, control loops to step 334.
Otherwise, the drive control module 300 continues with step 340 and
turns off the HPDD 310. In step 344, data to be stored (e.g. from
the host) is transferred to the LPDD 312.
[0124] If step 324 is false, the drive control module 300 continues
with step 350 and determines whether there is a data retrieving
request. If not, control returns to step 324. Otherwise, control
continues with step 354 and determines whether the data is located
in the LPDD 312. If step 354 is true, the drive control module 300
retrieves the data from the LPDD 312 in step 356 and continues with
step 324. Otherwise, the drive control module 300 powers the HPDD
310 in step 360. In step 364, the drive control module 300
determines whether there is sufficient space available on the LPDD
312 for the requested data. If not, the drive control module 300
transfers the least used data block to the HPDD 310 in step 366 and
continues with step 364. When step 364 is true, the drive control
module 300 transfers data to the LPDD 312 and retrieves data from
the LPDD 312 in step 368. In step 370, control turns off the HPDD
310 when the transfer of the data to the LPDD 312 is complete.
[0125] Referring now to FIG. 7B, a modified approach that is
similar to that shown in FIG. 7A is used and includes one or more
adaptive steps performed by the adaptive storage module 306. When
there is sufficient space available on the LPDD in step 328,
control determines whether the data to be stored is likely to be
used before the data in the least used block or blocks that are
identified by the least used block module in step 372. If step 372
is false, the drive control module 300 stores the data on the HPDD
in step 374 and control continues with step 324. By doing so, the
power that is consumed to transfer the least used block(s) to the
LPDD is saved. If step 372 is true, control continues with step 330
as described above with respect to FIG. 7A.
[0126] When step 354 is false during a data retrieval request,
control continues with step 376 and determines whether data is
likely to be used once. If step 376 is true, the drive control
module 300 retrieves the data from the HPDD in step 378 and
continues with step 324. By doing so, the power that would be
consumed to transfer the data to the LPDD is saved. If step 376 is
false, control continues with step 360. As can be appreciated, if
the data is likely to be used once, there is no need to move the
data to the LPDD. The power dissipation of the HPDD, however,
cannot be avoided.
[0127] Referring now to FIG. 7C, a more simplified form of control
can also be performed during low power operation. Maintenance steps
can also be performed during high power and/or low power modes
(using the LPDD maintenance module 308). In step 328, when there is
sufficient space available on the LPDD, the data is transferred to
the LPDD in step 344 and control returns to step 324. Otherwise,
when step 328 is false, the data is stored on the HPDD in step 380
and control returns to step 324. As can be appreciated, the
approach illustrated in FIG. 7C uses the LPDD when capacity is
available and uses the HPDD when LPDD capacity is not available.
Skilled artisans will appreciate that hybrid methods may be
employed using various combinations of the steps of FIGS.
7A-7D.
[0128] In FIG. 7D, maintenance steps are performed by the drive
control module 300 upon returning to the high power mode and/or at
other times to delete unused or low use files that are stored on
the LPDD. This maintenance step can also be performed in the low
power mode, periodically during use, upon the occurrence of an
event such as a disk full event, and/or in other situations.
Control begins in step 390. In step 392, control determines whether
the high power mode is in use. If not, control loops back to step
7D. If step 392 is true, control determines whether the last mode
was the low power mode in step 394. If not, control returns to step
392. If step 394 is false, control performs maintenance such as
moving aged or low use files from the LPDD to the HPDD in step 396.
Adaptive decisions may also be made as to which files are likely to
be used in the future, for example using criteria described above
and below in conjunction with FIGS. 8A-10.
[0129] Referring now to FIGS. 8A and 8B, storage control systems
400-1, 400-2 and 400-3 are shown. In FIG. 8A, the storage control
system 400-1 includes a cache control module 410 with an adaptive
storage control module 414. The adaptive storage control module 414
monitors usage of files and/or programs to determine whether they
are likely to be used in the low power mode or the high power mode.
The cache control module 410 communicates with one or more data
buses 416, which in turn, communicate with volatile memory 422 such
as L1 cache, L2 cache, volatile RAM such as DRAM and/or other
volatile electronic data storage. The buses 416 also communicate
with low power nonvolatile memory 424 (such as flash memory, a HDD
with a non-volatile memory IF and/or a LPDD) and/or high power
nonvolatile memory 426 such as a HPDD 426. In FIG. 8B, a
full-featured and/or restricted feature operating system 430 is
shown to include the adaptive storage control module 414. Suitable
interfaces and/or controllers (not shown) are located between the
data bus and the HPDD and/or LPDD.
[0130] In FIG. 8C, a host control module 440 includes the adaptive
storage control module 414. The host control module 440
communicates with a LPDD 426' and a hard disk drive 426'. The host
control module 440 can be a drive control module, an Integrated
Device Electronics (IDE), ATA, serial ATA (SATA) or other
controller. As can be seen in FIG. 8C, a HDD with a non-volatile
memory IF 431 may be used as the LPDD and/or in addition to the
LPDD. The host control module 440 communicates with the HDD with a
non-volatile memory IF 431 via a host non-volatile memory IF 429.
The host control module 440 may be integrated with the host
non-volatile memory IF 429.
[0131] Referring now to FIG. 9, steps performed by the storage
control systems in FIGS. 8A-8C are shown. In FIG. 9, control begins
with step 460. In step 462, control determines whether there is a
request for data storage to nonvolatile memory. If not, control
loops back to step 462. Otherwise, the adaptive storage control
module 414 determines whether data is likely to be used in the
low-power mode in step 464. If step 464 is false, data is stored in
the HPDD in step 468. If step 464 is true, the data is stored in
the nonvolatile memory 444 in step 474.
[0132] Referring now to FIG. 10, one way of determining whether a
data block is likely to be used in the low-power mode is shown. A
table 490 includes a data block descriptor field 492, a low-power
counter field 493, a high-power counter field 494, a size field
495, a last use field 496 and/or a manual override field 497. When
a particular program or file is used during the low-power or
high-power modes, the counter field 493 and/or 494 is incremented.
When data storage of the program or file is required to nonvolatile
memory, the table 492 is accessed. A threshold percentage and/or
count value may be used for evaluation. For example, if a file or
program is used greater than 80 percent of the time in the
low-power mode, the file may be stored in the low-power nonvolatile
memory such as flash memory, a HDD with a non-volatile memory IF
and/or the microdrive. If the threshold is not met, the file or
program is stored in the high-power nonvolatile memory.
[0133] As can be appreciated, the counters can be reset
periodically, after a predetermined number of samples (in other
words to provide a rolling window), and/or using any other
criteria. Furthermore, the likelihood may be weighted, otherwise
modified, and/or replaced by the size field 495. In other words, as
the file size grows, the required threshold may be increased
because of the limited capacity of the LPDD.
[0134] Further modification of the likelihood of use decision may
be made on the basis of the time since the file was last used as
recorded by the last use field 496. A threshold date may be used
and/or the time since last use may be used as one factor in the
likelihood determination. While a table is shown in FIG. 10, one or
more of the fields that are used may be stored in other locations
and/or in other data structures. An algorithm and/or weighted
sampling of two or more fields may be used.
[0135] Using the manual override field 497 allows a user and/or the
operating system to manually override of the likelihood of use
determination. For example, the manual override field may allow an
L status for default storage in the LPDD, an H status for default
storage in the HPDD and/or an A status for automatic storage
decisions (as described above). Other manual override
classifications may be defined. In addition to the above criteria,
the current power level of the computer operating in the LPDD may
be used to adjust the decision. Skilled artisans will appreciate
that there are other methods for determining the likelihood that a
file or program will be used in the high-power or low-power modes
that fall within the teachings of the present invention.
[0136] Referring now to FIGS. 11A and 11B, drive power reduction
systems 500-1, 500-2 and 500-3 (collectively 500) are shown. The
drive power reduction system 500 bursts segments of a larger
sequential access file such as but not limited audio and/or video
files to the low power nonvolatile memory on a periodic or other
basis. In FIG. 11A, the drive power reduction system 500-1 includes
a cache control module 520 with a drive power reduction control
module 522. The cache control module 520 communicates with one or
more data buses 526, which in turn, communicate with volatile
memory 530 such as L1 cache, L2 cache, volatile RAM such as DRAM
and/or other volatile electronic data storage, nonvolatile memory
534 such as flash memory, a HDD with a non-volatile memory IF
and/or a LPDD, and a HPDD 538. In FIG. 11B, the drive power
reduction system 500-2 includes a full-featured and/or restricted
feature operating system 542 with a drive power reduction control
module 522. Suitable interfaces and/or controllers (not shown) are
located between the data bus and the HPDD and/or LPDD.
[0137] In FIG. 11C, the drive power reduction system 500-3 includes
a host control module 560 with an adaptive storage control module
522. The host control module 560 communicates with one or more data
buses 564, which communicate with the LPDD 534' and the hard disk
drive 538'. The host control module 560 can be a drive control
module, an Integrated Device Electronics (IDE), ATA, serial ATA
(SATA) and/or other controller or interface. As can be seen in FIG.
11C, a HDD with a non-volatile memory IF 531 may be used as the
LPDD and/or in addition to the LPDD. The host control module 560
communicates with the HDD with a non-volatile memory IF 531 via a
host non-volatile memory IF 529. The host control module 560 may be
integrated with the host non-volatile memory IF 529.
[0138] Referring now to FIG. 12, steps performed by the drive power
reduction systems 500 in FIGS. 11A-11C are shown. Control begins
the step 582. In step 584, control determines whether the system is
in a low-power mode. If not, control loops back to step 584. If
step 586 is true, control continues with step 586 where control
determines whether a large data block access is typically requested
from the HPDD in step 586. If not, control loops back to step 584.
If step 586 is true, control continues with step 590 and determines
whether the data block is accessed sequentially. If not, control
loops back to 584. If step 590 is true, control continues with step
594 and determines the playback length. In step 598, control
determines a burst period and frequency for data transfer from the
high power nonvolatile memory to the low power nonvolatile
memory.
[0139] In one implementation, the burst period and frequency are
optimized to reduce power consumption. The burst period and
frequency are preferably based upon the spin-up time of the HPDD
and/or the LPDD, the capacity of the nonvolatile memory, the
playback rate, the spin-up and steady state power consumption of
the HPDD and/or LPDD, and/or the playback length of the sequential
data block.
[0140] For example, the high power nonvolatile memory is a HPDD
that consumes 1-2 W during operation, has a spin-up time of 4-10
seconds and a capacity that is typically greater than 20 Gb. The
low power nonvolatile memory is a microdrive that consumes 0.3-0.5
W during operation, has a spin-up time of 1-3 seconds, and a
capacity of 1-6 Gb. As can be appreciated, the forgoing performance
values and/or capacities will vary for other implementations. The
HPDD may have a data transfer rate of 1 Gb/s to the microdrive. The
playback rate may be 10 Mb/s (for example for video files). As can
be appreciated, the burst period times the transfer rate of the
HPDD should not exceed the capacity of the microdrive. The period
between bursts should be greater than the spin-up time plus the
burst period. Within these parameters, the power consumption of the
system can be optimized. In the low power mode, if the HPDD is
operated to play an entire video such as a movie, a significant
amount of power is consumed. Using the method described above, the
power dissipation can be reduced significantly by selectively
transferring the data from the HPDD to the LPDD in multiple burst
segments spaced at fixed intervals at a very high rate (e.g.,
100.times. the playback rate) and then the HPDD can be shut down.
Power savings that are greater than 50% can easily be achieved.
[0141] Referring now to FIG. 13, a multi-disk drive system 640
according to the present invention is shown to include a drive
control module 650 and one or more HPDD 644 and one or more LPDD
648. The drive control module 650 communicates with a host device
via host control module 651. To the host, the multi-disk drive
system 640 effectively operates the HPDD 644 and LPDD 648 as a
unitary disk drive to reduce complexity, improve performance and
decrease power consumption, as will be described below. The host
control module 651 can be an IDE, ATA, SATA and/or other control
module or interface.
[0142] Referring now to FIG. 14, in one implementation the drive
control module 650 includes a hard disk controller (HDC) 653 that
is used to control one or both of the LPDD and/or HPDD. A buffer
656 stores data that is associated the control of the HPDD and/or
LPDD and/or aggressively buffers data to/from the HPDD and/or LPDD
to increase data transfer rates by optimizing data block sizes. A
processor 657 performs processing that is related to the operation
of the HPDD and/or LPDD.
[0143] The HPDD 648 includes one or more platters 652 having a
magnetic coating that stores magnetic fields. The platters 652 are
rotated by a spindle motor that is schematically shown at 654.
Generally the spindle motor 654 rotates the platter 652 at a fixed
speed during the read/write operations. One or more read/write arms
658 move relative to the platters 652 to read and/or write data
to/from the platters 652. Since the HPDD 648 has larger platters
than the LPDD, more power is required by the spindle motor 654 to
spin-up the HPDD and to maintain the HPDD at speed. Usually, the
spin-up time is higher for HPDD as well.
[0144] A read/write device 659 is located near a distal end of the
read/write arm 658. The read/write device 659 includes a write
element such as an inductor that generates a magnetic field. The
read/write device 659 also includes a read element (such as a
magneto-resistive (MR) element) that senses the magnetic field on
the platter 652. A preamp circuit 660 amplifies analog read/write
signals.
[0145] When reading data, the preamp circuit 660 amplifies low
level signals from the read element and outputs the amplified
signal to the read/write channel device. While writing data, a
write current is generated that flows through the write element of
the read/write device 659 and is switched to produce a magnetic
field having a positive or negative polarity. The positive or
negative polarity is stored by the platter 652 and is used to
represent data. The LPDD 644 also includes one or more platters
662, a spindle motor 664, one or more read/write arms 668, a
read/write device 669, and a preamp circuit 670.
[0146] The HDC 653 communicates with the host control module 651
and with a first spindle/voice coil motor (VCM) driver 672, a first
read/write channel circuit 674, a second spindleNCM driver 676, and
a second read/write channel circuit 678. The host control module
651 and the drive control module 650 can be implemented by a system
on chip (SOC) 684. As can be appreciated, the spindle VCM drivers
672 and 676 and/or read/write channel circuits 674 and 678 can be
combined. The spindle/VCM drivers 672 and 676 control the spindle
motors 654 and 664, which rotate the platters 652 and 662,
respectively. The spindle/VCM drivers 672 and 676 also generate
control signals that position the read/write arms 658 and 668,
respectively, for example using a voice coil actuator, a stepper
motor or any other suitable actuator.
[0147] Referring now to FIGS. 15-17, other variations of the
multi-disk drive system are shown. In FIG. 15, the drive control
module 650 may include a direct interface 680 for providing an
external connection to one or more LPDD 682. In one implementation,
the direct interface is a Peripheral Component Interconnect (PCI)
bus, a PCI Express (PCIX) bus, and/or any other suitable bus or
interface.
[0148] In FIG. 16, the host control module 651 communicates with
both the LPDD 644 and the HPDD 648. A low power drive control
module 650LP and a high power disk drive control module 650HP
communicate directly with the host control module. Zero, one or
both of the LP and/or the HP drive control modules can be
implemented as a SOC. As can be seen in FIG. 16, a HDD with a
non-volatile memory IF 695 may be used as the LPDD and/or in
addition to the LPDD. The host control module 651 communicates with
the HDD with a non-volatile memory IF 695 via a host non-volatile
memory IF 693. The host control module 651 may be integrated with
the host non-volatile memory IF 693.
[0149] In FIG. 17, one exemplary LPDD 682 is shown to include an
interface 690 that supports communications with the direct
interface 680. As set forth above, the interfaces 680 and 690 can
be a Peripheral Component Interconnect (PCI) bus, a PCI Express
(PCIX) bus, and/or any other suitable bus or interface. The LPDD
682 includes an HDC 692, a buffer 694 and/or a processor 696. The
LPDD 682 also includes the spindle/VCM driver 676, the read/write
channel circuit 678, the platter 662, the spindle motor 665, the
read/write arm 668, the read element 669, and the preamp 670, as
described above. Alternately, the HDC 653, the buffer 656 and the
processor 658 can be combined and used for both drives. Likewise
the spindle/VCM driver and read channel circuits can optionally be
combined. In the embodiments in FIGS. 13-17, aggressive buffering
of the LPDD is used to increase performance. For example, the
buffers are used to optimize data block sizes for optimum speed
over host data buses.
[0150] In conventional computer systems, a paging file is a hidden
file on the HPDD or HP nonvolatile memory that is used by the
operating system to hold parts of programs and/or data files that
do not fit in the volatile memory of the computer. The paging file
and physical memory, or RAM, define virtual memory of the computer.
The operating system transfers data from the paging file to memory
as needed and returns data from the volatile memory to the paging
file to make room for new data. The paging file is also called a
swap file.
[0151] Referring now to FIGS. 18-20, the present invention utilizes
the LP nonvolatile memory such as the LPDD, a HDD with a
non-volatile memory IF and/or flash memory to increase the virtual
memory of the computer system. In FIG. 18, an operating system 700
allows a user to define virtual memory 702. During operation, the
operating system 700 addresses the virtual memory 702 via one or
more buses 704. The virtual memory 702 includes both volatile
memory 708 and LP nonvolatile memory 710 such as flash memory, a
HDD with a non-volatile memory IF and/or a LPDD.
[0152] Referring now to FIG. 19, the operating system allows a user
to allocate some or all of the LP nonvolatile memory 710 as paging
memory to increase virtual memory. In step 720, control begins. In
step 724, the operating system determines whether additional paging
memory is requested. If not, control loops back to step 724.
Otherwise, the operating system allocates part of the LP
nonvolatile memory for paging file use to increase the virtual
memory in step 728.
[0153] In FIG. 20, the operating system employs the additional LP
nonvolatile memory as paging memory. Control begins in step 740. In
step 744, control determines whether the operating system is
requesting a data write operation. If true, control continues with
step 748 and determines whether the capacity of the volatile memory
is exceeded. If not, the volatile memory is used for the write
operation in step 750. If step 748 is true, data is stored in the
paging file in the LP nonvolatile memory in step 754. If step 744
is false, control continues with step 760 and determines whether a
data read is requested. If false, control loops back to step 744.
Otherwise, control determines whether the address corresponds to a
RAM address in step 764. If step 764 is true, control reads data
from the volatile memory in step 764 and continues with step 744.
If step 764 is false, control reads data from the paging file in
the LP nonvolatile memory in step 770 and control continues with
step 744.
[0154] As can be appreciated, using LP nonvolatile memory such as
flash memory, a HDD with a non-volatile memory IF and/or the LPDD
to increase the size of virtual memory will increase the
performance of the computer as compared to systems employing the
HPDD. Furthermore, the power consumption will be lower than systems
using the HPDD for the paging file. The HPDD requires additional
spin-up time due to its increased size, which increases data access
times as compared to the flash memory, which has no spin-up
latency, and/or the LPDD or a LPDD HDD with a non-volatile memory
IF, which has a shorter spin-up time and lower power
dissipation.
[0155] Referring now to FIG. 21, a Redundant Array of Independent
Disks (RAID) system 800 is shown to include one or more servers
and/or clients 804 that communicate with a disk array 808. The one
or more servers and/or clients 804 include a disk array controller
812 and/or an array management module 814. The disk array
controller 812 and/or the array management module 814 receive data
and perform logical to physical address mapping of the data to the
disk array 808. The disk array typically includes a plurality of
HPDD 816.
[0156] The multiple HPDDs 816 provide fault tolerance (redundancy)
and/or improved data access rates. The RAID system 800 provides a
method of accessing multiple individual HPDDs as if the disk array
808 is one large hard disk drive. Collectively, the disk array 808
may provide hundreds of Gb to 10's to 100's of Tb of data storage.
Data is stored in various ways on the multiple HPDDs 816 to reduce
the risk of losing all of the data if one drive fails and to
improve data access time.
[0157] The method of storing the data on the HPDDs 816 is typically
called a RAID level. There are various RAID levels including RAID
level 0 or disk striping. In RAID level 0 systems, data is written
in blocks across multiple drives to allow one drive to write or
read a data block while the next is seeking the next block. The
advantages of disk striping include the higher access rate and full
utilization of the array capacity. The disadvantage is there is no
fault tolerance. If one drive fails, the entire contents of the
array become inaccessible.
[0158] RAID level 1 or disk mirroring provides redundancy by
writing twice--once to each drive. If one drive fails, the other
contains an exact duplicate of the data and the RAID system can
switch to using the mirror drive with no lapse in user
accessibility. The disadvantages include a lack of improvement in
data access speed and higher cost due to the increased number of
drives (2N) that are required. However, RAID level 1 provides the
best protection of data since the array management software will
simply direct all application requests to the surviving HPDDs when
one of the HPDDs fails.
[0159] RAID level 3 stripes data across multiple drives with an
additional drive dedicated to parity, for error
correction/recovery. RAID level 5 provides striping as well as
parity for error recovery. In RAID level 5, the parity block is
distributed among the drives of the array, which provides more
balanced access load across the drives. The parity information is
used to recovery data if one drive fails. The disadvantage is a
relatively slow write cycle (2 reads and 2 writes are required for
each block written). The array capacity is N-1, with a minimum of 3
drives required.
[0160] RAID level 0+1 involves stripping and mirroring without
parity. The advantages are fast data access (like RAID level 0),
and single drive fault tolerance (like RAID level 1). RAID level
0+1 still requires twice the number of disks (like RAID level 1).
As can be appreciated, there can be other RAID levels and/or
methods for storing the data on the array 808.
[0161] Referring now to FIGS. 22A and 22B, a RAID system 834-1
according to the present invention includes a disk array 836 that
includes X HPDD and a disk array 838 that includes Y LPDD. One or
more clients and/or a servers 840 include a disk array controller
842 and/or an array management module 844. While separate devices
842 and 844 are shown, these devices can be integrated if desired.
As can be appreciated, X is greater than or equal to 2 and Y is
greater than or equal to 1. X can be greater than Y, less than Y
and/or equal to Y. For example, FIG. 22B shows a RAID system 834-1'
where X=Y=Z.
[0162] Referring now to FIGS. 23A, 23B, 24A and 24B, RAID systems
834-2 and 834-3 are shown. In FIG. 23A, the LPDD disk array 838
communicates with the servers/clients 840 and the HPDD disk array
836 communicates with the LPDD disk array 838. The RAID system
834-2 may include a management bypass path that selectively
circumvents the LPDD disk array 838. As can be appreciated, X is
greater than or equal to 2 and Y is greater than or equal to 1. X
can be greater than Y, less than Y and/or equal to Y. For example,
FIG. 23B shows a RAID system 834-2' where X=Y=Z. In FIG. 24A, the
HPDD disk array 836 communicates with the servers/clients 840 and
the LPDD disk array 838 communicates with the HPDD disk array 836.
The RAID system 834-2 may include a management bypass path shown by
dotted line 846 that selectively circumvents the LPDD disk array
838. As can be appreciated, X is greater than or equal to 2 and Y
is greater than or equal to 1. X can be greater than Y, less than Y
and/or equal to Y. For example, FIG. 24B shows a RAID system 834-3'
where X=Y=Z. The strategy employed may include write through and/or
write back in FIGS. 23A-24B.
[0163] The array management module 844 and/or the disk controller
842 utilizes the LPDD disk array 838 to reduce power consumption of
the HPDD disk array 836. Typically, the HPDD disk array 808 in the
conventional RAID system in FIG. 21 is kept on at all times during
operation to support the required data access times. As can be
appreciated, the HPDD disk array 808 dissipates a relatively high
amount of power. Furthermore, since a large amount of data is
stored in the HPDD disk array 808, the platters of the HPDDs are
typically as large as possible, which requires higher capacity
spindle motors and increases the data access times since the
read/write arms move further on average.
[0164] According to the present invention, the techniques that are
described above in conjunction with FIGS. 6-17 are selectively
employed in the RAID system 834 as shown in FIG. 22B to reduce
power consumption and data access times. While not shown in FIGS.
22A and 23A-24B, the other RAID systems according to the present
invention may also use these techniques. In other words, the LUB
module 304, adaptive storage module 306 and/or the LPDD maintenance
module that are described in FIGS. 6 and 7A-7D are selectively
implemented by the disk array controller 842 and/or the array
management controller 844 to selectively store data on the LPDD
disk array 838 to reduce power consumption and data access times.
The adaptive storage control module 414 that is described in FIGS.
8A-8C, 9 and 10 may also be selectively implemented by the disk
array controller 842 and/or the array management controller 844 to
reduce power consumption and data access times. The drive power
reduction module 522 that is described FIGS. 11A-11C and 12 may
also be implemented by the disk array controller 842 and/or the
array management controller 844 to reduce power consumption and
data access times. Furthermore, the multi-drive systems and/or
direct interfaces that are shown in FIGS. 13-17 may be implemented
with one or more of the HPDD in the HPDD disk array 836 to increase
functionality and to reduce power consumption and access times.
[0165] Referring now to FIG. 25, a network attached storage (NAS)
system 850 according to the prior art is shown to include storage
devices 854, storage requesters 858, a file server 862, and a
communications system 866. The storage devices 854 typically
include disc drives, RAID systems, tape drives, tape libraries,
optical drives, jukeboxes, and any other storage devices to be
shared. The storage devices 854 are preferably but not necessarily
object oriented devices. The storage devices 854 may include an I/O
interface for data storage and retrieval by the requesters 858. The
requesters 858 typically include servers and/or clients that share
and/or directly access the storage devices 854.
[0166] The file server 862 performs management and security
functions such as request authentication and resource location. The
storage devices 854 depend on the file server 862 for management
direction, while the requesters 858 are relieved of storage
management to the extent the file server 862 assumes that
responsibility. In smaller systems, a dedicated file server may not
be desirable. In this situation, a requester may take on the
responsibility for overseeing the operation of the NAS system 850.
As such, both the file server 862 and the requester 858 are shown
to include management modules 870 and 872, respectively, though one
or the other and/or both may be provided. The communications system
866 is the physical infrastructure through which components of the
NAS system 850 communicate. It preferably has properties of both
networks and channels, has the ability to connect all components in
the networks and the low latency that is typically found in a
channel.
[0167] When the NAS system 850 is powered up, the storage devices
854 identify themselves either to each other or to a common point
of reference, such as the file server 862, one or more of the
requesters 858 and/or to the communications system 866. The
communications system 866 typically offers network management
techniques to be used for this, which are accessible by connecting
to a medium associated with the communications system. The storage
devices 854 and requesters 858 log onto the medium. Any component
wanting to determine the operating configuration can use medium
services to identify all other components. From the file server
862, the requesters 858 learn of the existence of the storage
devices 854 they could have access to, while the storage devices
854 learn where to go when they need to locate another device or
invoke a management service like backup. Similarly the file server
862 can learn of the existence of storage devices 854 from the
medium services. Depending on the security of a particular
installation, a requester may be denied access to some equipment.
From the set of accessible storage devices, it can then identify
the files, databases, and free space available.
[0168] At the same time, each NAS component can identify to the
file server 862 any special considerations it would like known. Any
device level service attributes could be communicated once to the
file server 862, where all other components could learn of them.
For instance, a requester may wish to be informed of the
introduction of additional storage subsequent to startup, this
being triggered by an attribute set when the requester logs onto
the file server 862. The file server 862 could do this
automatically whenever new storage devices are added to the
configuration, including conveying important characteristics, such
as it being RAID 5, mirrored, and so on.
[0169] When a requester must open a file, it may be able to go
directly to the storage devices 854 or it may have to go to the
file server for permission and location information. To what extent
the file server 854 controls access to storage is a function of the
security requirements of the installation.
[0170] Referring now to FIG. 26, a network attached storage (NAS)
system 900 according to the present invention is shown to include
storage devices 904, requesters 908, a file server 912, and a
communications system 916. The storage devices 904 include the RAID
system 834 and/or multi-disk drive systems 930 described above in
FIGS. 6-19. The storage devices 904 typically may also include disc
drives, RAID systems, tape drives, tape libraries, optical drives,
jukeboxes, and/or any other storage devices to be shared as
described above. As can be appreciated, using the improved RAID
systems and/or multi-disk drive systems 930 will reduce the power
consumption and data access times of the NAS system 900.
[0171] Referring now to FIG. 27, a disk drive controller
incorporating a non-volatile memory and disk drive interface
controller. In other words, the HDD of FIG. 27 has a non-volatile
memory interface (hereinafter called HDD with non-volatile memory
interface (IF)). The device of FIG. 27 allows a HDD to be connected
to an existing non-volatile memory interface (IF) of a host device
to provide additional nonvolatile storage.
[0172] The disk drive controller 1100 communicates with a host 1102
and a disk drive 1104. The HDD with a non-volatile memory IF
includes the disk drive controller 1100 and the disk drive 1104.
The disk drive 1104 typically has an ATA, ATA-CE, or IDE type
interface. Also coupled to the disk drive controller 1100 is an
auxiliary non-volatile memory 1106, which stores firmware code for
the disk drive controller. In this case, the host 1102, while shown
as a single block, typically includes as relevant components an
industry standard non-volatile memory slot (connector) of the type
for connecting to commercially available non-volatile memory
devices, which in turn is connected to a standard non-volatile
memory controller in the host. This slot typically conforms to one
of the standard types, for instance, MMC (Multi Media Card), SD
(Secure Data), SD/MMC which is a combination of SD and MMC, HS-MMC
(High Speed-MMC), SD/HS-MMC which is a combination of SD and
HS-MMC, and Memory Stick. This list is not limiting.
[0173] A typical application is a portable computer or consumer
electronic device such as MP3 music player or cellular telephone
handset that has one application processor that communicates with
an embedded non-volatile memory through a non-volatile memory
interface. The non-volatile memory interface may include a flash
interface, a NAND flash interface and/or other suitable
non-volatile semiconductor memory interfaces. In accordance with
this disclosure, rather than a non-volatile semiconductor memory, a
hard disk drive or other type of disk drive is provided replacing
the non-volatile semiconductor memory and using its interface
signals. The disclosed method provides a non-volatile memory-like
interface for a disk drive, which makes it easier to incorporate a
disk drive in such a host system which normally only accepts flash
memory. One advantage of a disk drive over flash memory as a
storage device is far greater storage capacity for a particular
cost.
[0174] Only minimum changes in the host non-volatile memory
controller firmware and software need be made to incorporate the
disk drive using the disclosed interface controller. Also, minimum
command overhead is provided. Advantageously, there is open-ended
data transfer for any particular read or write operation, in terms
of the number of logic blocks transferred between the host and the
disk drive. Also, no sector count of the disk drive need be
provided by the host.
[0175] In certain embodiments the disk drive 1104 may be a small
form factor (SFF) hard disk drive, which typically has a physical
size of 650.times.15.times.70 mm. A typical data transfer rate of
such SSF hard disk drive is 25 megabytes per second.
[0176] The functions of the disk drive controller 1100 of FIG. 27
are further explained below. The disk drive controller 1100
includes an interface controller 1110, which presents to the host
system 1102 as a flash memory controller with a 14-line bus. The
interface controller 1110 also performs the functions of host
command interpretation and data flow control between the host 1102
and a buffer manager 1112. The buffer manager circuit 1112
controls, via a memory controller 1116, the actual buffer (memory),
which may be an SRAM or DRAM buffer 1118 that may be included as
part of the same chip as interface controller 1100 or be on a
separate chip. The buffer manager provides buffering features that
are described further below.
[0177] The buffer manager 1112 is also connected to a processor
Interface/Servo and ID-Less/Defect Manager (MPIF/SAIL/DM) circuit
1122, which performs the functions of track format generation and
defect management. The MPIF/SAIL/DM circuit 1122, in turn, connects
to the Advanced High Performance Bus (AHB) 1126. Connected to the
AHB bus 1126 is a line cache 1128, and a processor 1130; a Tightly
Coupled Memory (TCM) 1134 is associated with the processor 1130.
The processor 1130 may be implemented by an embedded processor or
by an microprocessor. The purpose of the line cache 1128 is to
reduce code execution latency. It may be coupled to an external
flash memory 1106.
[0178] The remaining blocks in the disk drive controller 1100
perform functions to support a disk drive and include the servo
controller 1140, the disk formatter and error correction circuit
1142, and the read channel circuitry 1144, which connects to the
pre-amplification circuit in the disk drive 1104. The 14-line
parallel bus with 8 lines (0-7) may carry the bi-directional in/out
(I/O) data. The remaining lines may carry the commands CLE, ALE,
/CE, /RE, /WE and R/B respectively.
[0179] Referring now to FIG. 28, the interface controller of FIG.
27 is shown in more detail. The interface controller 1110 includes
a flash controller (flash_ctl) block 1150, a flash register
(flash_reg) block 1152, a flash FIFO wrapper (flash_fifo_wrapper)
block 1154, and a flash system synchronization (flash_sys_syn)
block 1156.
[0180] The flash register block 1152 is used for register access.
It stores commands programmed by the processor 1130 and the host
1102. A flash state machine (not shown) in the flash controller
1150 decodes the incoming command from the host 1102 and provides
the controls for the disk drive controller 1100. The flash FIFO
wrapper 1154 includes a FIFO, which may be implemented by a
32.times.32 bi-directional asynchronous FIFO. It generates data and
control signals for transferring data to and receiving data from
the buffer manager 1112 via the buffer manager interface (BM IF).
The transfer direction of the FIFO may be controlled by the
commands stored in the flash register 1152. The flash system
synchronization block 1156 synchronizes control signals between the
interface controller and the buffer manager interface. It also
generates a counter clear pulse (clk2_clr) for the flash FIFO
wrapper 1154.
[0181] The flash controller 1150 may control the interface signal
lines to implement a random read of the LPDD. The flash controller
1150 may control the interface signal lines to implement a random
write of the LPDD. The flash controller 1150 may control the
interface signal lines to implement a sequential read of the LPDD
and may control the interface signal lines to implement a
sequential write of the LPDD. The flash controller 1150 may control
the interface signal lines to implement a transfer of commands
between the control module and the LPDD. The flash controller 1150
may map a set of LPDD commands to a corresponding set of flash
memory commands.
[0182] The register memory 1152 communicates with the interface
controller and a LPDD processor via a processor bus. The register
memory 1152 stores commands programmed by the LPDD processor and
the control module. The flash controller 1150 may store read data
from the LPDD in the buffer memory to compensate for differences in
data transfer rates between the control module and the LPDD and may
send a data ready signal to the control module to indicate there is
data in the memory buffer.
[0183] The flash controller 1150 may store write data from the
control module in the buffer memory to compensate for differences
in data transfer rates between the control module and the LPDD. The
flash controller 1150 may send a data ready signal to the control
module to indicate there is data in the memory buffer.
[0184] Referring now to FIG. 29, a functional block diagram of a
multi-disk drive system with a flash interface is shown generally
at 1200. While the preceding discussion related to the use of one
disk drive (such as the low power or high power disk drive) with a
flash interface, multiple disk drives can be connected via the
flash interface. More particularly, the multi-disk drive system
with a flash interface 1200 include a host flash interface 1206
that communicates with a flash interface of a host 1202. The host
flash interface 1202 operates as described above. A drive control
module 1208 selectively operates zero, one or both of the HPDD 1220
and the LPDD 1222. Control techniques that are described above with
respect to operation of low power and high power modes can be
performed by the drive control module 1208. In some
implementations, the host flash interface 1206 senses a power mode
of the host and/or receives information that identifies a power
mode of the host 1202.
[0185] Referring now to FIG. 30, a flowchart illustrating steps
performed by the multi-disk drive of FIG. 30 are shown. Control
begins with step 1230. In step 1232, control determines whether the
host is on. If step 1232 is true, control determines whether the
host is in a high power mode in step 1234. If step 1234 is true,
control powers up the LPDD 1222 and/or the HPDD 1220 as needed in
step 1236. If step 1234 is false, control determines whether the
host is in a low power mode in strp 1238. If step 1238 is true,
control powers down the HPDD and operates the LPDD as needed to
conserve power in step 1240. Control continues from step 1238 (if
false) and step 1240 with step 1232.
[0186] As can be appreciated, the HDDs with flash interfaces that
are described above can use the multi-disk drive with flash
interface as described above. Furthermore, any of the control
techniques described above with respect to systems with LPDD and
HPDD can be used in the multi-disk drive with flash interface shown
in FIG. 29. The LPDD or HPDD can be replaced in any of the
embodiments described above by any type of low power non-volatile
memory. For example, the LPDD or HPDD can be replaced by any
suitable non-volatile solid state memory such as but not limited to
flash memory. Likewise, the low power non-volatile memory described
in any of the embodiments described above may be replaced by the
low power disk drives. While flash memory is described above in
some embodiments, any type of non-volatile semiconductor memory can
be used.
[0187] Those skilled in the art can now appreciate from the
foregoing description that the broad teachings of the present
invention can be implemented in a variety of forms. Therefore,
while this invention has been described in connection with
particular examples thereof, the true scope of the invention should
not be so limited since other modifications will become apparent to
the skilled practitioner upon a study of the drawings, the
specification and the following claims.
* * * * *