U.S. patent application number 11/799786 was filed with the patent office on 2007-09-06 for insulating gate algan/gan hemts.
This patent application is currently assigned to CREE, INC.. Invention is credited to Umesh Mishra, Primit Parikh, Yifeng Wu.
Application Number | 20070205433 11/799786 |
Document ID | / |
Family ID | 23190213 |
Filed Date | 2007-09-06 |
United States Patent
Application |
20070205433 |
Kind Code |
A1 |
Parikh; Primit ; et
al. |
September 6, 2007 |
Insulating gate AlGaN/GaN HEMTs
Abstract
AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to
reduce trapping and also having additional layers to reduce gate
leakage and increase the maximum drive current. One HEMT according
to the present invention comprises a high resistivity semiconductor
layer with a barrier semiconductor layer on it. The barrier layer
has a wider bandgap than the high resistivity layer and a 2DEG
forms between the layers. Source and drain contacts contact the
barrier layer, with part of the surface of the barrier layer
uncovered by the contacts. An insulating layer is included on the
uncovered surface of the barrier layer and a gate contact is
included on the insulating layer. The insulating layer forms a
barrier to gate leakage current and also helps to increase the
HEMT's maximum current drive. The invention also includes methods
for fabricating HEMTs according to the present invention. In one
method, the HEMT and its insulating layer are fabricated using
metal-organic chemical vapor deposition (MOCVD). In another method
the insulating layer is sputtered onto the top surface of the HEMT
in a sputtering chamber.
Inventors: |
Parikh; Primit; (Goleta,
CA) ; Mishra; Umesh; (Santa Barbara, CA) ; Wu;
Yifeng; (Goleta, CA) |
Correspondence
Address: |
KOPPEL, PATRICK & HEYBL
555 ST. CHARLES DRIVE
SUITE 107
THOUSAND OAKS
CA
91360
US
|
Assignee: |
CREE, INC.
|
Family ID: |
23190213 |
Appl. No.: |
11/799786 |
Filed: |
May 3, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10201345 |
Jul 23, 2002 |
7230284 |
|
|
11799786 |
May 3, 2007 |
|
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60307546 |
Jul 24, 2001 |
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Current U.S.
Class: |
257/192 ;
257/E21.445; 257/E29.005; 257/E29.253; 438/172 |
Current CPC
Class: |
H01L 29/518 20130101;
H01L 29/7787 20130101; H01L 2924/00 20130101; H01L 29/432 20130101;
H01L 23/3171 20130101; H01L 29/517 20130101; H01L 29/7783 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; H01L 29/7786
20130101; H01L 23/291 20130101; H01L 29/2003 20130101 |
Class at
Publication: |
257/192 ;
438/172; 257/E21.445; 257/E29.005 |
International
Class: |
H01L 21/338 20060101
H01L021/338; H01L 29/06 20060101 H01L029/06 |
Claims
1. A high electron mobility transistor (HEMT), comprising: a high
resistivity semiconductor layer; a barrier semiconductor layer on
said high resistivity layer, said barrier layer having a wider
bandgap than said high resistivity layer; a two-dimensional
electron gas between said barrier layer and said high resistivity
layer; respective source and drain contacts contacting said barrier
layer, with part of the surface of said barrier layer uncovered by
said source and drain contacts; an insulating layer on said
uncovered surface of said barrier layer; and a gate contact on said
insulating layer, said insulating layer forming a barrier to gate
leakage current and increasing the HEMT's maximum current
drive.
2. The HEMT of claim 1, wherein said high resistivity semiconductor
layer and said barrier semiconductor layer are made of a Group III
nitride semiconductor material.
3. The HEMT of claim 1, wherein said high resistivity semiconductor
layer and said barrier semiconductor layer are made of a AlGaN/GaN
semiconductor material.
4. The HEMT of claim 1, wherein said insulating layer comprises
silicon nitride (SiN), aluminum nitride (AlN), silicon dioxide
(SiO.sub.2) or multiple layers thereof.
5. The HEMT of claim 1, wherein said insulating layer comprises
silicon nitride.
6. The HEMT of claim 1, wherein said insulating layer is only below
said gate contact and is sandwiched between said gate contact and
said barrier layer.
7. The HEMT of claim 8, wherein said insulating layer comprises a
layer of silicon nitride and a layer of aluminum nitride.
8. The HEMT of claim 6, further comprising a dielectric layer
covering the exposed surface of said barrier layer between said
contacts and the exposed surface of said insulating layer between
the lower edge of said gate contact and said barrier layer.
9. The HEMT of claim 1, wherein said insulating layer covers the
surface of said barrier layer between said source and drain
contacts.
10. A high electron mobility transistor (HEMT), comprising: a GaN
semiconductor layer that has high resistivity and is
non-conducting; an AlGaN semiconductor barrier layer on said GaN
layer, said AlGaN layer having a wider bandgap than said GaN layer;
a two dimensional electron gas between said AlGaN layer and said
GaN layer; source and drain contacts contacting said AlGaN layer,
the surface of said AlGaN layer uncovered between said source and
drain contacts; a gate contact in electrical contact with said
barrier layer; and a means for forming a barrier to gate leakage
current between said gate contact and said barrier layer, said
barrier also increasing the HEMT's maximum current drive.
11. The HEMT of claim 10, wherein said means for forming a barrier
comprises an insulating layer on said barrier layer with said gate
contact on said insulating layer, said insulating layer forming a
barrier to the gate leakage current.
12. The HEMT of claim 11, wherein said insulating layer comprises
silicon nitride (SiN), aluminum nitride (AlN), silicon dioxide
(SiO.sub.2) or multiple layers thereof
13. The HEMT of claim 11, further comprising a dielectric layer on
the surfaces of said insulating layer and barrier layer between
said contacts.
14. A method for manufacturing a HEMT with a barrier to gate
leakage, comprising: placing a substrate in an MOCVD reactor;
flowing source gasses into said reactor chamber for forming a high
resistivity GaN layer on said substrate; flowing source gasses into
said reactor chamber for forming an AlGaN barrier layer on said GaN
layer, said AlGaN layer having a wider bandgap than said GaN layer;
flowing source gasses into said reactor chamber for forming an
insulating layer on said AlGaN layer; cooling said reactor chamber;
and removing said substrate with its deposited layers from said
reactor chamber.
15. The method of claim 14, further comprising etching said
insulating layer and barrier layer for source and drain
contacts.
16. The method of claim 15, further comprising depositing source
and drain contacts in respective etched areas.
17. The method of claim 14, further comprising depositing a gate
contact on said insulating layer.
18. The method of claim 14, wherein said insulating layer comprises
silicon nitride (SiN), aluminum nitride (AlN), silicon dioxide
(SiO.sub.2) or multiple layers thereof.
19. The method of claim 14, wherein said insulating layer comprises
silicon nitride.
20. The method of claim 14, wherein said insulating layer comprises
a layer of silicon nitride and a layer of aluminum nitride, said
aluminum nitride layer sandwiched between said barrier layer and
said silicon nitride layer.
21. A method for manufacturing a HEMT with a barrier to gate
leakage, comprising: fabricating the active layers of said HEMT on
a substrate; placing said substrate in a sputtering chamber;
sputtering an insulating layer on said substrate in said sputtering
chamber; and removing said substrate from said sputtering
chamber.
22. The method of claim 21, wherein said insulating layer comprises
silicon nitride (SiN), aluminum nitride (AlN), silicon dioxide
(SiO.sub.2) or multiple layers thereof.
23. The method of claim 21, wherein said insulating layer comprises
silicon nitride.
24. The method of claim 21, wherein said insulating layer comprises
a layer of silicon nitride and a layer of aluminum nitride, said
aluminum nitride layer sandwiched between said barrier layer and
said silicon nitride layer.
25. The method of claim 21, further comprising forming source and
drain contacts in contact with said active layers.
26. The method of claim 27, further comprising forming a gate
contact on said insulating layer.
27. The method of claim 26, further comprising forming a dielectric
layer on the surface of said barrier layer and insulating layer
between said contacts.
28. The method of claim 21, wherein said active layers are
fabricated using metal-organic chemical vapor deposition
(MOCVD).
29. The method of claim 21, wherein said insulating layer is
silicon nitride and said layer is deposited on said HEMT active
layers by pumping down said sputtering chamber to a predetermined
pressure, bombarding a silicon source with a source gas to clean
its surface, changing the chamber conditions to sputter the
silicon, and allowing the sputtered silicon to react with nitrogen
to deposit a silicon nitride layer.
30. The method of claim 21, wherein said active layers include a
high resistivity GaN layer and an AlGaN barrier layer, said GaN
layer sandwiched between said substrate and said AlGaN layer.
31. The method of claim 30, wherein said AlGaN layer has a wider
bandgap than said GaN layer.
32. A transistor, comprising: a high resistivity semiconductor
layer; a barrier semiconductor layer on said high resistivity
layer; source and drain contacts contacting said barrier layer,
with part of the surface of said barrier layer uncovered between
said source and drain contacts; an insulating layer on said
uncovered surface of said barrier layer; and a gate contact on said
insulating layer, said insulating layer forming a barrier to gate
leakage current.
33. The transistor of claim 32, wherein said insulating layer
increases the maximum current drive of said transistor.
34. The transistor of claim 32, wherein said barrier layer has a
thickness that allows said transistor to produce efficient gain at
microwave frequencies.
35. The transistor of claim 32, wherein said insulating layer
comprises a layer of silicon nitride and a layer of aluminum
nitride, said aluminum nitride layer sandwiched between said
barrier layer and said silicon nitride layer.
36. The transistor of claim 32, further comprising a dielectric
layer covering the surface of said barrier layer between said
contacts that is not covered by said insulating layer.
37. A transistor comprising: a high resistivity semiconductor
layer; a Group III-nitride semiconductor layer on said high
resistivity layer, said Group III-nitride semiconductor layer
having a top surface opposite said high resistivity semiconductor
layer; source and drain contacts on said top surface; an insulating
layer on said top surface and between said source and drain
contacts; and a gate contact on said insulating layer, said
insulating layer forming a barrier to gate leakage.
38. The transistor of claim 37, wherein said insulating layer
increases the maximum current drive of said transistor.
39. The transistor of claim 37, wherein said Group-III nitride
layer has a thickness that allows said transistor to produce
efficient gain at microwave frequencies.
40. The transistor of claim 37, wherein said high resistivity
semiconductor layer is made of a Group III nitride semiconductor
material.
41. The transistor of claim 37, wherein said insulating layer
comprises silicon nitride (SiN), aluminum nitride (AlN), silicon
dioxide (SiO.sub.2) or multiple layers thereof.
42. The transistor of claim 37, wherein said insulating layer
comprises a layer of silicon nitride and a layer of aluminum
nitride, said aluminum nitride layer sandwiched between said Group
III-nitride semiconductor layer and said silicon nitride layer.
43. The transistor of claim 37, further comprising a dielectric
layer covering said top surface between said contacts that is not
covered by said insulating layer.
44. The transistor of claim 37, further comprising a dielectric
layer on the surface of said insulating layer between said
contacts.
45. The transistor of claim 37, comprising a field effect
transistor (FET).
Description
[0001] This application is a divisional of and claims the benefit
of U.S. patent application Ser. No. 10/201,345 filed on Jul. 23,
2002, which claims the benefit of provisional application Ser. No.
60/307,546 filed on Jul. 24, 2001.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to aluminum gallium nitride and
gallium nitride based high electron mobility transistors.
[0004] 2. Description of the Related Art
[0005] Microwave systems commonly use solid state transistors as
amplifiers and oscillators which has resulted in significantly
reduced system size and increased reliability. To accommodate the
expanding number of microwave systems, there is an interest in
increasing their operating frequency and power. Higher frequency
signals can carry more information (bandwidth), allow for smaller
antennas with very high gain, and provide radar with improved
resolution.
[0006] Field effect transistors (FETs) and high electron mobility
transistors (HEMTs) are common types of solid state transistors
that are fabricated from semiconductor materials such as Silicon
(Si) or Gallium Arsenide (GaAs). One disadvantage of Si is that it
has low electron mobility (approximately 1450 cm.sup.2/V-s), which
produces a high source resistance. This resistance seriously
degrades the high performance gain otherwise possible from Si based
HEMTs. [CRC Press, The Electrical Engineering Handbook, Second
Edition, Dorf, p. 994, (1997)]
[0007] GaAs is also a common material for use in HEMTs and has
become the standard for signal amplification in civil and military
radar, handset cellular, and satellite communications. GaAs has a
higher electron mobility (approximately 6000 cm.sup.2/V-s) and a
lower source resistance than Si, which allows GaAs based devices to
function at higher frequencies. However, GaAs has a relatively
small bandgap (1.42 eV at room temperature) and relatively small
breakdown voltage, which prevents GaAs based HEMTs from providing
high power at high frequencies.
[0008] Improvements in the manufacturing of gallium nitride (GaN)
and aluminum gallium nitride (AlGaN) semiconductor materials have
focused interest on the development of AlGaN/GaN based HEMTs. These
devices can generate large amounts of power because of their unique
combination of material characteristics including high breakdown
fields, wide bandgaps (3.36 eV for GaN at room temperature), large
conduction band offset, and high saturated electron drift velocity.
The same size AlGaN/GaN amplifier can produce up to ten times the
power of a GaAs amplifier operating at the same frequency.
[0009] U.S. Pat. No. 5,192,987 to Khan et al. discloses AlGaN/GaN
based HEMTs grown on a buffer and a substrate, and a method for
producing them. Other HEMTs have been described by Gaska et al.,
"High-Temperature Performance of AlGaN/GaN HFET's on SiC
Substrates," IEEE Electron Device Letters, Vol. 18 No 10, October
1997, Page 492; and Wu et al. "High Al-content AlGaN/GaN HEMTs With
Very High Performance", IEDM-1999 Digest pp. 925-927, Washington
DC, December 1999. Some of these devices have shown a
gain-bandwidth product (f.sub.T) as high as 100 gigahertz (Lu et
al. "AlGaN/GaN HEMTs on SiC With Over 100 GHz f.sub.t and Low
Microwave Noise", IEEE Transactions on Electron Devices, Vol. 48,
No. 3, March 2001, pp. 581-585) and high power densities up to 10
W/mm at X-band (Wu et al., "Bias-dependent Performance of
High-Power AlGaN/GaN HEMTs", IEDM-2001, Washington D.C., Dec. 2-6,
2001)
[0010] Despite these advances, AlGaN/GaN based FETs and HEMTs have
been unable to produce significant amounts of total microwave power
with high efficiency and high gain. They produce significant power
gain with DC gate drives, but with frequency step-ups as low as a
millihertz to a few kilohertz, their amplification drops off
significantly.
[0011] It is believed that the difference between AC and DC
amplification is primarily caused by surface traps in the device's
channel. Although the nomenclature varies somewhat, it is common to
refer to an impurity or defect center as a trapping center (or
simply trap) if, after capture of one type of carrier, the most
probable next event is re-excitation.
[0012] At equilibrium, the traps donate electrons to the
2-dimensional electron gas (2-DEG) in HEMTs. Trapping levels
located deep in a band gap are also slower in releasing trapped
carriers than other levels located near the conduction of valence
bands. This is due to the increased energy that is required to
re-excite a trapped electron from a center near the middle of the
band gap to the conduction band, compared to the energy required to
re-excite the electron from a level closer to the conduction
band.
[0013] Al.sub.xGa.sub.1-xN (X=0.about.1) has a surface trap density
comparable to the channel charge of the transistor with the traps
in deep donor states with activation energy ranging from 0.7 to 1.8
eV (depending on X). During HEMT operation, the traps capture
channel electrons. The slow trapping and de-trapping process
degrades transistor speed, which largely degrades the power
performance at microwave frequencies.
[0014] It is believed that the trap density of a AlGaN/GaN based
HEMTs is dependent upon the surface and volume of the AlGaN barrier
layer. Reducing the thickness of the AlGaN layer reduces the total
trapping volume, thereby reducing the trapping effect during high
frequency operation. However, reducing the thickness of the AlGaN
layer can have the undesirable effect of increasing the gate
leakage. During normal operation a bias is applied across the
source and drain contacts and current flows between the contacts,
primarily through the 2DEG. However, in HEMTs having thinner AlGaN
layers, current can instead leak into the gate creating an
undesirable current flow from the source to the gate. Also, the
thinner AlGaN layer can result in a reduction in the HEMT's
available maximum drive current.
SUMMARY OF THE INVENTION
[0015] The present invention seeks to provide an improved AlGaN/GaN
HEMT that addresses the above problems by having a thin AlGaN layer
to reduce trapping and also having additional layers to reduce gate
leakage and increase the maximum drive current. The invention also
discloses methods for manufacturing HEMTs with these
characteristics.
[0016] One HEMT according to the present invention comprises a high
resistivity semiconductor layer with a barrier semiconductor layer
on it. The barrier layer has a wider bandgap than the high
resistivity layer and a two dimensional electron gas forms between
the barrier and high resistivity layers. Source and drain contacts
are included that contact the barrier layer, with part of the
surface of the barrier layer uncovered by the contacts. An
insulating layer is included on the uncovered surface of the
barrier layer. A gate contact is deposited on the insulating layer
with the insulating layer forming a barrier to gate leakage current
and also increasing the HEMT's maximum current drive.
[0017] The invention also includes methods for fabricating HEMTs
according to the present invention. In one method, the active
layers of the HEMT are formed on a substrate in a metal-organic
chemical vapor deposition reactor. Source gasses are then fed into
the reactor for "in-situ" formation of an insulating layer on the
active HEMT's active layer. The HEMT can then be removed from the
reactor for further processing.
[0018] Another method for fabricating HEMTs according to the
present invention includes forming the active layers of a HEMT on a
substrate. The substrate is then placed in a sputtering chamber
where the insulating layer is sputtered onto the top surface of the
HEMT active layers. The HEMT can then be removed from the
sputtering chamber for further processing.
[0019] These and other further features and advantages of the
invention would be apparent to those skilled in the art from the
following detailed description, taking together with the
accompanying drawings, in which:
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a sectional view of a AlGaN/GaN HEMT according to
the present invention having an insulating layer on the AlGaN layer
and a gate contact on the insulating layer;
[0021] FIG. 2 is a sectional view of the HEMT in FIG. 1 with a
dielectric layer on its surface;
[0022] FIG. 3 is a sectional view of a AlGaN/GaN HEMT according to
the present invention with the insulating layer only under the gate
contact;
[0023] FIG. 4 is a sectional view of a AlGaN/GaN HEMT according to
the present invention having double insulating layers on the AlGaN
layer and a gate contact on the insulating layers;
[0024] FIG. 5 is a sectional view of the HEMT in claim 4 with a
dielectric layer on its surface;
[0025] FIG. 6 is a sectional view of a AlGaN/GaN HEMT according to
the present invention with the double insulating only under the
gate contact;
[0026] FIG. 7 is a simplified diagram of a metal-organic chemical
vapor deposition (MOCVD) reactor used in a method according to the
present invention for fabricating a HEMT; and
[0027] FIG. 8 is a simplified diagram of a sputtering chamber used
in a method according to the present invention for fabricating a
HEMT.
DETAILED DESCRIPTION OF THE INVENTION
[0028] FIG. 1 shows an AlGaN/GaN based HEMT 10 constructed in
accordance with this invention. It comprises a substrate 11 that
can be either sapphire (Al.sub.2O.sub.3) or silicon carbide (SiC),
with the preferred substrate being a 4H polytype of silicon
carbide. Other silicon carbide polytypes can also be used including
3C, 6H and 15R polytypes. An Al.sub.xGa.sub.1-xN buffer layer 12
(where x in between 0 and 1) is included on the substrate 11 and
provides an appropriate crystal structure transition between the
silicon carbide substrate and the remainder of the HEMT 10. Many
different materials can be used for the buffer layer 12 with a
suitable material for a buffer layer on SiC being
Al.sub.xGa.sub.1-xN, with x=1.
[0029] Silicon carbide has a much closer crystal lattice match to
Group III nitrides than sapphire and results in Group III nitride
films of higher quality. Silicon carbide also has a very high
thermal conductivity so that the total output power of Group III
nitride devices on silicon carbide is not limited by the thermal
dissipation of the substrate (as is the case with some devices
formed on sapphire). Also, the availability of semi insulating
silicon carbide substrates provides the capacity for device
isolation and reduced parasitic capacitance that make commercial
devices possible. SiC substrates are available from Cree Research,
Inc., of Durham, N.C. and methods for producing them are set forth
in the scientific literature as well as in a U.S. Pat. Nos. Re.
34,861; 4,946,547; and 5,200,022.
[0030] The HEMT 10 includes a high resistivity layer 20 on the
buffer layer 12 and a barrier layer 18 on said high resistivity
layer 20 such that the high resistivity layer 20 is sandwiched
between the barrier layer 18 and the buffer layer 12. The barrier
layer 18 is typically about 0.1 to 0.3 micrometers thick and the
barrier layer 18, high resistivity layer 20, and buffer layer 12,
are preferably formed on the substrate 11 by epitaxial growth or
ion implantation.
[0031] The HEMT also includes source and drain contacts 13, 14 that
are on the surface of the high resistivity layer 20. The barrier
layer 18 is disposed between the contacts 13 and 14, with each
contacting the edge of the barrier layer. An insulating layer 24 is
included on the barrier layer 18 between the contacts 13 and 14. In
the embodiment shown, the insulating layer 24 covers the entire
barrier layer 18, but in other embodiments (one described below)
all of the barrier layer 18 is not covered. The layer 24 can be
made of many different materials including but not limited to
silicon nitride (SiN), aluminum nitride (AlN), silicon dioxide
(SiO.sub.2) or a combination incorporating multiple layers
thereof.
[0032] The contacts 13 and 14 are usually separated by a distance
in the range 1.5 to 10 micrometers for microwave devices. A
rectifying Schottky contact (gate) 16 is located on the surface of
the insulator layer 24 between the source and drain contacts 13 and
14, and it typically has a length in the range of 0.1 to 2
micrometers. The total width of the HEMT depends on the total power
required. It can be wider than 30 millimeters, with the typical
width being in the range of 100 microns to 6 millimeters.
[0033] The Al.sub.xGa.sub.1-xN layer 18 has a wider bandgap than
the GaN layer 20 and this discontinuity in energy band gaps results
in a free charge transfer from the wider band gap to the lower band
gap material. A charge accumulates at the interface between the two
and creates a two dimensional electron gas (2DEG) 22 that allows
current to flow-between the source and drain contacts 13 and 14.
The 2DEG has very high electron mobility which gives the HEMT a
very high transconductance at high frequencies. The voltage applied
to the gate 16 electrostatically controls the number of electrons
in the 2DEG directly under the gate, and thus controls the total
electron flow.
[0034] The source and drain contact 13 and 14, are preferably
formed of alloys of titanium, aluminum, nickel and gold, and the
gate 16 is preferably formed of titanium, platinum, chromium,
nickel, alloys of titanium and tungsten, and platinum silicide. In
one embodiment, the contacts comprise an alloy of nickel, silicon,
and titanium that is formed by depositing respective layers of
these materials, and then annealing them. Because this alloy system
eliminates aluminum, it avoids unwanted aluminum contamination over
the device surface when the anneal temperature exceeds the melting
point of aluminum (660 degrees C.).
[0035] During operation, the drain contact 14 is biased at a
specified potential (positive drain potential for an n-channel
device) and the source is grounded. This causes current to flow
through the channel and 2DEG, from the drain to the source contacts
13, 14. The flow of current is controlled by the bias and frequency
potentials applied to the gate 16, which modulate the channel
current and provide gain.
[0036] As described above, the trap density of the AlGaN layer 18
is dependent on the layer's volume and by reducing the thickness of
the layer 18 the trapping density can also be reduced to decrease
the trapping effect. However, reducing the thickness of the AlGaN
layer increases gate leakage and reduces the devices maximum
current drive.
[0037] By having the insulating layer between the gate 16 and the
barrier layer 18, gate leakage of the HEMT is reduced. This has the
direct impact of improving the long-term reliability of the device,
since gate leakage is one of the sources of HEMT degradation. The
turn-on voltage of the HEMT 10 is dependent upon the type of
material used for the insulator layer 24 and the turn-on voltage
can be as high as 3-4 volts. The HEMT 10 can then be operated in
the accumulation mode with higher current level and higher input
drive level. The insulator layer also serves as a natural passivant
for the HEMT, which improves its reliability.
[0038] FIG. 2 shows an AlGaN based HEMT 30 similar to the HEMT 10
in FIG. 1. The HEMT 30 has similar layers including a substrate 11,
buffer layer 12, GaN layer 20, 2DEG 22, Al.sub.xGa.sub.1-xN barrier
layer 18 and insulating layer 24. The HEMT 30 also has source, gate
and drain contacts 13, 14, 16, similar to those on the HEMT 10. The
HEMT 30 includes an additional dielectic layer 32 disposed on the
surface of the insulating layer 24 between the source, gate and
drain contacts 13, 16, 14. The dielectric layer protects the HEMT
from undesirable passivation, impurities and damage that can occur
during handling. The dielectric layer can be made of many different
materials or combinations of materials, with a suitable material
being Si.sub.xN.sub.y.
[0039] The insulating layer 24 serves to reduce gate leakage and
allow increased current drive by the section of the layer 24 that
is sandwiched between the gate 16 and the barrier layer 18. The
sections of the layer 24 that extend beyond the gate 16 help in
protecting the surface of the barrier layer between the contacts,
but do not help in reducing gate leakage or increasing current
drive.
[0040] FIG. 3 shows another embodiment of a HEMT 40 according to
the present invention similar to the HEMTs 10 and 30 in FIGS. 1 and
2. The HEMT 40 has similar layers including a substrate 11, buffer
layer 12, GaN layer 20, 2DEG 22 and Al.sub.xGa.sub.1-xN barrier
layer 18. The HEMT 30 also has source, gate and drain contacts 13,
14 and 16, similar to those on the HEMTs 10 and 40. However, the
insulating layer 42 in HEMT 40 is only included below the gate
contact 16, such that the insulating layer is only sandwiched
between the gate contact 16 and the barrier layer 18. The surface
of the barrier layer 18 between the contacts 13, 14, 16, is
uncovered by the insulating layer 42. It can remain uncovered or
can include a layer of dielectic material 44 to help reduce the
effects of trapping and to help reduce any undesirable passivation
and damage to the HEMT's layers. It also helps to reduce the
introduction of impurities into the HEMT's layers.
[0041] The dielectric layer is preferably silicon nitride
(Si.sub.xN.sub.y) with silicon being the source of the donor
electrons to reduce trapping. To be most effective the layer 22 and
44 should meet the following conditions. First, it should have a
dopant that provides a high source of donor electrons. For silicon
nitride, the layer should have a high percentage of Si. Although
the applicant does not wish to be bound by any theory of operation,
it is presently believed that electrons from the layer fill surface
traps such that they become neutral and do not capture barrier
layer electrons during operation.
[0042] Second, the energy level of the dopant should be higher than
the energy level in the trap and for optimal results, the energy
should be higher than the energy level of the barrier layer's
conduction band edge. It is believed that this reduces the
possibility of an electron from the gate metal giving to the donor
states and prevents the trapping and de-trapping at that energy
level. The layer will also work if the dopant's energy level is
slightly below the energy level in the barrier layer's conduction
band, but the higher its energy the better.
[0043] Third, there should be little or no damage to the device's
surface and the forming of the dielectric layer should not increase
the surface damage. It is believed that surface damage can create
more surface traps. Fourth, the bond between the coating and the
surface of the conducting channel should be stable under stress. If
the bond is unstable, it is believed that the layer may fail under
actual device operation when subjected to the stress created by
increases in the electron field, voltage or temperature.
[0044] Low breakdown voltage can be experienced in HEMTs that have
an insulating layer that is deposited in-situ using metal-organic
chemical vapor deposition (MOCVD). Although applicants do not wish
to be bound by any one theory, it is believed that this low
breakdown voltage is attributable to the doping/degradation of the
AlGaN barrier layer during growth of the SiN layer. The growth
conditions such as the growth temperature of the SiN layer also
affected the mobility of the HEMT's sheet charge. Lowering the
growth temperature of the insulating layer resulted in less
degradation of the HEMT, but also resulted in a reduced growth rate
of the SiN.
[0045] To allow for the growth of an insulating layer at a normal
growth rate without doping or degrading the AlGaN barrier layer, a
double insulating layer arrangement can be used instead of the
single insulating layer. FIG. 4 shows a HEMT 50 that is similar to
the HEMTS 10, 30 and 40 in FIGS. 1, 2 and 3. The HEMT 50 has a
similar substrate 11, buffer layer 12, GaN layer 20, 2DEG 22, and
Al.sub.xGa.sub.1-xN barrier layer 18. The HEMT 30 also has similar
source, gate and drain contacts 13, 14, 16. However, the HEMT 50
has a double layer arrangement that is used instead of a single
layer. The double layers include an AlN spacer layer 52 on the
barrier layer 18 between the source and drain contacts 13, 14. A
SiN insulating layer 54 is included on the AlN layer 52 with the
gate contact 16 arranged on the insulating layer 54.
[0046] The AlN spacer layer 52 serves as a spacer or barrier
between the SiN insulating layer 54 and the active AlGaN barrier
layer 18. This spacer layer 52 prevents the doping/degradation of
the barrier layer 18 during growth of the SiN insulating layer 54
during normal growth conditions.
[0047] Other materials can be used for the spacer layer as long as
the material prevents the doping and degradation of the AlGaN
barrier layer 18 during deposition of the SiN insulating layer 54
at normal growth rates. Methods that allow for depositing the SiN
insulating layer directly on the AlGaN layer without a spacer layer
can also be used if doping and degradation can be avoided. The
important aspect of these features of the invention is that the
HEMTs low breakdown voltage is avoided.
[0048] FIG. 5 shows another HEMT 60 according to the present
invention that is similar to the HEMT 50 of FIG. 4 having a similar
substrate 11, buffer layer 12, GaN layer 20, 2DEG 22,
Al.sub.xGa.sub.1-xN barrier layer 18, AlN spacer layer 52 and SiN
insulating layer 54. The HEMT 60 also has similar source, gate and
drain contacts 13, 14 and 16. The HEMT 60 also includes a
dielectric layer 62 over the exposed surface of the SiN insulating
layer 54 between the contacts 13, 14, 16, similar to the dielectric
layer 32 of the HEMT 30 in FIG. 2. Just as layer 32 in HEMT 30, the
dielectric layer 54 helps protect the HEMT 60 from undesirable
passivation, impurities and damage that can occur during handling.
The dielectric layer can be made of many different materials or
combinations of materials, with a suitable material being
Si.sub.xN.sub.y.
[0049] FIG. 6 shows another HEMT 70 according to the present
invention that, similar to the HEMT 40 in FIG. 3, which has an
insulating layer only below the gate contact. The HEMT 70 has a
similar substrate 11, buffer layer 12, GaN layer 20, 2DEG 22,
Al.sub.xGa.sub.1-xN barrier layer 18 and source, gate and drain
contacts 13, 14 and 16. The HEMT's SiN insulating layer 72 and AlN
spacer layer 74 are only included below the gate 16, such that both
are sandwiched between the gate 16 and the barrier layer 18. In
another embodiment (not shown) the spacer layer 74 can extend
beyond the gate to cover the surface of the barrier layer between
the contacts 13, 14 and 16.
[0050] The HEMT 70 also includes a dielectric layer 76 that as
shown covers the surface of the barrier layer 18 between the
contacts 13, 14 and 16. As with the dielectric layer 44 in the HEMT
40 of FIG. 3, the dielectic layer 76 helps reduce the effects of
trapping and helps reduce the undesirable passivation and damage to
the HEMT's layers. It also helps to reduce the introduction of
impurities into the HEMT's layers. The dielectric layer 76 is
preferably silicon nitride (S.sub.xN.sub.y), with silicon being the
source of the donor electrons to fill any traps. To be most
effective the layer 76 should meet the four conditions described
above for dielectric layer 44 of FIG. 3.
[0051] The active layers of the HEMTs described above are made from
AlGaN/GaN, but they can also be made of other Group III nitride
materials. Group III nitrides refer to those semiconductor
compounds formed between nitrogen and the elements in Group III of
the periodic table, usually aluminum (Al), gallium (Ga), and indium
(In). The term also refers to ternary and tertiary compounds such
as AlGaN and AlInGaN.
Methods of Manufacturing
[0052] The present invention also discloses methods for fabricating
the HEMTs above with single or double insulating layer. The
insulating layers can be deposited on the AlGaN/GaN semiconductor
material using MOCVD, plasma chemical vapor deposition (CVD),
hot-filament CVD or sputtering.
[0053] FIG. 7 shows a MOCVD reactor 80 used in the new method to
grow the AlGaN/GaN active layers on a substrate and to deposit the
insulating layers. The reactor 80 comprises a reaction chamber 82
having growth platform 84 supported by a rotary shaft 86. In most
applications a substrate 88 such as either sapphire
(Al.sub.2O.sub.3) or silicon carbide (SiC) sapphire is disposed on
the growth platform 84, although other substrates can also be
used.
[0054] During growth, the platform 84 is heated by heater elements
90 to maintain substrate 88 at a predetermined temperature. The
temperature is typically between 400 and 1200 degrees centigrade
(.degree. C.), but can be higher or lower depending on the type of
growth desired. The heater elements 90 can be a variety of heating
devices but is usually a radio frequency (RF) or resistance
coil.
[0055] A carrier gas 92 is supplied to a gas line 94, the carrier
gas being hydrogen or nitrogen. The carrier gas 92 is also supplied
through mass flow controllers 95a, 95b, 95c, to respective bubblers
96a, 96b, 96c. Bubbler 96a has a growth compound, typically an
alkylated compound having a methyl or ethyl group, e.g. trimethyl
gallium TMG), trimethyl aluminum (TMA) or trimethyl indium (TMI).
Bubblers 96b and 96c may also contain a similar metalorganic
compound to be able to grow an alloy of a Group III compound. The
bubblers 96a, 96b, 96c are typically maintained at a predetermined
temperature by constant temperature baths 98a, 98b, 98c to ensure a
constant vapor pressure of the metal organic compound before it is
carried to the reaction chamber 82 by the carrier gas 92.
[0056] The carrier gas 92 which passes through bubblers 96a, 96c,
96c is mixed with the carrier gas 92 flowing within the gas line 94
by opening the desired combination of valves 100a, 110b, 100c. The
mixed gas is then introduced into the reaction chamber 82 through a
gas inlet port 102 formed at the upper end of the reaction chamber
82.
[0057] A nitrogen containing gas 104 such as ammonia is supplied to
the gas line 94 through a mass flow controller 106. The flow of
nitrogen containing gas is controlled by valve 108. If the carrier
gas 92 is mixed with the nitrogen containing gas 104, and the TMG
vapor within the gas line 94 is introduced into the reaction
chamber 82, the elements are present to grow gallium nitride on the
substrate 88 through thermal decomposition of the molecules in the
TMG and ammonia containing gas.
[0058] To dope alloys of gallium nitride on the substrate 88, one
of the bubblers 96a, 96b, 96c not being used for the TMG is used
for a dopant material, which is usually Magnesium (Mg) or Silicon
(Si), but can be other material such as beryllium, calcium, zinc,
or carbon. Bubbler 96b or 96c is used for an alloy material such as
boron, aluminum, indium, phosphorous, arsenic or other materials.
Once the dopant and alloy are selected and the appropriate valve
100a, 100b, 100c is opened to allow the dopant to flow into gas
line 94 with the gallium and nitrogen containing gas 104, the
growth of the doped layer of gallium nitride takes place on
substrate 88.
[0059] The gas within the reaction chamber 82 can be purged through
a gas purge line 110 connected to a pump 112 operable under
hydraulic pressure. Further, a purge valve 114 allows gas pressure
to build up or be bled off from the reaction chamber 82.
[0060] The growth process is typically stopped by shutting off the
gallium and dopant sources by closing valves 100a and 100b, and
keeping the nitrogen containing gas and the carrier gas flowing.
Alternatively, the reaction chamber 82 can be purged with a gas 116
that can be controlled through a mass flow controller 118 and valve
120. The purge is aided by opening valve 114 to allow the pump 112
to evacuate the reaction chamber 82 of excess growth gasses.
Typically, the purge gas 116 is hydrogen, but can be other gasses.
Turning off power to the heater elements 90 cools the substrate
88.
[0061] In one method according to the present invention, the
application of the insulating layer/layers occurs after growth of
the AlGaN/GaN semiconductor material and prior to or during cooling
of the reaction chamber 82 (referred to as in-situ). Following
growth of the semiconductor material in a reactor chamber 82, the
flow of undesired growth gasses is discontinued by closing the
appropriate combination of valves 100a, 100b, 100c. A short purge
of the reactor may be completed to remove the undesirable gasses as
described above. Gasses are then flowed into the reactor to deposit
the insulating layer(s) and in a preferred method, the gasses used
for the insulating layer(s) are provided from typical MOCVD
sources. When depositing a Si.sub.3N.sub.4 insulating layer on the
AlGaN/GaN semiconductor material, disilane (Si.sub.2H.sub.6) and
ammonia (NH.sub.6) are introduced into the reactor chamber 82,
through gas line 94. The molecules are now present to deposit the
Si.sub.3N.sub.4 through thermal decomposition on the AlGaN/GaN
material. When depositing double insulating layers, the appropriate
gasses are introduced into the chamber to form the AlN layer prior
to forming the Si.sub.3N.sub.4 layer.
[0062] In those embodiments of the HEMT having a dielectric layer,
the dielectric layer can also be deposited in-situ. Examples of
some of the compounds that can be used in the dielectric layer
include Si, Ge, MgO.sub.x, MgN.sub.x, ZnO, SiN.sub.x, SiO.sub.x,
ScO.sub.x, GdO.sub.x and alloys thereof. Multiple layers and
repeated stacks of layers of suitable materials can be used as
barrier layers as well, such as SiN.sub.x/Si, MgN.sub.x/SiN.sub.x
or MgN.sub.x/MgO.sub.x. The different barrier layers can be formed
from the following source gasses: Si from silane or disilane, Ge
from germane, MgN.sub.x from cyclopentadienyl magnesium or
methyl-cyclopentadienyl magnesium and ammonia, MgO from
cyclopentadienyl magnesium or methyl-cyclopentadienyl magnesium and
nitrous oxide, ZnO from dimethyl zinc or diethyl zinc and nitrous
oxide or water, SiN.sub.x from silane or disilane and ammonia or
nitrous oxide, and SiO.sub.x formed from silane or disilane and
nitrous oxide.
[0063] After the insulating and dielectric layers are deposited the
semiconductor material can be cooled in the reaction chamber 82.
The semiconductor material can then be removed from the cooled
reaction chamber 82. When the structure is ready for additional
processing such as metalization, the portion of the layers can be
removed by a number of different methods including but not limited
to wet chemical hydrofluoric acid (HF) etching, reactive ion
etching, or plasma etching.
[0064] Another method for depositing the insulating layers
according to the present invention is through sputtering. FIG. 8
shows a simplified sputtering chamber 130 that can be used to
deposit material on a substrate. In operation, a semiconductor
device 132 is placed on an anode 134. The chamber 136 is then
evacuated and an inert gas 138 such as argon is fed into gas line
140 and bled through the valve 142 to maintain a background
pressure. A cathode 144 made of the material to be deposited on the
substrate/device, is positioned within the chamber 136. With the
application of a high voltage 146 between the electrodes, the inert
gas is ionized and the positive ions 148 excel to the cathode 144.
On striking the cathode 144, they collide with the cathode atoms
150, giving them sufficient energy to be ejected. The sputtered
cathode atoms 150 travel through space, eventually covering the
anode 134 and the semiconductor device 132 with a coating 133 from
the sputtered atoms 150.
[0065] Other sputtering units can be more complex and detailed, but
they work on much the same basic physical mechanisms. Using the
more complex sputtering systems, it is possible to sputter and
deposit a range of metals and dielectric layers.
[0066] The sputtering method can be used to deposit the insulating
layers on an AlGaN/GaN HEMT. The HEMT is first formed on a
semiconductor wafer by a process such as MOCVD. The wafer is then
cleaned (rinsing with NH.sub.4OH:H.sub.2O (1:4) for approximately
10 to 60 seconds) and the device 132 is then loaded into a
sputtering chamber 136 having a silicon source at the cathode 144.
The Si.sub.xN.sub.y insulating layer is deposited on the wafer by
sputtering. The sputtering process includes the specific steps of
pumping down the chamber to a low pressure of about
3.times.10.sup.-7 Torr. Using a source gas having a flow of 20-100
sccm and a pressure of 5-10 mTorr the plasma is then started with
RF power of 200-300 W for about 2 minutes. This bombards the
silicon at the cathode 144, cleaning its surface. The sputtering
conditions are then changed such that the argon gas flow is 10-12
sccm, the nitrogen gas flow of 8-10 sccm, the chamber pressure of
2.5-5 mTorr, and the RF power of 200-300 W. This condition is
maintained for 2 minutes to sputter the Si cathode 144. The
sputtered silicon reacts with the nitrogen and the resulting
silicon nitride deposits on the device 132.
[0067] After sputtering, the next step 130 is to turn off the
nitrogen gas and turn up the argon gas flow to 20-100 sccm for 2
minutes to clean the Si surface. All gas and power are then turned
off and the chamber is allowed to cool down for five minutes and
vent. The device 132 can then be removed from the sputtering
chamber. The layers of the device can then be etched. Windows can
then be in the device layers for the source, gate and drain
contacts, using different methods including but not limited to wet
chemical hydrofluoric acid (HF) etching, reactive ion etching, or
plasma etching.
[0068] Alternatively, the contacts and gate could be deposited on
the device before depositing the insulating layer in the sputtering
chamber 130. The dielectric layer over the contacts and gate could
then be etched to allow for the connection of leads.
[0069] Although the present invention has been described in
considerable detail with reference to certain preferred
configurations thereof, other versions are possible. The insulating
layer can be used on HEMTs from different material systems and on
semiconductor devices. The insulating layer can also be applied
using many different methods beyond those mentioned above,
including PECVD, Electron Beam Deposition, Inductively Coupled
Plasma and ICP Deposition. Therefore, the spirit and scope of the
appended claims should not be limited to the preferred versions
described in the specification.
* * * * *