U.S. patent application number 11/730584 was filed with the patent office on 2007-08-09 for apparatus for radio telecommunication system and method of building up output power.
Invention is credited to Kazuhiko Hikasa, Kazuhisa Okada, Patrick Wurm.
Application Number | 20070184797 11/730584 |
Document ID | / |
Family ID | 9937892 |
Filed Date | 2007-08-09 |
United States Patent
Application |
20070184797 |
Kind Code |
A1 |
Okada; Kazuhisa ; et
al. |
August 9, 2007 |
Apparatus for radio telecommunication system and method of building
up output power
Abstract
A polar loop based radio telecommunication apparatus which has a
phase control loop for controlling the phase of a carrier outputted
from an oscillator for transmitter, and an amplitude control loop
for controlling the amplitude of a transmission output signal
outputted from a power amplifier circuit, wherein precharge means
is provided on a forward path from a current source, through the
power amplifier circuit, to a detection circuit, forming the
amplitude control loop, for rapidly increasing a control voltage
for the power amplifier circuit to a power threshold upon starting
transmission.
Inventors: |
Okada; Kazuhisa; (Kiryu,
JP) ; Hikasa; Kazuhiko; (Hamura, JP) ; Wurm;
Patrick; (Comberton, GB) |
Correspondence
Address: |
MATTINGLY, STANGER, MALUR & BRUNDIDGE, P.C.
1800 DIAGONAL ROAD
SUITE 370
ALEXANDRIA
VA
22314
US
|
Family ID: |
9937892 |
Appl. No.: |
11/730584 |
Filed: |
April 3, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10372919 |
Feb 26, 2003 |
7209717 |
|
|
11730584 |
Apr 3, 2007 |
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Current U.S.
Class: |
455/127.1 ;
455/126 |
Current CPC
Class: |
H04L 27/361 20130101;
H03F 2200/451 20130101; H03F 2200/294 20130101; H04L 27/2017
20130101; H04L 27/2071 20130101; H03F 1/30 20130101; H03F 1/0205
20130101; H04L 27/0008 20130101; H03G 3/3047 20130101; H03F
2200/513 20130101; H03F 1/32 20130101; H03F 3/24 20130101 |
Class at
Publication: |
455/127.1 ;
455/126 |
International
Class: |
H01Q 11/12 20060101
H01Q011/12; H04B 1/04 20060101 H04B001/04 |
Foreign Application Data
Date |
Code |
Application Number |
May 31, 2002 |
GB |
0212737.1 |
Claims
1.-12. (canceled)
13. A method of building up output power in a radio
telecommunication apparatus having a phase control loop for
controlling the phase of a carrier outputted from an oscillator for
a transmitter, and an amplitude control loop for controlling the
amplitude of a transmission output signal outputted from a power
amplifier circuit, said method comprising the steps of: starting
first said phase control loop; opening said amplitude control loop
after said phase control loop is stabilized to perform a precharge
for raising the control signal of the power amplifier so that the
output power rises up to a power threshold; terminating said
precharge when said forward path reaches the power threshold; and
closing said amplitude control loop to build up the output power of
said power amplifier circuit.
14. An apparatus for controlling a power amplifier operating on a
carrier signal, the apparatus comprising a feedback path for
conveying a sample of the output of the power amplifier to
comparison means arranged to output an amplitude control signal
related to the difference in amplitude of said sampled amplifier
output and a modulation signal to be amplitude-modulated onto the
carrier signal, and a forward path for conveying the amplitude
control signal to an input of the power amplifier to control the
power amplification, wherein the forward path includes control
means which operates at start up of the power amplifier under low
power conditions to remove the amplitude control signal from the
input and apply a ramping voltage to the input to increase the
speed with which the output of the power amplifier reaches a power
threshold, at which the ramping voltage is terminated and the
amplitude control signal is re-applied to the input of the power
amplifier.
15. An apparatus as claimed in claim 14, in which the forward path
includes a loop filter comprising a capacitor, and in which the
control means comprises a current source which is connected to the
capacitor to generate said ramping voltage.
16. An apparatus as claimed in claim 14, in which the amplitude
control signal is removed from the input of the power amplifier by
tri-stating a device in the forward path.
17. An apparatus as claimed in claim 14, in which the forward path
includes a variable gain amplifier, and the control means
short-circuits the inputs of the variable gain amplifier to retain
the reference voltage from the comparison means when the amplitude
control signal is removed from the power amplifier.
18. An apparatus as claimed in claim 14, including detector means
to detect the amplitude peak signals at the inputs of the
comparison means that receive said sampled amplifier output and
modulation signal, respectively, the detector means being adapted
to produce a control signal that disconnects the predetermined
voltage signal from the power amplifier and reconnects the
amplitude control signal.
19. An apparatus as claimed in claim 18, in which the detector
means produces said control signal when the sampled amplifier
output equals or exceeds said modulation signal.
20. An apparatus as claimed in claim 14, in which the control means
includes a timer that operates to ensure that the ramping voltage
is terminated and the amplitude control signal is re-applied to the
power amplifier a predetermined maximum time after the ramping
voltage is applied to the input.
21. A mobile telecommunications terminal incorporating apparatus as
claimed in claim 14.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application relates to subject matters described
in the U.S. patent applications being file based on the United
Kingdom Patent Applications No. 0212725.6 filed on May 31, 2002,
No. 0212729.8 filed on May 21, 2002, No. 0212723.1 filed on May 21,
2002, No. 0212735.5 filed on May 31, 2002, and No. 0212732.2 filed
on May 31, 2002. All of those U.S. applications are assigned to the
same assignees of the present application.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to techniques for improving
the controllability of output power by a power control signal of a
high frequency power amplifier circuit and for building up without
fail the output power of the high frequency power amplifier circuit
upon starting, and more particularly, to techniques suitable for
application in a semiconductor integrated circuit for communication
which contains a phase detection circuit and an amplitude detection
circuit, and an apparatus for radio telecommunication system such
as a portable telephone which incorporates the semiconductor
integrated circuit for communication.
[0003] One of conventional schemes for radio telecommunication
apparatus (mobile telecommunication apparatus) such as a portable
telephone is GSM (Global System for Mobile Communication) which is
employed in Europe. This GSM scheme uses a phase modulation mode
called GMSK (Gaussian Minimum Shift Keying) which shifts the phase
of a carrier in accordance with transmission data.
[0004] Generally, a high frequency power amplifier circuit is
incorporated in a transmission output unit in a radio
telecommunication apparatus. A conventional GSM-based radio
telecommunication apparatus employs a configuration for controlling
a bias voltage of a high frequency power amplifier circuit to
provide output power required for a call by means of a control
voltage outputted from a circuit, called an APC (Automatic Power
Control) circuit, which generates a control signal for a
transmission output based on a signal from a detector for detecting
a transmission output and a level required for transmission from a
baseband LSI.
[0005] In recent portable telephones, an EDGE (Enhanced Data Rates
for GMS Evolution) scheme has been proposed. The EDGE scheme has
dual-mode communication functions, and relies on GMSK modulation to
perform audio signal communications and on 3.pi./8 rotating 8-PSK
(Phase Shift Keying) modulation to perform data communication. The
8-PSK modulation is such modulation that adds an extra amplitude
shift to a phase shift of a carrier in the GMSK modulation. Since
the 8-PSK modulation can send 3-bit information per symbol, in
contrast with the GMSK modulation which sends 1-bit information per
symbol, the EDGE scheme can achieve communications at a higher
transmission rate as compared with the GSM scheme.
[0006] As one implementation of a modulation mode for imparting
information on a phase component and an amplitude component,
respectively, of a transmission signal, there is a conventionally
known method called "polar loop" which involves separating a signal
intended for transmission into a phase component and an amplitude
component, subsequently applying feedback to the separated
components through a phase control loop and an amplitude control
loop, and combining the resulting components by an amplifier for
outputting the combined components (for example, "High Linearity RF
Amplifier Design" by Kenington, Peter B., p 162, published by
ARTECH HOUSE, INC. in 1979).
[0007] A GSM-based communication system is only required to output
a phase modulated signal in accordance with a required output
level, so that a high frequency power amplifier circuit at a final
stage can be operated in a saturation region, whereas a radio
communication system capable of EDGE-based transmission/reception
must perform an amplitude control, so that a high frequency power
amplifier circuit at a final stage must be linearly operated in a
non-saturation region. However, with a method of driving a high
frequency power amplifier circuit used in a conventional GSM-based
communication system, it is difficult to ensure the linearity which
is required by the high frequency power amplifier circuit in a
small output level region. On the other hand, the polar loop
configuration can advantageously satisfy the requirement for the
linearity of the high frequency power amplifier circuit, and
improve the power efficiency in the low output level region.
SUMMARY OF THE INVENTION
[0008] In this regard, the present inventors considered the
employment of the polar loop configuration in an EDGE-based radio
communication system. As a result, while a prescription is given
for portable telephone terminals supporting EDGE or GSM to increase
output power OUT of an output power amplifier to a power threshold
within a fixed time upon starting transmission, it was found that
the polar loop configuration suffers from a long time taken until
an amplitude control loop is stabilized upon building up the output
power, and resulting difficulties in building up the output power
within the prescribed time.
[0009] Further, an investigation on the cause of the problems
revealed that the amplitude control loop is instable due to a small
phase margin and a narrow frequency bandwidth thereof because
currently provided output power amplifiers do not ensure their
operations in a region in which an output control voltage is very
small.
[0010] More specifically, among characteristics required for an
output power amplifier, the control voltage--power characteristic
is desired to linearly increase output power POUT with respect to
an output control voltage VRAMP, as indicated by a solid line A in
FIG. 10. In addition, the output power--gain characteristic is
desired to provide a constant gain GPA of the amplifier with
respect to the output power OUT, as indicated by a solid line AA in
FIG. 11. However, an actual output power amplifier exhibits the
control voltage--power characteristic, as indicated by a broken
line B in FIG. 10, in which the output power POUT does not linearly
change within a range in which the output control voltage VRAMP is
small, and the output power--gain characteristic, as indicated by a
broken line BB in FIG. 11, in which the gain is lower than a
desired level in the range in which the output control voltage
VRAMP is small. As a result, it becomes apparent that if an attempt
is made to build up the output power of the output power amplifier
while the amplitude control loop is left closed, a long time is
taken until the amplitude control loop is stabilized, thus making
it difficult to build up the output power within a prescribed
time.
[0011] It is an object of the present invention to provide a highly
reliable apparatus for radio telecommunication system, such as a
portable telephone that has a function of performing phase
modulation and amplitude modulation, which is capable of preventing
a long delay in stabilizing an amplitude control loop due to a
reduction in closed loop frequency bandwidth caused by a change in
the open loop gain. An additional drawback is the reduction of
phase margin caused by the reduction of open loop gain that may
reduce the stability of the amplitude loop.
[0012] It is another object of the present invention to provide a
highly reliable apparatus for a radio telecommunication system,
such as a portable telephone that has a function of performing
phase modulation and amplitude modulation, which is capable of
increasing the output power of an output power amplifier to a power
threshold without fail within a prescribed time upon starting
transmission.
[0013] It is another object of the present invention to provide a
highly reliable apparatus for a radio telecommunication system
which is capable of increasing the output power of an output power
amplifier to a power threshold without fail within a prescribed
time upon starting transmission under all conditions of
operations.
[0014] The aforementioned and other objects and novel features of
the present invention will become apparent from the description of
the specification and the accompanying drawings.
[0015] A representative one of inventions disclosed in the present
application will be briefly summarized as follows.
[0016] Specifically, a polar loop based radio telecommunication
apparatus of the present invention has a phase control loop for
controlling the phase of a carrier outputted from an oscillator for
transmitter, and an amplitude control loop for controlling the
amplitude of a transmission output signal outputted from a power
amplifier circuit, wherein the apparatus includes precharge means
on a forward path from an amplitude detection circuit to the power
amplifier circuit, forming the amplitude control loop, for rapidly
increasing a control voltage for the power amplifier circuit to a
power threshold upon starting transmission. In this way, the
amplitude loop operates in an open loop way during precharge, thus
ensuring that the output power of the power amplifier circuit can
be increased to a power threshold within a prescribed time upon
starting transmission.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a block diagram illustrating the general
configuration of a polar loop based transmitter circuit according
to a first embodiment of the present invention, and an exemplary
configuration of a radio communication system using the same;
[0018] FIG. 2 is a block diagram illustrating an exemplary
configuration of a polar loop in the transmitter circuit of FIG. 1
in greater detail;
[0019] FIG. 3 is a flow chart illustrating a control procedure in
the polar loop based transmitter circuit according to the first
embodiment of the present invention upon building up output
power;
[0020] FIG. 4 is an explanatory diagram showing a relationship
between a change in output level upon building up the output power
from the polar loop based transmitter circuit according to the
first embodiment of the present invention and a time mask when a
required output level, prescribed in the GSM system standard, is
low;
[0021] FIG. 5 is an explanatory diagram showing a relationship
between a change in output level upon building up the output power
from the polar loop based transmitter circuit of the present
invention and a time mask when a required output level, prescribed
in the GSM system standard, is high;
[0022] FIG. 6 is a schematic circuit diagram illustrating an
exemplary configuration of a forward path of an amplitude control
loop in detail, showing a second embodiment of the present
invention;
[0023] FIG. 7 is a schematic circuit diagram illustrating an
exemplary configuration of a forward path of an amplitude control
loop in detail, showing a third embodiment of the present
invention;
[0024] FIG. 8 is a graph showing a level change in the forward path
of the amplitude control loop upon building up the output power in
the third embodiment;
[0025] FIG. 9 is a circuit diagram illustrating an exemplary
specific circuit configuration of a variable gain amplifier
circuit;
[0026] FIG. 10 is a characteristic diagram showing a relationship
between the output power and output control voltage of an output
power amplifier that forms part of a radio communication system
which uses the polar loop based transmitter circuit according to
another embodiment of the present invention;
[0027] FIG. 11 is a characteristic diagram showing a relationship
between the output power and power gain of the output power
amplifier that forms part of the radio communication system which
uses the polar loop based transmitter circuit according to another
embodiment of the present invention; and
[0028] FIGS. 12A and 12B are graphs showing a relationship among an
output control voltage VRAMP and the gains of an output power
amplifier and a variable gain amplifier circuit, and a relationship
between the output control voltage VRAMP and the output power of
the output power amplifier in the polar loop based transmitter
circuit according to another embodiment of the present
invention.
DESCRIPTION OF THE INVENTION
[0029] FIG. 1 illustrates the general configuration a polar loop
based radio telecommunication apparatus according one embodiment of
the present invention. In FIG. 1, the polar loop based radio
telecommunication apparatus comprises a high frequency IC 100 which
is capable of performing the GMSK modulation in a GSM system, and
the 8-PSK modulation in an EDGE system; a power module 200 which
includes a high frequency power amplifier circuit (hereinafter
called the power amplifier) 210 for driving an antenna ANT for
transmission, a coupler 220 for detecting transmission power, and
the like; a baseband circuit 300 for generating I/Q signals based
on transmission data (baseband signal), and generating a control
signal for the high frequency IC 100 and a bias voltage VBIAS for
the power amplifier 210 in the power module 200; an oscillator for
transmitter TxVCO for generating a phase modulated transmission
signal (carrier); and a loop filter LPF1 for limiting the bandwidth
of a phase loop.
[0030] The high frequency IC 100 is implemented as a semiconductor
integrated circuit on a single semiconductor chip. The chip of the
high frequency IC 100 is formed thereon with a reception-related
circuit 190 comprising a low noise amplifier (LNA); a mixer
(Rx-MIX) for directly downconverting a received signal to a
baseband signal; a high gain programmable gain amplifier (PGA); and
the like, in addition to transmission-related circuits, as
described below in detail. The high frequency IC 100, oscillator
for transmitter TxVCO, loop filter LPF, and the like may be mounted
on a single insulating substrate such as a ceramic substrate to
form a module.
[0031] The foregoing high frequency IC 100 of the embodiment, which
constitutes a polar loop, comprises a phase divider circuit 110 for
generating a signal, the phase of which is shifted by 90.degree.
from an oscillating signal .phi.IF at an intermediate frequency
generated by an oscillator IF-VCO; a quadrature modulation circuit
120 for mixing I/Q signals supplied from the baseband LSI 300 with
the signal divided by the phase divider circuit 110 for quadrature
modulation; a mixer 131 for mixing a feedback signal from the
oscillator for transmitter TxVCO with an oscillating signal .phi.RF
from a high frequency oscillator RF-VCO for downconversion to a
signal such as 80 MHz; a phase detection circuit 140 for detecting
a difference in phase between an output signal of the mixer 131 and
an output signal of the quadrature modulation circuit 120; a mixer
132 for mixing a detection signal from the coupler 220 for
detecting an output level of the power amplifier 210 with the
oscillating signal .phi.RF from a high frequency oscillator RF-VCO;
a feedback variable gain amplifier circuit MVGA for amplifying an
output of the mixer 132; an amplitude detection circuit 150 for
comparing the amplified signal with the output signal of the
quadrature modulation circuit 120 to detect an amplitude
difference; a loop filter LPF2 for generating a voltage in
accordance with an output of the amplitude detection circuit 150
and for limiting a frequency bandwidth of an amplitude loop; a
forward variable gain amplifier circuit IVGA for amplifying an
output of the loop filter LFP2; a gain control circuit 160 for
controlling the gains of the variable gain amplifier circuit MVGA
and IVGA; a register 170 for setting control information, operation
mode and the like within the chip; a sequencer 180 for outputting a
timing signal for each of the circuits within the chip based on
values set in the register 170 to operate the circuit in a
predetermined order in accordance with an operation mode; and the
like. After IVGA, there are a VIC (voltage to current controller),
a capacitor C4 and a level shifter LVS, followed by the switch
SW1.
[0032] In this embodiment, an amplitude loop is formed by the
coupler 220--mixer 132--variable gain amplifier circuit
MVGA--amplitude detection circuit 150--loop filter LPF2--variable
gain amplifier circuit IVGA--power amplifier 210. Also, a phase
loop is formed by the phase detection circuit 140--loop filter
LPF1--oscillator for transmitter TxVCO--mixer 131--phase detection
circuit 140. Specifically, if there is a phase difference between
an output signal of the quadrature modulation circuit 120 and a
feedback signal from the mixer 131, a voltage for reducing the
phase difference is supplied to a frequency control terminal of the
oscillator for transmitter TxVCO, such that the phase of the
feedback signal from the mixer 131 matches the phase of the output
signal of the quadrature modulation circuit 120. This phase loop
performs such a control that prevents the phase of the output of
the oscillator for transmitter TxVCO from shifting due to
fluctuations in power supply voltage and a change in temperature.
The oscillator for transmitter TxVCO has a constant amplitude.
[0033] Further, in this embodiment, the output of the variable gain
amplifier circuit MVGA is fed back to the phase detection circuit
140 such that a path comprised of the coupler 220--mixer
132--variable gain amplifier circuit MVGA can be used as a common
feedback path for the amplitude loop and phase loop.
[0034] In the amplitude loop, the output of the power amplifier 210
is detected by the coupler 220, the detection signal of which is
converted to an intermediate frequency bandwidth (IF) by the mixer
132, and amplified by the variable gain amplifier circuit MVGA to
generate a feedback signal SFB which is supplied to the amplitude
detection circuit 150. Then, the amplitude detection circuit 150
compares a transmission signal modulated by the quadrature
modulation circuit 120 with the feedback signal SFB to detect an
amplitude difference which is then amplified by the variable gain
amplifier circuit MVGA, and applied to an output control terminal
of the power amplifier 210 as a control voltage VAPC for performing
an amplitude control.
[0035] In this embodiment, the gains of the variable gain amplifier
circuits MVGA, IVGA are controlled by the gain control circuit 160
in a reverse direction in accordance with a control voltage VRAMP
from the baseband LSI 300 such that the sum of their gains is
substantially constant. This control is performed by the following
reason. As the open loop gain must be kept constant for maintaining
a constant frequency bandwidth for the amplitude loop, when the
amplitude loop is used to control the output power of the power
amplifier 210, a change in the gain of the variable gain amplifier
circuit MVGA on the feedback path causes a change in the gain in
the amplitude loop, resulting in a reduced bandwidth, a reduced
phase margin and a lower stability of the loop.
[0036] In this embodiment, for controlling the output power of the
power amplifier 210, when the gain of the variable gain amplifier
circuit MVGA on the feedback path is increased, the gain of the
variable gain amplifier circuit IVGA on the forward path is reduced
on the contrary, and when the gain of the variable gain amplifier
circuit MVGA on the feedback path is reduced, the gain of the
variable gain amplifier circuit IVGA on the forward path is
increased on the contrary. In this way, the open loop gain can be
kept constant, so that the frequency bandwidth for the amplitude
loop is kept constant as well.
[0037] Now, detailed description will be made on a gain control for
the variable gain amplifier circuit IVGA on the forward path and
the variable gain amplifier circuit MVGA on the feedback path.
[0038] A portable telephone terminal which supports EDGE or GSM
controls a power amplifier to increase or reduce the output power
POUT to a desired value within a fixed time. In a polar loop, this
power control is performed by controlling the gain of the variable
gain amplifier circuit MVGA. Specifically, since a reduction in the
gain of the variable gain amplifier circuit MVGA results in a
smaller feedback signal in the amplitude loop, the amplitude loop
reacts by increasing the RF gain GPA (POUT/PIN) of the power
amplifier, in order to match the feedback signal with a reference
signal SREF from the modulation circuit 120, and consequently this
reaction increases the output power POUT. For reducing the output
power POUT, the gain of the variable gain amplifier circuit MVGA
may be increased. In this embodiment, the gain of the variable gain
amplifier circuit MVGA is controlled by the control voltage VRAMP
from the baseband LSI 300. Moreover, the proportion of a reduction
or an increase in the gain GMVGA of the variable gain amplifier
circuit MVGA is always equal to the proportion of an increase or a
reduction in the RF gain GPA of the power amplifier.
[0039] For this control strategy, a change in the gain of the
variable gain amplifier circuit MVGA in response to the control
voltage VRAMP exhibits a straight line descending to the right, as
indicated by a solid line GMA in FIG. 12A, while a change in the
gain of the power amplifier 210 in response to the control voltage
VRAMP exhibits a straight line ascending to the right, as indicated
by a solid line GPA in FIG. 12A. Also, this causes the output power
POUT of the power amplifier 210 to linearly increase in response to
the control voltage VRAMP, as shown in FIG. 12B. The output power
POUT of the power amplifier 210 expressed in dBm linearly increases
with the VRAMP expressed in volts.
[0040] On the other hand, the reference signal SREF from the
modulation circuit 120, which is modulated in conformity to 8-PSK
and has a varying amplitude component, is controlled by the action
of the amplitude control loop such that an amplitude component of
the output power POUT of the power amplifier 210 matches the
reference signal SREF. In this event, the output power POUT of the
power amplifier 210 is modulated at a desired value by the
aforementioned power control. In this way, the polar loop can
modulate the output power of the power amplifier in conformity with
8-PSK. In addition, since the polar loop can simultaneously support
GMSK as well, an operated output power control function (APC
function), which has been conventionally provided by an externally
attached IC, is not required anymore.
[0041] In addition to the foregoing, this embodiment is configured
such that the power amplifier 210 can be selectively supplied, at
its output control terminal, with an output voltage of the variable
gain amplifier circuit IVGA or the control voltage VRAMP from the
baseband LSI 300 through a switch SW1. Specifically, the high
frequency power amplifier circuit 210 is controlled by a control
voltage from the amplitude loop in an 8-PSK modulation mode, while
in a GMSK modulation mode, the power amplifier 210 is directly
supplied with the control voltage VRAMP from the baseband LSI 300,
instead of the control voltage from the amplitude loop, such that
the output of the power amplifier 210 can be controlled. The
embodiment also allows the amplitude loop to control the power
amplifier when operating in GMSK mode. The switch SW1 can be
switched by setting the register 170 from the baseband LSI 300.
[0042] As described above, since the polar loop can correctly
control the phase and amplitude of the output of the power
amplifier 210 by a common action of the phase loop and amplitude
loop, this is suitable for a dual mode transmitter circuit which
supports both GMSK and EDGE modulation schemes. This is because
GMSK modulation scheme provides transmission information only in a
phase component, whereas the EDGE scheme additionally provides
information in an amplitude component for increasing the data rate.
Thus, a transmitter circuit which supports only the GMSK scheme
conventionally performs such a control that provides only a
constant amplitude at the output of the power amplifier, so that
the conventional transmitter circuit cannot support a scheme such
as EDGE which involves a varying amplitude. Since the polar loop
compares the feedback signal from the output of the power amplifier
210 with the output of the modulation circuit 120, the output of
the power amplifier 210 (precisely, average output power of the
power amplifier) can be controlled by varying the gain of the
variable gain amplifier circuit as previously described. This is
used during power ramping only.
[0043] During power ramping, the reference signal is always of
constant amplitude. The only way to increase the output power of
the power amplifier is to reduce the gain of the variable gain
amplifier MVGA to control power ramping.
[0044] During the useful part of the burst, the variable gain
amplifier gain is maintained constant, so that the output power of
the power amplifier perfectly replicates the amplitude modulation
of the reference signal. So, when the GSMK mode is used, the output
power remains constant and, when the EDGE mode is used, the output
power varies like as 8-PSK signal.
[0045] In either of the GSM and EDGE schemes, however, the standard
prescribes that the power in a rising (build-up) period, a falling
(build-down) period, and a data transmission period must always
fall within a predetermined time mask at an antenna end, but it is
relatively difficult to implement a circuit which satisfies the
standard particularly in respect to the rising period. In the
following, an embodiment which can satisfy the standard in this
respect will be described in greater detail.
[0046] FIG. 2 illustrates the configuration of the phase loop and
amplitude loop in greater detail. As illustrated in FIG. 2, an
attenuator ATT is provided between the coupler 220 and mixer 132
for attenuating the output of the coupler 220 and supplying the
attenuated output to the mixer 132, and low pass filters MLPF1,
MLPF2 are provided between the mixer 132 and variable gain
amplifier circuit MVGA and between the variable gain amplifier
circuit MVGA and amplitude detection circuit 150, respectively, for
removing unwanted harmonics. Also, in this embodiment, a switch SW0
is provided for selectively inputting the output level of the power
amplifier 210 detected by the coupler 220 and fed back through the
feedback path to the phase detection circuit 140 or amplitude
detection circuit 150.
[0047] Further, in this embodiment, provided behind the variable
gain amplifier circuit IVGA are a charge pump CGP for charging or
discharging depending on a differential output of the variable gain
amplifier circuit IVGA to generate a voltage in accordance with the
output of the variable gain amplifier circuit IVGA, and a level
shift circuit LVS for shifting the voltage generated by the charge
pump CGP by approximately 0.6 V in the negative direction.
Additionally, the LVS can be designed to produce the same gain. The
charge pump CGP is comprised of a pair of current sources IS1, IS2,
and a capacitor C4, and a switch SW11 is provided between the
current sources IS1, IS2 and the capacitor C4 for shutting down the
loop.
[0048] An output node N1 of the charge pump CGP is connected to a
precharge current source PCI for precharging this node through a
switch SW12. Further provided in this embodiment are a level
detection circuit DCT for comparing a signal from the modulation
circuit 120 with a feedback signal of the amplitude loop to detect
whether or not the feedback signal reaches a predetermined level,
and a flip-flop FF1 operated by an output signal of the level
detection circuit DCT to generate an ON/OFF control signal for the
switches SW11, SW12. The level detection circuit DCT is configured
such that its output signal changes to high level when the feedback
signal reaches -5.9 dBm. The feedback signal at -5.9 dBm
corresponds to the level of the feedback signal when the output
control terminal (VAPC) of the power module 200 is at a level such
as -11 dBm. The shift level circuit LVS is provided because the
charge pump CGP is not capable of providing 0 V due to the nature
of the current source IS2.
[0049] Next, the operation involved in building up the output power
in the polar loop based transmitter circuit according to this
embodiment will be described with reference to a flow chart of FIG.
3.
[0050] In the output power build-up operation, the oscillator for
transmitter TxVCO is first turned on (step S1). Subsequently, I, Q
signals are sent from the baseband LSI 300 to the modulation
circuit 120 to modulate an intermediate frequency signal .phi.IF
and supplies the modulated signal to the phase detection circuit
140 and amplitude detection circuit 150. In this event, the phase
detection circuit 140 is fed back with a transmission signal of the
oscillator for transmitter TxVCO after downconverted by the mixer
131. The phase detection circuit 140 compares the phase of the
feedback signal with that of the modulated signal to start such a
control that matches the phases of the two signals with each other
(step S2). The amplitude detection circuit 150 is also applied with
the modulated signal and a detection signal from the coupler 220
through the feedback path.
[0051] Next, the flip-flop FF1 is reset by a reset signal RS, and
the switch SW11 on the forward path of the amplitude loop is turned
off by the output signal of the flip-flop FF1 to open the loop
(step S3). In this event, when the variable gain amplifier circuit
IVGA is implemented by a general differential amplifier circuit as
illustrated in FIG. 9, the variable gain amplifier circuit IVGA is
short-circuited between an inverting input terminal and a
non-inverting input terminal. This is done in order to maintain a
reference voltage for capacitors C2, C3 and a resistor R3 within
the loop filter LPF2 on the amplitude loop and to avoid sudden
fluctuations in the output of the variable gain amplifier circuit
IVGA when the amplitude loop is closed.
[0052] Also, substantially simultaneously with the loop being
opened, the switch SW12 is turned on to start precharging the
capacitor C4 of the charge pump CGP by the precharge current source
PCI (step S4). Subsequently, as the level detection circuit DCT
determines that the modulated signal matches in level with the
feedback signal from the amplitude loop, the level detection
circuit DCT operates the flip-flop FF1 as a latch to change its
output (steps S5, S6). This causes the switch SW12 to turn off to
stop precharging, and the switch SW11 on the forward path to turn
on to close the amplitude loop, thereby starting the amplitude
control (step S7). Also, at this time, the variable gain amplifier
circuit IVGA releases the differential input terminals from the
short-circuited state.
[0053] The foregoing operation is automatically executed by a
sequencer 180 by sending a transmission starting command from the
baseband LSI 300 to the high frequency IC 100. Then, the output
control voltage VRAMP is already active before the switch SW11 is
turned on to close the amplitude loop to control the power module
200 to build up its output power to a desired level.
[0054] As described above, in this embodiment, as soon as the
capacitor C4 in the amplitude loop is precharged, the output power
can be ramped up in the required time condition, as shown in FIG.
4, thereby making it possible to build up the output power within a
time mask prescribed in the EDGE scheme (the same applies to the
GMSK scheme). FIG. 4 shows a time mask and an associated build-up
operation when a required output level is relatively high such as
27 dBm at a location relatively far from a base station, while FIG.
5 shows a time mask and an associated build-up operation when a
required output level is relatively high such as 13 dBm at a
location relatively far from a base station. When the required
output level is relatively low, the output power can be built up
within the prescribed time mask by delaying the start of precharge
by a predetermined time, for example, 10 .mu.sec, as shown in FIG.
5.
[0055] FIG. 6 illustrates a second embodiment of a precharge
circuit.
[0056] The precharge circuit in the second embodiment comprises a
timer TMR for controlling the precharge current source PCI in
addition to the like circuit in the first embodiment. The timer TMR
can be configured to measure the time in response to a clock signal
supplied from the baseband LSI 300. Also, the timer TMR may be
provided integrally with other timers within the sequencer 180. The
timer TMR is started simultaneously with the start of precharge at
step S4 in FIG. 3, and the precharge current source PCI is turned
off, for example, after the lapse of 5 .mu.sec. In this way, the
precharge can be terminated even if no change is found in the
output of the level detection circuit DTC because the feedback
signal has not reached the predetermined level at that time.
[0057] Even if constants of elements constituting the precharge
circuit are set by design such that the output of the level shift
circuit LVS, i.e., the output control voltage (VAPC) of the power
module 200 reaches a level such as -11 dB in about 5 .mu.sec after
the start of precharge, variations due to manufacturing may cause a
build-up rate of the output power to be lower than expectancy.
Therefore, if the precharge takes a long time, a time significantly
longer than 5 .mu.sec, the output power of the power module 200
cannot be build up to a power threshold within a predetermined time
(28 sec) defined by the time mask. The second embodiment solves
this problem.
[0058] In the embodiment of FIG. 6, the precharge current source
PCI is controlled to be on and off by the timer TMR. Alternatively,
an AND gate may be provided for taking logical AND of the output of
the flip-flop FF1 (invertor INV in FIG. 6) and the output of the
timer TMR, such that the switch SW12 is turned off by the earlier
one of these outputs to terminate the precharge. However, it is
preferable from a viewpoint of timing to control on and off the
precharge current source PCI using the timer TMR and to turn off
the switch SW12 using the output of the flip-flop FF1 (invertor
INV), as is the case with the embodiment of FIG. 6.
[0059] More specifically, a regulated current source generally
presents a slower reaction than the switch SW12, so that if the
precharge were terminated by turning off the precharge current
source PCI using the output of the flip-flop FF1 when the level
detection circuit DTC presents a change in the output, the output
power could fall within a prohibited range of the time mask due to
a delay in the reaction of the current source PCI when variations
due to manufacturing cause the output power to be much higher than
expected. Thus, the switch SW12 is preferably turned off using the
output of the flip-flop FF1 (invertor INV) as is done in the
foregoing embodiment.
[0060] On the other hand, considering that variations due to
manufacturing cause the build-up rate of the output power to be
lower than expected, when the precharge current source PCI is
turned off using the timer TMR in such a case, as is done in the
foregoing embodiment, the output power reached at the end of the
precharge period is higher than the output power that the amplitude
loop would reach by itself due to a delayed reaction of the
precharge current source PCI. For this reason, the embodiment
configured as such is advantageous in its ability to advance, even
slightly, the build-up of the output power.
[0061] The embodiments in FIG. 6 and next FIG. 7 show exemplary
configurations of the level detection circuit DTC. The level
detection circuit DTC in these embodiments comprises a first AC-DC
converting means comprised of a diode D1 and a capacitor C11 for
converting a signal (for example, an AC signal at 80 MHz) SREF
supplied from the modulation circuit 120 for defining a reference
level of -5.9 dBm to a DC signal; a second AC-DC converting means
comprised of a diode D2 and a capacitor C12 for converting a
feedback signal SFB from the feedback path of the amplitude loop to
a DC signal; and a comparator CMP comprised of a differential
amplifier for comparing the converted signals with each other.
[0062] FIG. 7 illustrates a third embodiment of the precharge
circuit.
[0063] The third embodiment applies a two-stage precharge method
for precharging in stages the capacitor C4 which forms part of the
charge pump CGP. Specifically, a switch SW13 is provided between a
regulated voltage source CV1 (0.1 V) which provides a voltage as a
reference for a shift amount (-0.6 V on the output side) in the
level shift circuit LVS, and the node N1 to which the capacitor C4
is connected, such that the regulated voltage source CV1 can be
utilized as a precharge power supply. In addition, the precharge
current source PCI used herein supplies a smaller current value
than the precharge current sources PCI in the first and second
embodiments. Then, in the third embodiment, as illustrated in FIG.
8, the switch SW13 is first turned on within a short time T1
immediately after the output power is build up to precharge the
capacitor C4 to 0.1 V by the regulated voltage source CV1.
Subsequently, the switch SW12 is turned on to slowly precharge the
capacitor C4 to approximately 0.4 V by the precharge current source
PCI over a relatively long time T2.
[0064] In the foregoing embodiment, the switch SW12 for precharge
control is turned off using the output of the level detection
circuit DCT in order to prevent a delay in timing at which the
precharge is terminated. Considering more strictly, there is a
detection delay in the level detection circuit DCT which detects
that the output power of the power module 200 reaches -11 dBm, and
a delay in the timing at which the switch SW12 is turned off using
the output of the level detection circuit DCT indicative of the
detection, so that the capacitor C4 is likely to be excessively
precharged in the meantime. Therefore, the third embodiment employs
the precharge current source PCI which supplies a relatively small
current value to reduce the precharge rate. In addition, before the
capacitor C4 is precharged by the precharge current source PCI, the
capacitor C4 is relatively rapidly precharged up to 0.6 V so that
the LVS output reaches 0.1 V, utilizing the regulated voltage
source CV1 for shifting, and then is slowly precharged by the
precharge current source PCI. In this way, the capacitor C4 can be
prevented from the excessive precharge.
[0065] During the precharge, the variable gain amplifier circuit
IVGA is short-circuited between the inverting input terminal and
non-inverting input terminal, and its output is opened (by SW11 in
FIG. 7). Then, simultaneously with the termination of the
precharge, the two input terminals are active, while the output is
also active.
[0066] While the invention made by the present inventors has been
specifically described in connection with several embodiments, it
should be understood that the present invention is not limited to
the aforementioned embodiments but may be modified in various
manner without departing from the spirit and scope of the
invention. For example, while the third embodiment utilizes the
regulated voltage source CV1 for shifting in the level shift
circuit LVS for the precharge at the first stage, a separate
regulated voltage source may be provided for supplying a voltage
lower than a target precharge level (for example, 0.4 V) for the
amplitude loop to perform the precharge at the first stage.
However, an increase in circuit scale can be prevented by utilizing
the regulated voltage source CV1 for shifting as in the third
embodiment.
[0067] While the present invention has been described in connection
with a dual-band system to which the present invention is applied,
where the system is configured to provide for communications in
accordance with two schemes, i.e., the GSM 900 scheme and DCS 1800
scheme, the present invention can be utilized as well for
permitting communications which involves phase modulation in
accordance with an 8-PSK modulation mode, in addition to a GMSK
modulation mode, in a triple-band system which is configured to
provide for communications in accordance with either the GSM scheme
or DCS scheme, or in accordance with a PCS (Personal Communication
System) 1900 scheme in addition to these schemes or communications
using 850 MHz.
[0068] It should be further understood by those skilled in the art
that although the foregoing description has been made on
embodiments of the invention, the invention is not limited thereto
and various changes and modifications may be made without departing
from the spirit of the invention and the scope of the appended
claims.
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