U.S. patent application number 11/697174 was filed with the patent office on 2007-08-02 for thin film transistor array panel for liquid crystal display and method for manufacturing the same.
Invention is credited to Hak-Sun Chang, Nam-Hung Kim, Chang-Hun Lee, Jae-Jin Lyu.
Application Number | 20070176178 11/697174 |
Document ID | / |
Family ID | 26639365 |
Filed Date | 2007-08-02 |
United States Patent
Application |
20070176178 |
Kind Code |
A1 |
Lee; Chang-Hun ; et
al. |
August 2, 2007 |
Thin Film Transistor Array Panel for Liquid Crystal Display and
Method for Manufacturing the Same
Abstract
In a method of fabricating a liquid crystal display, an
insulating layer for storage capacitors is reduced in thickness to
increase the storage capacity while maintaining the aperture ratio
in a stable manner. A thin film transistor array panel for the
liquid crystal display includes an insulating substrate, and a gate
line assembly and a storage capacitor line assembly formed on the
insulating substrate. The gate line assembly has gate lines and
gate electrodes. A gate insulating layer covers the gate line
assembly and the storage capacitor line assembly. A semiconductor
pattern is formed on the gate insulating layer. A data line
assembly and storage capacitor conductive patterns are formed on
the gate insulating layer overlaid with the semiconductor pattern.
The data line assembly has data lines, source electrodes and drain
electrodes. The storage capacitor conductive patterns are partially
overlapped with the storage capacitor line assembly to thereby form
first storage capacitors. A passivation layer covers the data line
assembly, the storage capacitor conductive patterns and the
semiconductor pattern. First and second contact holes are formed at
the passivation layer while exposing the drain electrodes and the
storage capacitor conductive patterns. Pixel electrodes are formed
on the passivation layer while being connected to the drain
electrodes and the storage capacitor conductive patterns through
the first and the second contact holes. The pixel electrodes form
second storage capacitors in association with parts of the storage
capacitor line assembly.
Inventors: |
Lee; Chang-Hun; (Suwon-city,
KR) ; Kim; Nam-Hung; (Suwon-city, KR) ; Chang;
Hak-Sun; (Seoul, KR) ; Lyu; Jae-Jin;
(Kwangju-kun, KR) |
Correspondence
Address: |
Frank Chau, Esq.;F. CHAU & ASSOCIATES, LLP
Suite 501
1900 Hempstead Turnpike
East Measow
NY
11554
US
|
Family ID: |
26639365 |
Appl. No.: |
11/697174 |
Filed: |
April 5, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10432833 |
Nov 12, 2003 |
7209192 |
|
|
PCT/KR02/00334 |
Feb 27, 2002 |
|
|
|
11697174 |
Apr 5, 2007 |
|
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|
Current U.S.
Class: |
257/59 ; 257/72;
257/E27.111; 257/E27.113; 257/E27.131; 349/43 |
Current CPC
Class: |
G02F 1/136213 20130101;
G02F 1/13306 20130101; G02F 1/136295 20210101; G02F 1/136286
20130101; G02F 1/136227 20130101; H01L 27/124 20130101; H01L
27/1255 20130101; G02F 1/13458 20130101 |
Class at
Publication: |
257/059 ;
257/072; 349/043; 257/E27.131 |
International
Class: |
H01L 29/04 20060101
H01L029/04; G02F 1/136 20060101 G02F001/136 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 26, 2001 |
KR |
2001-59637 |
Dec 10, 2001 |
KR |
2001-77838 |
Claims
1. A thin film transistor array panel comprising: an insulating
substrate; a gate line assembly and storage capacitor electrode
lines formed on the insulating substrate, the gate line assembly
having gate lines and gate electrodes; a gate insulating layer
covering the gate line assembly and the storage capacitor electrode
lines; first contact holes formed at the gate insulating layer
while exposing the storage capacitor electrode lines; a
semiconductor pattern formed on the gate insulating layer while
being overlapped with the gate electrodes; a data line assembly and
storage capacitor conductive patterns formed on the gate insulating
layer overlaid with the semiconductor pattern, the data line
assembly having data lines, source electrodes and drain electrodes,
the storage capacitor conductive patterns being connected to the
storage capacitor electrode lines through the first contact holes;
a passivation layer covering the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern; second
contact holes formed at the passivation layer while exposing the
drain electrodes; and pixel electrodes formed at the passivation
layer while being connected to the drain electrodes through the
second contact holes, the pixel electrodes being overlapped with
the storage capacitor conductive patterns to thereby form first
storage capacitors while being partially overlapped with the
storage capacitor electrode lines to thereby form second storage
capacitors.
2. The thin film transistor array panel of claim 1 wherein the
storage capacitor electrode lines proceed parallel to the gate
lines.
3. The thin film transistor array panel of claim 1 wherein the
storage capacitor conductive patterns are overlapped with the
storage capacitor electrode lines.
4. The thin film transistor array panel of claim 3 wherein the
storage capacitor conductive patterns are formed within pixel
regions defined by the gate lines and the data lines.
5. The thin film transistor array panel of claim 1 wherein the
storage capacitor electrode patterns are formed with a bar shape
along the data lines while being overlapped with peripheral
portions of the pixel electrodes.
6. A liquid crystal display comprising: the thin film transistor
array panel of claim 1; a counter substrate facing the thin film
transistor array panel; and a liquid crystal layer sandwiched
between the thin film transistor array panel and the counter
panel.
7. The liquid crystal display of claim 6 wherein the first and the
second storage capacitors have an electrostatic capacitance greater
than the electrostatic capacitance of the liquid crystal layer by
90% or more.
8. A thin film transistor array panel comprising: an insulating
substrate; a gate line assembly formed on the insulating substrate,
the gate line assembly having first gate lines, gate electrodes
connected to the first gate lines, and second gate lines spaced
apart from the first gate lines with a predetermined distance; a
gate insulating layer covering the gate line assembly; first
contact holes formed at the gate insulating layer while partially
exposing the second gate lines; a semiconductor pattern formed on
the gate insulating layer while being overlapped with the gate
electrodes; a data line assembly and storage capacitor conductive
patterns formed on the gate insulating layer overlaid with the
semiconductor pattern, the data line assembly having data lines
crossing over the first and the second gate lines, source
electrodes and drain electrodes, the storage capacitor conductive
patterns being connected to the second gate lines through the first
contact holes; a passivation layer covering the data line assembly,
the storage capacitor conductive patterns and the semiconductor
pattern; second contact holes formed at the passivation layer while
exposing the drain electrodes; and pixel electrodes formed at the
passivation layer while being connected to the drain electrodes
through the second contact holes, the pixel electrodes being
overlapped with the storage capacitor conductive patterns to
thereby form first storage capacitors while being partially
overlapped with the second gate lines to thereby form second
storage capacitors.
9. A liquid crystal display comprising: the thin film transistor
array panel of claim 8; a counter substrate facing the thin film
transistor array panel; and a liquid crystal layer sandwiched
between the thin film transistor array panel and the counter
panel.
10. The liquid crystal display of claim 9 wherein the first and the
second storage capacitors have an electrostatic capacitance greater
than the electrostatic capacitance of the liquid crystal layer by
90% or more.
Description
CROSS REFERENCE TO PRIOR APPLICATION
[0001] This application is a Divisional Application from a U.S.
patent application Ser. No. 10/432,833 filed May 24, 2003. which is
herein specifically incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a thin film transistor
array panel for a liquid crystal display, and a method for
manufacturing the same.
[0004] 2. Description of the Related Art
[0005] Generally, a liquid crystal display has two substrates with
electrodes, and a liquid crystal layer sandwiched between the two
substrates. Voltages are applied to the electrodes so that the
liquid crystal molecules in the liquid crystal layer are
re-oriented to thereby control the light transmission. The
electrodes may be all formed at one of the substrates. One of the
substrates is called the "thin film transistor array panel", and
the other is called the "color filter substrate."
[0006] The thin film transistor array panel has a plurality of gate
lines, data lines crossing over the gate lines while defining pixel
regions, thin film transistors formed at the respective pixel
regions while being electrically connected to the gate and the data
lines, and pixel electrodes electrically connected to the thin film
transistors.
[0007] Storage capacitors are formed at the thin film transistor
array panel to keep the voltage applied to the liquid crystal
disposed between the two substrates in a stable manner. For that
purpose, a storage capacitor line assembly is formed at the same
layer as the gate lines such that it is overlapped with the pixel
electrodes to thereby form storage capacitors. Meanwhile, the
electrostatic capacitance of the storage capacitors should be
increased to enhance the brightness of the display device or to
make rapid response speed thereof. In this connection, it is
necessary to enlarge the area of the storage capacitor line
assembly, but this causes decreased aperture or opening ratio.
SUMMARY OF THE INVENTION
[0008] It is an object of the present invention to provide a thin
film transistor array panel for a liquid crystal display which
involves storage capacitors with increased electrostatic
capacitance while bearing a reasonable aperture ratio.
[0009] This and other objects may be achieved by a thin film
transistor array panel for a liquid crystal display where the
storage capacitor line assembly is formed at the same layer as the
data lines, or the thickness of the insulating layer for the
storage capacitors is minimized.
[0010] According to one aspect of the present invention, the thin
film transistor array panel includes an insulating substrate, and a
gate line assembly formed on the insulating substrate and including
gate lines, and gate electrodes. A gate insulating layer covers the
gate line assembly. A semiconductor pattern is formed on the gate
insulating layer. A data line assembly is formed on the gate
insulating layer overlaid with the semiconductor pattern. The data
line assembly has data lines crossing over the gate lines, source
electrodes connected to the data lines and the semiconductor
pattern, and drain electrodes facing the source electrodes and
connected to the semiconductor pattern. Storage capacitor electrode
lines are formed between the neighboring data lines while crossing
over the gate lines. A passivation layer covers the data line
assembly, the storage capacitor electrode lines and the
semiconductor pattern while bearing contact holes exposing the
drain electrodes. Pixel electrodes are formed on the passivation
layer while being connected to the drain electrodes through the
contact holes. The pixel electrodes are overlapped with the storage
capacitor electrode lines.
[0011] The thin film transistor array panel may further include a
common interconnection line commonly interconnecting the storage
capacitor electrode lines. The common interconnection line may
formed with the same material as the pixel electrodes or the gate
lines while crossing over the data lines in an insulated
manner.
[0012] The passivation layer has a plurality of contact holes
exposing the storage capacitor electrode lines, and the common
interconnection line is connected to the storage capacitor
electrode lines through the contact holes. A subsidiary
interconnection line may be connected to the storage capacitor
electrode lines. The storage capacitor electrode lines and the
subsidiary interconnection line are formed with the same
material.
[0013] Gate pads are formed at one-sided portions of the gate
lines, and data pads are formed at one-sided end portions of the
data lines. First contact holes are formed at the passivation layer
and the gate insulating layer while exposing the gate pads, and
second contact holes are formed at the passivation layer while
exposing the data pads. Subsidiary gate and data pads are connected
to the gate and the data pads through the first and the second
contact holes.
[0014] In addition to the above-structured thin film transistor
array panel, the liquid crystal display includes a counter
substrate facing the thin film transistor array panel, and a liquid
crystal layer sandwiched between the thin film transistor array
panel and the counter panel. The liquid crystal display has storage
capacitors with an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal capacitor having
the liquid crystal layer by 90% or more.
[0015] According to another aspect of the present invention, the
thin film transistor array panel includes an insulating substrate,
and a gate line assembly and a storage capacitor line assembly
formed on the insulating substrate. The gate line assembly has gate
lines and gate electrodes. A gate insulating layer covers the gate
line assembly and the storage capacitor line assembly. A
semiconductor pattern is formed on the gate insulating layer. A
data line assembly and storage capacitor conductive patterns are
formed on the gate insulating layer overlaid with the semiconductor
pattern. The data line assembly has data lines, source electrodes
and drain electrodes. The storage capacitor conductive patterns are
partially overlapped with the storage capacitor line assembly to
thereby form first storage capacitors. A passivation layer covers
the data line assembly, the storage capacitor conductive patterns
and the semiconductor pattern. First and second contact holes are
formed at the passivation layer while exposing the drain electrodes
and the storage capacitor conductive patterns, respectively. Pixel
electrodes are formed on the passivation layer while being
connected to the drain electrodes and the storage capacitor
conductive patterns through the first and the second contact holes.
The pixel electrodes form second storage capacitors in association
with parts of the storage capacitor line assembly.
[0016] The storage capacitor line assembly has storage capacitor
electrode lines proceeding parallel to the gate lines, and storage
capacitor electrode patterns connected to the storage capacitor
electrode lines. The storage capacitor electrode patterns are
overlapped with the storage capacitor conductive patterns to
thereby form the first storage capacitors, and the storage
capacitor electrode lines are overlapped with the pixel electrodes
to thereby form the second storage capacitors.
[0017] The storage capacitor electrode patterns are formed within
pixel regions defined by the gate lines and the data lines. The
storage capacitor electrode patterns are formed with a bar shape
along the data lines while being overlapped with peripheral
portions of the pixel electrodes.
[0018] In addition to the above-structured thin film transistor
array panel, the liquid crystal display includes a counter
substrate facing the thin film transistor array panel, and a liquid
crystal layer sandwiched between the thin film transistor array
panel and the counter panel. The first and the second storage
capacitors have an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal layer by 90% or
more.
[0019] According to still another aspect of the present invention,
the thin film transistor array panel includes an insulating
substrate, and a gate line assembly formed on the insulating
substrate. The gate line assembly has first gate lines, gate
electrodes connected to the first gate lines, and second gate lines
spaced apart from the first gate lines with a predetermined
distance. A gate insulating layer covers the gate line assembly. A
semiconductor pattern is formed on the gate insulating layer while
being overlapped with the gate electrodes. A data line assembly and
storage capacitor conductive patterns are formed on the gate
insulating layer overlaid with the semiconductor pattern. The data
line assembly has data lines crossing over the first and the second
gate lines, source electrodes and drain electrodes. The storage
capacitor conductive patterns are partially overlapped with the
second gate lines to thereby form first storage capacitors. A
passivation layer covers the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern. First
and second contact holes are formed at the passivation layer while
exposing the drain electrodes and the storage capacitor conductive
patterns, respectively. Pixel electrodes are formed at the
passivation layer while being connected to the drain electrodes and
the storage capacitor conductive patterns through the first and the
second contact holes. The pixel electrodes are partially overlapped
with the second gate lines to thereby form second storage
capacitors.
[0020] In addition to the above-structured thin film transistor
array panel, the liquid crystal display includes a counter
substrate facing the thin film transistor array panel, and a liquid
crystal layer sandwiched between the thin film transistor array
panel and the counter panel. The first and the second storage
capacitors have an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal layer by 90% or
more.
[0021] According to still another aspect of the present invention,
the thin film transistor array panel includes an insulating
substrate, and a gate line assembly and storage capacitor electrode
lines formed on the insulating substrate. The gate line assembly
has gate lines and gate electrodes. A gate insulating layer covers
the gate line assembly and the storage capacitor electrode lines.
First contact holes are formed at the gate insulating layer while
exposing the storage capacitor electrode lines. A semiconductor
pattern is formed on the gate insulating layer while being
overlapped with the gate electrodes. A data line assembly and
storage capacitor conductive patterns are formed on the gate
insulating layer overlaid with the semiconductor pattern. The data
line assembly has data lines, source electrodes and drain
electrodes. The storage capacitor conductive patterns are connected
to the storage capacitor electrode lines through the first contact
holes. A passivation layer covers the data line assembly, the
storage capacitor conductive patterns and the semiconductor
pattern. Second contact holes are formed at the passivation layer
while exposing the drain electrodes. Pixel electrodes are formed at
the passivation layer while being connected to the drain electrodes
through the second contact holes. The pixel electrodes are
overlapped with the storage capacitor conductive patterns to
thereby form first storage capacitors while being partially
overlapped with the storage capacitor electrode lines to thereby
form second storage capacitors.
[0022] The storage capacitor electrode lines proceed parallel to
the gate lines, and the storage capacitor conductive patterns are
overlapped with the storage capacitor electrode lines. The storage
capacitor conductive patterns are formed within pixel regions
defined by the gate lines and the data lines. The storage capacitor
electrode patterns are formed with a bar shape along the data lines
while being overlapped with peripheral portions of the pixel
electrodes.
[0023] In addition to the above-structured thin film transistor
array panel, the liquid crystal display includes a counter
substrate facing the thin film transistor array panel, and a liquid
crystal layer sandwiched between the thin film transistor array
panel and the counter panel. The first and the second storage
capacitors have an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal layer by 90% or
more.
[0024] According to still another aspect of the present invention,
the thin film transistor array panel includes an insulating
substrate, and a gate line assembly formed on the insulating
substrate. The gate line assembly has first gate lines, gate
electrodes connected to the first gate lines, and second gate lines
spaced apart from the first gate lines with a predetermined
distance. A gate insulating layer covers the gate line assembly.
First contact holes are formed at the gate insulating layer while
partially exposing the second gate lines. A semiconductor pattern
is formed on the gate insulating layer while being overlapped with
the gate electrodes. A data line assembly and storage capacitor
conductive patterns are formed on the gate insulating layer
overlaid with the semiconductor pattern. The data line assembly has
data lines crossing over the first and the second gate lines,
source electrodes and drain electrodes. The storage capacitor
conductive patterns are connected to the second gate lines through
the first contact holes. A passivation layer covers the data line
assembly, the storage capacitor conductive patterns and the
semiconductor pattern. Second contact holes are formed at the
passivation layer while exposing the drain electrodes. Pixel
electrodes are formed at the passivation layer while being
connected to the drain electrodes through the second contact holes.
The pixel electrodes are overlapped with the storage capacitor
conductive patterns to thereby form first storage capacitors while
being partially overlapped with the second gate lines to thereby
form second storage capacitors.
[0025] In addition to the above-structured thin film transistor
array panel, the liquid crystal display includes a counter
substrate facing the thin film transistor array panel, and a liquid
crystal layer sandwiched between the thin film transistor array
panel and the counter panel. The first and the second storage
capacitors have an electrostatic capacitance greater than the
electrostatic capacitance of the liquid crystal layer by 90% or
more.
[0026] According to another aspect of the present invention, in a
method of fabricating a thin film transistor array panel, a gate
line assembly and a storage capacitor line assembly are formed on
an insulating substrate such that the gate line assembly has gate
lines and gate electrodes. A gate insulating layer is formed on the
substrate such that it covers the gate line assembly and the
storage capacitor line assembly. A semiconductor pattern is formed
on the gate insulating layer. A data line assembly and storage
capacitor conductive patterns are formed on the gate insulating
layer overlaid with the semiconductor pattern such that the data
line assembly has data lines, source electrodes and drain
electrodes, and the storage capacitor conductive patterns are
partially overlapped with the storage capacitor line assembly to
thereby form first storage capacitors. A passivation layer is
formed on the substrate such that it covers the data line assembly,
the storage capacitor conductive patterns and the semiconductor
pattern. First and second contact holes are formed at the
passivation layer such that they expose the drain electrodes and
the storage capacitor conductive patterns, respectively. Pixel
electrodes are formed on the passivation layer such that they are
connected to the drain electrodes and the storage capacitor
conductive patterns through the first and the second contact holes
while forming second storage capacitors in association with parts
of the storage capacitor lines assembly.
[0027] The storage capacitor line assembly has storage capacitor
electrode lines proceeding parallel to the gate lines, and storage
capacitor electrode patterns connected to the storage capacitor
electrode lines.
[0028] According to still another aspect of the present invention,
in a method of fabricating a thin film transistor array panel, a
gate line assembly is formed on an insulating substrate such that
it has first gate lines, gate electrodes connected to the first
gate lines, and second gate lines spaced apart from the first gate
lines with a predetermined distance while proceeding parallel to
the first gate lines. A gate insulating layer is formed on the
substrate such that it covers the gate line assembly. A
semiconductor pattern is formed on the gate insulating layer such
that it is overlapped with the gate electrodes. A data line
assembly and storage capacitor conductive patterns are formed on
the gate insulating layer overlaid with the semiconductor pattern
such that the data line assembly has data lines crossing over the
first and the second gate lines, source electrodes and drain
electrodes, and the storage capacitor conductive patterns are
partially overlapped with the second gate lines to thereby form
first storage capacitors. A passivation layer is formed on the
substrate such that it covers the data line assembly, the storage
capacitor conductive patterns and the semiconductor pattern. First
and second contact holes are formed at the passivation layer such
that the first and the second contact holes expose the drain
electrodes and the storage capacitor conductive patterns,
respectively. Pixel electrodes are formed on the passivation layer
such that they are connected to the drain electrodes and the
storage capacitor conductive patterns through the first and the
second contact holes while forming second storage capacitors in
association with parts of the second gate lines.
[0029] According to still another aspect of the present invention,
in a method of fabricating a thin film transistor array panel, a
gate line assembly and storage capacitor electrode lines are formed
on an insulating substrate such that the gate line assembly has
gate lines and gate electrodes. A gate insulating layer is formed
on the substrate such that it covers the gate line assembly and the
storage capacitor electrode lines. First contact holes are formed
at the gate insulating layer such that they expose the storage
capacitor electrode lines. A semiconductor pattern is formed on the
gate insulating layer such that it is overlapped with the gate
electrodes. A data line assembly and storage capacitor conductive
patterns are formed on the gate insulating layer overlaid with the
semiconductor pattern such that the data line assembly has data
lines, source electrodes and drain electrodes, and the storage
capacitor conductive patterns are connected to the storage
capacitor electrode lines through the first contact holes. A
passivation layer is formed on the substrate such that it covers
the data line assembly, the storage capacitor conductive patterns
and the semiconductor pattern. Second contact holes are formed at
the passivation layer such that they expose the drain electrodes.
Pixel electrodes are formed on the passivation layer such that they
are connected to the drain electrodes through the second contact
holes. The pixel electrodes are overlapped with the storage
capacitor conductive patterns to thereby form first storage
capacitors while being partially overlapped with the storage
capacitor electrode lines to thereby form second storage
capacitors.
[0030] According to still another aspect of the present invention,
in a method of fabricating a thin film transistor array panel, a
gate line assembly is formed on an insulating substrate such that
it has first gate lines, gate electrodes connected to the first
gate lines, and second gate lines spaced apart from the first gate
lines with a predetermined distance while proceeding parallel to
the first gate lines. A gate insulating layer is formed on the
substrate such that it covers the gate line assembly. First contact
holes are formed at the gate insulating layer such that they
partially expose the second gate lines. A semiconductor pattern is
formed on the gate insulating layer such that it is overlapped with
the gate electrodes. A data line assembly and storage capacitor
conductive patterns are formed on the gate insulating layer
overlaid with the semiconductor pattern such that the data line
assembly has data lines crossing over the first and the second gate
lines, source electrodes and drain electrodes, and the storage
capacitor conductive patterns are connected to the second gate
lines through the first contact holes. A passivation layer is
formed on the substrate such that it covers the data line assembly,
the storage capacitor conductive patterns and the semiconductor
pattern. Second contact holes are formed at the passivation layer
such that they expose the drain electrodes. Pixel electrodes are
formed on the passivation layer such that they are connected to the
drain electrodes through the second contact holes. The pixel
electrodes are overlapped with the storage capacitor conductive
patterns to thereby form first storage capacitors while being
partially overlapped with the second gate lines to thereby form
second storage capacitors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] A more complete appreciation of the invention, and many of
the attendant advantages thereof, will be readily apparent as the
same becomes better understood by reference to the following
detailed description when considered in conjunction with the
accompanying drawings in which like reference symbols indicate the
same or the similar components, wherein:
[0032] FIG. 1 is a plan view of a thin film transistor array panel
according to a first preferred embodiment of the present
invention;
[0033] FIGS. 2 and 3 are cross sectional views of the thin film
transistor array panel taken along the II-II' line and the III-III'
line of FIG. 1;
[0034] FIG. 4 illustrates the layout of gate lines, data lines and
storage capacitor electrode lines at the thin film transistor array
panel shown in FIG. 1;
[0035] FIG. 5A illustrates the first step of fabricating the thin
film transistor array panel shown in FIG. 1;
[0036] FIGS. 5B and 5C are cross sectional views of the thin film
transistor array panel taken along the VB-VB' line and the VC-VC'
line of FIG. 5A;
[0037] FIG. 6A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
5A;
[0038] FIGS. 6B and 6C are cross sectional views of the thin film
transistor array panel taken long the VIB-VIB' line and the
VIC-VIC' line of FIG. 6A;
[0039] FIG. 7A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
6A;
[0040] FIGS. 7B and 7C are cross sectional views of the thin film
transistor array panel taken long the VIIB-VIIB' line and the
VIIC-VIIC' line of FIG. 7A;
[0041] FIG. 8 is a plan view of a thin film transistor array panel
according to a second preferred embodiment of the present
invention;
[0042] FIG. 9 is a cross sectional view of the thin film transistor
array panel taken along the IX-IX' line of FIG. 8;
[0043] FIG. 10A illustrates the first step of fabricating the thin
film transistor array panel shown in FIG. 8;
[0044] FIG. 10B is a cross sectional view of the thin film
transistor array panel taken long the XBb-XB' line of FIG. 10A;
[0045] FIG. 11A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
10A;
[0046] FIG. 11B is a cross sectional view of the thin film
transistor array panel taken long the XIB-XIB' line of FIG.
11A;
[0047] FIG. 12A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
11A;
[0048] FIG. 12B is a cross sectional view of the thin film
transistor array panel taken long the XIIB-XIIB' line of FIG.
12A;
[0049] FIG. 13A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
12A;
[0050] FIG. 13B is a cross sectional view of the thin film
transistor array panel taken long the XIIIB-XIIIB' line of FIG.
13A;
[0051] FIG. 14 is a plan view of a thin film transistor array panel
according to a third preferred embodiment of the present
invention;
[0052] FIG. 15 is a cross sectional view of the thin film
transistor array panel taken along the XV-XV' line of FIG. 14;
[0053] FIG. 16 is a plan view of a thin film transistor array panel
according to a fourth preferred embodiment of the present
invention;
[0054] FIG. 17 is a cross sectional view of the thin film
transistor array panel taken long the XVII-XVII' line of FIG.
16;
[0055] FIG. 18 is a plan view of a thin film transistor array panel
according to a fifth preferred embodiment of the present
invention;
[0056] FIG. 19 is a cross sectional view of the thin film
transistor array panel taken long the XIX-XIX' line of FIG. 18;
[0057] FIG. 20A illustrates the first step of fabricating the thin
film transistor array panel shown in FIG. 18;
[0058] FIG. 20B is a cross sectional view of the thin film
transistor array panel taken long the XXB-XXB' line of FIG.
20A;
[0059] FIG. 21A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
20A;
[0060] FIG. 21B is a cross sectional view of the thin film
transistor array panel taken long the XXIB-XXIB' line of FIG.
21A;
[0061] FIG. 22A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
21A;
[0062] FIG. 22B is a cross sectional view of the thin film
transistor array panel taken long the XXIIB-XXIIB' line of FIG.
22A;
[0063] FIG. 23A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
22A;
[0064] FIG. 23B is a cross sectional view of the thin film
transistor array panel taken long the XXIIIB-XXIIIB' line of FIG.
23A;
[0065] FIG. 24A illustrates the step of fabricating the thin film
transistor array panel following the step illustrated in FIG.
23A;
[0066] FIG. 24B is a cross sectional view of the thin film
transistor array panel taken long the XXIVB-XXIVB' line of FIG.
24A;
[0067] FIG. 25 is a plan view of a thin film transistor array panel
according to a sixth preferred embodiment of the present
invention;
[0068] FIG. 26 is a cross sectional view of the thin film
transistor array panel taken long the XXVI-XXVI' of FIG. 25;
[0069] FIG. 27 is a plan view of a thin film transistor array panel
according to a seventh preferred embodiment of the present
invention;
[0070] FIG. 28 is a cross sectional view of the thin film
transistor array panel taken long the XXVIII-XXVIII' line of FIG.
27; and
[0071] FIG. 29 illustrates a waveform curve of the response speed
in a liquid crystal display.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0072] Preferred embodiments of this invention will be explained
with reference to the accompanying drawings.
[0073] FIG. 1 is a plan view of a thin film transistor array panel
for a liquid crystal display according to a first preferred
embodiment of the present invention, and FIGS. 2 and 3 are cross
sectional views of the thin film transistor array panel taken along
the II-II' line and the III-III' line of FIG. 1.
[0074] A gate line assembly is formed on an insulating substrate 10
with a conductive material such as aluminum, aluminum alloy,
chrome, chrome alloy, molybdenum, molybdenum alloy, chrome nitride,
and molybdenum nitride while bearing a thickness of 1000-3500
.ANG.. The gate line assembly includes gate lines 22 proceeding in
the horizontal direction, gate pads 24 connected to the one-sided
ends of the gate lines 22 while electrically contacting external
driving circuits (not shown), and gate electrodes 26 being parts of
the gate lines 22 while forming thin film transistors with other
electrode components.
[0075] The gate assembly may have a multiple-layered structure
where one layer is formed with a low resistance metallic material,
and the other layer with a material bearing a good contact
characteristic with other materials.
[0076] A gate insulating layer 30 with a thickness of 2,500-4,500
.ANG. is formed on the insulating substrate 10 with silicon nitride
or silicon oxide while covering the gate line assembly.
[0077] A semiconductor pattern 42 with a thickness of 800-1500
.ANG. is formed on the gate insulating layer 30 with amorphous
silicon while being overlapped with the gate electrodes 26. Ohmic
contact patterns 55 and 56 with a thickness of 500-800 .ANG. are
formed on the semiconductor pattern 42 with amorphous silicon where
n type impurities are doped at high concentration.
[0078] A data line assembly and storage capacitor electrode lines
69 are formed on the ohmic contact patterns 55 and 56, and the gate
insulating layer 30 with a conductive material such as aluminum,
aluminum alloy, chrome, chrome alloy, molybdenum, molybdenum alloy,
chrome nitride and molybdenum nitride while bearing a thickness of
500-3500 .ANG.. The data line assembly includes data lines 65
proceeding in the vertical direction while crossing over the gate
lines 22 to define pixel regions, data pads 64 connected to the
one-sided ends of the data lines 62 while electrically contacting
external driving circuits, source electrodes 65 connected to the
data lines 62 while being extended over the ohmic contact pattern
55, and drain electrodes 66 facing the source electrodes 65 while
being placed over the other ohmic contact pattern 56. The drain
electrodes 66 are extended over the gate insulating layer 30 within
the pixel regions.
[0079] The storage capacity electrode lines 69 are placed at the
same plane as the data line assembly while proceeding in the
vertical direction such that they are alternately arranged with the
date lines 62. The storage capacity electrode lines 69 are
overlapped with pixel electrodes 82 to thereby form storage
capacitors.
[0080] The data line assembly may have a multiple-layered structure
where at least one layer is formed with a low resistance metallic
material.
[0081] A passivation layer 70 covers the data line assembly, the
storage capacitor electrode lines 69 and the semiconductor pattern
42 while bearing a thickness of 500-2000 .ANG.. The passivation
layer 70 is formed with an insulating material such as silicon
nitride and silicon oxide.
[0082] First and second contact holes 72 and 74 are formed at the
passivation layer 70 while exposing the drain electrodes 66 and the
data pads 64. Third contract holes 76 are formed at the passivation
layer 70 while exposing the gate pads 24 together with the gate
insulating layer 30. Furthermore, fourth contact holes 79 are
formed at the passivation layer 70 while exposing the end portions
of the storage capacitor electrode lines 69 sided with the data
pads 64.
[0083] Pixel electrodes 82 are formed on the passivation layer 70
to receive picture signals and generate electric fields together
with a common electrode (not shown) of the counter panel. The pixel
electrodes 82 are electrically connected to the drain electrodes 66
through the first contact holes 72.
[0084] The pixel electrodes 82 are overlapped with the storage
capacitor electrode lines 69 while interposing the passivation
layer 70 to thereby form storage capacitors. As the passivation
layer 70 disposed between the pixel electrodes 82 and the storage
capacitor electrode lines 69 bears a thin thickness, the resulting
storage capacitors bear a great electrostatic capacitance even when
the storage capacitor electrode lines 69 bear a narrow width.
[0085] Subsidiary data pads 84 and subsidiary gate pads 86 are
formed on the passivation layer 70 while being connected to the
data pads 64 and the gate pads 24 through the second and the third
contact holes 74 and 76. Furthermore, a common interconnection line
88 is formed external to the display area while proceeding parallel
to the gate lines 22. The display area refers to the sum of the
pixel regions. The common interconnection line 88 interconnects all
of the storage capacitor electrode lines 69 through the fourth
contact holes 79.
[0086] The pixel electrodes 82, the subsidiary data pads 84, the
subsidiary gate pads 86 and the common interconnection line 88 are
formed at the same plane with a transparent conductive material
such as ITO and IZO.
[0087] The common interconnection line 88 may be formed with the
same material as the gate line assembly during the process of
forming the gate line assembly. In this case, a plurality of
contact holes are formed at the gate insulating layer 30 while
exposing the common interconnection line 88. The plurality of
storage capacitor electrode lines 69 contact the common
interconnection line 88 through the contact holes formed at the
gate insulating layer 30.
[0088] FIG. 4 illustrates the arrangement of the gate lines, the
data lines and the storage capacitor electrode lines at the thin
film transistor array panel shown in FIG. 1.
[0089] As shown in FIG. 4, the plurality of gate lines 22 proceed
in the horizontal direction parallel to each other, and the
plurality of data lines 62 proceed in the vertical direction
parallel to each other. The data lines 62 cross over the gate lines
22 while defining the pixel regions. The display area 110 refers to
the sum of the pixel regions.
[0090] The one-sided end portions of the data lines 62 being the
data pads are electrically connected to data driving circuits 300
to receive data signals from the. Similarly, the one-sided end
portions of the gate lines 22 being the gate pads are electrically
connected to gate driving circuits (not shown) to receive gate
signals from them.
[0091] The storage capacitor electrode lines 69 are alternately
arranged with the data lines 62. The storage capacitor electrode
lines 69 are connected to each other by way of a subsidiary
interconnection line 61 placed external to the display area 110. It
is preferable that the storage capacitor electrode lines 69 and the
subsidiary interconnection line 61 are formed with the same
material while being commonly interconnected.
[0092] The common interconnection line 88 is placed at the ends of
the storage capacitor electrode lines 69 sided with the data
driving circuits while interconnecting all of the storage capacitor
electrode lines 69. It is preferable that the common
interconnection line 88 is formed with the same material as the
pixel electrodes 82 or the gate line assembly. This is to prevent
the common interconnection line 88 from being short circuited with
the portions of the data lines 62 connected to the data driving
circuits 300 external to the display area 110.
[0093] The storage capacitor electrode lines 69 are electrically
connected to the data driving circuits 300 to receive common
electrode voltages from them.
[0094] A method of fabricating the thin film transistor array panel
will be now explained with reference to FIGS. 5A to 7C as well as
FIGS. 1 to 4.
[0095] As shown in FIGS. 5A to 5C, a gate line assembly layer is
deposited onto an insulating substrate 10, and patterned through
photolithography to thereby form a gate line assembly. The gate
line assembly includes gate lines 22, gate pads 24, and gate
electrodes 26.
[0096] Thereafter, a gate insulating layer 30 based on an
insulating material such as silicon nitride is deposited onto the
insulating substrate 10 such that it covers the gate line
assembly.
[0097] An amorphous silicon layer and a conductive type
impurities-doped amorphous silicon layer are sequentially deposited
onto the gate insulating layer 30, and patterned through
photolithography to thereby form a semiconductor pattern 42 and an
ohmic contact pattern 52.
[0098] As shown in FIGS. 6A to 6C, a metallic layer is deposited
onto the entire surface of the substrate, and patterned through
photolithography to thereby form a data line assembly and storage
capacitor electrode lines 69. The data line assembly includes data
lines 62, data pads 64, source electrodes 65, and drain electrodes
66. The storage capacitor electrode lines 69 are alternately
arranged with the data lines 62.
[0099] The ohmic contact pattern 52 is etched using the source
electrode 65 and the drain electrode 66 as a mask to thereby
separate it into a first portion 55 contacting the source electrode
65, and a second portion 56 contacting the drain electrode 66.
[0100] As shown in FIGS. 7A to 7C, a passivation layer 70 covers
the data line assembly, the storage capacitor electrode lines 69,
and the semiconductor pattern 42. The passivation layer 70 is
formed with silicon nitride while bearing a thin thickness. In
consideration of the electrostatic capacitance of the storage
capacitors to be formed, it is preferable that the thickness of the
passivation layer 70 is controlled in an appropriate manner.
[0101] The passivation layer 70 and the gate insulating layer 30
are patterned through photolithography to thereby form first to
fourth contact holes 72, 74, 76 and 79.
[0102] As shown in FIGS. 1 to 3, a transparent conductive layer
based on ITO or IZO is deposited onto the entire surface of the
substrate 10.
[0103] The transparent conductive layer is patterned through
photolithography to thereby form pixel electrodes 82, subsidiary
data pads 84, subsidiary gate pads 86, and a common interconnection
line 88. The pixel electrodes 82 are connected to the drain
electrodes 66 through the first contact holes 72. The subsidiary
data and gate pads 84 and 86 are connected to the data and gate
pads 64 and 24 through the second and the third contact holes 74
and 76. The common interconnection line 88 interconnects all of the
storage capacitor electrode lines 69 through the fourth contact
holes 79.
[0104] The common interconnection line 88 may be formed with the
same material as the gate line assembly. For that purpose, the
common interconnection line is formed during the process of forming
the gate line assembly while being followed by the formation of the
gate insulating layer 30. A plurality of contact holes exposing the
common interconnection line are then formed at the gate insulating
layer 30. The storage capacitor electrode lines 69 are formed
during the process of forming the data line assembly. In this
process, the storage capacitor electrode lines 69 are connected to
the common interconnection line through the contact holes.
[0105] As described above, the storage capacitor electrode lines
are formed at the same plane as the data lines such that they are
overlapped with the pixel electrodes while interposing the
passivation layer bearing a thin thickness to thereby form storage
capacitors.
[0106] Alternatively, the storage capacitors may be formed using a
gate insulating layer instead of the passivation layer.
[0107] FIG. 8 is a plan view of a thin film transistor array panel
according to a second preferred embodiment of the present
invention, and FIG. 9 is a cross sectional view of the thin film
transistor array panel taken along the IX-IX' line of FIG. 8.
[0108] A gate line assembly and a storage capacitor line assembly
are formed on an insulating substrate 10 with a conductive material
such as aluminum, aluminum alloy, chrome, chrome alloy, molybdenum,
molybdenum alloy, chrome nitride, and molybdenum nitride while
bearing a thickness of 1000-3500 .ANG..
[0109] The gate line assembly includes gate lines 22 proceeding in
the horizontal direction, gate pads 24 formed at the one-sided end
portions of the gate lines 22 while electrically contacting
external driving circuits (not shown), and gate electrodes 26 being
parts of the gate lines 22 while forming thin film transistors with
other components.
[0110] The storage capacitor line assembly includes
rectangular-shaped storage capacitor electrode patterns 28 disposed
between the neighboring gate lines 22, and storage capacitor
electrode lines 29 connected to the storage capacitor electrode
patterns in the neighboring pixel regions while proceeding in the
horizontal direction parallel to the gate lines 22.
[0111] The gate lines assembly and the storage capacitor line
assembly may have a multiple-layered structure where at least one
layer is formed with a low resistance metallic material.
[0112] A gate insulating layer 30 with a thickness of 2500-4500
.ANG. is formed on the insulating substrate 10 with silicon nitride
or silicon oxide while covering the gate line assembly and the
storage capacitor line assembly.
[0113] A semiconductor pattern 42 with a thickness of 800-1500
.ANG. is formed on the gate insulating layer 30 with amorphous
silicon while being overlapped with the gate electrodes 26. Ohmic
contact patterns 55 and 56 with a thickness of 500-800 .ANG. are
formed on the semiconductor pattern 42 with amorphous silicon where
n type impurities are doped at high concentration.
[0114] A data line assembly and storage capacitor conductive
patterns 68 are formed on the ohmic contact patterns 55 and 56 and
the gate insulating layer 30 with a conductive material such as
aluminum, aluminum alloy, chrome, chrome alloy, molybdenum,
molybdenum alloy, chrome nitride and molybdenum nitride while
bearing a thickness of 500-3500 .ANG..
[0115] The data line assembly includes data lines 62 proceeding in
the vertical direction while crossing over the gate lines 22 to
define pixel regions, data pads 64 formed at the one-sided end
portions and the data lines 62 while electrically contacting
external driving circuits, source electrodes 65 connected to the
data lines 62 while being extended over the ohmic contact pattern
55, and drain electrodes 66 facing the source electrodes 65 while
being placed over the other ohmic contact pattern 56. The drain
electrodes 66 are extended over the gate insulating layer 30 within
the pixel regions.
[0116] The storage capacity conductive patterns 68 are placed at
the same plane as the data line assembly while bearing an island
shape such that they are overlapped with the storage capacitor
electrode patterns 28 while interposing the gate insulating layer
30 to thereby form storage capacitors. The storage capacitor
conductive patterns 68 are electrically connected to pixel
electrodes 62 to be described later to receive picture signal
voltages.
[0117] The data line assembly and the storage capacitor conductive
patterns 68 may have a multiple-layered structure where at least
one layer is formed with a low resistance metallic material.
[0118] A passivation layer 70 covers the data line assembly, the
storage capacitor conductive patterns 68 and the semiconductor
pattern 42 while bearing a thickness of 500-2000 .ANG.. The
passivation layer 70 is form with an insulating material such as
silicon nitride and silicon oxide.
[0119] First and second contact holes 72 and 74 are formed at the
passivation layer 70 while exposing the drain electrodes 66 and the
data pads 64. Third contact holes 76 are formed at the passivation
layer 70 while exposing the gate pads 24 together with the gate
insulating layer 30. Furthermore, fourth contact holes 78 are
formed at the passivation layer 70 while exposing the storage
capacitor conductive patterns 68.
[0120] Pixel electrodes 82 are formed on the passivation layer 70
such that they are electrically connected to the drain electrodes
66 and the storage capacitor conductive patterns 68 through the
first and the fourth contact holes 72 and 78.
[0121] Subsidiary data pads 84 and subsidiary gate pads 86 are
formed on the passivation layer 70 while being connected to the
data pads 64 and the gate pads 24 through the second and the third
contact holes 74 and 76.
[0122] The pixel electrodes 82, the subsidiary data pads 84 and the
subsidiary gate pads 86 are formed with a transparent conductive
material such as ITO and IZO.
[0123] The pixel electrodes 82 are overlapped with the storage
capacitor line assembly while interposing the passivation layer 70
and the gate insulating layer 30 to thereby form storage
capacitors.
[0124] The pixel electrodes 82 are connected to the storage
capacitor conductive patterns 68. In this way, the storage
capacitor conductive patterns 68 form other storage capacitors in
association with the storage capacitor electrode patterns 28 while
interposing the gate insulating layer 30. In this case, as the
thickness of the gate insulating layer 30 disposed between the
storage capacitor conductive patterns 68 and the storage capacitor
electrode patterns 28 is small, the electrostatic capacitance of
the resulting storage capacitors becomes increased even with the
same overlapping area compared to the overlapping of the storage
capacitor electrode patterns 28 and the pixel electrodes 82.
Consequently, the aperture ratio with respect to the storage
capacity becomes enhanced.
[0125] A method of fabricating the thin film transistor array panel
will be now explained with reference to FIGS. 10A to 13B as well as
FIGS. 8 and 9.
[0126] As shown in FIGS. 10A and 10B, a metallic layer is deposited
onto an insulating substrate 10, and patterned through
photolithography to thereby form a gate line assembly and a storage
capacitor line assembly. The gate line assembly includes gate lines
22, gate pads 24, and gate electrodes 26. The storage capacitor
line assembly includes storage capacitor electrode patterns 28, and
storage capacitor electrode lines 29.
[0127] Thereafter, as shown in FIGS. 11A and 11B, a gate insulating
layer 30 based on an insulating material such as silicon nitride is
deposited onto the insulating substrate 10 such that it covers the
gate line assembly and the storage capacitor line assembly.
[0128] An amorphous silicon layer and a conductive type
impurities-doped amorphous silicon layer are sequentially deposited
onto the gate insulating layer 30, and patterned through
photolithography to thereby form a semiconductor pattern 42 and an
ohmic contact pattern 52.
[0129] As shown in FIGS. 12A and 12B, a metallic layer is deposited
onto the entire surface of the substrate 10, and patterned through
photolithography to thereby form a data line assembly, and storage
capacitor conductive patterns 68. The data line assembly includes
data lines 62, data pads 64, source electrodes 65, and drain
electrodes 66. The storage capacitor conductive patterns 68 are
overlapped with the storage capacitor electrode patterns 28.
[0130] The ohmic contact pattern 52 is etched using the source
electrode 65 and the drain electrode 66 as a mask to thereby
separate it into a first portion 55 contacting the source electrode
65, and a second portion 56 contacting the drain electrode 66.
[0131] As shown in FIGS. 13A and 13B, a passivation layer 70 is
formed on the entire surface of the substrate 10 having the data
line assembly, the storage capacitor conductive patterns 68 and the
semiconductor pattern 42 with silicon nitride or silicon oxide. The
passivation layer 70 and the gate insulating layer 30 are patterned
through photolithography to there by form first to fourth contact
holes 72, 74, 76 and 78. The first contact holes 72, the second
contact holes 74 and the fourth contact holes 78 are formed at the
passivation layer 70 while exposing the drain electrodes 66, the
data pads 64 and the storage capacitor conductive patterns 68,
respectively. Furthermore, the third contact holes 76 are formed at
the passivation layer 70 and the gate insulating layer 30 while
exposing the gate pads 24.
[0132] As shown in FIGS. 8 and 9, a transparent conductive layer
based on ITO or IZO is deposited onto the entire surface of the
substrate 10.
[0133] The transparent conductive layer is patterned through
photolithography to thereby form pixel electrodes 82, subsidiary
data pads 84, and subsidiary gate pads 86. The pixel electrodes 82
are connected to the drain electrodes 66 and the storage capacitor
conductive patterns 68 through the first and the fourth contact
holes 72 and 78. The subsidiary data and gate pads 84 and 86 are
connected to the data and gate pads 64 and 24 through the second
and the third contact holes 74 and 76.
[0134] In this preferred embodiment, the storage capacitor
conductive patterns 68 are placed at the pixel regions between the
neighboring gate lines while bearing an island shape.
Alternatively, the storage capacitor conductive patterns 68 may be
formed at the periphery of the pixel regions while bearing a bar
shape. In this case, the storage capacitor electrode patterns 28
for forming storage capacitors in association with the storage
capacitor conductive patterns 68 are also formed with a bar
shape.
[0135] FIG. 14 is a plan view of a thin film transistor array panel
according to a third preferred embodiment of the present invention,
and FIG. 15 is a cross sectional view of the thin film transistor
array panel taken along the XV-XV' line of FIG. 14.
[0136] In this preferred embodiment, the storage capacitor
electrode patterns 28 are placed at both peripheral sides of the
pixel regions while bearing a bar shape. Of course, the respective
storage capacitor electrode patterns 28 are connected to the
storage capacitor electrode lines 29.
[0137] The storage capacitor conductive patterns 68 for forming
storage capacitors in association with the storage capacitor
electrode patterns 28 are overlapped with the storage capacitor
electrode patterns 28 while interposing the gate insulating layer
30.
[0138] The fourth contact holes 78 through which the storage
capacitor conductive patterns 68 are connected to the pixel
electrodes 82 are established to partially expose the storage
capacitor conductive patterns 68.
[0139] In this structure, the storage capacitor electrode lines 29
form storage capacitors in association with the pixel electrodes 82
while interposing the gate insulating layer 30 and the passivation
layer 70. Furthermore, the storage capacitor electrode patterns 28
form storage capacitors in association with the storage capacitor
conductive patterns 68 while interposing the gate insulating layer
30.
[0140] With such a structure, the electrostatic capacitance of the
resulting storage capacitors becomes increased even with the same
overlapping area compared to the case where the storage capacitor
electrode patterns 28 are overlapped with only the pixel electrodes
82. Consequently, the aperture ratio with respect to the storage
capacity becomes enhanced.
[0141] Furthermore, as the bar-shaped storage capacitor electrode
patterns 28 or storage capacitor conductive patterns 68 are placed
between the pixel electrodes 82 and the data lines 62, leakage of
light between the pixel electrodes 82 and the data lines 62 can be
prevented.
[0142] In the second and third preferred embodiments of the present
invention, the storage capacitor line assembly is formed in a
separate manner. Alternatively, parts of the gate lines may be
utilized as the storage capacitor electrodes.
[0143] FIG. 16 is a plan view of a thin film transistor array panel
according to a fourth preferred embodiment of the present
invention, and FIG. 17 is a cross sectional view of the thin film
transistor array panel taken along the XVII-XVII' line of FIG.
16.
[0144] In this preferred embodiment, the pixel electrodes arranged
at any one gate line are overlapped with parts of the previous gate
line to form storage capacitors. That is, parts of the gate lines
are used to form the desired storage capacitors without forming a
storage capacitor line assembly in a separate manner.
[0145] As shown in FIG. 16, the pixel electrodes 82 at the nth gate
line 22 (Gn) are overlapped with the (n-1)th gate line 22 (Gn-1)
while being extended in its area.
[0146] The storage capacitor conductive patterns 68 are partially
overlapped with the gate lines 22 while interposing the gate
insulating layer 30. The storage capacitor conductive patterns 68
are placed at the same plane as the data line assembly. The fourth
contact holes 78 exposing the storage capacitor conductive patterns
68 are formed at the passivation layer 70, and the pixel electrodes
82 at any one gate line 22 are connected to the storage capacitor
conductive patterns 68 placed over the previous gate line 22
through the fourth contact holes 78.
[0147] The storage capacitor conductive patterns 68 are overlapped
with the gate lines 22 while interposing the gate insulating layer
30 to thereby form storage capacitors. The storage capacitor
conductive patterns 68 placed over the (n-1)th gate line 22 (Gn-1)
receive the relevant signals from the pixel electrodes 82 at the
nth gate line 22 (Gn).
[0148] In the above structure, the storage capacity becomes
significantly increased compared to the case where the storage
capacitors are formed only through overlapping the pixel electrodes
82 with the gate lines 22. Furthermore, as a separate storage
capacitor line assembly is not needed, the aperture ratio can be
further enhanced.
[0149] FIG. 18 is a plan view of a thin film transistor array panel
according to a fifth preferred embodiment of the present invention,
and FIG. 19 is a cross sectional view of the thin film transistor
array panel taken along the XIX-XIX' line of FIG. 18.
[0150] A gate line assembly and storage capacitor electrode lines
27 are formed on an insulating substrate 10 with a conductive
material such as aluminum, aluminum alloy, chrome, chrome alloy,
molybdenum, molybdenum alloy, chrome nitride, and molybdenum
nitride while bearing a thickness of 1000-3500 .ANG..
[0151] The gate line assembly includes gate lines 22 proceeding in
the horizontal direction, gate pads 24 formed at the one-sided end
portions of the gate lines 22 while electrically contacting
external driving circuits (not shown), and gate electrodes 26 being
parts of the gate lines 22 while forming thin film transistors with
other electrode components.
[0152] The storage capacitor electrode lines 27 are placed between
the neighboring gate lines 22 while proceeding in the horizontal
direction parallel to the gate lines 22.
[0153] The gate line assembly and the storage capacitor electrode
lines 27 may have a multiple-layered structure where at least one
layer is formed with a low resistance metallic material.
[0154] A gate insulating layer 30 with a thickness of 2500-4500
.ANG. is formed on the insulating substrate 10 with silicon nitride
or silicon oxide while covering the gate line assembly and the
storage capacitor electrode lines 27.
[0155] First contact holes 32 are formed at the gate insulating
layer 30 while exposing the storage capacitor electrode lines
27.
[0156] A semiconductor pattern 42 with a thickness of 800-1500
.ANG. is formed on the gate insulating layer 30 with amorphous
silicon while being overlapped with the gate electrodes 26. Ohmic
contact patterns 55 and 56 with a thickness of 500-800 .ANG. are
formed on the semiconductor pattern 42 with amorphous silicon where
n type impurities are doped at high concentration.
[0157] A data line assembly and storage capacitor conductive
patterns 67 are formed on the ohmic contact patterns 55 and 56 and
the gate insulating layer 30 with a conductive material such as
aluminum, aluminum alloy, chrome, chrome alloy, molybdenum,
molybdenum alloy, chrome nitride and molybdenum nitride while
bearing a thickness of 500-3500 .ANG..
[0158] The data line assembly includes data lines 62 proceeding in
the vertical direction while crossing over the gate lines 22 to
define pixel regions, data pads 64 connected to the one-sided ends
of the data lines 62 while electrically contacting external driving
circuits, source electrodes 65 protruded from the data lines 62
while being extended over the ohmic contact pattern 55, and drain
electrodes 66 facing the source electrodes 65 while being placed
over the over ohmic contact pattern 56. The drain electrodes 66 are
extended over the gate insulating layer 30 within the pixel
regions.
[0159] The storage capacity conductive patterns 67 are placed at
the same plane as the data line assembly while being connected to
the storage capacitor electrode lines 27 through the first contact
holes 32. The storage capacitor conductive patterns 67 are
overlapped with pixel electrodes 82 to be described later to
thereby form storage capacitors. The storage capacitor conductive
patterns 67 are connected to the storage capacitor electrode lines
27 to receive common voltages.
[0160] The data line assembly and the storage capacitor conductive
patterns 67 may have a multiple-layered structure where at least
one layer is formed with a low resistance metallic material.
[0161] A passivation layer 70 covers the data line assembly, the
storage capacitor conductive patterns 67 and the semiconductor
pattern 42 while bearing a thickness of 500-2000 .ANG.. The
passivation layer 70 is formed with an insulating material such as
silicon nitride and silicon oxide.
[0162] Second and third contact holes 72 and 74 are formed at the
passivation layer 70 while exposing the drain electrodes 66, and
the data pads 64. Fourth contact holes 76 are further formed at the
passivation layer 70 while exposing the gate pads 24 together with
the gate insulating layer 30.
[0163] Pixel electrodes 82 are formed on the passivation layer 70
such that they are electrically connected to the drain electrodes
66 through the second contact holes 72.
[0164] Subsidiary data pads 84 and subsidiary gate pads 86 are
formed on the passivation layer 70 while being connected to the
data pads 64 and the gate pads 24 through the third and the fourth
contact holes 74 and 76.
[0165] The pixel electrodes 82, the subsidiary data pads 84 and the
subsidiary gate pads 86 are formed with a transparent conductive
material such as ITO and IZO.
[0166] The pixel electrodes 82 are overlapped with the storage
capacitor electrode lines 27 while interposing the passivation
layer 70 and the gate insulating layer 30 to thereby form storage
capacitors.
[0167] The pixel electrodes 82 are also overlapped with the storage
capacitor conductive patterns 67 connected to the storage capacitor
electrode lines 27 while interposing the passivation layer 70 to
thereby form other storage capacitors. In this case, as the
thickness of the passivation layer 70 disposed between the pixel
electrodes 82 and the storage capacitor conductive patterns 67 is
small, the electrostatic capacitance of the resulting storage
capacitors becomes increased even with the same overlapping area
compared to the overlapping of the storage capacitor electrode
lines 27 and the pixel electrodes 82. Consequently, the aperture
ratio with respect to the storage capacity becomes enhanced.
[0168] A method of fabricating the thin film transistor array panel
will be now explained with reference to FIGS. 20A to 24B as well as
FIGS. 18 and 19.
[0169] As shown in FIGS. 20A and 20B, a metallic layer is deposited
onto an insulating substrate 10, and patterned through
photolithography to thereby form a gate line assembly and storage
capacitor electrode lines 27. The gate line assembly includes gate
lines 22, gate pads 24, and gate electrodes 26.
[0170] Thereafter, as shown in FIGS. 21A and 21B, a gate insulating
layer 30 based on an insulating material such as silicon nitride is
deposited onto the insulating substrate 10 such that it covers the
gate line assembly and the storage capacitor electrode lines 27.
Subsequently, an amorphous silicon layer 40 and a conductive type
impurities-doped amorphous silicon layer 50 are sequentially
deposited onto the gate insulating layer 30.
[0171] Thereafter, the amorphous silicon layer 40, the
impurities-doped amorphous silicon layer 50 and the gate insulating
layer 30 are patterned through photolithography to thereby form
first contact holes 32 exposing the storage capacitor electrode
lines 27.
[0172] As shown in FIGS. 22A and 22B, the amorphous silicon layer
40 and the impurities-doped amorphous silicon layer 50 patterned
through photolithography to thereby form a semiconductor pattern 42
and an ohmic contact pattern 52.
[0173] As shown in FIGS. 23A and 23B, a metallic layer is deposited
onto the entire surface of the substrate 10, and patterned through
photolithography to thereby form a data line assembly, and storage
capacitor conductive patterns 67. The data line assembly includes
data lines 62, data pads 64, source electrodes 65, and drain
electrodes 66. The storage capacitor conductive patterns 67 are
connected to the storage capacitor electrode lines 27 through the
first contact holes 32.
[0174] The ohmic contact pattern 52 is etched using the source
electrode 65 and the drain electrode 66 as a mask to thereby
separate it into a first portion 55 contacting the source electrode
65, and a second portion 56 contacting the drain electrode 66.
[0175] As shown in FIGS. 24A and 24B, a passivation layer 70 is
formed on the entire surface of the substrate 10 having the data
line assembly, the storage capacitor conductive patterns 67 and the
semiconductor pattern 42 with silicon nitride or silicon oxide. The
passivation layer 70 and the gate insulating layer 30 are patterned
through photolithography to thereby form second to fourth contact
holes 72, 74 and 76. The second and the third contact holes 72 and
74 are formed at the passivation layer 70 while exposing the drain
electrodes 66, and the data pads 64. The fourth contact holes 76
are formed at the passivation layer 70 and the gate insulating
layer 30 while exposing the gate pads 24.
[0176] As shown in FIGS. 18 and 19, a transparent conductive layer
based on ITO or IZO is deposited onto the entire surface of the
substrate 10.
[0177] The transparent conductive layer is patterned through
photolithography to thereby form pixel electrodes 82, subsidiary
data pads 84, and subsidiary gate pads 86. The pixel electrodes 82
are connected to the drain electrodes 66 through the second contact
holes 72. The subsidiary data and gate pads 84 and 86 are connected
to the data and gate pads 64 and 24 through the third and the
fourth contact holes 74 and 76.
[0178] In this preferred embodiment, the storage capacitor
conductive patterns 67 are placed at the pixel regions between the
neighboring gate lines. Alternatively, the storage capacitor
conductive patterns 67 may be formed at the periphery of the pixel
regions while bearing a bar shape.
[0179] FIG. 25 is a plan view of a thin film transistor array panel
according to a sixth preferred embodiment of the present invention,
and FIG. 26 is a cross sectional view of the thin film transistor
array panel taken along the XXVI-XXVI' line of FIG. 25.
[0180] In this preferred embodiment, the storage capacitor
conductive patterns 67 are place at both peripheral sides of the
pixel regions while bearing a bar shape. The storage capacitor
conductive patterns 67 are connected to the storage capacitor
electrode lines 27 through the first contact holes 32 formed at the
gate insulating layer 30.
[0181] The storage capacitor electrode lines 27 form storage
capacitors in association with the pixel electrodes 82 while
interposing the gate insulating layer 30 and the passivation layer
70. Furthermore, the storage capacitor conductive patterns 67 form
other storage capacitors in association with the pixel electrodes
82 while interposing the passivation layer 70.
[0182] With such a structure, the electrostatic capacitance of the
storage capacitors becomes increased even with the same overlapping
area compared to the case where only the storage capacitor
electrode lines 27 are overlapped with the pixel electrodes 82.
Consequently, the aperture ratio with respect to the storage
capacity becomes enhanced.
[0183] Furthermore, as the bar-shaped storage capacitor conductive
patterns 67 are placed between the pixel electrodes 82 and the data
lines 62, leakage of light between the pixel electrodes 82 and the
data lines 62 can be prevented.
[0184] In the fifth and sixth preferred embodiments of the present
invention, the storage capacitor line assembly is formed in a
separate manner. Alternatively, parts of the gate lines may be
utilized as the storage capacitor electrodes.
[0185] FIG. 27 is a plan view of a thin film transistor array panel
according to a seventh preferred embodiment of the present
invention, and FIG. 28 is a cross sectional view of the thin film
transistor array panel taken along the XXVIII-XXVIII' line of FIG.
27.
[0186] In this preferred embodiment, the pixel electrodes arranged
at any one gate line are overlapped with parts of the previous gate
line to form storage capacitors. That is, parts of the gate lines
are used to form the desired storage capacitors without forming a
storage capacitor line assembly in a separate manner.
[0187] As shown in FIG. 27, the pixel electrodes 82 at the nth gate
line 22 (Gn) are overlapped with the (n-1)th gate line 22 (Gn-1)
while being extended in its area.
[0188] The storage capacitor conductive patterns 67 are partially
overlapped with the gate lines 22 while interposing the gate
insulating layer 30. The storage capacitor conductive patterns 67
are placed at the same plane as the data line assembly. The fourth
contact holes 78 exposing the storage capacitor conductive patterns
67 are formed at the passivation layer 70. The storage capacitor
conductive patterns 67 placed over the (n-1)th gate line 22 (Gn-1)
are connected to the pixel electrodes 82 at the nth gate line 22
(Gn).
[0189] The storage capacitor conductive patterns 67 are overlapped
with the gate lines 22 while interposing the gate insulating layer
30 to thereby form storage capacitors. The storage capacitor
conductive patterns 68 placed over the (n-1)th gate line 22 (Gn-1)
receive the relevant signals from the pixel electrodes 82 at the
nth gate line 22 (Gn).
[0190] In the above structure, the storage capacity becomes
significantly increased compared to the case where the storage
capacitors are formed only through overlapping the pixel electrodes
82 with the gate lines 22. Furthermore, as a separate storage
capacitor line assembly is not needed, the aperture ratio can be
further enhanced.
[0191] The inventive structure may be well adapted to use with all
of the liquid crystal display modes. Particularly, in case such a
structure is employed for use with the optically compensated
birefringence (OCB) mode, various advantages are resulted.
[0192] As the .DELTA. .epsilon. value of the liquid crystal is
great with the OCB mode liquid crystal display, the difference
between the dielectric constant at the initial state and the
dielectric constant at the succeeding state as a function of the
gray values is also great, and therefore, variation in the liquid
crystal voltage is inevitably made to a large scale.
[0193] Meanwhile, as shown in FIG. 29, the waveform
(lime-brightness) curve of the response speed measured with all of
the liquid crystal display modes bears a two-stepped waveform
exhibiting two stepped differences.
[0194] As the response speed is measured while altering the total
brightness from 10% to 90%, it turns out to be slower in case the
brightness at the two-stepped portion is less than 90%.
[0195] The OCB mode liquid crystal display exhibits a
characteristic in that the two-stepped waveform occurs at the first
frame, and a normal brightness is maintained at the second frame or
the third frame. Therefore, in case the electrostatic capacitance
at the two-stepped portion is increased to be 90% or more,
particularly 95% or more, the desired normal brightness can be
maintained at the first frame, thereby making rapid response
speed.
[0196] Table 1 lists the brightness values at the two-stepped
portion over the waveform (time-brightness) curve of the response
speed as a function of the ratio of the electrostatic capacitance
Cst of the storage capacitors to the electrostatic capacitance Clc
of the liquid crystal in the OCB mode liquid crystal display.
TABLE-US-00001 TABLE 1 Clc:Cst 1.00:0.70 1.00:0.91 Two-stepped
portion (brightness %) 81.8% 87.3%
[0197] It can be known from Table 1 that as the storage capacity
Cst is increased, the brightness at the two-stepped portion is
approximated to 90%. Therefore, the rapid response speed can be
obtained through increasing the storage capacity such that the
brightness at the two-stepped portion goes over 90%. Particularly,
in case the storage capacity is increased such that the brightness
at the two-stepped portion goes over 95%, the response speed can be
further enhanced. In order to increase the storage capacity to such
a degree, the storage capacitors according to the first to seventh
preferred embodiments may be applied for use in the OCB mode liquid
crystal display. That is, the storage capacitor electrode lines are
formed at the same plane as the data line assembly such that they
are overlapped with the pixel electrodes while interposing only the
passivation layer. In this structure, the storage capacity as well
as the aperture ratio are significantly enhanced without enlarging
the area of the storage capacitor electrode lines, compared to the
case where the storage capacitor electrode lines are formed at the
same plan as the gate line assembly such that they are overlapped
with the pixel electrodes while interposing the passivation layer
and the gate insulating layer. As only one of the passivation layer
and the gate insulating layer is disposed between the storage
capacitor electrodes, it is not needed to enlarge the area of the
storage capacitor electrode components. Consequently, the storage
capacity can be increased without decreasing the aperture
ratio.
[0198] As described above, with the inventive structure, the
storage capacity can be increased without decreasing the aperture
ratio while enhancing the response speed.
[0199] While the present invention has been described in detail
with reference to the preferred embodiments, those skilled in the
art will appreciate that various modifications and substitutions
can be made thereto without departing from the spirit and scope of
the present invention as set forth in the appended claims.
* * * * *