U.S. patent application number 11/613548 was filed with the patent office on 2007-07-26 for semiconductor storage device.
This patent application is currently assigned to MegaChips LSI Solutions Inc.. Invention is credited to Kumiko Mito, Takashi Oshikiri.
Application Number | 20070171737 11/613548 |
Document ID | / |
Family ID | 38015286 |
Filed Date | 2007-07-26 |
United States Patent
Application |
20070171737 |
Kind Code |
A1 |
Mito; Kumiko ; et
al. |
July 26, 2007 |
SEMICONDUCTOR STORAGE DEVICE
Abstract
The present invention provides a semiconductor storage device
that requires no specialized circuit or the like for reading
redundancy data from a redundancy region, and that is capable of
freely changing the arrangement of the redundancy region in the
memory array area. A semiconductor storage device of the present
invention includes a memory array configured as shown below. The
memory array includes a user region which is composed of given page
units and where user data is stored, and a redundancy region which
is composed of the same given page units and where redundancy data
is stored. The area in the memory array can be used either as the
user region or as the redundancy region.
Inventors: |
Mito; Kumiko; (Osaka,
JP) ; Oshikiri; Takashi; (Osaka, JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Assignee: |
MegaChips LSI Solutions
Inc.
Osaka-shi
JP
|
Family ID: |
38015286 |
Appl. No.: |
11/613548 |
Filed: |
December 20, 2006 |
Current U.S.
Class: |
365/200 ;
711/E12.008; 714/E11.049 |
Current CPC
Class: |
G06F 11/1048 20130101;
G06F 11/1076 20130101; G06F 12/0246 20130101 |
Class at
Publication: |
365/200 |
International
Class: |
G11C 29/00 20060101
G11C029/00; G11C 7/00 20060101 G11C007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 20, 2006 |
JP |
2006-012211 |
Claims
1. A semiconductor storage device comprising a memory array, said
memory array comprising: a user region where user data is stored;
and a redundancy region where redundancy data is stored, wherein
said user region and said redundancy region are each formed of
given page units, so that an area in said memory array can be used
either as said user region or as said redundancy region.
2. The semiconductor storage device according to claim 1, further
comprising: an I/O portion that receives, from outside, a read
command that contains information about a user address indicating
an address in said user region where a specified piece of said user
data is stored, and information about a redundancy address
indicating an address in said redundancy region where a piece of
said redundancy data that corresponds to said specified piece of
user data is stored; and a controller that reads said specified
piece of user data from said user region on the basis of said
information about said user address, and that reads said piece of
redundancy data that corresponds to said specified piece of user
data from said redundancy region on the basis of said information
about said redundancy address.
3. The semiconductor storage device according to claim 2, wherein
said information about said redundancy address is an address value
or an index value used in relative addressing, said semiconductor
storage device further comprises a redundancy address offset
register that is capable of setting an offset value, and said
controller reads said specified piece of redundancy data from said
redundancy region on the basis of said address value or said index
value and said offset value set in said redundancy address offset
register.
4. The semiconductor storage device according to claim 3, wherein
said redundancy address offset register is capable of setting said
offset value through an operation of external equipment.
5. The semiconductor storage device according to claim 2, wherein
said information about said redundancy address indicates a
variation from a previous address, and said controller specifies a
current address on the basis of the variation from said previous
address and reads said piece of redundancy data that corresponds to
said specified piece of user data from said redundancy region on
the basis of the specified current address.
6. The semiconductor storage device according to claim 2, wherein
said information about said redundancy address indicates a given
expression for calculation, and said controller specifies the
address on the basis of said given expression for calculation and
reads said piece of redundancy data that corresponds to said
specified piece of user data from said redundancy region on the
basis of the specified address.
7. The semiconductor storage device according to claim 1, further
comprising a redundancy data storing register capable of
temporarily storing said redundancy data read from said redundancy
region.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to semiconductor storage
devices, and particularly to a semiconductor storage device that
has a user region and a redundancy region.
[0003] 2. Description of the Background Art
[0004] In a semiconductor storage device having a nonvolatile
memory (hereinafter referred to as a memory array) that contains
faulty bits, the memory array includes a user region and a
redundancy region. The user region is a region where user data is
stored, and the redundancy region is a region where redundancy data
is stored, such as error-correcting code, fault map, etc. For
example, Japanese Patent Application Laid-Open No. 8-235028(1996)
(hereinafter referred to as Patent Document 1) discloses a memory
array configuration having a user region and a redundancy
region.
[0005] In the memory array of Patent Document 1, each page includes
a pair of a user region and a redundancy region. The redundancy
region is provided as a region that is added to the user region.
Each redundancy region functions for correction etc. of the user
region that forms a pair with that redundancy region. The capacity
of the redundancy region is much smaller than the capacity of the
user region.
[0006] The memory array configuration of Patent Document 1 may
require specialized circuitry for reading redundancy data from the
redundancy regions. However, separately providing such specialized
circuitry leads to increased manufacturing costs. It also requires
extra tests for testing the specialized circuitry, which
complicates the process of testing the semiconductor storage
device.
[0007] Also, in the memory array configuration of Patent Document
1, the areas of the memory that are used as redundancy regions can
function only to store redundancy data, and the areas of the memory
that are used as user regions can function only to store user
data.
[0008] That is, the memory areas serving as redundancy regions
cannot be used as user regions, and the memory areas serving as
user regions cannot be used as redundancy regions. It is therefore
impossible to locate the redundancy regions in appropriate
positions according to variations among individual memory
arrays.
SUMMARY OF THE INVENTION
[0009] An object of the present invention is to provide a
semiconductor storage device that requires no specialized circuit
or the like for reading redundancy data from a redundancy region,
and that is capable of freely changing the arrangement of the
redundancy region in the memory array area.
[0010] According to a first aspect of the invention, a
semiconductor storage device includes a memory array, and the
memory array includes a user region where user data is stored, and
a redundancy region where redundancy data is stored. The user
region and the redundancy region are each composed of given page
units, so that an area in the memory array can be used either as
the user region or as the redundancy region.
[0011] Accordingly, it is not necessary to provide a specialized
circuit for reading the redundancy data from the redundancy region.
This reduces the manufacturing costs and eliminates the need for
more complicated test process. Also, the configuration described
above allows the position of the redundancy region to be freely
changed in the memory array.
[0012] According to a second aspect of the invention, the
semiconductor storage device of the first aspect includes an I/O
portion and a controller. The I/O portion receives a read command
from outside. The read command contains information about a user
address indicating an address in the user region where a specified
piece of the user data is stored, and information about a
redundancy address indicating an address in the redundancy region
where a piece of the redundancy data that corresponds to the
specified piece of user data is stored. The controller reads the
specified piece of user data from the user region on the basis of
the information about the user address. Also, the controller reads
the piece of redundancy data that corresponds to the specified
piece of user data from the redundancy region on the basis of the
information about the redundancy address.
[0013] Thus, it is possible to read specified user data and the
corresponding redundancy data on the basis of the single read
command, from the memory array having the configuration of the
first aspect. That is, it is possible to enhance the speed of the
operation of reading specified user data and the corresponding
redundancy data.
[0014] According to a third aspect of the invention, in the
semiconductor storage device of the second aspect, the information
about the redundancy address is an address value or an index value
used in relative addressing. The semiconductor storage device
further includes a redundancy address offset register that is
capable of setting an offset value. The controller reads the
specified piece of redundancy data from the redundancy region on
the basis of the address value or the index value and the offset
value set in the redundancy address offset register.
[0015] Thus, it is possible to read specified redundancy data by
relative addressing, from the memory array having the configuration
of the first aspect.
[0016] According to a fourth aspect of the invention, in the
semiconductor storage device of the third aspect, the redundancy
address offset register is capable of setting the offset value
through an operation of external equipment.
[0017] Thus, it is possible to freely change the starting address
of the redundancy region through an operation of external
equipment. That is, it is possible to freely change the position of
the redundancy region in the memory array through an external
operation.
[0018] According to a fifth aspect of the invention, in the
semiconductor storage device of the second aspect, the information
about the redundancy address indicates a variation from the
previous address. The controller specifies the current address on
the basis of the variation from the previous address. Then, the
controller reads the piece of redundancy data that corresponds to
the specified piece of user data from the redundancy region on the
basis of the specified current address.
[0019] Thus, it is possible to read specified redundancy data on
the basis of the amount of variation from the previous address,
from the memory array having the configuration of the second
aspect.
[0020] According to a sixth aspect of the invention, in the
semiconductor storage device of the second aspect, the information
about the redundancy address indicates a given expression for
calculation. The controller specifies the address on the basis of
the given expression for calculation. The controller then reads the
piece of redundancy data that corresponds to the specified piece of
user data from the redundancy region on the basis of the specified
address.
[0021] Thus, it is possible to read specified redundancy data on
the basis of the given expression for calculation, from the memory
array having the configuration of the second aspect.
[0022] According to a seventh aspect of the invention, the
semiconductor storage device of the first aspect further includes a
redundancy data storing register capable of temporarily storing
redundancy data read from the redundancy region.
[0023] This allows variations of the sequence of operations of
reading redundancy data.
[0024] These and other objects, features, aspects and advantages of
the present invention will become more apparent from the following
detailed description of the present invention when taken in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a block diagram illustrating the configuration of
the semiconductor storage device according to the present
invention;
[0026] FIG. 2 is a diagram illustrating the configuration of the
memory array of the invention;
[0027] FIG. 3 is a timing chart illustrating an operation of
reading specified user data and corresponding redundancy data;
[0028] FIG. 4 is a diagram showing the structure of a read
command;
[0029] FIG. 5 is a timing chart illustrating another example of the
operation of reading specified user data and corresponding
redundancy data; and
[0030] FIG. 6 is a block diagram showing another example of the
configuration of the semiconductor storage device of the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0031] The present invention will now be specifically described
referring to the diagrams illustrating the preferred
embodiments.
[0032] <Configuration of the Semiconductor Storage
Device>
[0033] FIG. 1 is a block diagram showing the configuration of a
semiconductor storage device and external equipment (hereinafter
referred to as a host system) according to the invention.
[0034] As shown in FIG. 1, the semiconductor storage device 100
includes a memory array (a nonvolatile memory such as Flash EEPROM,
for example) 10, an I/O portion 20, a controller 30, and a
redundancy address offset register 40. A host system 200 is
provided externally to the semiconductor storage device 100, and
the host system 200 and the semiconductor storage device 100 send
and receive data, commands, etc. to and from each other.
[0035] The I/O portion 20 sends out data and the like stored in the
memory array 10 to the host system 200. The I/O portion 20 receives
commands sent from the host system 200. The data and commands are
transmitted in a time-division manner through a bus between the
semiconductor storage device 100 and the host system 200.
[0036] The host system 200 sends a chip select signal (csb) and a
clock signal (clock) to the controller 30 through the I/O portion
20. The controller 30 sends to the memory array 10 a chip select
signal (memcsb) for the memory array 10 and a clock signal
(memclock) for the memory array 10.
[0037] <Configuration of the Memory Array>
[0038] The controller 30 controls individual circuits in the
semiconductor storage device 100. The redundancy address offset
register 40 is used to set an offset value. In the redundancy
address offset register 40, a given offset value is set, e.g.,
through an operation of the host system 200, as a starting address
of a redundancy region 2 described later (see FIG. 2).
[0039] FIG. 2 is a diagram schematically showing the structure of
the memory array 10.
[0040] As shown in FIG. 2, the memory array 10 of the invention,
containing faulty bits, includes a user region (the area with no
pattern) 1 and a redundancy region (the hatched area) 2. The user
region 1 is a region where user data is stored, and the redundancy
region 2 is a region where information about the user region is
stored, such as error-correcting code, fault map, etc. (the
information can be regarded as redundancy data, and it is
hereinafter referred to as redundancy data).
[0041] The user region 1 and the redundancy region 2 are both
composed of, and managed as, given page units. That is, the memory
array is configured such that (user region 1, redundancy region
2)=(given page unit).times.n (an integer). As can be seen from FIG.
2, the given page units forming the user region 1 and the
redundancy region 2 have the same data capacities (for example, a
given page unit (one page) of FIG. 2 is formed of 512 bytes, but
the number of bytes can be arbitrarily changed and "512 bytes" is
shown by way of example and not of limitation).
[0042] <Operation of the Semiconductor Storage Device
(Specifically, an Operation of Reading Data from the Memory
Array)>
[0043] Next, the operation of the semiconductor storage device 100
of the invention will be described referring to FIGS. 1, 2 and 3
(more specifically, an operation of reading specified user data and
redundancy data that corresponds to the specified user data from
the memory array 10 will be described).
[0044] FIG. 3 is a timing chart illustrating an operation of
reading specified user data and redundancy data that corresponds to
the specified user data from the memory array 10. The timing chart
of FIG. 3 is shown by way of illustration and not of limitation,
and another example of a timing chart will be shown later. The
description below illustrates an example of operation in which the
redundancy data is read according to a relative addressing
scheme.
[0045] The host system 200 sends an "enable" chip select signal
(csb) and a given-cycle clock signal (clock) to the controller 30,
and the controller 30 sends an "enable" chip select signal (memcsb)
and a given clock signal (memclock) to the memory array 10.
[0046] In this condition, as shown in FIG. 3, the host system 200
sends a read command, structured as shown in FIG. 4, for example,
to the semiconductor storage device 100 (more specifically, to the
controller 30 through the I/O portion 20).
[0047] As shown in FIG. 4, the read command, for reading data,
includes an ID, a user-data page address (which can be regarded as
information about the user address), and a redundancy address
(which can be regarded as information about the redundancy
address).
[0048] Now, the ID includes ID information. The user-data page
address includes information about the page address in the user
region 1 where the specified user data is stored. The redundancy
address includes information about the redundancy address in the
redundancy region 2 where the redundancy data corresponding to the
specified user data is stored.
[0049] It is assumed here that the redundancy address is a relative
address. However, needless to say, the redundancy address may be an
absolute address. That is, the scheme of addressing may be relative
addressing (Scheme A) as described herein, or may be absolute
addressing (Scheme B).
[0050] The addressing may adopt an addressing scheme (Scheme C) in
which the current address is specified on the basis of the amount
of variation from the previous address (which can be regarded as
information about the redundancy address), or an addressing scheme
(Scheme D) in which the controller 30 specifies the address on the
basis of a given expression for calculation (which can be regarded
as information about the redundancy address). The expression for
calculation can be set from the host system 200.
[0051] In the Schemes A and C, the command argument (i.e., the
information about the redundancy address shown in FIG. 4) may be an
address value or an index value. In the Scheme D, the command
argument is an index value.
[0052] Now, the controller 30 receives the read command structured
as shown in FIG. 4, and reads one page (e.g., 512 bytes) of user
data (see memdata of FIG. 3) from the user region 1 of the memory
array 10, on the basis of the page address of the read command
(which can be regarded as the user address of memadrs of FIG.
3).
[0053] During this process, the user data is read out after a given
latency time has passed after the controller 30 outputted the user
address to the memory array 10. The user data is thus read from the
memory array 10 and then sent directly to the host system 200 (see
FIG. 3).
[0054] The controller 30 also obtains the absolute address where
the specified redundancy data is stored (which can be regarded as
the redundancy absolute address shown in FIG. 3) on the basis of
the offset value previously set in the redundancy address offset
register 40 and the redundancy address (relative address) in the
read command.
[0055] In the redundancy address offset register 40, a given offset
value is set as the starting address of the redundancy region 2 as
described later, e.g., through an operation of the host system 200.
More specifically, the controller 30 receives a given command sent
from the host system 200 and sets the offset value on the basis of
the command.
[0056] The redundancy absolute address is thus derived, and the
user data has been read out, and then the controller 30 reads the
redundancy data (see memdata of FIG. 3) that corresponds to the
user data, from the redundancy region 2 of the memory array 10 on
the basis of the redundancy absolute address (see the redundancy
absolute address of memadrs of FIG. 3).
[0057] The specified redundancy data is read out after a given
latency time has passed after the controller 30 outputted the
redundancy absolute address to the memory array 10. The redundancy
data is thus read and then sent directly to the host system 200
(see FIG. 3).
[0058] The memory array 10 of the present invention is composed of,
and managed as, the user region 1 formed of given page units and
the redundancy region 2 formed of the same given page units. That
is, an area formed of given page units in the memory array 10 can
be used either as the user region 1 or as the redundancy region 2.
This offers the effects below.
[0059] That is, the circuitry for reading redundancy data from the
redundancy region 2 can be used also as circuitry for reading user
data from the user region 1. Accordingly, it is not necessary to
provide a specialized circuit for reading redundancy data from the
redundancy region 2, and so the manufacturing costs are not
increased and the process of testing the semiconductor storage
device is not complicated (first effect).
[0060] Also, it is possible to flexibly change the arrangement of
the redundancy region 2 in the memory array 10 according to the
tendency of faults in the memory array 10 (i.e., according to
variations among individual memory arrays 10) (second effect).
[0061] For example, when the memory array 10 is used as OTP
(One-Time Programmable), an error-free area can be set as the
redundancy region 2. This eliminates the need for error correction
of the redundancy region 2, allowing the system to operate at
higher speed.
[0062] Also, the error-correcting scheme can be selected freely,
e.g., according to the tendency of errors in each memory array 10,
which allows optimization of the redundancy region 2.
[0063] Also, in the memory array configured as shown in Patent
Document 1, when the memory array 10 is a perfect memory, for
example, it is impossible to remove the redundancy regions, which
results in a waste of area. However, in the memory array 10
configured according to the present invention, the entire memory
array area can be set as the user region 1.
[0064] Also, with the memory array configuration of Patent Document
1, the host system may issue a user-data read command and a
redundancy-data read command in order to read specified user data
and the corresponding redundancy data.
[0065] On the other hand, in the configuration of the memory array
10 of the invention, specified user data and the corresponding
redundancy data can be read by the issue of a single read command
as shown in FIG. 4. Accordingly, the semiconductor storage device
100 of the invention is capable of performing the reading operation
at higher speed, as compared with the operation of reading user
data and redundancy data with two commands as mentioned in the
preceding paragraph.
[0066] Also, when the redundancy address in the read command is an
address value or an index value used in relative addressing and the
semiconductor storage device 100 includes the redundancy address
offset register 40 capable of setting an offset value, it is then
possible to read the specified redundancy data according to a
relative addressing scheme under control by the controller 30.
[0067] The redundancy address offset register 40 is capable of
setting the offset value through an operation of the external
equipment (the host system 200). The starting address of the
redundancy region can thus be freely changed through an operation
of the external equipment. That is, the position of the redundancy
region in the memory array can be freely changed through an
external operation.
[0068] The data reading timing chart of FIG. 3 is shown by way of
example, and specified user data and the corresponding redundancy
data may be read according to the timing chart shown in FIG. 5, for
example.
[0069] In the read operation shown in FIG. 5, the redundancy data
corresponding to the specified user data is read from the memory
array 10 first. Then, that redundancy data is temporarily stored in
a redundancy data storing register 50 as provided in the
semiconductor storage device 100 shown in FIG. 6, for example.
Subsequently, the specified user data is read from the memory array
10. The redundancy data stored in the redundancy data storing
register 50 is then outputted to the host system 200 following the
user data (FIG. 5).
[0070] In the example above, the redundancy data that corresponds
to the specified user data is read on the basis of the redundancy
address in the read command shown in FIG. 4.
[0071] However, one page of data that includes the redundancy data
corresponding to the specified user data may be read from the
memory array 10 on the basis of the redundancy address of the
command, in which case only the redundancy data that corresponds to
the specified user data may then be stored in, e.g., the redundancy
data storing register 50 shown in FIG. 6, and the data stored in
the redundancy data storing register 50 is adopted.
[0072] As can be seen from the examples of read operation,
additionally providing the redundancy data storing register 50 as
shown in FIG. 6 allows variations of the sequence of operations of
reading the redundancy data (for example, FIGS. 3 and 5).
[0073] While the invention has been described in detail, the
foregoing description is in all aspects illustrative and not
restrictive. It is understood that numerous other modifications and
variations can be devised without departing from the scope of the
invention.
* * * * *