U.S. patent application number 11/717818 was filed with the patent office on 2007-07-19 for nanotip electrode non-volatile memory resistor cell.
This patent application is currently assigned to Sharp Laboratories of America, Inc.. Invention is credited to Robert A. Barrowcliff, Sheng Teng Hsu, Gregory M. Stecker, Fengyan Zhang.
Application Number | 20070167008 11/717818 |
Document ID | / |
Family ID | 36684465 |
Filed Date | 2007-07-19 |
United States Patent
Application |
20070167008 |
Kind Code |
A1 |
Hsu; Sheng Teng ; et
al. |
July 19, 2007 |
Nanotip electrode non-volatile memory resistor cell
Abstract
A non-volatile memory resistor cell with a nanotip electrode,
and corresponding fabrication method are provided. The method
comprises: forming a first electrode with nanotips; forming a
memory resistor material adjacent the nanotips; and, forming a
second electrode adjacent the memory resistor material, where the
memory resistor material is interposed between the first and second
electrodes. Typically, the nanotips are iridium oxide (IrOx) and
have a tip base size of about 50 nanometers, or less, a tip height
in the range of 5 to 50 nm, and a nanotip density of greater than
100 nanotips per square micrometer. In one aspect, the substrate
material can be silicon, silicon oxide, silicon nitride, or a noble
metal. A metalorganic chemical vapor deposition (MOCVD) process is
used to deposit Ir. The IrOx nanotips are grown from the deposited
Ir.
Inventors: |
Hsu; Sheng Teng; (Camas,
WA) ; Zhang; Fengyan; (Vancouver, WA) ;
Stecker; Gregory M.; (Vancouver, WA) ; Barrowcliff;
Robert A.; (Vancouver, WA) |
Correspondence
Address: |
SHARP LABORATORIES OF AMERICA, INC.;C/O LAW OFFICE OF GERALD MALISZEWSKI
P.O. BOX 270829
SAN DIEGO
CA
92198-2829
US
|
Assignee: |
Sharp Laboratories of America,
Inc.
|
Family ID: |
36684465 |
Appl. No.: |
11/717818 |
Filed: |
March 14, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11039544 |
Jan 19, 2005 |
7208372 |
|
|
11717818 |
Mar 14, 2007 |
|
|
|
Current U.S.
Class: |
438/681 ;
257/E27.071; 257/E45.003 |
Current CPC
Class: |
H01L 45/147 20130101;
H01L 45/1233 20130101; H01L 45/16 20130101; H01L 45/04 20130101;
H01L 27/101 20130101; H01L 45/1675 20130101; H01L 45/1273
20130101 |
Class at
Publication: |
438/681 |
International
Class: |
H01L 21/44 20060101
H01L021/44 |
Claims
1-28. (canceled)
29. A nanotip electrode non-volatile memory resistor cell, the
memory cell comprising: a first electrode with nanotips; memory
resistor material adjacent the nanotips; and a second electrode
adjacent the memory resistor material, where the memory resistor
material is interposed between the first and second electrodes.
30. The memory cell of claim 29 wherein the first electrode
nanotips have a tip base size of about 50 nanometers, or less.
31. The memory cell of claim 29 wherein the first electrode
nanotips have a tip height in the range of 5 to 50 nm.
32. The memory cell of claim 29 wherein the first electrode
nanotips have a nanotip density of greater than 100 nanotips per
square micrometer.
33. The memory cell of claim 29 wherein the first electrode
nanotips are made from iridium oxide (IrOx).
34. The memory cell of claim 33 further comprising: a substrate; a
refractory metal film interposed between the substrate and the
first electrode.
35. The memory cell of claim 29 further comprising: a substrate,
made from a material selected from the group including silicon,
silicon oxide, silicon nitride, and noble metals; and wherein the
first electrode is formed adjacent the substrate.
36. The memory cell of claim 29 wherein the memory resistor
material is a material selected from the group including
Pr.sub.0.3Ca.sub.0.7MnO.sub.3 (PCMO), colossal magnetoresistive
(CMR) film, transition metal oxides, Mott insulators, and
high-temperature super conductor (HTSC) material.
37. The memory cell of claim 29 wherein the first electrode
nanotips have ends; and wherein the memory resistor material has a
thickness, between the first electrode nanotip ends and the second
electrode, in the range of 30 to 200 nm.
38. The memory cell of claim 29 wherein the second electrode is a
material selected from the group including Pt, refractory metals,
refractory metal oxides, refractory metal nitrides, and A1.
39. The memory cell of claim 29 wherein the memory resistor
material is adjacent to the nanotips in a relationship selected
from the group including on the nanotips, surrounding the nanotips,
and between the nanotips.
Description
RELATED APPLICATIONS
[0001] This application is a Divisional Application of a pending
patent application entitled, NON-VOLATILE MEMORY RESISTOR CELL WITH
NANOTIP ELECTRODE, invented by Hsu et al., Ser. No. 11/039,544,
filed Jan. 19, 2005, Attorney Docket No. SLA0892, which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention generally relates to integrated circuit (IC)
fabrication and, more particularly, to a memory resistor cell made
using an electrode with nanotips.
[0004] 2. Description of the Related Art
[0005] Semiconductor IC memory devices have replaced magnetic-core
memory devices, as IC devices have lower fabrications cost and
exhibit higher performance. An IC memory circuit includes a
repeated array of memory cells, each of which stores one state of a
two-state information (0 or 1), or multi-state information (for
example, 00, 01, 10, or 11 of 4 states). This array of cells works
together with support circuitry such as a row decoder, a column
decoder, a write circuit to write to the memory cell array, a
control circuitry to select the correct memory cell, and a sense
amplifier to amplify the signal.
[0006] One conventional memory circuit, the flip-flop, has an
output that is stable for only one of two possible voltage levels.
SRAM (static random access memory) circuits store information in
flip-flops where the information can be read from any memory cell
at random (random access memory), and where the stored information
can be kept indefinitely as long as the circuit receives power.
[0007] The more recently developed memory cell is a DRAM (dynamic
random access memory) cell. A DRAM cell typically includes a
transistor and a capacitor. The capacitor stores information in the
form of electrical charge and the transistor provides access to the
capacitor. Because of the inherent leakage of the capacitor charge,
DRAM cells must be rewritten or refreshed at frequent
intervals.
[0008] SRAM and DRAM memories cannot retain the stored information
without a power source. Therefore, they belong to a class of memory
called volatile memory. Another class of memory is called
non-volatile memory, which retains the stored information even
after the power is turned off.
[0009] A typical non-volatile memory is ferroelectric random access
memory (FRAM). Similar to a DRAM cell, a FRAM cell includes an
access transistor and a storage capacitor. The difference is that
FRAM cell uses ferroelectric material for its capacitor dielectric,
and the information is stored as the polarization state of the
ferroelectric material. Ferroelectric material can be polarized by
an electric field with a polarization lifetime of longer than 10
years.
[0010] Recent developments in materials, with changeable electrical
resistance, have introduced a new kind of non-volatile memory,
called RRAM (resistive random access memory). The basic component
of a RRAM cell is a variable resistor. The variable resistor can be
programmed to have high resistance or low resistance (in two-state
memory circuits), or any intermediate resistance value (in
multi-state memory circuits). The different resistance values of
the RRAM cell represent the information stored in the RRAM circuit.
The advantages of RRAM are the simplicity of the circuit, resulting
in smaller devices, non-volatile memory characteristics, and an
inherently stable memory state.
[0011] Since a resistor is a passive component, and cannot actively
influence nearby electrical components, a basic RRAM cell can
formed with just a variable resistor, arranged in a cross point
resistor network to form a cross point memory array. To prevent
cross talk or a parasitic current path, a RRAM cell can further
include a diode. This resistor/diode combination is sometimes
called a 1R1D (or 1D1R) cross point memory cell. To provide better
access, a RRAM can include an access transistor, as in a DRAM or
FRAM cell, and this combination is sometimes called a 1R1T (or
1T1R) cross point memory cell.
[0012] The resistance states of the RRAM can be represented by
different techniques such as structural, polarization, or
magnetization state. A Chalcogenide alloy is an example of
structural state RRAM device. Chalcogenide alloys can exhibit two
different stable reversible structural phases, namely an amorphous
phase with high electrical resistance, and a polycrystalline phase
with lower electrical resistance. Resistive heating by an
electrical current pulse can change the phases of the chalcogenide
materials. One example of polarization state is a polymer memory
element. The resistance state of a polymer memory element is
dependent upon the orientation of polarization of the polymer
molecules. The polarization of a polymer memory element can be
written by applying an electric field.
[0013] Conventional memory resistor RRAM cells are made using
planer metal top and bottom electrodes. The field intensity and the
current density are typically very uniform across the electrode.
Further, the physical structure of these devices is typically quite
symmetrical. The symmetrical cell construction and uniform field
intensities dictate that the memory states be changed using
unipolar switching. That is, the resistor may be reversibly
programmed to a high or a low resistance state by unipolar
electrical pulses having different pulse widths. The power
dissipation is, therefore, equal to IV. A relatively high current
density is required for programming, which may be higher than the
capacity of minimum-sized MOS transistors. For use in practical
commercial applications, it would be desirable if the RRAM memory
states could be switched using bipolar electrical pulses. One
approach this problem has been to build physically asymmetric
cells. Another approach has been to structure the memory resistor
material, to create non-uniform field intensities in the memory
resistor. However, these solutions may require extra fabrication
processes.
[0014] It would be advantageous if a non-volatile resistor memory
cell could be fabricated, that would be suitable for low-power,
high-density, large-scale memory applications.
[0015] It would be advantageous if a non-volatile resistor memory
cell could be practically fabricated using conventional CMOS
processes, that could be programmed using bipolar pulses, as well
as unipolar pulses.
SUMMARY OF THE INVENTION
[0016] The present application describes a memory resistor cell
where one of the electrodes is formed with nanotips extending into
the memory resistor material. The conductive nanotips create an
asymmetric electrode structure that creates non-uniform fields. The
non-uniform fields promote bipolar switching characteristics. The
electric field at the nanotips is much higher than the average
field. Therefore, lower voltage, low-power electrical pulses may be
used for programming the resistor.
[0017] Accordingly, a method is provided for fabricating a nanotip
electrode non-volatile memory resistor cell, the method comprises:
forming a first electrode with nanotips; forming a memory resistor
material adjacent the nanotips; and, forming a second electrode
adjacent the memory resistor material, where the memory resistor
material is interposed between the first and second electrodes.
Typically, the nanotips are iridium oxide (IrOx) and have a tip
base size of about 50nanometers, or less, a tip height in the range
of 5 to 50 nm, and a nanotip density of greater than 100 nanotips
per square micrometer.
[0018] In one aspect, the substrate material can be silicon,
silicon oxide, silicon nitride, or a noble metal. The specification
below provides details of a metalorganic chemical vapor deposition
(MOCVD) process that is used to deposit Ir. The IrOx nanotips are
grown from the deposited Ir. In another aspect, a refractory metal
film is formed overlying the substrate, and the IrOx nanotips are
grown from Ir deposited on the refractory metal. The memory
resistor material can be any conventional material, such as
Pr.sub.0.3Ca.sub.0.7MnO.sub.3 (PCMO), colossal magnetoresistive
(CMR) film, transition metal oxides, Mott insulators, or
high-temperature super conductor (HTSC) material.
[0019] In one aspect, the first electrode is the bottom electrode
of the memory cell, and the memory resistor material is conformally
deposited over the bottom electrode and bottom electrode nanotips.
Then, the memory resistor material is planarized, and a top
(second) electrode is formed overlying the memory resistor
material. The top electrode can be made from a conventional
material such as Pt, refractory metals, refractory metal oxides,
refractory metal nitrides, or A1.
[0020] Additional details of the above-described method, and a
nanotip electrode, non-volatile memory resistor cell are provided
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a partial cross-sectional view of a nanotip
electrode non-volatile memory resistor cell.
[0022] FIG. 2 is a partial cross-sectional view of the cell of FIG.
1, depicting some nanotips details.
[0023] FIG. 3 is a partial cross-sectional view of a first
variation of the memory cell of FIG. 1.
[0024] FIG. 4 is a partial cross-sectional view of a second
variation of a nanotip electrode memory cell.
[0025] FIG. 5 is a partial cross-sectional view of a third
variation of a nanotip electrode memory cell.
[0026] FIGS. 6 and 7 depict steps in the fabrication of the nanotip
electrode non-volatile memory resistor RRAM cell.
[0027] FIG. 8 is a scanning electron microscope (SEM) photo showing
a detailed view of a nanotip end.
[0028] FIG. 9 is a SEM photo of an initial stage of IrOx nanotip
grown.
[0029] FIG. 10 is a SEM photo of fully-grown IrOx nanotips.
[0030] FIGS. 11A and 11B are flowcharts illustrating a method for
fabricating a nanotip electrode non-volatile memory resistor
cell.
[0031] FIG. 12 is a flowchart illustrating a method for changing
memory states in a memory resistor cell.
DETAILED DESCRIPTION
[0032] FIG. 1 is a partial cross-sectional view of a nanotip
electrode non-volatile memory resistor cell. The memory cell 100
comprises a first electrode 102 with nanotips 104. A memory
resistor material 106 is adjacent the nanotips 104. A second
electrode 108 is adjacent the memory resistor material 106. More
specifically, the memory resistor material 106 is interposed
between the first electrode 102 and second electrode 108. A number
of different arrangements of memory resistor material are possible.
Generally, the memory resistor material 106 may be on the nanotips
104, surrounding and on the nanotips, and between and on the
nanotips. The arrangement shown in FIG. 1 satisfies all these
descriptions, but other variations of the cell 100 are presented
below.
[0033] As used herein, the word "nanotip" is not intended to be
limited to any particular physical characteristics, shapes, or
dimensions. The nanotips may alternately be known as nanorods,
nanotubes, or nanowires. In some aspects (not shown), the nanotips
may form a hollow structure. In other aspects (not shown), the
nanotips may be formed with a plurality of tips ends.
[0034] FIG. 2 is a partial cross-sectional view of the cell of FIG.
1, depicting some nanotips details. The first electrode nanotips
104 have a tip base size 200 of about 50 nanometers, or less. The
first electrode nanotips 104 have a tip height 202 in the range of
5 to 50 nm. Typically, the nanotip density is greater than 100
nanotips per square micrometer. That is, the number of nanotips
growing from a 1-square micrometer surface area of the first
electrode 102 exceeds typically exceeds 100. Typically, a higher
nanotip density creates a larger differential between high and low
resistance in the memory resistor material (assuming constant
voltage pulses).
[0035] In one aspect, the first electrode nanotips 104 are made
from iridium oxide (IrOx). The value of "x" may be 2, in which case
the Ir is completely oxidized, to values approaching zero, in which
case the Ir is incompletely oxidized. Although IrOx nanotips are
used to illustrate to illustrate the invention, it is expected that
nanotips can also be formed from the conductive oxides of other
transition metals.
[0036] Returning to FIG. 1, some aspects the memory cell 100
further comprise a substrate 110 made from a material such as
silicon, silicon oxide, silicon nitride, or a noble metal. The
first electrode 102 is formed adjacent (overlying) the substrate
110.
[0037] FIG. 3 is a partial cross-sectional view of a first
variation of the memory cell of FIG. 1. In some aspects, the memory
cell 100 comprises a substrate 110, with a refractory metal film
300 interposed between the substrate 110 and the first electrode
102.
[0038] Returning to FIG. 1, the memory resistor material 106 may be
a material such as Pr.sub.0.3Ca.sub.0.7MnO.sub.3(PCMO), colossal
magnetoresistive (CMR) film, transition metal oxides, Mott
insulators, or high-temperature super conductor (HTSC) material.
The cell 100 is not necessarily limited to this list of materials,
as the invention can be enabled with other materials that exhibit
memory resistance characteristics.
[0039] The first electrode nanotips 104 each have an end 112. As
shown, the memory resistor material 106 has a thickness 114,
between the first electrode nanotip ends 112 and the second
electrode 108, in the range of 30 to 200 nm. The second electrode
108 may be a material such as Pt, refractory metals, refractory
metal oxides, refractory metal nitrides, or A1. However, the cell
could also be enabled with other materials.
[0040] FIG. 4 is a partial cross-sectional view of a second
variation of a nanotip electrode memory cell. In this variation,
the memory cell material 106 is shown "on" the nanotips 104.
Material 400 may be a memory resistor material, different than
material 106, or a dielectric without memory resistance
characteristics.
[0041] FIG. 5 is a partial cross-sectional view of a third
variation of a nanotip electrode memory cell. In this variation,
the memory cell material 106 is shown between the nanotips 104.
Material 500 may be a memory resistor material, different than
material 106, or a dielectric without memory resistance
characteristics. In one aspect, material 500 is crystallized
Ir.
Functional Description
[0042] FIGS. 6 and 7 depict steps in the fabrication of the nanotip
electrode non-volatile memory resistor RRAM cell. As shown, the
bottom electrode is made of iridium oxide nanotips. The memory
resistor, for the sake of simplicity, is denoted as CMR. The top
electrode is a non-oxidiziable refractory metal or a refractory
metal compound, such as Pt or TiN.
[0043] When a voltage is applied between the two electrodes, a very
high field intensity is developed at the end of the IrOx nanotips.
When a positive voltage pulse is applied to the top electrode, a
high electron density is injected into the memory resistor from the
IrOx nanotips. Hence, the CMR in the vicinity of the IrOx tips is
turned to the high resistance phase. When a negative voltage pulse
is applied to the top electrode, the high field intensity at the
IrOx nanotips converts the CMR in the vicinity of the nanotips into
low resistance phase CMR.
[0044] FIG. 8 is a scanning electron microscope (SEM) photo showing
a detailed view of a nanotip end. Since the IrOx nanotips have a
pointy end, with a diameter in the order of a few nanometers, a
high field intensity may generated at the tip end areas, even if
the amplitude of the voltage pulse applied to the electrode, is
relatively small. Also, the current is not uniformly distributed.
Therefore, the programming power of this non-volatile memory device
is very low. The tip size (diameter) is about 50 nm, which can be
controlled by variations in the nanotip growth process. The IrOx
tips height is typically from 5 nm to 50 nm, although 100 nm tips
heights are also possible. The IrOx nanotips density is typically
greater than 100 per square-micrometer, however the density can be
greater than 3,000/micrometer.sup.2. Uniform device properties can
be achieved for device sizes down to the deep sub-micron diameter
region.
[0045] One of the methods of growing IrOx nanotips is to deposit a
thin layer of Ti onto silicon substrate, to enhance the vertical
alignment of the IrOx nanotips. The IrOx nanotips is grown by
MOCVD, using (Methylcyclopentadieyl)(1,5-cycleectahiene) iridium as
a source reagent, at temperature of 350.degree. C., under an oxygen
pressure of 10 to 50 torr. The density and the height of the
nanotips can be controlled by the sub-layer titanium thickness, the
deposition pressure, temperature, and time.
[0046] After the growth of the IrOx nanotips, any conventional
method may be used to fabricate the resistor memory cells. A layer
of memory material, such as PCMO, or other Mott insulator material
is deposited. The thickness of the memory resistor material is
typically is in the range of 50 nm to 200 nm. The wafer is
planarized using chemical-mechanical planarization (CMP) process
prior to the deposition of the top electrode. After CMP, the
thickness of the memory resistance material, from the end of the
IrOx tip, to the top electrode bottom surface, is typically 30 nm
to 200 nm. Hard mask and photoresist are used for selective etching
the top electrode, the memory resistance material, and the bottom
electrode of IrOx and Ti, out of the field region. A passivation
layer, such as 10 nm to 50 nm of silicon nitride or aluminum oxide
is deposited, followed by an additional silicon oxide deposition
and CMP planarized as is shown in FIG. 7. The silicon nitride or
aluminum oxide passivation layer is not showed in FIG. 7.
[0047] FIG. 9 is a SEM photo of an initial stage of IrOx nanotip
grown. Only a few isolated nanotips are visible.
[0048] FIG. 10 is a SEM photo of fully-grown IrOx nanotips. A
high-density vertical array of nanotips is shown.
[0049] FIGS. 11A and 11B are flowcharts illustrating a method for
fabricating a nanotip electrode non-volatile memory resistor cell.
Although the method is depicted as a sequence of numbered steps for
clarity, no order should be inferred from the numbering unless
explicitly stated. It should be understood that some of these steps
may be skipped, performed in parallel, or performed without the
requirement of maintaining a strict order of sequence. Some details
of the method may be better understood in context of the
explanations of FIGS. 1-10, above. The method starts at Step
1100.
[0050] Step 1104 forms a first electrode with nanotips. Step 1106
forms a memory resistor material adjacent the nanotips. More
explicitly, Step 1106 forms the memory resistor material
surrounding the nanotips, on the nanotips, and between the
nanotips. Step 1108 forms a second electrode adjacent the memory
resistor material, where the memory resistor material is interposed
between the first and second electrodes.
[0051] With respect to Step 1104, the nanotips formed may have a
tip base size of about 50 nanometers, or less, a tip height in the
range of 5 to 50 nm, and a nanotip density of greater than 100
nanotips per square micrometer. Typically, the nanotips are iridium
oxide.
[0052] In one aspect, Step 1102 provides a substrate, made from a
material such as silicon, silicon oxide, silicon nitride, or a
noble metal. Then, forming IrOx nanotips in Step 1104 includes
substeps. Step 1104asupplies a
(Methylcyclopendieyl)(1,5-cycleectahiene) precursor. Step 1104b
deposits Ir using a metalorganic chemical vapor deposition (MOCVD)
process. Step 1104c grows IrOx nanotips from the deposited Ir. Step
1104d deposits the Ir at a temperature of about 350.degree. C, and
Step 1104e deposits the Ir at an oxygen partial pressure in the
range of 10 to 50 torr.
[0053] In a variation of the method, Step 1103 forms a refractory
metal film overlying the substrate. Then, depositing Ir using an
MOCVD process in Step 1104b includes depositing Ir overlying the
refractor metal film.
[0054] In one aspect, forming the memory resistor material adjacent
the nanotips in Step 1106 includes. forming a memory resistor
material such as Pr.sub.0.3Ca.sub.0.7MnO.sub.3 (PCMO), colossal
magnetoresistive (CMR) film, transition metal oxides, Mott
insulators, or high-temperature super conductor (HTSC) material. In
another aspect, Step 1104 includes forming a bottom electrode with
nanotips having nanotip ends, and Step 1106 includes substeps. Step
1106a conformally deposits the memory resistor material overlying
the bottom electrode with nanotips. Step 1106b planarizes the
memory resistor material. Then, Step 1108 forms a top electrode
overlying the memory resistor material.
[0055] In one aspect, Step 1106a conformally deposits memory
resistor material, having a thickness in the range of 50 to 200 nm,
overlying the nanotips. Step 1106b planarizes the memory resistor
material, leaving a thickness of memory resistor material, in the
range of 30 to 200 nm, interposed between the nanotip ends and the
top electrode.
[0056] In one aspect, forming the top electrode in Step 1108
includes substeps. Step 1108a conformally deposits top electrode
material. Step 1108b selectively etches the top electrode material,
memory resistor material, and the bottom electrode. Step 1110 forms
a passivation layer adjacent the memory cell (see FIG. 7). The
second (top) electrode can be a material such as Pt, refractory
metals, refractory metal oxides, refractory metal nitrides, or
A1.
[0057] FIG. 12 is a flowchart illustrating a method for changing
memory states in a memory resistor cell. The method starts at Step
1200. Step 1202 supplies a resistor memory cell with a second
electrode, memory resistor material, and a first electrode having
nanotips adjacent the memory resistor material. Step 1204 supplies
a voltage pulse to the second electrode. Step 1206 creates a field
(in the memory resistor material) in the vicinity of the nanotips.
Step 1208 generates resistance characteristics of the memory
resistor material in response to the field. The high resistance can
be in the range of 1000 to 100,000 times greater than the low
resistance.
[0058] In a bipolar switching aspect, Step 1204 supplies a
narrow-width positive voltage pulse to the second (top) electrode.
Then, Step 1208 generates a high resistance in the memory resistor
material. In another aspect, Step 1204 supplies a narrow-width
negative voltage pulse, and Step 1208 generates a low resistance.
Typically, Step 1204 supplies a pulse with an absolute voltage
value (positive or negative) in the range of 1.5 to 7 volts, and a
narrow-width pulse width in the range of 1 to 500 nanoseconds
(ns).
[0059] Alternately, in the unipolar switching aspect of the
invention, Step 1204 uses a narrow-width pulse to create a high
resistance as described above, but supplies a large-width positive
voltage pulse to the second electrode, with a voltage value in the
range of 1.5 to 7 volts, and a pulse width in the range of 1
millisecond (ms) to 10 ms. Then, Step 1208 generates a low
resistance in the memory resistor material in response to the
large-width positive pulse.
[0060] The above steps describe an arrangement where nanotips are
grown from the first electrode and pulses are applied to the second
electrode. Alternately, the pulses could be applied to the first
electrode, so that the cell acts 1R1D type of cell. A negative
pulse applied to the first electrode generates the same memory
resistance characteristics as a positive pulse applied to the
second electrode. Likewise, a positive pulse applied to the first
electrode generates the same memory resistance characteristics as a
negative pulse applied to the second electrode.
[0061] As noted earlier, the nanotips formed in Step 1202 are
likely to be IrOx, having a tip base size of about 50 nm, or less,
a tip height in the range of 5 to 50 nm, and a nanotip density of
greater than 100nanotips per square micrometer. The memory resistor
material is likely to be PCMO, CMR film, transition metal oxides,
Mott insulators, or HTSC material. The second electrode material is
likely to be Pt, refractory metals, refractory metal oxides,
refractory metal nitrides, or A1. Further, the memory resistor
material typically has a thickness, between the nanotip ends and
the second electrode, in the range of 30 to 200 nm.
[0062] A memory resistor cell made with a nanotip electrode, and a
corresponding fabrication process has been provided. Specific
materials and fabrication details have been given as examples to
help illustrate the invention. However, the invention is not
limited to merely these examples. Other variations and embodiments
of the invention will occur to those skilled in the art.
* * * * *