U.S. patent application number 11/682613 was filed with the patent office on 2007-07-05 for method of driving a dual gated mosfet.
This patent application is currently assigned to Fairchild Semiconductor Corporation. Invention is credited to Alan Elbanhawy.
Application Number | 20070152729 11/682613 |
Document ID | / |
Family ID | 34714325 |
Filed Date | 2007-07-05 |
United States Patent
Application |
20070152729 |
Kind Code |
A1 |
Elbanhawy; Alan |
July 5, 2007 |
METHOD OF DRIVING A DUAL GATED MOSFET
Abstract
A method of driving a dual-gated MOSFET having a Miller
capacitance between the MOSFET gate and drain includes preparing
the MOSFET to switch from a blocking mode to a conduction mode by
applying to the MOSFET shielding gate a first voltage signal having
a first voltage level. The first voltage level is selected to
charge the Miller capacitance and thereby reduce switching losses.
A second voltage signal is applied to the switching gate to switch
the MOSFET from the blocking to the conduction mode. The first
voltage signal is then changed to a level selected to reduce the
conduction mode drain-to-source resistance and thereby reduce
conduction losses. The first voltage signal is returned to the
first voltage level to prepare the MOSFET for being switched from
the conduction mode to the blocking mode.
Inventors: |
Elbanhawy; Alan; (Hollister,
CA) |
Correspondence
Address: |
HISCOCK & BARCLAY, LLP
2000 HSBC PLAZA
100 Chestnut Street
ROCHESTER
NY
14604-2404
US
|
Assignee: |
Fairchild Semiconductor
Corporation
South Portland
ME
|
Family ID: |
34714325 |
Appl. No.: |
11/682613 |
Filed: |
March 6, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11052264 |
Feb 7, 2005 |
7195979 |
|
|
11682613 |
Mar 6, 2007 |
|
|
|
10686859 |
Oct 16, 2003 |
6870217 |
|
|
11052264 |
Feb 7, 2005 |
|
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10640742 |
Aug 14, 2003 |
6870220 |
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10686859 |
Oct 16, 2003 |
|
|
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60405369 |
Aug 23, 2002 |
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Current U.S.
Class: |
327/389 |
Current CPC
Class: |
H01L 29/402 20130101;
H03K 17/063 20130101; H03K 17/04106 20130101; H01L 29/7801
20130101; H03K 2017/6878 20130101; H03K 17/6877 20130101; H03K
2217/0036 20130101; H01L 29/407 20130101; H01L 29/7813 20130101;
H01L 29/7802 20130101 |
Class at
Publication: |
327/389 |
International
Class: |
H03K 17/16 20060101
H03K017/16 |
Claims
1. A method for driving a dual-gated MOSFET, the dual-gated MOSFET
being switchable between conduction and blocking modes, the
dual-gated MOSFET having a shielding gate, a switching gate, a
gate-to-drain overlap regions and a drain-to-source resistance when
the MOSFET is in the conduction mode, said method comprising:
applying a first voltage signal to the shielding gate; maintaining
the first voltage signal at a first voltage level prior to
switching the MOSFET from the blocking mode to the conduction mode,
the first voltage level being selected to substantially completely
charge the gate-to-drain overlap region of the MOSFET; and further
applying a second voltage signal to the switching gate, the second
voltage signal switching the MOSFET between the blocking and
conduction modes.
2. The method of claim 1, wherein said maintaining step comprises
one of continuously maintaining the first voltage signal at the
first voltage level and maintaining the first voltage signal at the
first voltage level for a predetermined amount of time prior to
switching the MOSFET from the blocking to the conduction mode.
3. The method of claim 1, wherein said further applying step
comprises switching the second voltage signal from a low voltage
level to a high voltage level to thereby place the MOSFET in the
conduction mode.
4. The method of claim 3, further comprising the steps of: delaying
a first delay time after the further applying step; and changing
the first voltage signal from the first voltage level selected to
substantially completely charge the gate-to-drain overlap region of
the MOSFET to a fourth voltage level selected to reduce the
resistance between the drain and source of the MOSFET while in the
conduction mode.
5. The method of claim 4, wherein said first delay time comprises
the rise time of the switching gate.
6. The method of claim 4, further comprising the steps of:
returning the first voltage signal from the fourth voltage level
selected to reduce the resistance between the drain and source of
the MOSFET while in the conduction mode to one of the first voltage
level selected to substantially completely charge the gate-to-drain
overlap region of the MOSFET or ground potential; delaying a second
delay time; and further returning the second voltage signal from
the high voltage level to the low voltage level to a thereby place
the MOSFET in the blocking mode.
7. The method of claim 6, wherein said second delay time comprises
the fall time of the shielding gate.
8. A method of driving a dual-gated MOSFET, the dual-gated MOSFET
having a shielding gate, a switching gate, a Miller capacitance
between the MOSFET gate and drain, and a drain-to-source resistance
when the MOSFET is in the conduction mode, said method comprising:
preparing the MOSFET to switch from the blocking mode to the
conduction mode by applying a first voltage signal at a first
voltage level to the shielding gate, the first voltage level being
selected to substantially completely charge the Miller capacitance
and thereby reduce switching losses; and applying a second voltage
signal to the switching gate to switch the MOSFET between the
blocking and conduction modes.
9. The method of claim 8, further comprising: delaying a first
delay time following said applying step; and changing the first
voltage signal to a fourth voltage level selected to substantially
reduce the resistance between the drain and source of the MOSFET to
thereby reduce conduction losses.
10. The method of claim 9, wherein said first delay time comprises
the rise time of the switching gate.
11. The method of claim 9, further comprising the step of returning
the first voltage signal to the first voltage level to thereby
substantially completely discharge the Miller capacitance thereby
preparing the MOSFET to switch from the conduction mode to the
blocking mode.
12. The method of claim 11, further comprising the steps of:
further delaying a second delay time following said returning step;
and switching said second voltage signal to said low voltage
level.
13. The method of claim 8, wherein said preparing step comprises
one of continuously maintaining the first voltage signal at the
first voltage level or maintaining the first voltage signal at the
first voltage level for a predetermined amount of time prior to
switching the MOSFET from the blocking to the conduction mode.
14. The method of claim 8, wherein said preparing step comprises
one of continuously maintaining the first voltage signal at the
first voltage level or maintaining the first voltage signal at the
first voltage level for a predetermined amount of time prior to
switching the MOSFET from the blocking to the conduction mode.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 11/052,264 filed Feb. 7, 2005, which is a
divisional of U.S. patent application Ser. No. 10/686,859, filed 16
Oct. 2003, which is a continuation-in-pant of U.S. patent
application Ser. No. 10/640,742, filed Aug. 14, 2003 and entitled
METHOD AND APPARATUS FOR IMPROVED MOS GATING TO REDUCE MILLER
CAPACITANCE AND SWITCHING LOSSES, which is incorporated herein by
reference, which, in turn, claims the benefit of U.S. Provisional
Patent Application Ser. No. 60/405,369, filed Aug. 23, 2002, which
is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to semiconductors and, more
particularly, to a method of and apparatus for driving dual-gate
metal-oxide semiconductor field effect transistors (MOSFET).
DESCRIPTION OF THE RELATED ART
[0003] MOSFETs are used extensively in switching applications, such
as, for example, switching power supplies, practically to the
exclusion of other types of transistors. MOSFETs are suited to such
switching applications due to their relatively high switching speed
and low power requirements. However, the dynamic losses in
conventional MOSFETs represent a large percentage of the total
losses in DC-to-DC converters. The dynamic losses of conventional
MOSFETS are directly proportional to the device rise and fall times
which are, in turn, proportional to the gate-to-drain capacitance,
i.e., the Miller capacitance, of the devices (C.sub.GD or
Q.sub.GD).
[0004] The Miller capacitance is reduced by reducing the area over
which the gate and drain regions overlap. In prior art devices,
this overlap area includes the bottom of the gate trench. Many
prior art attempts to reduce the Miller capacitance have therefore
focused on narrowing the trench width to thereby reduce the width
of the trench bottom and thus the overlap area. However, the
ability to further reduce trench width is limited by the ability to
etch narrow trenches, and the corresponding need to be able to fill
the narrow trenches with gate electrode material.
[0005] A dual-gated MOSFET device as described in co-pending U.S.
patent application Ser. No. 10/640,742, filed Aug. 14, 2003 and
entitled METHOD AND APPARATUS FOR IMPROVED MOS GATING TO REDUCE
MILLER CAPACITANCE AND SWITCHING LOSSES, the disclosure of which is
incorporated herein by reference, virtually eliminates the Miller
capacitance and the switching losses associated therewith by
providing a dual-gated structure that reduces the area over which
the gate and drain regions overlap. Generally, the dual-gated
structure includes a shielding gate and a control gate. The
shielding gate is biased into the on or conduction state either
continuously or just prior to a switching event thereby placing the
device into the conduction mode. The shielding gate charges the
gate-to-drain overlap region, which as stated above is the region
that generates the Miller capacitance in a conventional device.
With the shielding gate thus biased, the current flow through the
dual-gated device is controlled and is easily switched on and/or
off by the voltage level applied to the switching or control
gate.
[0006] In order to gain the full advantage of the desirable
characteristics of such a dual-gated device, however, drive signals
having specific voltage levels at particular times must be applied
to each of the shielding and switching gates. More particularly,
drive signals having a specific sequence of voltage levels must be
applied to each of the shielding and switching gates in order to
achieve both fast switching times and low resistance between the
drain and source when the device is in the on or conduction state
(RDSon).
[0007] Therefore, what is needed in the art is a method and
apparatus for driving a dual-gated MOSFET.
SUMMARY OF THE INVENTION
[0008] The present invention provides a method and apparatus for
driving a dual-gated MOSFET.
[0009] The invention comprises, in one form thereof; a method of
driving a dual-gated MOSFET having a Miller capacitance between the
MOSFET gate and drain. The method includes preparing the MOSFET to
switch from a blocking mode to a conduction mode by applying to the
MOSFET shielding gate/electrode a first voltage signal having a
first voltage level. The first voltage level is selected to charge
the Miller capacitance and thereby reduce switching losses. A
second voltage signal is applied to the switching Gate to switch
the MOSFET from the blocking to the conduction mode. The first
voltage signal is then changed to a level selected to reduce the
conduction mode drain-to-source resistance and thereby reduce
conduction losses. The first voltage signal is returned to the
first voltage level to prepare the MOSFET for being switched from
the conduction mode to the blocking mode.
[0010] An advantage of the present invention is that the gate
voltage signals are applied to the gates of the dual-gated MOSFET
in such levels and in such a sequence so as to substantially reduce
drain-to-source resistance in the on-state.
[0011] Yet another advantage of the present invention is that the
gate voltage signals are applied to the gates of the dual-gated
MOSFET in such levels and in such a sequence so as to substantially
increase switching times.
[0012] A still further advantage of the present invention is that
the gate voltage signals are applied to the gates of the dual-gated
MOSFET in such levels and in such a sequence so as to substantially
reduce Miller capacitance and switching losses.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The above-mentioned and other features and advantages of
this invention, and the manner of attaining them, will become
apparent and be better understood by reference to the following
description of one embodiment of the invention in conjunction with
the accompanying drawings, wherein:
[0014] FIG. 1 is a plot of the applied gate voltage versus gate
charge for both a conventional MOSFET and a dual-gated MOSFET;
[0015] FIG. 2 is a schematic diagram of one embodiment of a circuit
of the present invention for driving a dual-gated MOSFET; and
[0016] FIG. 3 shows the voltage signals applied to the gates of a
dual-gated MOSFET according to one embodiment of the method for
driving a dual-gated MOSFET of the present invention.
[0017] Corresponding reference characters indicate corresponding
parts throughout the several views. The exemplifications set out
herein illustrate one preferred embodiment of the invention, in one
form, and such exemplifications are not to be construed as limiting
the scope of the invention in any manner.
DETAILED DESCRIPTION OF THE DRAWINGS
[0018] Referring now to the drawings, and particularly to FIG. 1,
the gate voltage Vg.sub.CONV of a conventional MOSFET and the gate
voltage Vg.sub.DUAL of a dual-gated MOSFET device are each plotted
versus the gate charge applied thereto. As FIG. 1 shows, a "flat"
region M exists in the gate charge curve Vg.sub.CONV of the
conventional MOSFET. Within flat region M the gate charge
Q.sub.gate increases from approximately -0.5 to approximately
2.00.times.10.sup.-15 Coulombs per micrometer while the voltage
applied to the gate remains relatively constant at approximately
1.5 Volts. Flat region M, referred to as the Miller region, occurs
due to the Miller capacitance of the conventional MOSFET.
[0019] Flat region M corresponds to the charging and/or discharging
of the Miller capacitance as the conventional MOSFET undergoes the
transition from a blocking state to a conducting state or from a
conducting state to a blocking state. It is in the Miller region M
that most of the switching losses in a conventional MOSFET occur
since the device current and voltage are each relatively high.
Reducing the Miller capacitance reduces the time the device
requires to undergo the transition from conduction to blocking or
vice-versa, and thereby reduces switching losses. In contrast to
the conventional MOSFET device, the gate voltage waveform
Vg.sub.DUAL for the dual-gated MOSFET device has virtually no flat
or Miller region. Thus, the dual-gated MOSFET device has a
substantially reduced Miller capacitance relative to a conventional
MOSFET.
[0020] Referring now to FIG. 2, there is shown a schematic
representation of one embodiment of a driving circuit of the
present invention for driving a dual-gated MOSFET. Generally, dual
gate driving circuit 10 is configured for driving dual-gated MOSFET
20, which has a dual overlapping gate structure that reduces Miller
capacitance and improves switching speed. More particularly,
dual-gated MOSFET 20 includes shielding gate 22, switching/control
gate 24, drain 26 and source 28. The structure, method of
manufacture, and theory of operation of MOSFET 20 are thoroughly
described in the above-mentioned U.S. patent application Ser. No.
10/640,742, filed Aug. 14, 2003 and entitled METHOD AND APPARATUS
FOR IMPROVED MOS GATING TO REDUCE MILLER CAPACITANCE AND SWITCHING
LOSSES, which has been incorporated herein by reference. Driving
circuit 10 also includes first or shield gate voltage signal
generating means 32 and second or switching gate voltage generating
means 34.
[0021] First or shield gate voltage signal generating means 32,
hereinafter referred to as voltage signal source 32, is
electrically connected to shielding gate 22 and provides thereto
shield gate voltage signal Vg.sub.SHIELD. Second or switching gate
voltage signal generating means 34, hereinafter referred to as
voltage signal source 34, is electrically connected to
switching/control gate 24 and provides thereto switching/control
gate voltage signal Vg.sub.SWITCH. Shield gate voltage source 32
and switching gate voltage source 34 are each configured, for
example, as voltage sources 40a, 40b, respectively, that are
selectively connected to corresponding voltage-divider circuits
42a, 42b, through transistor switches 44a, 44b, respectively. Each
of transistor switches 44a, 44b, are electrically connected to
respective outputs of a microprocessor, analog or digital
controller 50, via corresponding buffers or drivers (not shown) if
necessary. The microprocessor or controller 50 opens and/or closes
transistor switches 44a, 44b to selectively connect voltage sources
40a, 40b to the corresponding voltage divider circuits 44a, 44b.
Thus, microprocessor or controller 50 controls the voltage across
the voltage divider circuit and thereby produces the gate voltage
waveforms Vg.sub.SHIELD and Vg.sub.SWITCH. Voltage supply 52 is
electrically connected with shielding gate 22, and maintains
shielding gate 22 at a predetermined voltage level as is more
particularly described hereinafter.
[0022] Referring now to FIG. 3, the voltage signals generated by
voltage signal source 32 and voltage signal source 34, and which
are applied to each of the gates of dual-gated MOSFET 20 according
to one embodiment of the method for driving a dual-gated MOSFET of
the present invention, are shown. More particularly, FIG. 3 shows
the voltage signals Vg.sub.SHIELD and Vg.sub.SWITCH which as
described above are electrically connected to and drive shielding
22 and switching 24 electrodes/gates, respectively, of dual-gated
MOSFET 20. The resulting voltage signal V.sub.DS between drain 26
and source 28 is also shown. Generally, voltage signal
Vg.sub.SHIELD prepares MOSFET 20 to be switched and thereby reduces
the undesirable effects of the Miller capacitance on the switching
characteristics of MOSFET 20, whereas Vg.sub.SWITCH controls the
actual switching of MOSFET 20 between the conduction and blocking
states. Once MOSFET 20 has been placed into the conduction mode,
the voltage level of Vg.sub.SHIELD is controlled to optimize/reduce
the resistance between drain 26 and source 28.
[0023] More particularly, at and/or prior to time t.sub.0 signal
VG.sub.SHIELD maintains shielding gate 22 at voltage level V.sub.1,
such as, for example, approximately three to six volts. Voltage
supply 52 either continuously maintains voltage signal
Vg.sub.SHIELD at voltage level V.sub.1 or brings voltage signal
Vg.sub.SHIELD to voltage level V.sub.1 at a predetermined amount of
time prior to a switching event. Voltage level V.sub.1 is selected
to be of a sufficient level to support a driving voltage level,
i.e., to substantially completely charge the Miller capacitance and
prepare the channel of MOSFET 20 for conduction, thereby minimizing
the effects of the Miller capacitance on the switching
characteristics of MOSFET 20. In effect, application of voltage
signal Vg.sub.SHIELD at voltage level V.sub.1 to shield gate 22
charges the gate-to-drain overlap region of MOSFET 20, which is the
region that generates the Miller capacitance in a conventional
MOSFET device, and thereby optimizes the rise and/or fall times of
switching gate 22. Once that gate-to-drain overlap region is
charged by the application of voltage signal Vg.sub.SHIELD at
voltage level V.sub.1 to shield electrode or gate 22, MOSFET 20 is
easily and quickly switched on and/or off by a relatively small
change in the voltage level of voltage signal Vg.sub.SWITCH applied
to switching electrode/gate 24.
[0024] In short, the application of voltage level V.sub.1 to
shielding gate 22 preparatorily charges the Miller capacitance of
MOSFET 20 for an impending or an eventual switching event, thereby
optimizing the rise and fall times of switching gate 24. Once
shield gate 22 has been switched, only conduction losses (which are
relatively small compared to switching losses or losses due to
Miller capacitance) occur during the switching of MOSFET 20.
[0025] A switching event is commenced at time t.sub.1 by causing
signal Vg.sub.SWITCH to transition from voltage level V.sub.2, such
as, for example, approximately zero volts or ground potential,
toward voltage level V.sub.3, such as, for example, from
approximately 5 to 10 Volts, to thereby switch MOSFET 20 from a
blocking mode into a conduction mode. This transition is reflected
by the corresponding transition at approximately time t.sub.1 of
V.sub.DS from a high voltage level to a low voltage. At time
t.sub.2 signal Vg.sub.SHIELD begins to transition from voltage
level V.sub.1 toward voltage level V.sub.4. The delay time t.sub.D1
is the duration between times t.sub.1 and t.sub.2, and is dependent
at least in part upon the rise time of switching gate 24.
Preferably, delay time t.sub.D1 is approximately equal to the rise
time of switching gate 24. However, various sources may introduce
additional delay between times t.sub.1 and t.sub.2 thereby making
t.sub.D1 somewhat greater than the rise time of switching gate 24.
Therefore, Vg.sub.SWITCH may reach voltage level V.sub.3 prior to
time t.sub.2, and thus prior to the beginning of the transition of
Vg.sub.SHIELD from voltage level V.sub.1 toward voltage level
V.sub.4. Vg.sub.SWITCH remains at voltage level V.sub.3 for a
duration of time t.sub.p.
[0026] Vg.sub.SHIELD rises at time t.sub.2 from voltage level
V.sub.1 toward voltage level V.sub.4, such as, for example, from
approximately 9 to 13 Volts, that is selected to optimize/reduce
the resistance between drain 26 and source 28 while MOSFET 20 is in
the on or conduction state, i.e., R.sub.DSon. Thus, conduction
losses during the on-state operation of MOSFET 20 are substantially
reduced.
[0027] In preparation for and/or in order to commence a second or
return switching event, and switch MOSFET 20 from the conduction to
the blocking mode, the voltage level of Vg.sub.SHIELD is reduced at
time t.sub.3 from voltage level V.sub.4 back toward voltage level
V.sub.1. Thereafter, Vg.sub.SHIELD is either continuously
maintained at voltage level V.sub.1, or is reduced to a different
voltage level, such as, for example, ground potential, and then
returned to voltage level V.sub.1 at a predetermined amount of time
prior to the next switching event.
[0028] At time t.sub.4 Vg.sub.SWITCH is switched from voltage level
V.sub.3 back toward voltage level V.sub.2. The delay time t.sub.D2
is the duration between times t.sub.3 and t.sub.4, and is dependent
at least in part upon the fall time of switching gate 24. This
transition is reflected by a corresponding transition at
approximately time t.sub.4 of VDS from a low voltage to a high
voltage level. Preferably, delay time t.sub.D2 is approximately
equal to the fall time of switching gate 24. However, various
sources may introduce additional delay between times t.sub.3 and
t.sub.4 thereby making t.sup.D2 somewhat greater than the fall time
of switching gate 24.
[0029] In the embodiment shown, the shield and switching gate
voltage sources are configured as voltage sources driving
voltage-divider circuits through transistor switches which are
electrically connected to respective outputs of a microprocessor,
analog or digital controller, via corresponding buffers or drivers
if necessary, to thereby produce the gate voltage waveforms
Vg.sub.SHIELD and Vg.sub.SWITCH. However, it is to be understood
that the actual configuration of the shield and switching gate
voltage sources can be alternately configured various ways.
[0030] While this invention has been described as having a
preferred design, the present invention can be further modified
within the spirit and scope of this disclosure. This application is
therefore intended to cover any variations, uses, or adaptations of
the present invention using the general principles disclosed
herein. Further, this application is intended to cover such
departures from the present disclosure as come within the known or
customary practice in the art to which this invention pertains and
which fall within the limits of the appended claims.
* * * * *