U.S. patent application number 11/708905 was filed with the patent office on 2007-06-28 for liquid crystal display device and manufacturing method thereof.
This patent application is currently assigned to Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Yoshiharu Hirakata, Shunpei Yamazaki.
Application Number | 20070146568 11/708905 |
Document ID | / |
Family ID | 18593358 |
Filed Date | 2007-06-28 |
United States Patent
Application |
20070146568 |
Kind Code |
A1 |
Yamazaki; Shunpei ; et
al. |
June 28, 2007 |
Liquid crystal display device and manufacturing method thereof
Abstract
An electro-optical device typified by an active matrix type
liquid crystal display device, is manufactured by cutting a rubbing
process, and in addition, a reduction in the manufacturing cost and
an improvement in the yield are realized by reducing the number of
process steps to manufacture a TFT. By forming a pixel TFT portion
having a reverse stagger type n-channel TFT, and a storage
capacitor, by performing three photolithography steps using three
photomasks, and in addition, by having a uniform cell gap by
forming wall-like spacers by performing one photolithography step,
without performing a rubbing process, a multi-domain perpendicular
orientation type liquid crystal display device having a wide
viewing angle display, and in which a switching direction of the
liquid crystal molecules is controlled, can be realized.
Inventors: |
Yamazaki; Shunpei;
(Setagaya, JP) ; Hirakata; Yoshiharu; (Atsugi,
JP) |
Correspondence
Address: |
ERIC ROBINSON
PMB 955
21010 SOUTHBANK ST.
POTOMAC FALLS
VA
20165
US
|
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd.
Atsugi-shi
JP
|
Family ID: |
18593358 |
Appl. No.: |
11/708905 |
Filed: |
February 22, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09566742 |
May 9, 2000 |
|
|
|
11708905 |
Feb 22, 2007 |
|
|
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Current U.S.
Class: |
349/43 |
Current CPC
Class: |
G02F 1/133707 20130101;
G02F 1/136213 20130101; G02F 1/1393 20130101; G02F 1/136204
20130101; H01L 2224/16225 20130101; H01L 2224/48091 20130101; H01L
27/124 20130101; G02F 1/1337 20130101; G02F 1/13394 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
349/043 |
International
Class: |
G02F 1/136 20060101
G02F001/136 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 17, 2000 |
JP |
2000-075467 |
Claims
1. A method of manufacturing an active matrix liquid crystal device
comprising: forming a spacer over a first substrate by
photolithography; forming an orientation film for vertical
alignment over the first substrate after forming the spacer so that
the spacer is located between the orientation film and the first
substrate; dripping a liquid crystal onto one of the first
substrate and a second substrate; and joining the first substrate
and the second substrate by a sealing member with the liquid
crystal interposed therebetween.
2. The method according to claim 1 wherein the spacer has a
wall-like shape.
3. The method according to claim 1, wherein the spacer comprises an
organic resin.
4. A method of manufacturing an active matrix liquid crystal device
comprising: forming a spacer over a first substrate by
photolithography; forming an orientation film for vertical
alignment over the first substrate after forming the spacer so that
the spacer is located between the orientation film and the first
substrate; forming a thin film transistor over a second substrate;
forming a pixel electrode over the second substrate wherein the
thin film transistor is electrically connected to the pixel
electrode; dripping a liquid crystal onto one of the first
substrate and the second substrate; and joining the first substrate
and the second substrate by a sealing member with the liquid
crystal interposed therebetween.
5. The method according to claim 4 wherein the spacer has a
wall-like shape.
6. The method according to claim 4, wherein the spacer comprises an
organic resin.
7. The method according to claim 4 wherein a channel of the thin
film transistor comprises amorphous silicon.
8. A method of manufacturing an active matrix liquid crystal device
comprising: forming a spacer over a first substrate by
photolithography; forming a first orientation film for vertical
alignment over the first substrate after forming the spacer so that
the spacer is located between the first orientation film and the
first substrate; forming a convex portion over a second substrate;
forming a second orientation film for vertical alignment over the
second substrate after forming the convex portion so that the
convex portion is located between the second orientation film and
the second substrate; dripping a liquid crystal onto one of the
first substrate and the second substrate; and joining the first
substrate and the second substrate by a sealing member with the
liquid crystal interposed therebetween.
9. The method according to claim 8 wherein the spacer has a
wall-like shape.
10. The method according to claim 8, wherein the spacer comprises
an organic resin.
11. The method according to claim 8 wherein the convex portion
comprises an organic resin.
12. The method according to claim 8 wherein the convex portion
includes a portion which has a stripe shape.
13. A method of manufacturing an active matrix liquid crystal
device comprising: forming a spacer over a first substrate by
photolithography; forming a convex portion over the first
substrate; forming an orientation film for vertical alignment over
the first substrate after forming the spacer and the convex portion
so that the spacer and the convex portion are located between the
orientation film and the first substrate; dripping a liquid crystal
onto one of the first substrate and a second substrate; and joining
the first substrate and the second substrate by a sealing member
with the liquid crystal interposed therebetween.
14. The method according to claim 13 wherein the spacer has a
wall-like shape.
15. The method according to claim 13, wherein the spacer comprises
an organic resin.
16. The method according to claim 13 wherein the convex portion
comprises an organic resin.
17. The method according to claim 13 wherein the convex portion
includes a portion which has a stripe shape.
18. A method of manufacturing an active matrix liquid crystal
device comprising: forming a convex portion over a first substrate;
forming an orientation film for vertical alignment over the first
substrate after forming the convex portion so that the convex
portion is located between the orientation film and the first
substrate; dripping a liquid crystal onto one of the first
substrate and a second substrate; and joining the first substrate
and the second substrate by a sealing member with the liquid
crystal interposed therebetween.
19. The method according to claim 18, wherein the spacer comprises
an organic resin.
20. The method according to claim 18 wherein the convex portion
comprises an organic resin.
21. The method according to claim 18 wherein the convex portion
includes a portion which has a stripe shape.
22. A method of manufacturing an active matrix liquid crystal
device comprising: forming a spacer over a first substrate by
photolithography; forming a first orientation film for vertical
alignment over the first substrate after forming the spacer so that
the spacer is located between the first orientation film and the
first substrate; forming a thin film transistor over a second
substrate; forming a pixel electrode over the second substrate
wherein the thin film transistor is electrically connected to the
pixel electrode; forming a convex portion over the pixel electrode;
forming a second orientation film for vertical alignment over the
second substrate after forming the convex portion so that the
convex portion is located between the second orientation film and
the second substrate; dripping a liquid crystal onto one of the
first substrate and the second substrate; and joining the first
substrate and the second substrate by a sealing member with the
liquid crystal interposed therebetween.
23. The method according to claim 22 wherein the spacer has a
wall-like shape.
24. The method according to claim 22, wherein the spacer comprises
an organic resin.
25. The method according to claim 22 wherein the convex portion
comprises an organic resin.
26. The method according to claim 22 wherein the convex portion
includes a portion which has a stripe shape.
27. The method according to claim 22 wherein a channel of the thin
film transistor comprises amorphous silicon.
28. A method of manufacturing an active matrix liquid crystal
device comprising: forming a spacer over a first substrate by
photolithography; forming a convex portion over the first
substrate; forming an orientation film for vertical alignment over
the first substrate after forming the spacer and the convex portion
so that the spacer and the convex portion are located between the
orientation film and the first substrate; forming a thin film
transistor over a second substrate; forming a pixel electrode over
the second substrate wherein the thin film transistor is
electrically connected to the pixel electrode; dripping a liquid
crystal onto one of the first substrate and the second substrate;
and joining the first substrate and the second substrate by a
sealing member with the liquid crystal interposed therebetween.
29. The method according to claim 28 wherein the spacer has a
wall-like shape.
30. The method according to claim 28, wherein the spacer comprises
an organic resin.
31. The method according to claim 28 wherein the convex portion
comprises an organic resin.
32. The method according to claim 28 wherein the convex portion
includes a portion which has a stripe shape.
33. The method according to claim 28 wherein a channel of the thin
film transistor comprises amorphous silicon.
34. A method of manufacturing an active matrix liquid crystal
device comprising: forming a convex portion over a first substrate;
forming an orientation film for vertical alignment over the first
substrate after forming the convex portion so that the convex
portion is located between the orientation film and the first
substrate; forming a thin film transistor over a second substrate;
forming a pixel electrode over the second substrate wherein the
thin film transistor is electrically connected to the pixel
electrode; dripping a liquid crystal onto one of the first
substrate and the second substrate; and joining the first substrate
and the second substrate by a sealing member with the liquid
crystal interposed therebetween.
35. The method according to claim 34 wherein the convex portion
comprises an organic resin.
36. The method according to claim 34 wherein the convex portion
includes a portion which has a stripe shape.
37. The method according to claim 34 wherein a channel of the thin
film transistor comprises amorphous silicon.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field to Which the Invention Belongs
[0002] The present invention relates to a semiconductor device
having a circuit composed of a thin film transistor (hereafter
referred to as TFT), and to a method of manufacturing thereof. For
example, the present invention relates to an electro-optical
device, typically a liquid crystal display panel, and to electronic
equipment loaded with this type of electro-optical device as a
part.
[0003] 2. Prior Art
[0004] In recent years, techniques of structuring a thin film
transistor (TFT) by using a semiconductor thin film (with a
thickness on the order of several nm to several hundred of nm)
formed on a substrate having an insulating surface have been in the
spotlight. The thin film transistor is being widely applied in an
electronic device such as an IC or an electro-optical device, and
in particular, its development as a switching element of an image
display device has been proceeding rapidly.
[0005] Conventionally, a liquid crystal display device is known as
an image display device. Active matrix type liquid crystal display
devices have come into widespread due to the fact that, compared to
passive type liquid crystal display devices, a higher definition
image can be obtained. By driving pixel electrodes arranged in a
matrix state in the active matrix type liquid crystal display
device, a display pattern is formed on a screen. In more detail, by
applying a voltage between a selected pixel electrode and an
opposing electrode corresponding to the pixel electrode, optical
modulation of a liquid crystal layer arranged between the pixel
electrode and the opposing electrode is performed, and the optical
modulation is recognized as a display pattern by an observer.
[0006] The use of this type of active matrix type electro-optical
device is spreading, and along with making the screen size larger,
demands for higher definition, higher aperture ratio, and higher
reliability are increasing. Further, at the same time, demands are
increasing for improving productivity and lowering costs.
[0007] Conventionally, a TN mode oriented with a 90.degree. twist
between the direction of light incident to a liquid crystal
molecules and the direction of light emitted from the liquid
crystal molecules is generally used as an orientation mode of a
liquid crystal layer used by a transmitting type liquid crystal
display device.
[0008] When manufacturing the TN mode liquid crystal display
device, an orientation film is formed on one substrate and on
another substrate, and a process such as a rubbing process is
performed in order to set the orientation direction of the liquid
crystal. These substrates are then put together such that the
rubbing directions of the substrates are perpendicular to each
other. By injecting a liquid crystal material, in which a chiral
material for determining the twist rotation direction has been
mixed in, between the pair of substrates, a liquid crystal display
device having a preset twist direction is formed.
[0009] At this point, the major axis of the liquid crystal
molecules is arranged parallel with respect to the substrate
surface in order to have the energetically most stable arrangement,
and depending upon the rubbing conditions and orientation film
material, the liquid crystals are arranged possessing an angle from
several degrees to approximately 10.degree. with respect to the
substrate surface.
[0010] This angle is referred to as a pre-tilt angle, and by
maintaining this pre-tilt angle, change of the arrangement occurs
by a predetermined lining up of an edge portion in both edge
portions of the major axes of the liquid crystal molecules when an
electric field is applied. The orientation thus becomes continuous
during operation, and an orientation defect referred to as reverse
tilt domain during display can be prevented.
[0011] However, with the above TN mode, the contrast
characteristics deteriorate extremely outside a specific viewing
range, and a problem of a phenomenon referred to as reverse
gradation develops.
[0012] This is because light having different optical modulation is
seen due to: changes in arrangement, in which the orientation state
of the liquid crystal molecules becomes vertical with respect to
the substrate surface due to the electric field; and changes in the
light advancement distance within the liquid crystal layer, and
changes in the index of refraction of the light during
transmission, depending upon the viewing angle and position at
which an observer watches the liquid crystal display device.
[0013] Further, the liquid crystal molecules near the interface
with the substrate receive strongly regulated orientation with this
mode, and the initial orientation state is nearly maintained.
Therefore, even if a very high liquid crystal saturation voltage
(5V or more) is applied, the liquid crystal molecules in this
neighborhood will not become vertical.
[0014] These are considered the primary factors causing the
narrowing of the field of view characteristics of the TN mode.
[0015] In addition, a perpendicular orientation type liquid crystal
mode is known as another liquid crystal display mode. The
perpendicular orientation type liquid crystal mode is an
orientation mode in which the initial orientation of the liquid
crystals is vertical with respect to the substrate. An n-type
liquid crystal material possessing negative dielectric anisotropy
is used in this mode. Display is realized for this mode as well by
applying an electric field between electrodes formed on the
substrates.
[0016] However, because this is a mode which utilizes the double
refraction of the liquid crystal, a small amount of dispersion in
the pre-tilt angle is conspicuous as a dispersion in the amount of
light transmitted or in the amount of light reflected. Small
differences in the contact of the brush tip during the rubbing
process become a cause of wavy display, which easily becomes a
problem.
[0017] Further, the rubbing process itself is a process of rubbing
the surface of the orientation film on the substrate with a soft
hairs, and therefore this becomes a source of dust contamination.
In addition, it is necessary to have sufficient counter measures
against stress and deterioration of the elements on the substrate
which accompanies the generation of static electricity.
[0018] Therefore, a method of orienting the liquid crystals and
realizing a uniform orientation without performing the rubbing
process has generally been searched for. For example, a means of
manufacturing a liquid crystal display device is known in which a
structure is formed on the substrate, and physical parameters such
as the slope of the face of the structure which contacts the liquid
crystal, the gap, and the height are regulated, and in addition, by
controlling orientation together with the electric field action due
to the dielectric constant of the structure. A wide angle of view
equal to or greater than 160.degree. can thus be realized by this
method. However, although the conventional rubbing process becomes
unnecessary with this method, complicated additional processes are
required in order to orient the liquid crystal.
SUMMARY OF THE INVENTION
Problems to be Solved by the Invention
[0019] Conventionally, TFTs are manufactured on a substrate by a
photolithography technique using a minimum of 5 or more photomasks
for an active matrix type electro-optical device, and therefore the
production cost is large. In order to increase productivity and
improve yield, an effective means in which the number of steps is
reduced has been considered.
[0020] Specifically, it is necessary to reduce the number of
photomasks needed to produce the TFT. The photomask is used in a
photolithography technique in order to form a photoresist pattern,
which becomes an etching process mask, on the substrate.
[0021] By using one photomask, there are applied with steps such as
applying resist, pre-baking, exposure, development, and
post-baking, and steps of film deposition and etching before and
after, and in addition, resist peeling, cleaning, and drying steps
are added. Therefore, the entire process becomes complex, which
leads to a problem.
[0022] Further, static electricity is generated by causes such as
friction during manufacturing steps because the substrate is an
insulator. If static electricity is generated, then short circuits
develop at an intersection portion of wirings formed on the
substrate, and deterioration or breakage of the TFT due to static
electricity leads to display faults or deterioration of image
quality in electro-optical devices. In particular, static
electricity develops during rubbing in the liquid crystal orienting
process performed in the manufacturing steps, and this becomes a
problem.
[0023] The present invention is for answering these types of
problems, and an object of the present invention is to realize a
lowering of the production cost and a raise in the yield by:
manufacturing an electro-optical device, typically an active matrix
type liquid crystal display device, by cutting the rubbing process;
and additionally, by reducing the number of steps for the
manufacture of TFTs.
[0024] In addition, an object of the present invention is to
improve the viewing angle characteristics of the liquid crystal
display device.
Means for Solving the Problem
[0025] A structure of the present invention disclosed by this
specification is a liquid crystal display device having a pair of
substrates and a liquid crystal maintained between the pair of
substrates, characterized in that [0026] formed on one substrate of
the pair of substrates are: [0027] a gate wiring; [0028] an
insulating film on the gate wiring; [0029] an amorphous
semiconductor film on the insulating film; [0030] a source region
and a drain region on the amorphous semiconductor film; [0031] a
source wiring or an electrode on the source region or the drain
region; [0032] a pixel electrode formed on the electrode; and
[0033] a gap retaining material formed for maintaining a constant
gap between the pair of substrates, and characterized in that
[0034] a pre-tilt angle of the liquid crystal is controlled by a
side face of the gap retaining material, orienting the liquid
crystal.
[0035] Further, another structure of the present invention is a
liquid crystal display device having a pair of substrates and a
liquid crystal maintained between the pair of substrates,
characterized in that [0036] formed on one substrate of the pair of
substrates are: [0037] a gate wiring; [0038] an insulating film on
the gate wiring; [0039] an amorphous semiconductor film on the
insulating film; [0040] a source region and a drain region on the
amorphous semiconductor film; [0041] a source wiring or an
electrode on the source region or the drain region; [0042] a pixel
electrode formed on the electrode; and [0043] a gap retaining
material formed for maintaining a constant gap between the pair of
substrates, and characterized in that [0044] a pre-tilt angle of
the liquid crystal is controlled by a side face of the gap
retaining material, and a concave portion or a convex portion
formed on at least one of the substrates, orienting the liquid
crystal.
[0045] In each of the above structures, at least one of the
substrates has an orientation film used for perpendicular
orientation.
[0046] Further, the gap retaining material has a constant taper
angle in each of the above structures. The taper angle is from
75.0.degree. to 89.9.degree., preferably from 82.degree. to
87.degree.. Furthermore, the gap retaining material is: an organic
resin material having at least one material chosen from the group
consisting of acrylics, polyimides, polyimide amines, and epoxies
as its main constituent; or an inorganic material chosen from the
group consisting of silicon oxide, silicon nitride, and silicon
nitride oxide, or a lamination film of such materials.
[0047] Further, the major axis direction of the liquid crystal
molecules in the vicinity of the side face of the gap retaining
material has strongly regulated orientation so as to be roughly
parallel with respect to the side face in each of the above
structures.
[0048] In addition, in each of the above structures, the liquid
crystal has negative dielectric anisotropy.
[0049] Furthermore, one end surface of the drain region or the
source region roughly coincides with an end surface of the
amorphous semiconductor film and an end surface of the electrode in
each of the above structures.
[0050] Further, in each of the above structures:
[0051] one end surface of the drain region or the source region
roughly coincides with an end surface of the amorphous
semiconductor film and an end surface of the electrode; and
[0052] another end surface of the drain region or the source region
roughly coincides with an end surface of the pixel electrode and
another end surface of the electrode.
[0053] Further, each of the above structures is characterized in
that the source region and the drain region is made from an
amorphous semiconductor film containing an impurity element which
imparts n-type conductivity.
[0054] Still further, each of the above structures is characterized
in that the insulating film, the amorphous semiconductor film, the
source region, and the drain region are formed in succession
without exposure to the atmosphere.
[0055] In addition, each of the above structures is characterized
in that the insulating film, the amorphous semiconductor film, the
source region, or the drain region is formed by a sputtering
method.
[0056] In addition, each of the above structures is characterized
in that the insulating film, the amorphous semiconductor film, the
source region, or the drain region is formed by a plasma CVD
method.
[0057] In addition, each of the above structures is characterized
in that the source region and the drain region are formed by using
the same mask as that of the amorphous semiconductor film and the
electrode.
[0058] In addition, each of the above structures is characterized
in that the source region and the drain region are formed by using
the same mask as that of the source wiring.
[0059] Furthermore, each of the above structures is characterized
in that the source region and the drain region are formed by using
the same mask as that of the source wiring and the pixel
electrode.
[0060] Further, each of the above structures is characterized in
that the pixel electrode contacts the insulating film.
[0061] Additionally, each of the above structures is characterized
in that the film thickness of regions of the amorphous
semiconductor film which contact the source region and the drain
region is thicker than the film thickness of a region between the
region contacting the source region and the region contacting the
drain region, the regions functioning as an active layer of a
channel etch type TFT.
[0062] Still further, each of the above structures is characterized
in that the region of the amorphous semiconductor film between the
region contacting the source region and the region contacting the
drain region is protected by being covered by the gap retaining
material made from the inorganic insulating film.
[0063] A structure of the present invention to realize the above
structures is a method of manufacturing a liquid crystal display
device, characterized by having: [0064] a first step of forming a
gate wiring on a first substrate by using a first mask; [0065] a
second step of forming an insulating film covering the gate wiring;
[0066] a third step of forming a first amorphous semiconductor film
on the insulating film; [0067] a fourth step of forming a second
semiconductor film, containing an impurity element which imparts
n-type conductivity, on the first amorphous semiconductor film;
[0068] a fifth step of forming a first conductive film on the
second amorphous semiconductor film; [0069] a sixth step of: [0070]
patterning the first amorphous semiconductor film by using a second
mask; [0071] patterning the second amorphous semiconductor film by
using the second mask; and [0072] patterning the first conductive
film by using the second mask, forming a wiring from the first
conductive film; [0073] a seventh step of forming a second
conductive film contacting and overlapping the wiring; [0074] an
eighth step of: [0075] patterning the second conductive film by
using a third mask, forming a pixel electrode made from the second
conductive film; [0076] patterning the wiring by using the third
mask, forming a source wiring and an electrode; [0077] patterning
the second amorphous semiconductor film by using the third mask,
forming a source region and a drain region made from the second
amorphous semiconductor film; and [0078] removing a portion of the
first amorphous semiconductor film by using the third mask; [0079]
a ninth step of forming an orientation film on the pixel electrode;
[0080] a tenth step of forming a gap retaining material on the
orientation film; [0081] an eleventh step of joining together the
first substrate and a second substrate; and [0082] a twelfth step
of injecting a liquid crystal between the first substrate and the
second substrate.
[0083] The above structure is characterized in that the gap
retaining material maintains a gap between the first substrate and
the second substrate at a fixed distance.
[0084] Further, in the above structure, a pre-tilt angle of the
liquid crystal is controlled by a side surface of the gap retaining
material, orienting the liquid crystal. Furthermore, control of the
pre-tilt angle of the liquid crystal is performed by using the
orientation film. The orientation film may be formed on one of the
first substrate and the second substrate, or may be formed on both
substrates.
EMBODIMENT MODE OF THE INVENTION
[0085] Embodiment modes of the present invention will be explained
below.
[0086] The present invention is characterized by, in order to solve
the above problems, employing a channel etch type bottom gate TFT
structure and by performing patterning of a source region and a
drain region with the same photomask as that used for patterning of
a pixel electrode.
[0087] A method of manufacturing the present invention is explained
simply below.
[0088] First, a gate wiring 102 is formed using a first mask
(photomask number 1).
[0089] Next, an insulating film (gate insulating film) 104a, a
first amorphous semiconductor film 105, a second amorphous
semiconductor film 106 containing an impurity element which imparts
n-type conductivity, and a first conductive film 107 are formed and
laminated in order. (See FIG. 2(A).) Note that a microcrystalline
semiconductor film may be used as a substitute for the amorphous
semiconductor film, and that a microcrystalline semiconductor film
containing an impurity element which imparts n-type conductivity
may be used as a substitute for the amorphous semiconductor film
containing the impurity element which imparts n-type conductivity.
In addition, these films (104a, 105, 106, and 107) can be formed by
sputtering or plasma CVD in succession inside a plurality of
chambers, or within the same chamber, without exposure to the
atmosphere. The mixing in of impurities can be prevented by having
no exposure to the atmosphere.
[0090] Next, using a second mask (photomask number 2): a wiring
(later becoming a source wiring and an electrode (drain electrode))
111 made from the first conductive film is formed by patterning the
first conductive film 107; a second amorphous semiconductor film
110 containing the impurity element which imparts n-type
conductivity is formed by patterning the second amorphous
semiconductor film 106; and a first amorphous semiconductor film
109 is formed by patterning the first amorphous semiconductor film
105. (See FIG. 2(B).)
[0091] A second conductive film 112 is deposited on the entire
surface afterward. (See FIG. 2(D).) Note that a transparent
conductive film may be used as the second conductive film 112, and
that a conductive film having reflective characteristics may also
be used.
[0092] Next, by using a third mask (photomask number 3): a pixel
electrode 119 made from the second conductive film is formed by
patterning the second conductive film 112; a source wiring 117 and
an electrode (drain electrode) 118 are formed by patterning the
wiring; a source region 115 and a drain region 116 made from the
second amorphous semiconductor film containing the impurity element
which imparts n-type conductivity are formed by patterning the
second amorphous semiconductor film 110 containing the impurity
element which imparts n-type conductivity; and a first amorphous
semiconductor film 114 is formed by removing a portion of the first
amorphous semiconductor film 109. (See FIG. 3(A).)
[0093] By using this type of constitution, the number of photomasks
used in the photolithography technique can be set to 3 when
manufacturing a pixel TFT portion.
[0094] In addition, the liquid crystal display device is
manufactured by the present invention without increasing the number
of steps and without performing a rubbing process.
[0095] A gap retaining material is formed in order to maintain a
constant gap between a pair of substrates (a substrate 100 and an
opposing substrate 124) with the present invention, as shown in
FIG. 1. As the gap retaining material here, wall spacers 121 and
122 are given sloped side faces and control a pre-tilt angle of a
liquid crystal having negative dielectric anisotropy, orienting the
liquid crystal.
[0096] The cross sectional shape of the wall spacers 121 and 122
is, for example, set to that of FIG. 17(a) or FIG. 17(b) throughout
this specification. In particular, a taper angle a such as that of
FIG. 17(a) is defined as the angle between the bottom face and the
side face of the trapezoid-shape cross section. It is preferable to
set the taper angle .alpha. from 75.0.degree. to 89.90, more
preferably between 82.degree. and 87.degree., in the present
invention.
[0097] The orientation of the liquid crystal molecules within FIG.
1 shows a schematic diagram when no voltage is applied. Note that
portions painted black show edge portions of the liquid crystal
molecules close to the opposing substrate.
[0098] When there is no applied voltage, the liquid crystal
molecules receive regulation power from the side faces of the
wall-like spacers, are oriented nearly parallel to the side faces,
and are oriented perpendicular to the substrate surface having a
certain pre-tilt angle, but when there is an applied voltage, the
liquid crystal molecules are oriented parallel to the substrate
surface.
[0099] In other words, by using the wall-like spacers having side
faces with the taper angle a, the switching direction of the liquid
crystal molecules can be controlled.
[0100] Further, the wall-like spacers are formed by a
photolithography method or by a printing method. In addition, an
orientation film used for perpendicular orientation is formed
either before or after forming the wall-like spacers.
[0101] Furthermore, the wall-like spacers may be formed on only the
substrate 100, or on only the opposing substrate 124. The wall-like
spacers may also be formed on both the substrate 100 and the
opposing substrate 124. Provided that a reduction in the number of
photomasks during manufacture of an active matrix substrate is
given priority, it is preferable to use a method of formation by
printing, or it is preferable to form the wall-like spacers only on
the opposing substrate. When applying the liquid crystal display
device in which the wall-like spacers are only formed on the
opposing substrate to a normally white mode, a portion in which
there is orientation disorder in the periphery of the wall-like
spacers, or a portion having non-uniform threshold voltage due to
disordered orientation, is hidden from the recognition of the user
of the display by the wall-like spacers themselves, and light
leakage can be reduced. Therefore, a high contrast, high-grade
display liquid crystal display device can be obtained by
suppressing light leakage through the wall-like spacers.
[0102] An organic resin material having at least one material
chosen from the group consisting of acrylics, polyimides, polyimide
amines, and epoxies as its main constituent; or an inorganic
material chosen from the group consisting of silicon oxide, silicon
nitride, and silicon nitride oxide, or a lamination film of such
materials can be used as the material for the wall-like
spacers.
[0103] Furthermore, when an inorganic material, for example silicon
nitride, is used for the wall-like spacers in the above channel
etch TFT, in particular, when the spacers are arranged so as to
cover a portion of the amorphous semiconductor film 114 which is
exposed, then an effect as a protecting film can be obtained, and
the reliability is increased.
[0104] In addition, the pre-tilt angle of the liquid crystal may be
controlled and the liquid crystal may be oriented both by an uneven
portion formed by arranging wirings such as the gate wiring, the
source wiring, and a capacitor wiring, and the electrode in
suitable preset locations, and by the wall-like spacers arranged in
suitably preset locations.
[0105] When using the present invention, the orientation process
corresponding to the rubbing process which leads to static
electricity damage can be omitted, and further, the wall-like
spacers possess a role of maintaining the substrate gap, and
therefore it is possible to omit a ball shape spacer spraying step,
and the productivity is increased. In addition, the present
invention has the advantage of being able to predict the
development of display unevenness by only investigating the
uniformity of the wall-like spacers formed on the substrate.
[0106] Furthermore, it is possible to have a stripe shape, a
T-shape, or a ladder-like as the shape of the wall-like spacers
when seen from above, but the embodiment mode of the present
invention is not limited to these shapes.
[0107] A more detailed explanation of the present invention having
the above constitution is performed using the embodiments shown
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0108] FIG. 1 is a diagram showing a cross-sectional view and a
liquid crystal molecule orientation state of the present
invention.
[0109] FIG. 2 is a cross-sectional view showing a process of
manufacturing an active matrix substrate.
[0110] FIG. 3 is a cross-sectional view showing the process of
manufacturing the active matrix substrate.
[0111] FIG. 4 is a top view showing the process of manufacturing
the active matrix substrate.
[0112] FIG. 5 is a top view showing the process of manufacturing
the active matrix substrate.
[0113] FIG. 6 is a top view showing the process of manufacturing
the active matrix substrate.
[0114] FIG. 7 is a top view explaining the placement of the pixel
portion and the input terminal portion of the liquid crystal
display panel.
[0115] FIG. 8 is a cross-sectional view showing an example of a
method of mounting a liquid crystal display panel.
[0116] FIG. 9 is a top view and a cross-sectional view showing the
input terminal portion.
[0117] FIG. 10 is a top view showing the manufacturing
apparatus.
[0118] FIG. 11 is a top view showing the manufacturing
apparatus.
[0119] FIG. 12 is a diagram showing an example of a method of
mounting the liquid crystal display panel.
[0120] FIG. 13 is a cross-sectional view showing an example of a
method of mounting a liquid crystal display panel.
[0121] FIG. 14 is a diagram showing a cross-sectional view and a
liquid crystal molecule orientation state of the present
invention.
[0122] FIG. 15 is a diagram showing a cross-sectional view and a
liquid crystal molecule orientation state of the present
invention.
[0123] FIG. 16 is a diagram showing a cross-sectional view and a
liquid crystal molecule orientation state of the present
invention.
[0124] FIG. 17 is a diagram showing perspective views of wall-like
spacers of the present invention.
[0125] FIG. 18 is a diagram showing top views of wall-like spacers
of the present invention.
[0126] FIG. 19 is a top view and a circuit diagram of a protecting
circuit.
[0127] FIG. 20 is a diagram showing examples of electronic
equipment.
[0128] FIG. 21 is a diagram showing examples of electronic
equipment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiment 1
[0129] An embodiment of the invention is explained using FIGS. 1 to
7, 9 and 17. Embodiment 1 shows a method of manufacturing a liquid
crystal display panel, and a detailed explanation of a method of
forming a TFT of a pixel portion on a substrate by a reverse
stagger type TFT, and manufacturing a storage capacitor connected
to the TFT, is made in accordance with the processes used. Further,
a manufacturing process for a terminal section, formed in an edge
portion of the substrate, and for electrically connecting to
wirings of circuits formed on other substrates, is shown at the
same time in the same figures.
[0130] In FIG. 2(A), a glass substrate, comprising such as barium
borosilicate glass or aluminum borosilicate glass, typically
Corning Corp. #7059 or #1737, can be used as a substrate 100 having
translucency. In addition, a translucent substrate such as a quartz
substrate or a plastic substrate can also be used.
[0131] Next, after forming a conductive layer on the entire surface
of the substrate, a first photolithography process is performed, a
resist mask is formed, unnecessary portions are removed by etching,
and wirings and electrodes (the gate wiring 102 including a gate
electrode, a capacitor wiring 103 and a terminal 101) are formed.
Etching is performed at this time to form a tapered portion in at
least an edge portion of the gate electrode 102. A top view of this
stage is shown in FIG. 4.
[0132] It is preferable to form the gate wiring 102 including the
gate electrode, the capacitor wiring 103, and the terminal 101 of
the terminal section from a low resistivity conductive material
such as aluminum (Al) or copper (Cu), but simple Al has problems
such as inferior heat resistance and easily corrodes, and therefore
it is combined with a heat resistant conductive material. Further,
an Ag--Pd--Cu alloy may also be used as the low resistance
conductive material. One element selected from the group consisting
of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo),
chromium (Cr), or an alloy comprising the above elements, or an
alloy film of a combination of the above elements, or a nitrated
compound comprising the above elements is formed as the heat
resistant conductive material. For example, a lamination film of Ti
and Cu, and a lamination film of TaN and Cu can be given.
Furthermore, forming in combination with a heat resistant
conductive material such as Ti, Si, Cr, or Nd, it is preferable
because of improved levelness. Further, only such heat resistant
conductive film may also be formed, for example, a combination of
Mo and W may be formed.
[0133] In realizing the liquid crystal display device, it is
preferable to form the gate electrode and the gate wiring by a
combination of a heat resistant conductive material and a low
electrical resistance conductive material. An appropriate
combination in this case is explained.
[0134] Provided that the screen size is on the order of, or less
than, 5 inch diagonal type, a two layer structure of a lamination
of a conductive layer (A) made from a nitride compound of a heat
resistant conductive material, and a conductive layer (B) made from
a heat resistant conductive material is used. The conductive layer
(B) may be formed from an element selected from the group
consisting of Al, Cu, Ta, Ti, W, Nd, and Cr, or from an alloy of
the above elements, or from an alloy film of a combination of the
above elements, and the conductive layer (A) is formed from a film
such as a tantalum nitride (TaN) film, a tungsten nitride (WN)
film, or a titanium nitride (TiN) film. For example, it is
preferable to use a double layer structure of a lamination of Cr as
the conductive layer (A) and Al containing Nd as the conductive
layer (B). The conductive layer (A) is given a thickness of 10 to
100 nm (preferably between 20 and 50 nm), and the conductive layer
(B) is made with a thickness of 200 to 400 nm (preferably between
250 and 350 nm).
[0135] On the other hand, in order to be applied to a large screen,
it is preferable to use a three layer structure of a lamination of
a conductive layer (A) made from a heat resistant conductive
material, a conductive layer (B) made from a low electrical
resistance conductive material, and a conductive layer (C) made
from a heat resistant conductive material. The conductive layer (B)
made from the low electrical resistance conductive material is
formed from a material comprising aluminum (Al), and in addition to
pure Al, Al containing between 0.01 and 5 atomic % of an element
such as scandium (Sc), Ti, Nd, or silicon (Si) is used. The
conductive layer (C) is effective in preventing generation of
hillocks in the Al of the conductive layer (B). The conductive
layer (A) is given a thickness of 10 to 100 nm (preferably between
20 and 50 nm), the conductive layer (B) is made from 200 to 400 nm
thick (preferable between 250 and 350 nm), and the conductive layer
(C) is from 10 to 100 nm thick (preferably between 20 and 50 nm).
In Embodiment 1, the conductive layer (A) is formed from a Ti film
with a thickness of 50 nm, made by sputtering with a Ti target, the
conductive layer (B) is formed from an Al film with a thickness of
200 nm, made by sputtering with an Al target, and the conductive
layer (C) is formed from a 50 nm thick Ti film, made by sputtering
with a Ti target.
[0136] An insulating film 104a is formed next on the entire
surface. The insulating film 104a is formed using sputtering, and
has a film thickness of 50 to 200 nm.
[0137] For example, a silicon nitride film is used as the
insulating film 104a, and formed to a thickness of 150 nm. Of
course, the gate insulating film is not limited to this type of
silicon nitride film, and another insulating film such as a silicon
oxide film, a silicon oxynitride film, or a tantalum oxide film may
also be used, and the gate insulating film may be formed from a
single layer or a lamination structure made from these materials.
For example, a lamination structure having a silicon nitride film
as a lower layer and a silicon oxide film as an upper layer may be
used.
[0138] Next, a first amorphous semiconductor film 105 is formed
with a thickness of 50 to 200 nm (preferably between 100 and 150
nm) on the insulating film 104a over the entire surface by using a
known method such as plasma CVD or sputtering (not shown in the
figure). Typically, an amorphous silicon (a-Si) film is formed with
a thickness of 100 nm by sputtering using a silicon target. In
addition, it is also possible to apply a microcrystalline
semiconductor film, or a compound semiconductor film having an
amorphous structure, such as an amorphous silicon germanium film
(SixGe.sub.(1-x), where 0<x<1), or an amorphous silicon
carbide (Si.sub.xC.sub.y).
[0139] A second amorphous semiconductor film which contains an
impurity element imparting one conductivity type (n-type or p-type)
is formed next with a thickness of 20 to 80 nm. The second
amorphous semiconductor film which contains an impurity element
imparting one conductivity type (n-type or p-type) is formed on the
entire surface by a known method such as plasma CVD or sputtering.
In this Embodiment, the second amorphous semiconductor film 106,
containing an n-type impurity element, is formed using a silicon
target in which phosphorous (P) has been added. Alternatively, film
deposition may be performed by sputtering using a silicon target in
an atmosphere containing phosphorous. In addition, the second
amorphous semiconductor film, containing an n-type impurity element
may also be formed from a hydrogenated microcrystalline silicon
film (pc-Si:H).
[0140] Next, a first conductive film 107 made from a metallic
material is formed by sputtering or vacuum evaporation. Provided
that ohmic contact with the second amorphous semiconductor film 106
can be made, there are no particular limitation on the material of
the first semiconductor film 107, and an element selected from the
group consisting of Al, Cr, Ta, and Ti, or an alloy comprising the
above elements, and an alloy film of a combination of the above
elements or the like can be given. Sputtering is used in Embodiment
1, and a 50 to 150 nm thick Ti film, an aluminum (Al) film with a
thickness between 300 and 400 nm above the Ti film, and a Ti film
with a thickness of 100 to 150 nm thereon are formed as the first
conductive film 107. (FIG. 2(A))
[0141] The insulating film 104a, the first amorphous semiconductor
film 105, the second amorphous semiconductor film 106 containing an
impurity element which imparts n-type conductivity, and the first
conductive film 107 are all manufactured by a known method, and can
be manufactured by plasma CVD or sputtering. These films (104a,
105, 106, and 107) are formed in succession by sputtering, and
suitably changing the target or the sputtering gas in Embodiment 1.
The same reaction chamber, or a plurality of reaction chambers, in
the sputtering apparatus is used at this time, and it is preferable
to laminate these films in succession without exposure to the
atmosphere. By thus not exposing the films to the atmosphere, the
mixing in of impurities can be prevented.
[0142] Next, a second photolithography process is then performed, a
resist mask 108 is formed, and by removing unnecessary portions by
etching, a wiring (becoming a source wiring and a drain electrode
by subsequent processing) 111 is formed. Wet etching or dry etching
is used as the etching process at this time. The first conductive
film 107, the second amorphous semiconductor film 106 containing an
impurity element which imparts n-type conductivity, and the first
amorphous semiconductor film 105 are etched in order with the
resist mask 108 as a mask. The wiring 111 composed of the first
conductive film, a second amorphous conductive film 110 containing
an impurity element which imparts n-type conductivity, and a first
amorphous semiconductor film 109 are each formed in the pixel TFT
portion. In Embodiment 1, the first conductive film 107 in which
the Ti film, the Al film, and the Ti film are laminated in order is
etched by dry etching using a gas mixture of SiCl.sub.4, Cl.sub.2,
and BCl.sub.3 as a reaction gas, and the reaction gas is
substituted with a gas mixture of CF.sub.4 and O.sub.2, and the
first amorphous semiconductor film 105 and the second amorphous
semiconductor film 106, containing the impurity element for
imparting n-type conductivity, are selectively removed. (FIG. 2(B))
Further, the capacitor wiring 103 and the insulating film 104a
remain in a capacitor portion, and the terminal 101 and the
insulating film 104a also remain similarly in a terminal
portion.
[0143] Next, after removing the resist mask 108, a resist mask is
formed using a shadow mask, and the insulating film 104a covering
the pad portion of the terminal portion is selectively removed,
forming an insulating film 104b, after which the resist mask is
removed. (FIG. 2(C)) Further, as a substitute for the shadow mask,
a resist mask may also be formed by screen printing as an etching
mask.
[0144] A second conductive film 112 is deposited next on the entire
surface from a transparent conductive film. (FIG. 2(D)) Further, a
top view at this point is shown in FIG. 5. Note that, for
simplification, the second conductive film 112 formed on the entire
surface is not shown in FIG. 5.
[0145] The second conductive film 112 is formed from a material
such as indium oxide (In.sub.2O.sub.3) or indium oxide tin oxide
alloy (In.sub.2O.sub.3--SnO.sub.2, abbreviated as ITO) using a
method such as sputtering or vacuum evaporation. The etching
process for this type of material is performed using a solution of
hydrochloric acid type. However, a residue is easily generated,
particularly by ITO etching, and therefore an indium oxide zinc
oxide alloy (In.sub.2O.sub.3--ZnO) may be used in order to improve
the etching workability. The indium oxide zinc oxide alloy has
superior surface smoothing characteristics, and has superior
thermal stability compared to ITO, and therefore even if the wiring
111 contacting the second conductive film 112 is made from an Al
film, a corrosion reaction can be prevented. Similarly, zinc oxide
(ZnO) is also a suitable material, and in addition, in order to
increase the transmittivity of visible light and increase the
conductivity, a material such as zinc oxide in which gallium (Ga)
is added (ZnO:Ga) can be used.
[0146] Resist masks 113a to 113c are formed next by a third
photolithography process. Unnecessary portions are then removed by
etching, forming a first amorphous semiconductor film 114, a source
region 115, a drain region 116, the source electrode 117, the drain
electrode 118, and the pixel electrode 119. (FIG. 3(A))
[0147] The third photolithography process patterns the second
conductive film 112, and at the same time removes a part of the
wiring 111, the second amorphous semiconductor film 110 containing
an impurity element which imparts n-type conductivity and the first
amorphous semiconductor film 109 by etching, forming an opening. In
Embodiment 1, the second conductive film 112 made from ITO is
selectively removed first by wet etching using a mixed solution of
nitric acid and hydrochloric acid, or a ferric chloride solution,
and after selectively removing the wiring 111 by wet etching, a
portion of the second amorphous semiconductor film 110 containing
the impurity element which imparts n-type conductivity and the
amorphous semiconductor film 109 are etched by dry etching. Note
that wet etching and dry etching are used in Embodiment 1, but the
operator may perform only dry etching by suitably selecting the
reaction gas, and the operator may perform only wet etching by
suitably selecting the reaction solution.
[0148] Further, the lower portion of the opening reaches the first
amorphous semiconductor film, and the first amorphous semiconductor
film 114 is formed having a concave portion. The wiring 111 is
separated into the source wiring 117 and the drain electrode 118 by
the opening, and the second amorphous semiconductor film 110,
containing an impurity element which imparts n-type conductivity,
is separated into the source region 115 and the drain region 116.
Furthermore, the second conductive film 120 contacting the source
wiring covers the source wiring, and during subsequent
manufacturing processes, especially during a rubbing process,
fulfills a role of preventing static electricity from developing.
An example of forming the second conductive film 120 on the source
wiring is shown in this Embodiment, but the second conductive film
120 may also be removed.
[0149] Moreover, a storage capacitor is formed in the third
photolithography process by the capacitor wiring 103 and the pixel
electrode 119, with the insulating film 104b in the capacitor
portion as a dielectric.
[0150] In addition, the second conductive film made from the
transparent conductive film formed in the terminal portion and
covered by the resist mask 113c remains after the third
photolithography process.
[0151] The resist masks 113a to 113c are removed next. A cross
section diagram of this state is shown in FIG. 3(B). Note that FIG.
6 is a top view of one pixel, and FIG. 3(B) corresponds to cross
sections taken along the lines A-A' and B-B'.
[0152] Furthermore, FIG. 9(A) shows top views of a gate wiring
terminal portion 501 and a source wiring terminal portion 502 in
this state. Note that the same symbols are used for area
corresponding to those of FIG. 1 to FIG. 3. Further, FIG. 9(B)
corresponds to a cross-sectional view taken along the lines E-E'
and F-F' in FIG. 9(A). Reference numeral 503 in FIG. 9(A) denotes a
connecting electrode made from a transparent conductive film and
functioning as an input terminal. In addition, in FIG. 9(B)
reference numeral 504 denotes an insulating film (extended from
104b), reference numeral 505 denotes a first amorphous
semiconductor film (extended from 114), and reference numeral 506
denotes a second amorphous semiconductor film containing an
impurity element which imparts n-type conductivity (extended from
115).
[0153] By thus using three photomasks and performing three
photolithography processes, the pixel TFT portion having the
reverse stagger type n-channel type TFT 201 and the storage
capacitor 202 can be completed. By placing these in a matrix state
corresponding to each pixel and thus composing the pixel portion,
one substrate can be made in order to manufacture an active matrix
type electro-optical device. For convenience, this type of
substrate is referred to as an active matrix substrate throughout
this specification.
[0154] Alignment films 131 and 132 are next formed on the active
matrix substrate. JALS-2021 (manufactured by JSR Corp.) is formed
by printing here and then fired.
[0155] After forming the alignment films, a gap holding member
which holds the substrate gap, a wall-like spacer 127 shown in FIG.
17(a) in this Embodiment, is formed by performing the fourth
photolithography process. Further, a process of exposing light to
the negative type resin from the back side of the substrate may be
used. Further, it is possible to form the wall-like spacer having
the above described shape by using dry etching or plasma
etching.
[0156] NN700 (manufactured by JSR Corp.), which is a material
having a photosensitive acrylic material as the principle
component, is deposited on the entire surface of the substrate by
spinner into 4.2 .mu.m thickness. An acrylic resin is used because
of its readiness for formation. The dielectric constant of the
acrylic resin NN700 used in the invention is 3.4. A resist mask is
next formed, unnecessary portions are removed by etching and a
wall-like spacer of the shape as shown in FIG. 17(a) is formed. In
case the top portion is made flat, a mechanical strength as a
liquid crystal display panel can be secured. According to SEM
observation, the height of the wall-like spacer was 4 .mu.m. It is
preferable that the taper angle of the wall-like spacer has an
angle between 75.0.degree. and 89.9.degree., preferably between
82.degree. and 87.degree..
[0157] The active matrix substrate, and an opposing substrate 124
on which a wall-like spacer 122 which is similarly formed with the
above described wall-like spacer is formed, are next joined
together by a sealant while maintaining a gap between the
substrates using the wall-like spacers 121 and 122, after which a
liquid crystal material 125 is injected into the space between the
active matrix substrate and the opposing substrate. A liquid
crystal material having a negative dielectric anisotropy (n-type
liquid crystal), in this Embodiment MLC-2038 (manufactured by
Merck), is used for the liquid crystal material 125. When the
pre-tilt angle is measured, the pre-tilt angle is prescribed within
a range between 2 and 5.degree., and it is almost uniform at
3.degree. in the display region. Accordingly the region near the
surface of NN700 has an alignment regulating effect which makes the
longitudinal axis direction of the liquid crystal molecule
approximately parallel with respect to the surface.
[0158] After injecting the liquid crystal material, the injecting
entrance is sealed by a resin material.
[0159] A state shown in FIG. 1 is obtained through the above
processes. Note that only the state of 3 wall like spacers and
liquid crystal molecules between them are shown in FIG. 1 for the
simplification.
[0160] In this state the liquid crystal molecules are arranged
approximately parallel with the side walls of the wall-like spacers
121 and 122 by the influence of the side walls, when voltage is not
applied. Further, the liquid crystal molecules that are not in the
proximity of the side walls are also influenced by these liquid
crystal molecules. Thus a stable orientation having a pre-tilt
angle of several degrees is obtained in the whole pixel. By
applying a voltage larger than the threshold voltage of the liquid
crystal, a uniform operation is made towards an inclinating
direction determined by the pre-tilt angle. Namely, by using the
wall-like spacers 121 and 122 the orientation of the whole display
portion is controlled.
[0161] Further, top views of the wall-like spacers 121 and 122
disposed on the both substrates are shown in FIG. 18(a). The plane
cut along the dotted line X-X' corresponds to the cross section of
FIG. 1.
[0162] Next, a flexible printed circuit (FPC) is connected to the
input terminal 101 of the terminal portion. The FPC is formed by a
copper wiring 128 on an organic resin film 129 such as polyimide,
and is connected to the transparent conductive film covering the
input terminal by an anisotropic conductive adhesive. The
anisotropic conductive adhesive comprises an adhesive 126 and
particles 127, with a diameter of several tens to several hundred
of .mu.m and having a conductive surface plated by a material such
as gold, which are mixed therein. The particles 127 form an
electrical connection in this portion by connecting the transparent
conductive film on the input terminal 101 and the copper wiring
128. In addition, in order to increase the mechanical strength of
this region, a resin layer 130 is formed. (FIG. 3(C))
[0163] FIG. 7 is a diagram explaining the placement of the pixel
portion and the terminal portion of the active matrix substrate. A
pixel portion 211 is formed on a substrate 210, gate wirings 208
and source wirings 207 are formed intersecting on the pixel
portion, and the n-channel TFT 201 connected to this is formed
corresponding to each pixel. The pixel electrode 119 and a storage
capacitor 202 are connected to the drain side of the n-channel TFT
201, and the other terminal of the storage capacitor 202 is
connected to a capacitor wiring 209. The structure of the n-channel
TFT 201 and the storage capacitor 202 is the same as that of the
n-channel TFT 201 and the storage capacitor 202 shown by FIG.
3(B).
[0164] An input terminal portion 205 for inputting a scanning
signal is formed in one edge portion of the substrate, and is
connected to a gate wiring 208 by a connection wiring 206. Further,
an input terminal portion 203 for inputting an image signal is
formed in the other edge portion, and is connected to a source
wiring 207 by a connection wiring 204. A plurality of the gate
wiring 208, the source wiring 207, and the capacitor wiring 209 are
formed in accordance with the pixel density. Furthermore, an input
terminal portion 212 for inputting an image signal and a connection
wiring 213 may be formed, and may be connected to the source wiring
alternately with the input terminal portion 203. An arbitrary
number of the input terminal portions 203, 205, and 212 are formed,
which may be suitably determined by the operator.
[0165] Thus an active matrix liquid crystal display panel can be
formed in this Embodiment by going through photolithography
processes 4 times by using 4 photo-masks.
[0166] Though this Embodiment used a wall-like spacer, it is
acceptable to use a columnar spacer and the liquid crystal
molecules are oriented in multi-domain in its periphery.
Embodiment 2
[0167] FIG. 8 is an example of a method of mounting a liquid
crystal display device. The liquid crystal display panel has an
input terminal portion 302 formed in an edge portion of a substrate
301 on which TFTs are formed, and as shown by embodiment 1, this is
formed by a terminal 303 formed from the same material as a gate
wiring. An opposing substrate 304 is joined to the substrate 301 by
a sealant 305 encapsulating spacers 306, and in addition,
polarizing plates 307 and 308, and a color filter (not shown) are
formed. This is then fixed to a casing 321 by spacers 322.
[0168] Note that the TFT obtained in Embodiment 1 having an active
layer formed by an amorphous semiconductor film has a low electric
field effect mobility, and only approximately 1 cm.sup.2/Vsec is
obtained. Therefore, a driver circuit for performing image display
is formed by an IC chip, and mounted by a TAB (tape automated
bonding) method or by a COG (chip on glass) method. In Embodiment
2, an example is shown of forming the driver circuit in an IC chip
313, and mounting by using the TAB method. A flexible printed
circuit (FPC) is used, and the FPC is formed by a copper wiring 310
on an organic resin film 309, such as polyimide, and is connected
to the input terminal 302 by an anisotropic conductive adhesive.
The input terminal is a transparent conductive film formed on and
contacting the wiring 303. The anisotropic conductive adhesive is
structured by an adhesive 311 and particles 312, with a diameter of
several tens to several hundred of .mu.m and having a conductive
surface plated by a material such as gold, which are mixed therein.
The particles 312 form an electrical connection in this portion by
connecting the input terminal 302 and the copper wiring 310. In
addition, in order to increase the mechanical strength of this
region, a resin layer 318 is formed.
[0169] The IC chip 313 is connected to the copper wiring 310 by a
bump 314, and is sealed by a resin material 315. The copper wiring
310 is then connected to a printed substrate 317 on which other
circuits such as a signal processing circuit, an amplifying
circuit, and a power supply circuit are formed, through a
connecting terminal 316. A light source 319 and a light conductor
320 are formed on the opposing substrate 304 and used as a back
light in the transmitting liquid crystal display panel.
[0170] Accordingly by using a liquid crystal display panel of
Embodiment 1 a multi-domain vertical orientation type liquid
crystal display device, which has wide viewing angle display with
few gap unevenness, can be obtained.
Embodiment 3
[0171] In this Embodiment, an example of forming a liquid crystal
display panel by forming a protecting film is shown in FIG. 14.
Note that this Embodiment is identical to Embodiment 1 through the
state of FIG. 3(B), and therefore only points of difference are
explained. Further, the same symbols are used for locations
corresponding to those in FIG. 3(B).
[0172] After first forming through the state of FIG. 3(B) in
accordance with Embodiment 1, a thin inorganic insulating film is
formed on the entire surface. An inorganic insulating film formed
by using plasma CVD or sputtering such as a silicon oxide film, a
silicon nitride film, a silicon oxynitride film, or a tantalum
oxide film is used as the thin inorganic insulating film, and a
single layer or a lamination structure made from these materials
may be formed.
[0173] A forth photolithography process is performed next, forming
a resist mask, and unnecessary portions are removed by etching,
forming an insulating film 402 in the pixel TFT portion, and an
inorganic insulating film 401 in the terminal portion. These
inorganic insulating films 401 and 402 function as passivation
films. Further, the thin inorganic insulating film 401 is removed
in the terminal portion by the fourth photolithography process,
exposing the second conductive film, made from the transparent
conductive film, formed on the terminal 101 of the terminal
portion.
[0174] The state shown in FIG. 14 can be obtained by following the
processes on and after of Embodiment 1. Note however the fourth
photolithography process of forming a wall-like spacer in
Embodiment 1 is referred to as the fifth photolithography
process.
[0175] The reverse stagger type n-channel TFT and the storage
capacitor, protected by the inorganic insulating film, can thus be
completed in Embodiment 3 by performing the photolithography
process using five photomasks five times in total. By thus
structuring the pixel portion by arranging these into a matrix
state corresponding to each pixel, one substrate for manufacturing
the active matrix liquid crystal display panel can be made.
[0176] Note that it is possible to freely combine the constitution
of this Embodiment with that of Embodiment 1 or Embodiment 2.
Embodiment 4
[0177] In Embodiment 1 an example centering on forming an
insulating film, a first amorphous semiconductor film, a second
amorphous semiconductor film, containing an impurity element which
imparts n-type conductivity, and a first conductive film by
sputtering, but this Embodiment shows an example of using plasma
CVD to form the films.
[0178] The insulating film, the first amorphous semiconductor film,
and the second amorphous semiconductor film, containing an impurity
element which imparts n-type conductivity are formed by plasma CVD
in this Embodiment.
[0179] In this Embodiment, a silicon oxynitride film is used as the
insulating film, and formed with a thickness of 150 nm by plasma
CVD. Plasma CVD may be performed at this point with a power supply
frequency of 13 to 70 MHz, preferably between 27 and 60 MHz. By
using a power supply frequency of 27 to 60 MHz, a dense insulating
film can be formed, and the voltage resistance can be increased as
a gate insulating film. Further, a silicon oxynitride film
manufactured by adding N.sub.2O to SiH.sub.4 and NH.sub.3 has a
reduction in fixed electric charge density, and therefore is a
material which is preferable for this use. Of course, the gate
insulating film is not limited to this type of silicon oxynitride
film, and a single layer or a lamination structure using other
insulating films such as s silicon oxide film, a silicon nitride
film, or a tantalum oxide film may be formed. Further, a lamination
structure of a silicon nitride film in a lower layer, and a silicon
oxide film in an upper layer may be used.
[0180] For example, when using a silicon oxide film, it can be
formed by plasma CVD using a mixture of tetraethyl orthosilicate
(TEOS) and O.sub.2, with the reaction pressure set to 40 Pa, a
substrate temperature of 250 to 350.degree. C., and discharge at a
high frequency (13.56 MHz) power density of 0.5 to 0.8 W/cm.sup.2.
Good characteristics as the gate insulating film can be obtained
for the silicon oxide film thus formed by a subsequent thermal
anneal at 300 to 400.degree. C.
[0181] Typically, a hydrogenated amorphous silicon (a-Si:H) film is
formed with a thickness of 100 nm by plasma CVD as the first
amorphous semiconductor film. At this point, plasma CVD may be
performed with a power supply frequency of 13 to 70 MHz, preferably
between 27 and 60 MHz, in the plasma CVD apparatus. By using a
power frequency of 27 to 60 MHz, it becomes possible to increase
the film deposition speed, and the deposited film is preferable
because it becomes an a-Si film having a low defect density. In
addition, it is also possible to apply a microcrystalline
semiconductor film and a compound semiconductor film having an
amorphous structure, such as an amorphous silicon germanium film,
as the first amorphous semiconductor film.
[0182] Further, if 100 to 100 k Hz pulse modulation discharge is
performed in the plasma CVD film deposition of the insulating film
and the first amorphous semiconductor film, then particle
generation due to the plasma CVD gas phase reaction can be
prevented, and pinhole generation in the formed film can also be
prevented, and therefore is preferable.
[0183] Further, in this Embodiment a second amorphous semiconductor
film, containing an impurity element which imparts n-type
conductivity is formed with a thickness of 20 to 80 nm as a
semiconductor film containing a single conductivity type impurity
element. For example, an a-Si:H film containing an n-type impurity
element may be formed, and in order to do so, phosphine (PH.sub.3)
is added at a 0.1 to 5% concentration to silane (SiH.sub.4).
Alternatively, a hydrogenated microcrystalline silicon film
(.mu.c-Si:H) may also be used as a substitute for the second
amorphous semiconductor film 106, containing an impurity element
which imparts n-type conductivity.
[0184] These films can be formed in succession by appropriately
changing the reaction gas. Further, these films can be laminated
successively without exposure to the atmosphere at this time by
using the same reaction chamber or a plurality of reaction chambers
in the plasma CVD apparatus. By thus depositing successively these
films without exposing the films to the atmosphere, the mixing in
of impurities specifically into the first amorphous semiconductor
film can be prevented.
[0185] Note that it is possible to combine this Embodiment with any
one of Embodiments 1 to 3.
Embodiment 5
[0186] Examples are shown in Embodiment 1 and Embodiment 4 of
laminating an insulating film, a first amorphous semiconductor
film, a second amorphous semiconductor film containing an impurity
element which imparts n-type conductivity, and a first conductive
film, in order and in succession. An example of an apparatus
prepared with a plurality of chambers, and used for cases of
performing this type of successive film deposition is shown in FIG.
10.
[0187] An outline of an apparatus (successive film deposition
system), shown by this Embodiment, is shown in FIG. 10 as seen from
above. Reference numerals 10 to 15 in FIG. 10 denote chambers
having airtight characteristics. A vacuum evacuation pump and an
inert gas introduction system are arranged in each of the
chambers.
[0188] The chambers denoted by reference numerals 10 and 15 are
load-lock chambers for bringing test pieces (processing substrates)
30 into the system. The chamber denoted by reference numeral 11 is
a first chamber for deposition of the insulating film 104. The
chamber denoted by reference numeral 12 is a second chamber for
deposition of the first amorphous semiconductor film 105. The
chamber denoted by reference numeral 13 is a third chamber for
deposition of the second amorphous semiconductor film 106 which
imparts n-type conductivity. The chamber denoted by reference
numeral 14 is a fourth chamber for deposition of the first
conductive film 107. Further, reference numeral 20 denotes a common
chamber of the test pieces, arranged in common with respect to each
chamber.
[0189] An example of operation is shown below.
[0190] After pulling an initial high vacuum state in all of the
chambers at first, a purge state (normal pressure) is made by using
an inert gas, nitrogen here. Furthermore, a state of closing all
gate valves 22 to 27 is made.
[0191] First, a cassette 28 loaded with a multiple number of
processing substrates is placed into the load-lock chamber 10.
After the cassette is placed inside, a door of the load-lock
chamber (not shown in the figure) is closed. In this state, the
gate valve 22 is opened and one of the processing substrates 30 is
removed from the cassette, and is taken out to the common chamber
20 by a robot arm 21. Position alignment is performed in the common
chamber at this time. Note that a substrate on which the wirings
101, 102, and 103 are formed, obtained in accordance with
Embodiment 1, is used for the substrate 30.
[0192] The gate valve 22 is then closed, and a gate valve 23 is
opened next. The processing substrate 30 is then moved into the
first chamber 11. Film deposition processing is performed within
the first chamber at a temperature of 150 to 300.degree. C., and
the insulating film 104 is obtained. Note that a film such as a
silicon nitride film, a silicon oxide film, a silicon oxynitride
film, or a lamination film of these films, can be used as the
insulating film. A single layer silicon nitride film is employed in
this Embodiment, but a two-layer, three-layer, or higher layer
lamination structure film may also be used. Note that a chamber
capable of plasma CVD is used here, but a chamber which is capable
of sputtering by use of a target may also be used.
[0193] After completing the deposition of the insulating film, the
processing substrate is pulled out into the common chamber by the
robot arm, and is then transported to the second chamber 12. Film
deposition is performed within the second chamber at a temperature
of 150 to 300.degree. C., similar to that of the first chamber, and
the first amorphous semiconductor film 105 is obtained by plasma
CVD. Note that a film such as a microcrystalline semiconductor
film, an amorphous germanium film, an amorphous silicon germanium
film, or a lamination film of these films can be used as the first
amorphous semiconductor film. Further, a heat treatment process for
reducing the concentration of hydrogen may be omitted with a
formation temperature of 350 to 500.degree. C. for the first
amorphous semiconductor film. Note that a chamber capable of plasma
CVD is used here, but a chamber which is capable of sputtering by
use of a target may also be used.
[0194] After completing deposition of the first semiconductor film,
the processing substrate is pulled out into the common chamber and
then transported to the third chamber 13. Film deposition process
is performed within the third chamber at a temperature of 150 to
300.degree. C., similar to that of the second chamber, and the
second amorphous semiconductor film 106, containing an impurity
element which imparts n-type conductivity (P or As), is obtained by
plasma CVD. Note that a chamber capable of plasma CVD is used here,
but a chamber which is capable of sputtering by use of a target may
also be used.
[0195] After completing deposition of the second amorphous
semiconductor film containing an impurity element which imparts
n-type conductivity, the processing substrate is pulled out into
the common chamber, and then is transported to the fourth chamber
14. The first conductive film 107 is obtained within the fourth
chamber by sputtering using a metallic target.
[0196] The processed substrate, on which four layers have thus been
formed in succession, is then transported to the load-lock chamber
15 by the robot arm, and is contained in a cassette 29.
[0197] Note that the apparatus shown in FIG. 10 is only one
example. Further, it is possible to freely combine this Embodiment
with any one of Embodiments 1 to 4.
Embodiment 6
[0198] In Embodiment 5, an example of successive lamination using a
plurality of chambers is shown, but in this Embodiment a method of
successive lamination within one chamber maintained at high vacuum
using the apparatus shown in FIG. 11 is employed.
[0199] The apparatus system shown in FIG. 11 is used in this
Embodiment. In FIG. 11, reference numeral 40 denotes a processing
substrate, reference numeral 50 denotes a common chamber, 44 and 46
denote load-lock chambers, 45 denotes a chamber, and reference
numerals 42 and 43 denote cassettes. In order to prevent
contamination developing during transport of the substrate,
lamination is performed in the same chamber in this Embodiment.
[0200] It is possible to freely combine this Embodiment with any
one of Embodiments 1 to 4.
[0201] Note that, when applied to Embodiment 1, a plurality of
targets are prepared in the chamber 45, and the insulating film
104, the first amorphous semiconductor film 105, the second
amorphous semiconductor film 106 containing an impurity element
which imparts n-type conductivity, and the first conductive film
107 may be laminated by changing the reaction gas in order.
[0202] Further, when applied to Embodiment 4, the insulating film
104, the first amorphous semiconductor film 105, and the amorphous
second semiconductor film 106, containing an impurity element which
imparts n-type conductivity, may be laminated by changing the
reaction gas in order.
Embodiment 7
[0203] In Embodiment 1, an example of forming the second amorphous
semiconductor film containing an impurity element which imparts
n-type conductivity by using sputtering is shown, but in this
Embodiment an example of forming it by using plasma CVD is shown.
Note that, except for the method of forming the second amorphous
semiconductor film containing an impurity element which imparts
n-type conductivity, this Embodiment is identical to Embodiment 1,
and therefore only differing points are stated below.
[0204] If phosphine (PH.sub.3) is added at a concentration of 0.1
to 5% with respect to silane (SiH.sub.4) as a reaction gas using
plasma CVD, then the second amorphous semiconductor film containing
an impurity element which imparts n-type conductivity can be
obtained.
Embodiment 8
[0205] In Embodiment 7, an example of forming the second amorphous
semiconductor film containing an impurity element which imparts
n-type conductivity by using plasma CVD is shown, and in this
Embodiment, an example of using a microcrystalline semiconductor
film containing an impurity element which imparts n-type
conductivity is shown.
[0206] By setting the substrate temperature from 80 to 300.degree.
C., preferably between 140 and 200.degree. C., taking a gas mixture
of silane diluted by hydrogen (SiH.sub.4:H.sub.2=1:10 to 100) and
phosphine (PH.sub.3) as the reaction gas, setting the gas pressure
from 0.1 to 10 Torr, and setting the discharge power from 10 to 300
mW/cm.sup.2, a microcrystalline silicon film can be obtained.
Further, the film may be formed by adding phosphorous after film
deposition of this microcrystalline silicon film by using plasma
doping.
Embodiment 9
[0207] FIG. 12 is a diagram which schematically shows a state of
constructing an electro-optical display device by using the COG
method. A pixel region 803, an external input-output terminal 804,
and a connection wiring 805 are formed on a first substrate.
Regions surrounded by dotted lines denote a region 801 for
attaching a scanning line side IC chip, and a region 802 for
attaching a data line side IC chip. An opposing electrode 809 is
formed on a second substrate 808, and this is joined to the first
substrate 800 by using a sealing material 810. A liquid crystal
layer 811 is formed inside the sealing material 810 by injecting a
liquid crystal. The first substrate and the second substrate are
joined with a predetermined gap, and this is set from 3 to 8 .mu.m
for a nematic liquid crystal, and from 1 to 4 .mu.m for a smectic
liquid crystal.
[0208] IC chips 806 and 807 have circuit structures which differ
between the data line side and the scanning line side. The IC chips
are mounted on the first substrate. An FPC (flexible printed
circuit) 812 is attached to the external input-output terminal 804
in order to input power supply and control signals from the
outside. In order to increase the adhesion strength of the FPC 812,
a reinforcing plate 813 may be formed. The electro-optical device
can thus be completed. If an electrical inspection is performed
before mounting the IC chips on the first substrate, then the final
process yield of the electro-optical device can be improved, and
the reliability can be increased.
[0209] Further, a method such as a method of connection using an
anisotropic conductive material or a wire bonding method, can be
employed as the method of mounting the IC chips on the first
substrate. FIG. 13 shows examples of such. FIG. 13(A) shows an
example in which an IC chip 908 is mounted on a first substrate 901
using an anisotropic conductive material. A pixel region 902, a
lead wire 906, a connection wiring and an input-output terminal 907
are formed on the first substrate 901. A second substrate is bonded
to the first substrate 901 by using a sealing material 904, and a
liquid crystal layer 905 is formed therebetween.
[0210] Further, an FPC 912 is bonded to one edge of the connection
wiring and the input-output terminal 907 by using an anisotropic
conductive material. The anisotropic conductive material is made
from a resin 915 and conductive particles 914 having a diameter of
several tens to several hundred of .mu.m and plated by a material
such as Au, and the wiring 913 formed with the FPC 912, and the
connection wiring and the input-output terminal 907 are
electrically connected by the conductive particles 914. The IC chip
908 is also similarly bonded to the first substrate by an
anisotropic conductive material. An input-output terminal 909
provided with the IC chip 908 and the lead wire 906 or a connection
wiring and the input-output terminal 907 are electrically connected
by conductive particles 910 mixed into a resin 911.
[0211] Furthermore, as shown by FIG. 13(B), the IC chip may be
fixed to the first substrate by an adhesive material 916, and an
input-output terminal of the IC chip and a lead wire or a
connection wiring may be connected by an Au wire 917. Then, this is
all sealed by a resin 918.
[0212] The method of mounting the IC chip is not limited to the
method based on FIGS. 12 and 13, and it is also possible to use a
known method not explained here, such as a COG method, a wire
bonding method or a TAB method.
[0213] It is possible to freely combine this Embodiment with any
one of Embodiments 1, and 3 to 8.
Embodiment 10
[0214] This Embodiment shows an example of using a plastic
substrate (or a plastic film) as a substrate. Note that, except for
the use of the plastic substrate as the substrate, this Embodiment
is nearly identical to Embodiment 1, and therefore only differing
points will be stated below.
[0215] PES (polyethylene sulfone), PC (polycarbonate), PET
(polyethylene terephthalate) and PEN (polyethylene naphthalate) can
be used as the plastic substrate material.
[0216] An active matrix substrate is completed using the plastic
substrate provided that manufacturing is performed in accordance
with Embodiment 1. Note that it is preferable to form the
insulating film, the first amorphous semiconductor film, and the
second amorphous semiconductor film containing an impurity element
which imparts n-type conductivity by sputtering with the relatively
low film deposition temperature.
[0217] A TFT having good characteristics can be formed on the
plastic substrate, and the resulting display device can be made low
weight. Further, it is possible to make a flexible electro-optical
device because the substrate is plastic. Furthermore, assembly
becomes easy.
[0218] Note that this Embodiment can be freely combined with any
one of Embodiments 1 to 3, and 9.
Embodiment 11
[0219] An example is shown in Embodiment 1 in which wall-like
spacers are formed on both the substrate 100 and the opposing
substrate 124, but in this Embodiment, an example is shown using
FIG. 15 in which the wall-like spacers are formed only in the
opposing substrate. Note that, except for the formation of
wall-like spacers 1501 on the opposing substrate 124, this
Embodiment is the same as Embodiment 1, and therefore only
differing points are explained.
[0220] A reverse stagger type n-channel TFT, and a storage
capacitor can be completed in this Embodiment by three
photolithography steps using three photomasks. A substrate prepared
with a pixel portion in which the reverse stagger type n-channel
TFTs are arranged in a matrix state corresponding to each of the
pixels can be used as one substrate of an active matrix type liquid
crystal display panel.
[0221] A top view of the wall-like spacers formed on the opposing
substrate is shown in FIG. 18(b). The cross-sectional diagrams of
FIG. 15 correspond to a face sectioned along the dotted line
Y-Y'.
[0222] Furthermore, when applying the liquid crystal display
device, in which the wall-like spacers are formed in the opposing
substrate, to a normally white mode, a portion in which there is
orientation disorder in the periphery of the wall-like spacers
1501, or a portion having non-uniform threshold voltage due to
disordered orientation, is hidden from the recognition of the user
of the display by the wall-like spacers themselves, and light
leakage can be reduced. Therefore, a multi-domain perpendicular
orientation type liquid crystal display device prepared with a high
contrast, high-grade display can be obtained by suppressing light
leakage through the wall-like spacers.
[0223] Note that it is possible to freely combine this Embodiment
with any one of Embodiments 1 to 10.
Embodiment 12
[0224] In Embodiment 12, an example of forming an orientation film
after forming a convex portion in an active matrix substrate is
shown in FIG. 16. Note that, except for the formation of
orientation films 1601 and 1602, and the formation of a convex
portion 1603, Embodiment 12 is the same as Embodiment 1, and
therefore only points of difference are explained.
[0225] An active matrix substrate is formed first in accordance
with Embodiment 1.
[0226] The convex portion 1603, having a shape which differs from
that of the wall-like spacers of Embodiment 1, is formed next. An
organic resin material having at least one material chosen from the
group consisting of acrylics, polyimides, polyimide amines, and
epoxies as its main constituent; or an inorganic material chosen
from the group consisting of silicon oxide, silicon nitride, and
silicon nitride oxide, or a lamination film of such materials can
be used as the material for the convex portion 1603.
[0227] Further, an example of forming the convex portion on a pixel
electrode is shown by FIG. 16, but a structure in which wirings are
arranged in desired locations and the convex portion is formed on
an insulating film covering the wirings, and in which liquid
crystals are oriented by using the convex portion may also be
used.
[0228] Next, the orientation film 1601 (JALS-2021; made by JSR) for
perpendicular orientation is formed on the convex portion 1603.
Wall-like spacers similar to those of Embodiment 1 are formed on an
opposing substrate. Further, the orientation film 1602 for
perpendicular orientation is also formed on the opposing substrate
124 in which an opposing electrode is formed. Then, after joining
together both substrates by using a sealant while maintaining the
substrate gap by the wall-like spacers formed on the opposing
substrate, an n-type liquid crystal material is injected between
both substrates. After injecting the liquid crystal material, the
injection port is sealed by a resin material.
[0229] Afterward, in accordance with Embodiment 1, a wiring for
performing external electrical connections is connected, and a
liquid crystal display panel is completed.
[0230] When there is no voltage applied, the orientation is
controlled by the wall-like spacers and the orientation film 1601
on the active matrix substrate, and by the wall-like spacers and
the orientation film 1602 on the opposing substrate, so that the
n-type liquid crystal has a constant direction. Using the liquid
crystal display panel of Embodiment 12, a multi-domain
perpendicular orientation type liquid crystal display device having
a wide viewing angle display and a little gap unevenness can be
obtained.
[0231] Note that it is possible to freely combine Embodiment 12
with any one of Embodiments 1 to 10.
Embodiment 13
[0232] A top view is shown in FIG. 18(a) of the wall-like spacers
shown in Embodiment 1. A wall-like spacer arrangement which differs
from that of Embodiment 1 is shown in Embodiment 13.
[0233] The wall-like spacers shown in FIG. 18(b) are an example of
wall-like spacers with a straight line shape and formed on only one
substrate, as shown in Embodiment 11.
[0234] The wall-like spacers shown in FIG. 18(c) have a branched
shape. A structure in which adjoining wall-like spacers are formed
on one substrate, or a structure in which they are formed on both
substrates may be used.
[0235] Further, the wall-like spacers shown in FIG. 18(d) are
lattice-shaped. The wall-like spacers are formed on one substrate
for the case of the wall-like spacers shown in FIG. 18(d).
Furthermore, when the wall-like spacers shown in FIG. 18(d) are
used, after dripping the liquid crystal, they are joined to another
substrate.
[0236] Note that the present invention is not limited to the top
arrangements shown in FIG. 18, and that any arrangement which can
orient an n-type liquid crystal may be used. For example, a T-shape
or a ladder-like arrangement may also be used.
[0237] Note that it is possible to freely combine Embodiment 13
with any one of Embodiments 1 to 12.
Embodiment 14
[0238] In Embodiment 14, an example of forming a protecting circuit
in a region other than a pixel portion, utilizing the same material
film as a pixel electrode is shown in FIG. 19.
[0239] In FIG. 19(A), reference numeral 701 denotes a wiring, and
shows a gate wiring, a source wiring, or a capacitor wiring
extended from the pixel portion. Further, an electrode 701 made
from a second conductive film is formed so as to be embedded in a
region in which the wiring 701 is not formed, and so as to not
overlap with the wiring 701. Embodiment 14 shows an example of
forming a protecting circuit without increasing the number of
masks, but is not particularly limited to the structure shown in
FIG. 19(A). For example, the protecting circuit may also be formed
by a protecting diode or TFTs by increasing the number of
masks.
[0240] Further, FIG. 19(B) shows an equivalent circuit diagram.
[0241] By using this type of structure, the generation of static
electricity due to friction between manufacturing devices and an
insulating substrate during manufacturing can be prevented. In
particular, elements such as TFTs can be protected from static
electricity generated during a liquid crystal orientation process
of rubbing performed during manufacture.
[0242] Note that Embodiment 14 can be freely combined with any one
of Embodiments 1 to 13.
Embodiment 15
[0243] A bottom gate type TFT formed by implementing any one of the
above Embodiments 1 to 14 can be used in various electro-optical
devices (such as an active matrix liquid crystal display device, an
active matrix EL display device, and an active matrix EC display
device). Namely, the present invention can be implemented in all
electronic appliances in which these electro-optical devices are
built into a display portion.
[0244] The following can be given as such electronic equipment: a
video camera, a digital camera, a projector (rear type or front
type), a head-mounted display (goggle type display), a car
navigation system, a car stereo, a personal computer, and a
portable information terminal (such as a mobile computer, a
portable telephone or an electronic book). Examples of these are
shown in FIGS. 20 and 21.
[0245] FIG. 20(A) is a personal computer, and it includes a main
body 2001, an image input portion 2002, a display portion 2003, and
a keyboard 2004. The present invention can be applied to the
display portion 2003.
[0246] FIG. 20(B) is a video camera, and it includes a main body
2101, a display portion 2102, an audio input portion 2103,
operation switches 2104, a battery 2105, and an image receiving
portion 2106. The present invention can be applied to the display
portion 2102.
[0247] FIG. 20(C) is a mobile computer, and it includes a main body
2201, a camera portion 2202, an image receiving portion 2203,
operation switches 2204, and a display portion 2205. The present
invention can be applied to the display portion 2205.
[0248] FIG. 20(D) is a player that uses a recording medium on which
a program is recorded (hereafter referred to as a recording
medium), and the player includes a main body 2401, a display
portion 2402, a speaker portion 2403, a recording medium 2404, and
operation switches 2405, etc. Note that this player uses a
recording medium such as a DVD (digital versatile disk) or a CD,
and the appreciation of music, the appreciation of film, game
playing and the Internet can be performed. The present invention
can be applied to the display portion 2402.
[0249] FIG. 20(E) is a digital camera, and it includes a main body
2501, a display portion 2502, an eyepiece portion 2503, operation
switches 2504, and an image receiving portion (not shown in the
figure), etc. The present invention can be applied to the display
portion 2502.
[0250] FIG. 21(A) is a portable telephone, and it includes a main
body 2901, an audio output portion 2902, an audio input portion
2903, a display portion 2904, operation switches 2905, and an
antenna 2906, etc. The present invention can be applied to the
display portion 2904.
[0251] FIG. 21(B) is a portable book (electronic book), and it
includes a main body 3001, display portions 3002 and 3003, a
recording medium 3004, operation switches 3005, and an antenna
3006. The present invention can be applied to the display portions
3002 and 3003.
[0252] FIG. 21(C) is a display, and it includes a main body 3101, a
support stand 3102, and a display portion 3103, etc. The present
invention can be applied to the display portion 3103. The display
of the present invention is advantageous for a large size screen in
particular, and is advantageous for a display equal to or greater
than 10 inches (especially equal to or greater than 30 inches) in
the opposite angle.
[0253] The applicable range of the present invention is thus
extremely wide, and it is possible to apply the present invention
to electronic equipment in all fields. Furthermore, the electronic
equipment of Embodiment 15 can be realized using a constitution
having any type of combination of Embodiments 1 to 14.
Effects of the Invention
[0254] By forming a pixel TFT portion having a reverse stagger type
n-channel TFT, and a storage capacitor, by three photolithography
steps using three photomasks, and in addition, by having a uniform
cell gap by forming wall-like spacers by one photolithography step,
without performing a rubbing process, a multi-domain perpendicular
orientation type liquid crystal display device having a wide
viewing angle display, and in which a switching direction of the
liquid crystal molecules is controlled, can be realized by the
present invention.
* * * * *